Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - add command queue telemetry counters for GEN6
Add slice-specific command queue counters for QAT GEN6 devices to monitor
utilization metrics, including wait time, execution duration, and release
events.
Update the documentation to reflect the new command queue counter
functionality.
Co-developed-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Vijay Sundar Selvamani
and committed by
Herbert Xu
3ed63344
9ea349e4
+210
+26
Documentation/ABI/testing/debugfs-driver-qat_telemetry
+26
Documentation/ABI/testing/debugfs-driver-qat_telemetry
···
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exec_cph<N> execution count of Cipher slice N
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util_ath<N> utilization of Authentication slice N [%]
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exec_ath<N> execution count of Authentication slice N
89
+
cmdq_wait_cnv<N> wait time for cmdq N to get Compression and verify
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+
slice ownership
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+
cmdq_exec_cnv<N> Compression and verify slice execution time while
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+
owned by cmdq N
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cmdq_drain_cnv<N> time taken for cmdq N to release Compression and
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verify slice ownership
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cmdq_wait_dcprz<N> wait time for cmdq N to get Decompression
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slice N ownership
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cmdq_exec_dcprz<N> Decompression slice execution time while
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+
owned by cmdq N
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+
cmdq_drain_dcprz<N> time taken for cmdq N to release Decompression
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+
slice ownership
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+
cmdq_wait_pke<N> wait time for cmdq N to get PKE slice ownership
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+
cmdq_exec_pke<N> PKE slice execution time while owned by cmdq N
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+
cmdq_drain_pke<N> time taken for cmdq N to release PKE slice
104
+
ownership
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+
cmdq_wait_ucs<N> wait time for cmdq N to get UCS slice ownership
106
+
cmdq_exec_ucs<N> UCS slice execution time while owned by cmdq N
107
+
cmdq_drain_ucs<N> time taken for cmdq N to release UCS slice
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+
ownership
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+
cmdq_wait_ath<N> wait time for cmdq N to get Authentication slice
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+
ownership
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+
cmdq_exec_ath<N> Authentication slice execution time while owned
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by cmdq N
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cmdq_drain_ath<N> time taken for cmdq N to release Authentication
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slice ownership
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======================= ========================================
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The telemetry report file can be read with the following command::
+104
drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c
+104
drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c
···
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#define SLICE_IDX(sl) offsetof(struct icp_qat_fw_init_admin_slice_cnt, sl##_cnt)
23
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+
#define ADF_GEN6_TL_CMDQ_WAIT_COUNTER(_name) \
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+
ADF_TL_COUNTER("cmdq_wait_" #_name, ADF_TL_SIMPLE_COUNT, \
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ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_wait_cnt, gen6))
27
+
#define ADF_GEN6_TL_CMDQ_EXEC_COUNTER(_name) \
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ADF_TL_COUNTER("cmdq_exec_" #_name, ADF_TL_SIMPLE_COUNT, \
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ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_exec_cnt, gen6))
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+
#define ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(_name) \
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ADF_TL_COUNTER("cmdq_drain_" #_name, ADF_TL_SIMPLE_COUNT, \
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ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_drain_cnt, \
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+
gen6))
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+
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#define CPR_QUEUE_COUNT 5
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#define DCPR_QUEUE_COUNT 3
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#define PKE_QUEUE_COUNT 1
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#define WAT_QUEUE_COUNT 7
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#define WCP_QUEUE_COUNT 7
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#define USC_QUEUE_COUNT 3
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#define ATH_QUEUE_COUNT 2
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+
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/* Device level counters. */
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static const struct adf_tl_dbg_counter dev_counters[] = {
26
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/* PCIe partial transactions. */
···
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[SLICE_IDX(ath)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ath),
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};
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+
static const struct adf_tl_dbg_counter cnv_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(cnv),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(cnv),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(cnv)
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};
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+
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#define NUM_CMDQ_COUNTERS ARRAY_SIZE(cnv_cmdq_counters)
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+
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static const struct adf_tl_dbg_counter dcprz_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(dcprz),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(dcprz),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(dcprz)
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};
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+
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static_assert(ARRAY_SIZE(dcprz_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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static const struct adf_tl_dbg_counter pke_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(pke),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(pke),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(pke)
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};
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+
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static_assert(ARRAY_SIZE(pke_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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static const struct adf_tl_dbg_counter wat_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(wat),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(wat),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(wat)
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};
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+
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static_assert(ARRAY_SIZE(wat_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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static const struct adf_tl_dbg_counter wcp_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(wcp),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(wcp),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(wcp)
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};
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+
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static_assert(ARRAY_SIZE(wcp_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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static const struct adf_tl_dbg_counter ucs_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(ucs),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(ucs),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(ucs)
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+
};
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+
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static_assert(ARRAY_SIZE(ucs_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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static const struct adf_tl_dbg_counter ath_cmdq_counters[] = {
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ADF_GEN6_TL_CMDQ_WAIT_COUNTER(ath),
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ADF_GEN6_TL_CMDQ_EXEC_COUNTER(ath),
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ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(ath)
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+
};
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+
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static_assert(ARRAY_SIZE(ath_cmdq_counters) == NUM_CMDQ_COUNTERS);
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+
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/* CMDQ drain counters. */
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static const struct adf_tl_dbg_counter *cmdq_counters[ADF_TL_SL_CNT_COUNT] = {
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/* Compression accelerator execution count. */
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[SLICE_IDX(cpr)] = cnv_cmdq_counters,
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/* Decompression accelerator execution count. */
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[SLICE_IDX(dcpr)] = dcprz_cmdq_counters,
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+
/* PKE execution count. */
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[SLICE_IDX(pke)] = pke_cmdq_counters,
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/* Wireless Authentication accelerator execution count. */
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[SLICE_IDX(wat)] = wat_cmdq_counters,
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+
/* Wireless Cipher accelerator execution count. */
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[SLICE_IDX(wcp)] = wcp_cmdq_counters,
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/* UCS accelerator execution count. */
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[SLICE_IDX(ucs)] = ucs_cmdq_counters,
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/* Authentication accelerator execution count. */
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[SLICE_IDX(ath)] = ath_cmdq_counters,
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};
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+
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/* Ring pair counters. */
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static const struct adf_tl_dbg_counter rp_counters[] = {
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/* PCIe partial transactions. */
···
229
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{
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tl_data->layout_sz = ADF_GEN6_TL_LAYOUT_SZ;
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tl_data->slice_reg_sz = ADF_GEN6_TL_SLICE_REG_SZ;
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tl_data->cmdq_reg_sz = ADF_GEN6_TL_CMDQ_REG_SZ;
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tl_data->rp_reg_sz = ADF_GEN6_TL_RP_REG_SZ;
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tl_data->num_hbuff = ADF_GEN6_TL_NUM_HIST_BUFFS;
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tl_data->max_rp = ADF_GEN6_TL_MAX_RP_NUM;
···
241
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tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
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tl_data->sl_util_counters = sl_util_counters;
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tl_data->sl_exec_counters = sl_exec_counters;
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tl_data->cmdq_counters = cmdq_counters;
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tl_data->num_cmdq_counters = NUM_CMDQ_COUNTERS;
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tl_data->rp_counters = rp_counters;
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tl_data->num_rp_counters = ARRAY_SIZE(rp_counters);
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tl_data->max_sl_cnt = ADF_GEN6_TL_MAX_SLICES_PER_TYPE;
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+
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tl_data->multiplier.cpr_cnt = CPR_QUEUE_COUNT;
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tl_data->multiplier.dcpr_cnt = DCPR_QUEUE_COUNT;
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tl_data->multiplier.pke_cnt = PKE_QUEUE_COUNT;
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tl_data->multiplier.wat_cnt = WAT_QUEUE_COUNT;
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tl_data->multiplier.wcp_cnt = WCP_QUEUE_COUNT;
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tl_data->multiplier.ucs_cnt = USC_QUEUE_COUNT;
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tl_data->multiplier.ath_cnt = ATH_QUEUE_COUNT;
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}
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EXPORT_SYMBOL_GPL(adf_gen6_init_tl_data);
+19
drivers/crypto/intel/qat/qat_common/adf_telemetry.c
+19
drivers/crypto/intel/qat/qat_common/adf_telemetry.c
···
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return ret;
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}
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+
static void adf_set_cmdq_cnt(struct adf_accel_dev *accel_dev,
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struct adf_tl_hw_data *tl_data)
217
+
{
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struct icp_qat_fw_init_admin_slice_cnt *slice_cnt, *cmdq_cnt;
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+
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slice_cnt = &accel_dev->telemetry->slice_cnt;
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cmdq_cnt = &accel_dev->telemetry->cmdq_cnt;
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+
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cmdq_cnt->cpr_cnt = slice_cnt->cpr_cnt * tl_data->multiplier.cpr_cnt;
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cmdq_cnt->dcpr_cnt = slice_cnt->dcpr_cnt * tl_data->multiplier.dcpr_cnt;
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cmdq_cnt->pke_cnt = slice_cnt->pke_cnt * tl_data->multiplier.pke_cnt;
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cmdq_cnt->wat_cnt = slice_cnt->wat_cnt * tl_data->multiplier.wat_cnt;
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cmdq_cnt->wcp_cnt = slice_cnt->wcp_cnt * tl_data->multiplier.wcp_cnt;
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+
cmdq_cnt->ucs_cnt = slice_cnt->ucs_cnt * tl_data->multiplier.ucs_cnt;
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cmdq_cnt->ath_cnt = slice_cnt->ath_cnt * tl_data->multiplier.ath_cnt;
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}
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+
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int adf_tl_run(struct adf_accel_dev *accel_dev, int state)
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{
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struct adf_tl_hw_data *tl_data = &GET_TL_DATA(accel_dev);
···
251
234
adf_send_admin_tl_stop(accel_dev);
252
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return ret;
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}
237
+
238
+
adf_set_cmdq_cnt(accel_dev, tl_data);
254
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telemetry->hbuffs = state;
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atomic_set(&telemetry->state, state);
+5
drivers/crypto/intel/qat/qat_common/adf_telemetry.h
+5
drivers/crypto/intel/qat/qat_common/adf_telemetry.h
···
28
28
struct adf_tl_hw_data {
29
29
size_t layout_sz;
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size_t slice_reg_sz;
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size_t cmdq_reg_sz;
31
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size_t rp_reg_sz;
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size_t msg_cnt_off;
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const struct adf_tl_dbg_counter *dev_counters;
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const struct adf_tl_dbg_counter *sl_util_counters;
35
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const struct adf_tl_dbg_counter *sl_exec_counters;
37
+
const struct adf_tl_dbg_counter **cmdq_counters;
36
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const struct adf_tl_dbg_counter *rp_counters;
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u8 num_hbuff;
38
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u8 cpp_ns_per_cycle;
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u8 bw_units_to_bytes;
40
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u8 num_dev_counters;
41
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u8 num_rp_counters;
44
+
u8 num_cmdq_counters;
42
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u8 max_rp;
43
46
u8 max_sl_cnt;
47
+
struct icp_qat_fw_init_admin_slice_cnt multiplier;
44
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};
45
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46
50
struct adf_telemetry {
···
73
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struct mutex wr_lock;
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struct delayed_work work_ctx;
75
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struct icp_qat_fw_init_admin_slice_cnt slice_cnt;
72
+
struct icp_qat_fw_init_admin_slice_cnt cmdq_cnt;
76
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};
77
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75
#ifdef CONFIG_DEBUG_FS
+52
drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c
+52
drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c
···
339
339
return 0;
340
340
}
341
341
342
+
static int tl_print_cmdq_counter(struct adf_telemetry *telemetry,
343
+
const struct adf_tl_dbg_counter *ctr,
344
+
struct seq_file *s, u8 cnt_id, u8 counter)
345
+
{
346
+
size_t cmdq_regs_sz = GET_TL_DATA(telemetry->accel_dev).cmdq_reg_sz;
347
+
size_t offset_inc = cnt_id * cmdq_regs_sz;
348
+
struct adf_tl_dbg_counter slice_ctr;
349
+
char cnt_name[MAX_COUNT_NAME_SIZE];
350
+
351
+
slice_ctr = *(ctr + counter);
352
+
slice_ctr.offset1 += offset_inc;
353
+
snprintf(cnt_name, MAX_COUNT_NAME_SIZE, "%s%d", slice_ctr.name, cnt_id);
354
+
355
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return tl_calc_and_print_counter(telemetry, s, &slice_ctr, cnt_name);
356
+
}
357
+
358
+
static int tl_calc_and_print_cmdq_counters(struct adf_accel_dev *accel_dev,
359
+
struct seq_file *s, u8 cnt_type,
360
+
u8 cnt_id)
361
+
{
362
+
struct adf_tl_hw_data *tl_data = &GET_TL_DATA(accel_dev);
363
+
struct adf_telemetry *telemetry = accel_dev->telemetry;
364
+
const struct adf_tl_dbg_counter **cmdq_tl_counters;
365
+
const struct adf_tl_dbg_counter *ctr;
366
+
u8 counter;
367
+
int ret;
368
+
369
+
cmdq_tl_counters = tl_data->cmdq_counters;
370
+
ctr = cmdq_tl_counters[cnt_type];
371
+
372
+
for (counter = 0; counter < tl_data->num_cmdq_counters; counter++) {
373
+
ret = tl_print_cmdq_counter(telemetry, ctr, s, cnt_id, counter);
374
+
if (ret) {
375
+
dev_notice(&GET_DEV(accel_dev),
376
+
"invalid slice utilization counter type\n");
377
+
return ret;
378
+
}
379
+
}
380
+
381
+
return 0;
382
+
}
383
+
342
384
static void tl_print_msg_cnt(struct seq_file *s, u32 msg_cnt)
343
385
{
344
386
seq_printf(s, "%-*s", TL_KEY_MIN_PADDING, SNAPSHOT_CNT_MSG);
···
394
352
struct adf_telemetry *telemetry = accel_dev->telemetry;
395
353
const struct adf_tl_dbg_counter *dev_tl_counters;
396
354
u8 num_dev_counters = tl_data->num_dev_counters;
355
+
u8 *cmdq_cnt = (u8 *)&telemetry->cmdq_cnt;
397
356
u8 *sl_cnt = (u8 *)&telemetry->slice_cnt;
398
357
const struct adf_tl_dbg_counter *ctr;
399
358
unsigned int i;
···
425
382
for (i = 0; i < ADF_TL_SL_CNT_COUNT; i++) {
426
383
for (j = 0; j < sl_cnt[i]; j++) {
427
384
ret = tl_calc_and_print_sl_counters(accel_dev, s, i, j);
385
+
if (ret)
386
+
return ret;
387
+
}
388
+
}
389
+
390
+
/* Print per command queue telemetry. */
391
+
for (i = 0; i < ADF_TL_SL_CNT_COUNT; i++) {
392
+
for (j = 0; j < cmdq_cnt[i]; j++) {
393
+
ret = tl_calc_and_print_cmdq_counters(accel_dev, s, i, j);
428
394
if (ret)
429
395
return ret;
430
396
}
+4
drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h
+4
drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h
···
44
44
(ADF_TL_DEV_REG_OFF(slice##_slices[0], qat_gen) + \
45
45
offsetof(struct adf_##qat_gen##_tl_slice_data_regs, reg))
46
46
47
+
#define ADF_TL_CMDQ_REG_OFF(slice, reg, qat_gen) \
48
+
(ADF_TL_DEV_REG_OFF(slice##_cmdq[0], qat_gen) + \
49
+
offsetof(struct adf_##qat_gen##_tl_cmdq_data_regs, reg))
50
+
47
51
#define ADF_TL_RP_REG_OFF(reg, qat_gen) \
48
52
(ADF_TL_DATA_REG_OFF(tl_ring_pairs_data_regs[0], qat_gen) + \
49
53
offsetof(struct adf_##qat_gen##_tl_ring_pair_data_regs, reg))