tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc architecture fixes from Helge Deller:

- Fix a bug in the C code which calculates the relevant futex spinlock
based on the futex virtual address. In some cases a wrong spinlock
(compared to what is calculated in the assembly code path) was
choosen which then can lead to deadlocks.

- The 64-bit kernel missed to clip the LWS number in the
Light-weight-syscall path for 32-bit processes.

- Prevent CPU register dump to show stale value in IIR register on
access rights traps.

- Remove unused ARCH_DEFCONFIG entries.

* tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: remove ARCH_DEFCONFIG
parisc: Fix mask used to select futex spinlock
parisc: Correct completer in lws start
parisc: Clear stale IIR value on instruction access rights trap

Linus Torvalds 3f066e88 07400405

+5 -8
-5
arch/parisc/Kconfig
··· 85 85 config STACK_GROWSUP 86 86 def_bool y 87 87 88 - config ARCH_DEFCONFIG 89 - string 90 - default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT 91 - default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT 92 - 93 88 config GENERIC_LOCKBREAK 94 89 bool 95 90 default y
+2 -2
arch/parisc/include/asm/futex.h
··· 14 14 _futex_spin_lock(u32 __user *uaddr) 15 15 { 16 16 extern u32 lws_lock_start[]; 17 - long index = ((long)uaddr & 0x3f8) >> 1; 17 + long index = ((long)uaddr & 0x7f8) >> 1; 18 18 arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; 19 19 preempt_disable(); 20 20 arch_spin_lock(s); ··· 24 24 _futex_spin_unlock(u32 __user *uaddr) 25 25 { 26 26 extern u32 lws_lock_start[]; 27 - long index = ((long)uaddr & 0x3f8) >> 1; 27 + long index = ((long)uaddr & 0x7f8) >> 1; 28 28 arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; 29 29 arch_spin_unlock(s); 30 30 preempt_enable();
+1 -1
arch/parisc/kernel/syscall.S
··· 472 472 extrd,u %r1,PSW_W_BIT,1,%r1 473 473 /* sp must be aligned on 4, so deposit the W bit setting into 474 474 * the bottom of sp temporarily */ 475 - or,ev %r1,%r30,%r30 475 + or,od %r1,%r30,%r30 476 476 477 477 /* Clip LWS number to a 32-bit value for 32-bit processes */ 478 478 depdi 0, 31, 32, %r20
+2
arch/parisc/kernel/traps.c
··· 730 730 } 731 731 mmap_read_unlock(current->mm); 732 732 } 733 + /* CPU could not fetch instruction, so clear stale IIR value. */ 734 + regs->iir = 0xbaadf00d; 733 735 fallthrough; 734 736 case 27: 735 737 /* Data memory protection ID trap */