tjh.dev / kernel
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clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent

Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF
clock: this is required to trigger clock source selection on
CLK_TOP_EDP, while avoiding to manage the enablement of the former
separately from the latter in the displayport driver.

Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Link: https://lore.kernel.org/r/20220816193257.658487-2-nfraprado@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd 3f0dadd2 568035b0

+6 -1
+6 -1
drivers/clk/mediatek/clk-mt8195-vdo0.c
··· 37 37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \ 38 38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 39 39 40 + #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ 41 + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ 42 + &mtk_clk_gate_ops_setclr, _flags) 43 + 40 44 static const struct mtk_gate vdo0_clks[] = { 41 45 /* VDO0_0 */ 42 46 GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), ··· 89 85 /* VDO0_2 */ 90 86 GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), 91 87 GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), 92 - GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16), 88 + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", 89 + "top_edp", 16, CLK_SET_RATE_PARENT), 93 90 }; 94 91 95 92 static int clk_mt8195_vdo0_probe(struct platform_device *pdev)