Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: ad7768-1: convert driver to use regmap
Convert the AD7768-1 driver to use the regmap API for register
access. This change simplifies and standardizes register interactions,
reducing code duplication and improving maintainability.
Create two regmap configurations, one for 8-bit register values and
other for 24-bit register values.
Since we are using regmap now, define the remaining registers from 0x32
to 0x34.
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Link: https://patch.msgid.link/aec9e5452c1ac16d5379a80dfce97c00d85614a2.1744325346.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Jonathan Santos
and committed by
Jonathan Cameron
3f4bc0b1
e5cdb098
+110
-51
+1
drivers/iio/adc/Kconfig
+1
drivers/iio/adc/Kconfig
+109
-51
drivers/iio/adc/ad7768-1.c
+109
-51
drivers/iio/adc/ad7768-1.c
···
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12
#include <linux/gpio/consumer.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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+
#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/sysfs.h>
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#include <linux/spi/spi.h>
···
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#define AD7768_REG_SPI_DIAG_ENABLE 0x28
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#define AD7768_REG_ADC_DIAG_ENABLE 0x29
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#define AD7768_REG_DIG_DIAG_ENABLE 0x2A
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-
#define AD7768_REG_ADC_DATA 0x2C
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#define AD7768_REG24_ADC_DATA 0x2C
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#define AD7768_REG_MASTER_STATUS 0x2D
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#define AD7768_REG_SPI_DIAG_STATUS 0x2E
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#define AD7768_REG_ADC_DIAG_STATUS 0x2F
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#define AD7768_REG_DIG_DIAG_STATUS 0x30
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#define AD7768_REG_MCLK_COUNTER 0x31
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#define AD7768_REG_COEFF_CONTROL 0x32
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#define AD7768_REG24_COEFF_DATA 0x33
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#define AD7768_REG_ACCESS_KEY 0x34
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/* AD7768_REG_POWER_CLOCK */
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#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
···
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/* AD7768_REG_CONVERSION */
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#define AD7768_CONV_MODE_MSK GENMASK(2, 0)
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#define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
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-
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#define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
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#define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
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enum ad7768_conv_mode {
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AD7768_CONTINUOUS,
···
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struct ad7768_state {
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struct spi_device *spi;
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struct regmap *regmap;
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struct regmap *regmap24;
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struct regulator *vref;
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struct clk *mclk;
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unsigned int mclk_freq;
···
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} data __aligned(IIO_DMA_MINALIGN);
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};
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-
static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
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-
unsigned int len)
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{
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unsigned int shift;
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int ret;
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static const struct regmap_range ad7768_regmap_rd_ranges[] = {
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regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE),
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regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
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regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H),
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regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO),
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regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
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regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL),
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regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
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};
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shift = 32 - (8 * len);
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st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
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static const struct regmap_access_table ad7768_regmap_rd_table = {
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.yes_ranges = ad7768_regmap_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges),
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};
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-
ret = spi_write_then_read(st->spi, st->data.d8, 1,
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&st->data.d32, len);
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if (ret < 0)
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return ret;
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static const struct regmap_range ad7768_regmap_wr_ranges[] = {
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regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
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regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE),
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regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO),
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regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
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regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS),
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regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL),
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regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
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};
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return (be32_to_cpu(st->data.d32) >> shift);
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-
}
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static const struct regmap_access_table ad7768_regmap_wr_table = {
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.yes_ranges = ad7768_regmap_wr_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges),
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};
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-
static int ad7768_spi_reg_write(struct ad7768_state *st,
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unsigned int addr,
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unsigned int val)
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{
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st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
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st->data.d8[1] = val & 0xFF;
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static const struct regmap_config ad7768_regmap_config = {
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.name = "ad7768-1-8",
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.reg_bits = 8,
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.val_bits = 8,
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.read_flag_mask = BIT(6),
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.rd_table = &ad7768_regmap_rd_table,
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.wr_table = &ad7768_regmap_wr_table,
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.max_register = AD7768_REG_ACCESS_KEY,
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.use_single_write = true,
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.use_single_read = true,
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};
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-
return spi_write(st->spi, st->data.d8, 2);
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-
}
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static const struct regmap_range ad7768_regmap24_rd_ranges[] = {
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regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA),
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regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
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};
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static const struct regmap_access_table ad7768_regmap24_rd_table = {
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.yes_ranges = ad7768_regmap24_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges),
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};
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static const struct regmap_range ad7768_regmap24_wr_ranges[] = {
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regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
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};
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+
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static const struct regmap_access_table ad7768_regmap24_wr_table = {
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.yes_ranges = ad7768_regmap24_wr_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges),
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};
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static const struct regmap_config ad7768_regmap24_config = {
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.name = "ad7768-1-24",
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.reg_bits = 8,
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.val_bits = 24,
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.read_flag_mask = BIT(6),
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.rd_table = &ad7768_regmap24_rd_table,
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.wr_table = &ad7768_regmap24_wr_table,
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.max_register = AD7768_REG24_COEFF_DATA,
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};
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static int ad7768_set_mode(struct ad7768_state *st,
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enum ad7768_conv_mode mode)
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{
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int regval;
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regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
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if (regval < 0)
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return regval;
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regval &= ~AD7768_CONV_MODE_MSK;
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regval |= AD7768_CONV_MODE(mode);
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return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
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return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION,
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AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode));
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}
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static int ad7768_scan_direct(struct iio_dev *indio_dev)
···
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if (!ret)
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return -ETIMEDOUT;
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readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
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-
if (readval < 0)
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return readval;
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ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval);
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if (ret)
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return ret;
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+
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/*
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* Any SPI configuration of the AD7768-1 can only be
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* performed in continuous conversion mode.
···
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if (!iio_device_claim_direct(indio_dev))
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return -EBUSY;
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ret = -EINVAL;
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if (readval) {
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ret = ad7768_spi_reg_read(st, reg, 1);
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-
if (ret < 0)
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goto err_release;
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*readval = ret;
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ret = 0;
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if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table))
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ret = regmap_read(st->regmap, reg, readval);
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if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table))
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ret = regmap_read(st->regmap24, reg, readval);
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} else {
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ret = ad7768_spi_reg_write(st, reg, writeval);
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if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table))
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ret = regmap_write(st->regmap, reg, writeval);
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+
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if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table))
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ret = regmap_write(st->regmap24, reg, writeval);
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+
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}
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err_release:
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iio_device_release_direct(indio_dev);
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return ret;
···
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else
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mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
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ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
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ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode);
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if (ret < 0)
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return ret;
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···
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*/
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pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
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AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
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ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
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ret = regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode);
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if (ret < 0)
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return ret;
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···
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* to 10. When the sequence is detected, the reset occurs.
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* See the datasheet, page 70.
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*/
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ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
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ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3);
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if (ret)
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return ret;
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ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
453
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ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2);
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if (ret)
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return ret;
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456
···
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* continuous read mode. Subsequent data reads do not require an
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* initial 8-bit write to query the ADC_DATA register.
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507
*/
555
-
return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
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return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01);
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}
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static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
559
512
{
560
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struct ad7768_state *st = iio_priv(indio_dev);
514
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unsigned int unused;
561
515
562
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/*
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* To exit continuous read mode, perform a single read of the ADC_DATA
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* reg (0x2C), which allows further configuration of the device.
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*/
566
-
return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
520
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return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused);
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}
568
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569
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static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
···
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}
635
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st->spi = spi;
589
+
590
+
st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config);
591
+
if (IS_ERR(st->regmap))
592
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return dev_err_probe(&spi->dev, PTR_ERR(st->regmap),
593
+
"Failed to initialize regmap");
594
+
595
+
st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config);
596
+
if (IS_ERR(st->regmap24))
597
+
return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24),
598
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"Failed to initialize regmap24");
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st->vref = devm_regulator_get(&spi->dev, "vref");
639
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if (IS_ERR(st->vref))