Merge tag 'counter-updates-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-next

+15 -15

MAINTAINERS

··· 210 210 F: drivers/hwmon/abituguru3.c 211 211 212 212 ACCES 104-DIO-48E GPIO DRIVER 213 - M: William Breathitt Gray <william.gray@linaro.org> 213 + M: William Breathitt Gray <wbg@kernel.org> 214 214 L: linux-gpio@vger.kernel.org 215 215 S: Maintained 216 216 F: drivers/gpio/gpio-104-dio-48e.c 217 217 218 218 ACCES 104-IDI-48 GPIO DRIVER 219 - M: William Breathitt Gray <william.gray@linaro.org> 219 + M: William Breathitt Gray <wbg@kernel.org> 220 220 L: linux-gpio@vger.kernel.org 221 221 S: Maintained 222 222 F: drivers/gpio/gpio-104-idi-48.c 223 223 224 224 ACCES 104-IDIO-16 GPIO DRIVER 225 - M: William Breathitt Gray <william.gray@linaro.org> 225 + M: William Breathitt Gray <wbg@kernel.org> 226 226 L: linux-gpio@vger.kernel.org 227 227 S: Maintained 228 228 F: drivers/gpio/gpio-104-idio-16.c 229 229 230 230 ACCES 104-QUAD-8 DRIVER 231 - M: William Breathitt Gray <william.gray@linaro.org> 231 + M: William Breathitt Gray <wbg@kernel.org> 232 232 L: linux-iio@vger.kernel.org 233 233 S: Maintained 234 234 F: drivers/counter/104-quad-8.c 235 235 236 236 ACCES IDIO-16 GPIO LIBRARY 237 - M: William Breathitt Gray <william.gray@linaro.org> 237 + M: William Breathitt Gray <wbg@kernel.org> 238 238 L: linux-gpio@vger.kernel.org 239 239 S: Maintained 240 240 F: drivers/gpio/gpio-idio-16.c 241 241 F: drivers/gpio/gpio-idio-16.h 242 242 243 243 ACCES PCI-IDIO-16 GPIO DRIVER 244 - M: William Breathitt Gray <william.gray@linaro.org> 244 + M: William Breathitt Gray <wbg@kernel.org> 245 245 L: linux-gpio@vger.kernel.org 246 246 S: Maintained 247 247 F: drivers/gpio/gpio-pci-idio-16.c 248 248 249 249 ACCES PCIe-IDIO-24 GPIO DRIVER 250 - M: William Breathitt Gray <william.gray@linaro.org> 250 + M: William Breathitt Gray <wbg@kernel.org> 251 251 L: linux-gpio@vger.kernel.org 252 252 S: Maintained 253 253 F: drivers/gpio/gpio-pcie-idio-24.c ··· 1453 1453 F: sound/aoa/ 1454 1454 1455 1455 APEX EMBEDDED SYSTEMS STX104 IIO DRIVER 1456 - M: William Breathitt Gray <william.gray@linaro.org> 1456 + M: William Breathitt Gray <wbg@kernel.org> 1457 1457 L: linux-iio@vger.kernel.org 1458 1458 S: Maintained 1459 1459 F: drivers/iio/addac/stx104.c ··· 5459 5459 F: drivers/hwmon/corsair-psu.c 5460 5460 5461 5461 COUNTER SUBSYSTEM 5462 - M: William Breathitt Gray <william.gray@linaro.org> 5462 + M: William Breathitt Gray <wbg@kernel.org> 5463 5463 L: linux-iio@vger.kernel.org 5464 5464 S: Maintained 5465 5465 T: git git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter.git ··· 6245 6245 F: sound/soc/codecs/da[79]*.[ch] 6246 6246 6247 6247 DIAMOND SYSTEMS GPIO-MM GPIO DRIVER 6248 - M: William Breathitt Gray <william.gray@linaro.org> 6248 + M: William Breathitt Gray <wbg@kernel.org> 6249 6249 L: linux-gpio@vger.kernel.org 6250 6250 S: Maintained 6251 6251 F: drivers/gpio/gpio-gpio-mm.c ··· 10756 10756 F: drivers/video/fbdev/i810/ 10757 10757 10758 10758 INTEL 8254 COUNTER DRIVER 10759 - M: William Breathitt Gray <william.gray@linaro.org> 10759 + M: William Breathitt Gray <wbg@kernel.org> 10760 10760 L: linux-iio@vger.kernel.org 10761 10761 S: Maintained 10762 10762 F: drivers/counter/i8254.c 10763 10763 F: include/linux/i8254.h 10764 10764 10765 10765 INTEL 8255 GPIO DRIVER 10766 - M: William Breathitt Gray <william.gray@linaro.org> 10766 + M: William Breathitt Gray <wbg@kernel.org> 10767 10767 L: linux-gpio@vger.kernel.org 10768 10768 S: Maintained 10769 10769 F: drivers/gpio/gpio-i8255.c ··· 11460 11460 F: drivers/irqchip/ 11461 11461 11462 11462 ISA 11463 - M: William Breathitt Gray <william.gray@linaro.org> 11463 + M: William Breathitt Gray <wbg@kernel.org> 11464 11464 S: Maintained 11465 11465 F: Documentation/driver-api/isa.rst 11466 11466 F: drivers/base/isa.c ··· 13472 13472 F: include/linux/mdio/mdio-regmap.h 13473 13473 13474 13474 MEASUREMENT COMPUTING CIO-DAC IIO DRIVER 13475 - M: William Breathitt Gray <william.gray@linaro.org> 13475 + M: William Breathitt Gray <wbg@kernel.org> 13476 13476 L: linux-iio@vger.kernel.org 13477 13477 S: Maintained 13478 13478 F: drivers/iio/dac/cio-dac.c ··· 23891 23891 F: drivers/watchdog/ebc-c384_wdt.c 23892 23892 23893 23893 WINSYSTEMS WS16C48 GPIO DRIVER 23894 - M: William Breathitt Gray <william.gray@linaro.org> 23894 + M: William Breathitt Gray <wbg@kernel.org> 23895 23895 L: linux-gpio@vger.kernel.org 23896 23896 S: Maintained 23897 23897 F: drivers/gpio/gpio-ws16c48.c

+2 -2

drivers/counter/counter-core.c

··· 49 49 kfree(container_of(counter, struct counter_device_allochelper, counter)); 50 50 } 51 51 52 - static struct device_type counter_device_type = { 52 + static const struct device_type counter_device_type = { 53 53 .name = "counter_device", 54 54 .release = counter_device_release, 55 55 }; 56 56 57 - static struct bus_type counter_bus_type = { 57 + static const struct bus_type counter_bus_type = { 58 58 .name = "counter", 59 59 .dev_name = "counter", 60 60 };

+447 -14

drivers/counter/stm32-timer-cnt.c

··· 8 8 * 9 9 */ 10 10 #include <linux/counter.h> 11 + #include <linux/interrupt.h> 11 12 #include <linux/mfd/stm32-timers.h> 12 13 #include <linux/mod_devicetable.h> 13 14 #include <linux/module.h> 15 + #include <linux/of.h> 14 16 #include <linux/pinctrl/consumer.h> 15 17 #include <linux/platform_device.h> 16 18 #include <linux/types.h> ··· 22 20 TIM_CCMR_IC1F | TIM_CCMR_IC2F) 23 21 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ 24 22 TIM_CCER_CC2P | TIM_CCER_CC2NP) 23 + 24 + #define STM32_CH1_SIG 0 25 + #define STM32_CH2_SIG 1 26 + #define STM32_CLOCK_SIG 2 27 + #define STM32_CH3_SIG 3 28 + #define STM32_CH4_SIG 4 25 29 26 30 struct stm32_timer_regs { 27 31 u32 cr1; ··· 42 34 u32 max_arr; 43 35 bool enabled; 44 36 struct stm32_timer_regs bak; 37 + bool has_encoder; 38 + unsigned int nchannels; 39 + unsigned int nr_irqs; 40 + spinlock_t lock; /* protects nb_ovf */ 41 + u64 nb_ovf; 45 42 }; 46 43 47 44 static const enum counter_function stm32_count_functions[] = { ··· 120 107 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; 121 108 break; 122 109 case COUNTER_FUNCTION_QUADRATURE_X2_A: 110 + if (!priv->has_encoder) 111 + return -EOPNOTSUPP; 123 112 sms = TIM_SMCR_SMS_ENCODER_MODE_1; 124 113 break; 125 114 case COUNTER_FUNCTION_QUADRATURE_X2_B: 115 + if (!priv->has_encoder) 116 + return -EOPNOTSUPP; 126 117 sms = TIM_SMCR_SMS_ENCODER_MODE_2; 127 118 break; 128 119 case COUNTER_FUNCTION_QUADRATURE_X4: 120 + if (!priv->has_encoder) 121 + return -EOPNOTSUPP; 129 122 sms = TIM_SMCR_SMS_ENCODER_MODE_3; 130 123 break; 131 124 default: ··· 235 216 return 0; 236 217 } 237 218 219 + static int stm32_count_prescaler_read(struct counter_device *counter, 220 + struct counter_count *count, u64 *prescaler) 221 + { 222 + struct stm32_timer_cnt *const priv = counter_priv(counter); 223 + u32 psc; 224 + 225 + regmap_read(priv->regmap, TIM_PSC, &psc); 226 + 227 + *prescaler = psc + 1; 228 + 229 + return 0; 230 + } 231 + 232 + static int stm32_count_prescaler_write(struct counter_device *counter, 233 + struct counter_count *count, u64 prescaler) 234 + { 235 + struct stm32_timer_cnt *const priv = counter_priv(counter); 236 + u32 psc; 237 + 238 + if (!prescaler || prescaler > MAX_TIM_PSC + 1) 239 + return -ERANGE; 240 + 241 + psc = prescaler - 1; 242 + 243 + return regmap_write(priv->regmap, TIM_PSC, psc); 244 + } 245 + 246 + static int stm32_count_cap_read(struct counter_device *counter, 247 + struct counter_count *count, 248 + size_t ch, u64 *cap) 249 + { 250 + struct stm32_timer_cnt *const priv = counter_priv(counter); 251 + u32 ccrx; 252 + 253 + if (ch >= priv->nchannels) 254 + return -EOPNOTSUPP; 255 + 256 + switch (ch) { 257 + case 0: 258 + regmap_read(priv->regmap, TIM_CCR1, &ccrx); 259 + break; 260 + case 1: 261 + regmap_read(priv->regmap, TIM_CCR2, &ccrx); 262 + break; 263 + case 2: 264 + regmap_read(priv->regmap, TIM_CCR3, &ccrx); 265 + break; 266 + case 3: 267 + regmap_read(priv->regmap, TIM_CCR4, &ccrx); 268 + break; 269 + default: 270 + return -EINVAL; 271 + } 272 + 273 + dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx); 274 + 275 + *cap = ccrx; 276 + 277 + return 0; 278 + } 279 + 280 + static int stm32_count_nb_ovf_read(struct counter_device *counter, 281 + struct counter_count *count, u64 *val) 282 + { 283 + struct stm32_timer_cnt *const priv = counter_priv(counter); 284 + unsigned long irqflags; 285 + 286 + spin_lock_irqsave(&priv->lock, irqflags); 287 + *val = priv->nb_ovf; 288 + spin_unlock_irqrestore(&priv->lock, irqflags); 289 + 290 + return 0; 291 + } 292 + 293 + static int stm32_count_nb_ovf_write(struct counter_device *counter, 294 + struct counter_count *count, u64 val) 295 + { 296 + struct stm32_timer_cnt *const priv = counter_priv(counter); 297 + unsigned long irqflags; 298 + 299 + spin_lock_irqsave(&priv->lock, irqflags); 300 + priv->nb_ovf = val; 301 + spin_unlock_irqrestore(&priv->lock, irqflags); 302 + 303 + return 0; 304 + } 305 + 306 + static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4); 307 + 238 308 static struct counter_comp stm32_count_ext[] = { 239 309 COUNTER_COMP_DIRECTION(stm32_count_direction_read), 240 310 COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), 241 311 COUNTER_COMP_CEILING(stm32_count_ceiling_read, 242 312 stm32_count_ceiling_write), 313 + COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, 314 + stm32_count_prescaler_write), 315 + COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array), 316 + COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), 317 + }; 318 + 319 + static const enum counter_synapse_action stm32_clock_synapse_actions[] = { 320 + COUNTER_SYNAPSE_ACTION_RISING_EDGE, 243 321 }; 244 322 245 323 static const enum counter_synapse_action stm32_synapse_actions[] = { ··· 359 243 switch (function) { 360 244 case COUNTER_FUNCTION_INCREASE: 361 245 /* counts on internal clock when CEN=1 */ 362 - *action = COUNTER_SYNAPSE_ACTION_NONE; 246 + if (synapse->signal->id == STM32_CLOCK_SIG) 247 + *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 248 + else 249 + *action = COUNTER_SYNAPSE_ACTION_NONE; 363 250 return 0; 364 251 case COUNTER_FUNCTION_QUADRATURE_X2_A: 365 252 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ 366 - if (synapse->signal->id == count->synapses[0].signal->id) 253 + if (synapse->signal->id == STM32_CH1_SIG) 367 254 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 368 255 else 369 256 *action = COUNTER_SYNAPSE_ACTION_NONE; 370 257 return 0; 371 258 case COUNTER_FUNCTION_QUADRATURE_X2_B: 372 259 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ 373 - if (synapse->signal->id == count->synapses[1].signal->id) 260 + if (synapse->signal->id == STM32_CH2_SIG) 374 261 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 375 262 else 376 263 *action = COUNTER_SYNAPSE_ACTION_NONE; 377 264 return 0; 378 265 case COUNTER_FUNCTION_QUADRATURE_X4: 379 266 /* counts up/down on both TI1FP1 and TI2FP2 edges */ 380 - *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 267 + if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG) 268 + *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 269 + else 270 + *action = COUNTER_SYNAPSE_ACTION_NONE; 271 + return 0; 272 + default: 273 + return -EINVAL; 274 + } 275 + } 276 + 277 + struct stm32_count_cc_regs { 278 + u32 ccmr_reg; 279 + u32 ccmr_mask; 280 + u32 ccmr_bits; 281 + u32 ccer_bits; 282 + }; 283 + 284 + static const struct stm32_count_cc_regs stm32_cc[] = { 285 + { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1, 286 + TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP }, 287 + { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2, 288 + TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP }, 289 + { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3, 290 + TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP }, 291 + { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4, 292 + TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP }, 293 + }; 294 + 295 + static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch, 296 + bool enable) 297 + { 298 + struct stm32_timer_cnt *const priv = counter_priv(counter); 299 + const struct stm32_count_cc_regs *cc; 300 + u32 ccmr, ccer; 301 + 302 + if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) { 303 + dev_err(counter->parent, "invalid ch: %d\n", ch); 304 + return -EINVAL; 305 + } 306 + 307 + cc = &stm32_cc[ch]; 308 + 309 + /* 310 + * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2... 311 + * Select both edges / non-inverted to trigger a capture. 312 + */ 313 + if (enable) { 314 + /* first clear possibly latched capture flag upon enabling */ 315 + if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits)) 316 + regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch)); 317 + regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask, 318 + cc->ccmr_bits); 319 + regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits); 320 + } else { 321 + regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits); 322 + regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask); 323 + } 324 + 325 + regmap_read(priv->regmap, cc->ccmr_reg, &ccmr); 326 + regmap_read(priv->regmap, TIM_CCER, &ccer); 327 + dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis", 328 + ch, ccmr, ccer); 329 + 330 + return 0; 331 + } 332 + 333 + static int stm32_count_events_configure(struct counter_device *counter) 334 + { 335 + struct stm32_timer_cnt *const priv = counter_priv(counter); 336 + struct counter_event_node *event_node; 337 + u32 dier = 0; 338 + int i, ret; 339 + 340 + list_for_each_entry(event_node, &counter->events_list, l) { 341 + switch (event_node->event) { 342 + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 343 + /* first clear possibly latched UIF before enabling */ 344 + if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE)) 345 + regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); 346 + dier |= TIM_DIER_UIE; 347 + break; 348 + case COUNTER_EVENT_CAPTURE: 349 + ret = stm32_count_capture_configure(counter, event_node->channel, true); 350 + if (ret) 351 + return ret; 352 + dier |= TIM_DIER_CC_IE(event_node->channel); 353 + break; 354 + default: 355 + /* should never reach this path */ 356 + return -EINVAL; 357 + } 358 + } 359 + 360 + /* Enable / disable all events at once, from events_list, so write all DIER bits */ 361 + regmap_write(priv->regmap, TIM_DIER, dier); 362 + 363 + /* check for disabled capture events */ 364 + for (i = 0 ; i < priv->nchannels; i++) { 365 + if (!(dier & TIM_DIER_CC_IE(i))) { 366 + ret = stm32_count_capture_configure(counter, i, false); 367 + if (ret) 368 + return ret; 369 + } 370 + } 371 + 372 + return 0; 373 + } 374 + 375 + static int stm32_count_watch_validate(struct counter_device *counter, 376 + const struct counter_watch *watch) 377 + { 378 + struct stm32_timer_cnt *const priv = counter_priv(counter); 379 + 380 + /* Interrupts are optional */ 381 + if (!priv->nr_irqs) 382 + return -EOPNOTSUPP; 383 + 384 + switch (watch->event) { 385 + case COUNTER_EVENT_CAPTURE: 386 + if (watch->channel >= priv->nchannels) { 387 + dev_err(counter->parent, "Invalid channel %d\n", watch->channel); 388 + return -EINVAL; 389 + } 390 + return 0; 391 + case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 381 392 return 0; 382 393 default: 383 394 return -EINVAL; ··· 517 274 .function_read = stm32_count_function_read, 518 275 .function_write = stm32_count_function_write, 519 276 .action_read = stm32_action_read, 277 + .events_configure = stm32_count_events_configure, 278 + .watch_validate = stm32_count_watch_validate, 279 + }; 280 + 281 + static int stm32_count_clk_get_freq(struct counter_device *counter, 282 + struct counter_signal *signal, u64 *freq) 283 + { 284 + struct stm32_timer_cnt *const priv = counter_priv(counter); 285 + 286 + *freq = clk_get_rate(priv->clk); 287 + 288 + return 0; 289 + } 290 + 291 + static struct counter_comp stm32_count_clock_ext[] = { 292 + COUNTER_COMP_FREQUENCY(stm32_count_clk_get_freq), 520 293 }; 521 294 522 295 static struct counter_signal stm32_signals[] = { 296 + /* 297 + * Need to declare all the signals as a static array, and keep the signals order here, 298 + * even if they're unused or unexisting on some timer instances. It's an abstraction, 299 + * e.g. high level view of the counter features. 300 + * 301 + * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2", 302 + * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used, 303 + * to indicate that a signal doesn't affect the counter. 304 + */ 523 305 { 524 - .id = 0, 525 - .name = "Channel 1 Quadrature A" 306 + .id = STM32_CH1_SIG, 307 + .name = "Channel 1" 526 308 }, 527 309 { 528 - .id = 1, 529 - .name = "Channel 1 Quadrature B" 530 - } 310 + .id = STM32_CH2_SIG, 311 + .name = "Channel 2" 312 + }, 313 + { 314 + .id = STM32_CLOCK_SIG, 315 + .name = "Clock", 316 + .ext = stm32_count_clock_ext, 317 + .num_ext = ARRAY_SIZE(stm32_count_clock_ext), 318 + }, 319 + { 320 + .id = STM32_CH3_SIG, 321 + .name = "Channel 3" 322 + }, 323 + { 324 + .id = STM32_CH4_SIG, 325 + .name = "Channel 4" 326 + }, 531 327 }; 532 328 533 329 static struct counter_synapse stm32_count_synapses[] = { 534 330 { 535 331 .actions_list = stm32_synapse_actions, 536 332 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 537 - .signal = &stm32_signals[0] 333 + .signal = &stm32_signals[STM32_CH1_SIG] 538 334 }, 539 335 { 540 336 .actions_list = stm32_synapse_actions, 541 337 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 542 - .signal = &stm32_signals[1] 543 - } 338 + .signal = &stm32_signals[STM32_CH2_SIG] 339 + }, 340 + { 341 + .actions_list = stm32_clock_synapse_actions, 342 + .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), 343 + .signal = &stm32_signals[STM32_CLOCK_SIG] 344 + }, 345 + { 346 + .actions_list = stm32_synapse_actions, 347 + .num_actions = ARRAY_SIZE(stm32_synapse_actions), 348 + .signal = &stm32_signals[STM32_CH3_SIG] 349 + }, 350 + { 351 + .actions_list = stm32_synapse_actions, 352 + .num_actions = ARRAY_SIZE(stm32_synapse_actions), 353 + .signal = &stm32_signals[STM32_CH4_SIG] 354 + }, 544 355 }; 545 356 546 357 static struct counter_count stm32_counts = { 547 358 .id = 0, 548 - .name = "Channel 1 Count", 359 + .name = "STM32 Timer Counter", 549 360 .functions_list = stm32_count_functions, 550 361 .num_functions = ARRAY_SIZE(stm32_count_functions), 551 362 .synapses = stm32_count_synapses, ··· 608 311 .num_ext = ARRAY_SIZE(stm32_count_ext) 609 312 }; 610 313 314 + static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) 315 + { 316 + struct counter_device *counter = ptr; 317 + struct stm32_timer_cnt *const priv = counter_priv(counter); 318 + u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ 319 + u32 sr, dier; 320 + int i; 321 + 322 + regmap_read(priv->regmap, TIM_SR, &sr); 323 + regmap_read(priv->regmap, TIM_DIER, &dier); 324 + /* 325 + * Some status bits in SR don't match with the enable bits in DIER. Only take care of 326 + * the possibly enabled bits in DIER (that matches in between SR and DIER). 327 + */ 328 + dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); 329 + sr &= dier; 330 + 331 + if (sr & TIM_SR_UIF) { 332 + spin_lock(&priv->lock); 333 + priv->nb_ovf++; 334 + spin_unlock(&priv->lock); 335 + counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0); 336 + dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n"); 337 + /* SR flags can be cleared by writing 0, only clear relevant flag */ 338 + clr &= ~TIM_SR_UIF; 339 + } 340 + 341 + /* Check capture events */ 342 + for (i = 0 ; i < priv->nchannels; i++) { 343 + if (sr & TIM_SR_CC_IF(i)) { 344 + counter_push_event(counter, COUNTER_EVENT_CAPTURE, i); 345 + clr &= ~TIM_SR_CC_IF(i); 346 + dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i); 347 + } 348 + } 349 + 350 + regmap_write(priv->regmap, TIM_SR, clr); 351 + 352 + return IRQ_HANDLED; 353 + }; 354 + 355 + static void stm32_timer_cnt_detect_channels(struct device *dev, 356 + struct stm32_timer_cnt *priv) 357 + { 358 + u32 ccer, ccer_backup; 359 + 360 + regmap_read(priv->regmap, TIM_CCER, &ccer_backup); 361 + regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); 362 + regmap_read(priv->regmap, TIM_CCER, &ccer); 363 + regmap_write(priv->regmap, TIM_CCER, ccer_backup); 364 + priv->nchannels = hweight32(ccer & TIM_CCER_CCXE); 365 + 366 + dev_dbg(dev, "has %d cc channels\n", priv->nchannels); 367 + } 368 + 369 + /* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */ 370 + #define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7)) 371 + 372 + static const char * const stm32_timer_trigger_compat[] = { 373 + "st,stm32-timer-trigger", 374 + "st,stm32h7-timer-trigger", 375 + }; 376 + 377 + static int stm32_timer_cnt_probe_encoder(struct device *dev, 378 + struct stm32_timer_cnt *priv) 379 + { 380 + struct device *parent = dev->parent; 381 + struct device_node *tnode = NULL, *pnode = parent->of_node; 382 + int i, ret; 383 + u32 idx; 384 + 385 + /* 386 + * Need to retrieve the trigger node index from DT, to be able 387 + * to determine if the counter supports encoder mode. It also 388 + * enforce backward compatibility, and allow to support other 389 + * counter modes in this driver (when the timer doesn't support 390 + * encoder). 391 + */ 392 + for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++) 393 + tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]); 394 + if (!tnode) { 395 + dev_err(dev, "Can't find trigger node\n"); 396 + return -ENODATA; 397 + } 398 + 399 + ret = of_property_read_u32(tnode, "reg", &idx); 400 + if (ret) { 401 + dev_err(dev, "Can't get index (%d)\n", ret); 402 + return ret; 403 + } 404 + 405 + priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx)); 406 + 407 + dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no"); 408 + 409 + return 0; 410 + } 411 + 611 412 static int stm32_timer_cnt_probe(struct platform_device *pdev) 612 413 { 613 414 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 614 415 struct device *dev = &pdev->dev; 615 416 struct stm32_timer_cnt *priv; 616 417 struct counter_device *counter; 617 - int ret; 418 + int i, ret; 618 419 619 420 if (IS_ERR_OR_NULL(ddata)) 620 421 return -EINVAL; ··· 726 331 priv->regmap = ddata->regmap; 727 332 priv->clk = ddata->clk; 728 333 priv->max_arr = ddata->max_arr; 334 + priv->nr_irqs = ddata->nr_irqs; 335 + 336 + ret = stm32_timer_cnt_probe_encoder(dev, priv); 337 + if (ret) 338 + return ret; 339 + 340 + stm32_timer_cnt_detect_channels(dev, priv); 729 341 730 342 counter->name = dev_name(dev); 731 343 counter->parent = dev; ··· 742 340 counter->signals = stm32_signals; 743 341 counter->num_signals = ARRAY_SIZE(stm32_signals); 744 342 343 + spin_lock_init(&priv->lock); 344 + 745 345 platform_set_drvdata(pdev, priv); 346 + 347 + /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */ 348 + if (priv->nr_irqs == 1) { 349 + /* All events reported through the global interrupt */ 350 + ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr, 351 + 0, dev_name(dev), counter); 352 + if (ret) { 353 + dev_err(dev, "Failed to request irq %d (err %d)\n", 354 + ddata->irq[0], ret); 355 + return ret; 356 + } 357 + } else { 358 + for (i = 0; i < priv->nr_irqs; i++) { 359 + /* 360 + * Only take care of update IRQ for overflow events, and cc for 361 + * capture events. 362 + */ 363 + if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC) 364 + continue; 365 + 366 + ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr, 367 + 0, dev_name(dev), counter); 368 + if (ret) { 369 + dev_err(dev, "Failed to request irq %d (err %d)\n", 370 + ddata->irq[i], ret); 371 + return ret; 372 + } 373 + } 374 + } 746 375 747 376 /* Reset input selector to its default input */ 748 377 regmap_write(priv->regmap, TIM_TISEL, 0x0);

+3 -5

drivers/counter/ti-ecap-capture.c

··· 369 369 }; 370 370 371 371 static struct counter_comp ecap_cnt_clock_ext[] = { 372 - COUNTER_COMP_SIGNAL_U64("frequency", ecap_cnt_clk_get_freq, NULL), 372 + COUNTER_COMP_FREQUENCY(ecap_cnt_clk_get_freq), 373 373 }; 374 374 375 375 static const enum counter_signal_polarity ecap_cnt_pol_avail[] = { ··· 537 537 return 0; 538 538 } 539 539 540 - static int ecap_cnt_remove(struct platform_device *pdev) 540 + static void ecap_cnt_remove(struct platform_device *pdev) 541 541 { 542 542 struct counter_device *counter_dev = platform_get_drvdata(pdev); 543 543 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 544 544 545 545 if (ecap_dev->enabled) 546 546 ecap_cnt_capture_disable(counter_dev); 547 - 548 - return 0; 549 547 } 550 548 551 549 static int ecap_cnt_suspend(struct device *dev) ··· 598 600 599 601 static struct platform_driver ecap_cnt_driver = { 600 602 .probe = ecap_cnt_probe, 601 - .remove = ecap_cnt_remove, 603 + .remove_new = ecap_cnt_remove, 602 604 .driver = { 603 605 .name = "ecap-capture", 604 606 .of_match_table = ecap_cnt_of_match,

+2 -4

drivers/counter/ti-eqep.c

··· 425 425 return 0; 426 426 } 427 427 428 - static int ti_eqep_remove(struct platform_device *pdev) 428 + static void ti_eqep_remove(struct platform_device *pdev) 429 429 { 430 430 struct counter_device *counter = platform_get_drvdata(pdev); 431 431 struct device *dev = &pdev->dev; ··· 433 433 counter_unregister(counter); 434 434 pm_runtime_put_sync(dev); 435 435 pm_runtime_disable(dev); 436 - 437 - return 0; 438 436 } 439 437 440 438 static const struct of_device_id ti_eqep_of_match[] = { ··· 443 445 444 446 static struct platform_driver ti_eqep_driver = { 445 447 .probe = ti_eqep_probe, 446 - .remove = ti_eqep_remove, 448 + .remove_new = ti_eqep_remove, 447 449 .driver = { 448 450 .name = "ti-eqep-cnt", 449 451 .of_match_table = ti_eqep_of_match,

+3 -1

include/linux/counter.h

··· 359 359 * @num_counts: number of Counts specified in @counts 360 360 * @ext: optional array of Counter device extensions 361 361 * @num_ext: number of Counter device extensions specified in @ext 362 - * @priv: optional private data supplied by driver 363 362 * @dev: internal device structure 364 363 * @chrdev: internal character device structure 365 364 * @events_list: list of current watching Counter events ··· 600 601 601 602 #define COUNTER_COMP_FLOOR(_read, _write) \ 602 603 COUNTER_COMP_COUNT_U64("floor", _read, _write) 604 + 605 + #define COUNTER_COMP_FREQUENCY(_read) \ 606 + COUNTER_COMP_SIGNAL_U64("frequency", _read, NULL) 603 607 604 608 #define COUNTER_COMP_POLARITY(_read, _write, _available) \ 605 609 { \

+13

include/linux/mfd/stm32-timers.h

··· 41 41 #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ 42 42 #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ 43 43 #define TIM_DIER_UIE BIT(0) /* Update interrupt */ 44 + #define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ 45 + #define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ 46 + #define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ 47 + #define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ 48 + #define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ 44 49 #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ 45 50 #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ 46 51 #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ ··· 54 49 #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ 55 50 #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ 56 51 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ 52 + #define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ 57 53 #define TIM_EGR_UG BIT(0) /* Update Generation */ 58 54 #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ 59 55 #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ ··· 66 60 #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ 67 61 #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ 68 62 #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ 63 + #define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ 64 + #define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ 65 + #define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ 66 + #define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ 69 67 #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ 70 68 #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ 71 69 #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ 72 70 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ 73 71 #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ 74 72 #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ 73 + #define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ 75 74 #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ 76 75 #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ 76 + #define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ 77 77 #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ 78 78 #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ 79 + #define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ 79 80 #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) 80 81 #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ 81 82 #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */

Configure Feed

Configure Feed