Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New Support:
- Qualcomm Eliza QMP UFS PHY
- Canaan K230 USB 2.0 PHY driver
- Mediatek mt8167 dsi-phy
- Eswin EIC7700 SATA PHY driver
Updates:
- Sorted subsytem Makefile/Kconfig and some kernel-doc udpates"
* tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY
phy: qcom: m31-eusb2: clear PLL_EN during init
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: apple: apple: Use local variable for ioremap return value
phy: qcom: qmp-usbc: Simplify check for non-NULL pointer
phy: marvell: mmp3-hsic: Avoid re-casting __iomem
phy: apple: atc: Make atcphy_dwc3_reset_ops variable static
dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
phy: usb: Add driver for Canaan K230 USB 2.0 PHY
dt-bindings: phy: Add Canaan K230 USB PHY
phy: phy-mtk-tphy: Update names and format of kernel-doc comments
phy: Sort the subsystem Kconfig
phy: Sort the subsystem Makefile
phy: move spacemit pcie driver to its subfolder
+816
-81
+35
Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
+35
Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Canaan K230 USB2.0 PHY
8
+
9
+
maintainers:
10
+
- Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
11
+
12
+
properties:
13
+
compatible:
14
+
const: canaan,k230-usb-phy
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
"#phy-cells":
20
+
const: 1
21
+
22
+
required:
23
+
- compatible
24
+
- reg
25
+
- "#phy-cells"
26
+
27
+
additionalProperties: false
28
+
29
+
examples:
30
+
- |
31
+
usbphy: usb-phy@91585000 {
32
+
compatible = "canaan,k230-usb-phy";
33
+
reg = <0x91585000 0x400>;
34
+
#phy-cells = <1>;
35
+
};
+92
Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
+92
Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Eswin EIC7700 SoC SATA PHY
8
+
9
+
maintainers:
10
+
- Yulin Lu <luyulin@eswincomputing.com>
11
+
- Huan He <hehuan1@eswincomputing.com>
12
+
13
+
properties:
14
+
compatible:
15
+
const: eswin,eic7700-sata-phy
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
clocks:
21
+
maxItems: 1
22
+
23
+
clock-names:
24
+
const: phy
25
+
26
+
resets:
27
+
maxItems: 2
28
+
29
+
reset-names:
30
+
items:
31
+
- const: port
32
+
- const: phy
33
+
34
+
eswin,tx-amplitude-tuning:
35
+
description: This adjusts the transmitter amplitude signal, and its value
36
+
is derived from eye diagram tuning. The three values correspond to Gen1,
37
+
Gen2, and Gen3 parameters respectively.
38
+
$ref: /schemas/types.yaml#/definitions/uint32-array
39
+
items:
40
+
- description: Gen1 parameter.
41
+
minimum: 0
42
+
maximum: 0x7f
43
+
- description: Gen2 parameter.
44
+
minimum: 0
45
+
maximum: 0x7f
46
+
- description: Gen3 parameter.
47
+
minimum: 0
48
+
maximum: 0x7f
49
+
default: [0, 0, 0]
50
+
51
+
eswin,tx-preemph-tuning:
52
+
description: This adjusts the transmitter de-emphasis signal, and its value
53
+
is derived from eye diagram tuning. The three values correspond to Gen1,
54
+
Gen2, and Gen3 parameters respectively.
55
+
$ref: /schemas/types.yaml#/definitions/uint32-array
56
+
items:
57
+
- description: Gen1 parameter.
58
+
minimum: 0
59
+
maximum: 0x3f
60
+
- description: Gen2 parameter.
61
+
minimum: 0
62
+
maximum: 0x3f
63
+
- description: Gen3 parameter.
64
+
minimum: 0
65
+
maximum: 0x3f
66
+
default: [0, 0, 0]
67
+
68
+
"#phy-cells":
69
+
const: 0
70
+
71
+
required:
72
+
- compatible
73
+
- reg
74
+
- clocks
75
+
- clock-names
76
+
- resets
77
+
- reset-names
78
+
- "#phy-cells"
79
+
80
+
additionalProperties: false
81
+
82
+
examples:
83
+
- |
84
+
sata-phy@50440300 {
85
+
compatible = "eswin,eic7700-sata-phy";
86
+
reg = <0x50440300 0x40>;
87
+
clocks = <&hspcrg 17>;
88
+
clock-names = "phy";
89
+
resets = <&hspcrg 0>, <&hspcrg 1>;
90
+
reset-names = "port", "phy";
91
+
#phy-cells = <0>;
92
+
};
+6
-2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+6
-2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
···
18
18
oneOf:
19
19
- items:
20
20
- enum:
21
+
- qcom,qcs8300-qmp-ufs-phy
22
+
- const: qcom,sa8775p-qmp-ufs-phy
23
+
- items:
24
+
- enum:
21
25
- qcom,qcs615-qmp-ufs-phy
22
26
- const: qcom,sm6115-qmp-ufs-phy
23
27
- items:
···
30
26
- const: qcom,sm8550-qmp-ufs-phy
31
27
- items:
32
28
- enum:
33
-
- qcom,qcs8300-qmp-ufs-phy
34
-
- const: qcom,sa8775p-qmp-ufs-phy
29
+
- qcom,eliza-qmp-ufs-phy
30
+
- const: qcom,sm8650-qmp-ufs-phy
35
31
- items:
36
32
- enum:
37
33
- qcom,kaanapali-qmp-ufs-phy
+46
-56
drivers/phy/Kconfig
+46
-56
drivers/phy/Kconfig
···
46
46
Provides a number of helpers a core functions for MIPI D-PHY
47
47
drivers to us.
48
48
49
+
config PHY_AIROHA_PCIE
50
+
tristate "Airoha PCIe-PHY Driver"
51
+
depends on ARCH_AIROHA || COMPILE_TEST
52
+
depends on OF
53
+
select GENERIC_PHY
54
+
help
55
+
Say Y here to add support for Airoha PCIe PHY driver.
56
+
This driver create the basic PHY instance and provides initialize
57
+
callback for PCIe GEN3 port.
58
+
59
+
config PHY_CAN_TRANSCEIVER
60
+
tristate "CAN transceiver PHY"
61
+
select GENERIC_PHY
62
+
select MULTIPLEXER
63
+
help
64
+
This option enables support for CAN transceivers as a PHY. This
65
+
driver provides function for putting the transceivers in various
66
+
functional modes using gpios and sets the attribute max link
67
+
rate, for CAN drivers.
68
+
49
69
config PHY_GOOGLE_USB
50
70
tristate "Google Tensor SoC USB PHY driver"
51
71
select GENERIC_PHY
···
77
57
both of which are integrated with the DWC3 USB DRD controller.
78
58
This driver currently supports USB high-speed.
79
59
60
+
config USB_LGM_PHY
61
+
tristate "INTEL Lightning Mountain USB PHY Driver"
62
+
depends on USB_SUPPORT
63
+
depends on X86 || COMPILE_TEST
64
+
select USB_PHY
65
+
select REGULATOR
66
+
select REGULATOR_FIXED_VOLTAGE
67
+
help
68
+
Enable this to support Intel DWC3 PHY USB phy. This driver provides
69
+
interface to interact with USB GEN-II and USB 3.x PHY that is part
70
+
of the Intel network SOC.
71
+
80
72
config PHY_LPC18XX_USB_OTG
81
73
tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
82
74
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
···
99
67
100
68
This driver is need for USB0 support on LPC18xx/43xx and takes
101
69
care of enabling and clock setup.
70
+
71
+
config PHY_NXP_PTN3222
72
+
tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
73
+
depends on I2C
74
+
depends on OF
75
+
select GENERIC_PHY
76
+
help
77
+
Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
78
+
This redriver performs translation between eUSB2 and USB2 signalling
79
+
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
80
+
Speed and High Speed.
102
81
103
82
config PHY_PISTACHIO_USB
104
83
tristate "IMG Pistachio USB2.0 PHY driver"
···
133
90
help
134
91
This option enables support for APM X-Gene SoC multi-purpose PHY.
135
92
136
-
config USB_LGM_PHY
137
-
tristate "INTEL Lightning Mountain USB PHY Driver"
138
-
depends on USB_SUPPORT
139
-
depends on X86 || COMPILE_TEST
140
-
select USB_PHY
141
-
select REGULATOR
142
-
select REGULATOR_FIXED_VOLTAGE
143
-
help
144
-
Enable this to support Intel DWC3 PHY USB phy. This driver provides
145
-
interface to interact with USB GEN-II and USB 3.x PHY that is part
146
-
of the Intel network SOC.
147
-
148
-
config PHY_CAN_TRANSCEIVER
149
-
tristate "CAN transceiver PHY"
150
-
select GENERIC_PHY
151
-
select MULTIPLEXER
152
-
help
153
-
This option enables support for CAN transceivers as a PHY. This
154
-
driver provides function for putting the transceivers in various
155
-
functional modes using gpios and sets the attribute max link
156
-
rate, for CAN drivers.
157
-
158
-
config PHY_AIROHA_PCIE
159
-
tristate "Airoha PCIe-PHY Driver"
160
-
depends on ARCH_AIROHA || COMPILE_TEST
161
-
depends on OF
162
-
select GENERIC_PHY
163
-
help
164
-
Say Y here to add support for Airoha PCIe PHY driver.
165
-
This driver create the basic PHY instance and provides initialize
166
-
callback for PCIe GEN3 port.
167
-
168
-
config PHY_NXP_PTN3222
169
-
tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
170
-
depends on I2C
171
-
depends on OF
172
-
select GENERIC_PHY
173
-
help
174
-
Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
175
-
This redriver performs translation between eUSB2 and USB2 signalling
176
-
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
177
-
Speed and High Speed.
178
-
179
-
config PHY_SPACEMIT_K1_PCIE
180
-
tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
181
-
depends on ARCH_SPACEMIT || COMPILE_TEST
182
-
depends on COMMON_CLK
183
-
depends on HAS_IOMEM
184
-
depends on OF
185
-
select GENERIC_PHY
186
-
default ARCH_SPACEMIT
187
-
help
188
-
Enable support for the PCIe and USB 3 combo PHY and two
189
-
PCIe-only PHYs used in the SpacemiT K1 SoC.
190
-
191
93
source "drivers/phy/allwinner/Kconfig"
192
94
source "drivers/phy/amlogic/Kconfig"
193
95
source "drivers/phy/apple/Kconfig"
194
96
source "drivers/phy/broadcom/Kconfig"
195
97
source "drivers/phy/cadence/Kconfig"
98
+
source "drivers/phy/canaan/Kconfig"
99
+
source "drivers/phy/eswin/Kconfig"
196
100
source "drivers/phy/freescale/Kconfig"
197
101
source "drivers/phy/hisilicon/Kconfig"
198
102
source "drivers/phy/ingenic/Kconfig"
103
+
source "drivers/phy/intel/Kconfig"
199
104
source "drivers/phy/lantiq/Kconfig"
200
105
source "drivers/phy/marvell/Kconfig"
201
106
source "drivers/phy/mediatek/Kconfig"
···
165
174
source "drivers/phy/sunplus/Kconfig"
166
175
source "drivers/phy/tegra/Kconfig"
167
176
source "drivers/phy/ti/Kconfig"
168
-
source "drivers/phy/intel/Kconfig"
169
177
source "drivers/phy/xilinx/Kconfig"
170
178
171
179
endmenu
+7
-5
drivers/phy/Makefile
+7
-5
drivers/phy/Makefile
···
7
7
obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o
8
8
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
9
9
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
10
+
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
10
11
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
11
12
obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o
13
+
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
12
14
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
13
-
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
15
+
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
14
16
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
15
17
obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
16
-
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
17
-
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
18
-
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
19
-
obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o
18
+
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
19
+
20
20
obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
21
21
amlogic/ \
22
22
apple/ \
23
23
broadcom/ \
24
24
cadence/ \
25
+
canaan/ \
26
+
eswin/ \
25
27
freescale/ \
26
28
hisilicon/ \
27
29
ingenic/ \
+6
-4
drivers/phy/apple/atc.c
+6
-4
drivers/phy/apple/atc.c
···
2023
2023
return 0;
2024
2024
}
2025
2025
2026
-
const struct reset_control_ops atcphy_dwc3_reset_ops = {
2026
+
static const struct reset_control_ops atcphy_dwc3_reset_ops = {
2027
2027
.assert = atcphy_dwc3_reset_assert,
2028
2028
.deassert = atcphy_dwc3_reset_deassert,
2029
2029
};
···
2202
2202
{ "pipehandler", &atcphy->regs.pipehandler, NULL },
2203
2203
};
2204
2204
struct resource *res;
2205
+
void __iomem *addr;
2205
2206
2206
2207
for (int i = 0; i < ARRAY_SIZE(resources); i++) {
2207
2208
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resources[i].name);
2208
-
*resources[i].addr = devm_ioremap_resource(&pdev->dev, res);
2209
-
if (IS_ERR(resources[i].addr))
2210
-
return dev_err_probe(atcphy->dev, PTR_ERR(resources[i].addr),
2209
+
addr = devm_ioremap_resource(&pdev->dev, res);
2210
+
if (IS_ERR(addr))
2211
+
return dev_err_probe(atcphy->dev, PTR_ERR(addr),
2211
2212
"Unable to map %s regs", resources[i].name);
2212
2213
2214
+
*resources[i].addr = addr;
2213
2215
if (resources[i].res)
2214
2216
*resources[i].res = res;
2215
2217
}
+14
drivers/phy/canaan/Kconfig
+14
drivers/phy/canaan/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
#
3
+
# Phy drivers for Canaan platforms
4
+
#
5
+
config PHY_CANAAN_USB
6
+
tristate "Canaan USB2 PHY Driver"
7
+
depends on (ARCH_CANAAN || COMPILE_TEST) && OF
8
+
select GENERIC_PHY
9
+
help
10
+
Enable this driver to support the USB 2.0 PHY controller
11
+
on Canaan K230 RISC-V SoCs. This PHY controller
12
+
provides physical layer functionality for USB 2.0 devices.
13
+
If you have a Canaan K230 board and need USB 2.0 support,
14
+
say Y or M here.
+2
drivers/phy/canaan/Makefile
+2
drivers/phy/canaan/Makefile
+284
drivers/phy/canaan/phy-k230-usb.c
+284
drivers/phy/canaan/phy-k230-usb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Canaan usb PHY driver
4
+
*
5
+
* Copyright (C) 2026 Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/io.h>
10
+
#include <linux/of_address.h>
11
+
#include <linux/phy/phy.h>
12
+
#include <linux/platform_device.h>
13
+
14
+
#define MAX_PHYS 2
15
+
16
+
/* Register offsets within the HiSysConfig system controller */
17
+
#define K230_USB0_TEST_REG_BASE 0x70
18
+
#define K230_USB0_CTL_REG_BASE 0xb0
19
+
#define K230_USB1_TEST_REG_BASE 0x90
20
+
#define K230_USB1_CTL_REG_BASE 0xb8
21
+
22
+
/* Relative offsets within each PHY's control/test block */
23
+
#define CTL0_OFFSET 0x00
24
+
#define CTL1_OFFSET 0x04
25
+
#define TEST_CTL3_OFFSET 0x0c
26
+
27
+
/* Bit definitions for TEST_CTL3 */
28
+
#define USB_IDPULLUP0 BIT(4)
29
+
#define USB_DMPULLDOWN0 BIT(8)
30
+
#define USB_DPPULLDOWN0 BIT(9)
31
+
32
+
/* USB control register 0 in HiSysConfig system controller */
33
+
/* PLL Integral Path Tune */
34
+
#define USB_CTL0_PLLITUNE_MASK GENMASK(23, 22)
35
+
36
+
/* PLL Proportional Path Tune */
37
+
#define USB_CTL0_PLLPTUNE_MASK GENMASK(21, 18)
38
+
39
+
/* PLL Bandwidth Adjustment */
40
+
#define USB_CTL0_PLLBTUNE_MASK GENMASK(17, 17)
41
+
42
+
/* VReg18 Bypass Control */
43
+
#define USB_CTL0_VREGBYPASS_MASK GENMASK(16, 16)
44
+
45
+
/* Retention Mode Enable */
46
+
#define USB_CTL0_RETENABLEN_MASK GENMASK(15, 15)
47
+
48
+
/* Reserved Request Input */
49
+
#define USB_CTL0_RESREQIN_MASK GENMASK(14, 14)
50
+
51
+
/* External VBUS Valid Select */
52
+
#define USB_CTL0_VBUSVLDEXTSEL0_MASK GENMASK(13, 13)
53
+
54
+
/* OTG Block Disable Control */
55
+
#define USB_CTL0_OTGDISABLE0_MASK GENMASK(12, 12)
56
+
57
+
/* Drive VBUS Enable */
58
+
#define USB_CTL0_DRVVBUS0_MASK GENMASK(11, 11)
59
+
60
+
/* Autoresume Mode Enable */
61
+
#define USB_CTL0_AUTORSMENB0_MASK GENMASK(10, 10)
62
+
63
+
/* HS Transceiver Asynchronous Control */
64
+
#define USB_CTL0_HSXCVREXTCTL0_MASK GENMASK(9, 9)
65
+
66
+
/* USB 1.1 Transmit Data */
67
+
#define USB_CTL0_FSDATAEXT0_MASK GENMASK(8, 8)
68
+
69
+
/* USB 1.1 SE0 Generation */
70
+
#define USB_CTL0_FSSE0EXT0_MASK GENMASK(7, 7)
71
+
72
+
/* USB 1.1 Data Enable */
73
+
#define USB_CTL0_TXENABLEN0_MASK GENMASK(6, 6)
74
+
75
+
/* Disconnect Threshold */
76
+
#define USB_CTL0_COMPDISTUNE0_MASK GENMASK(5, 3)
77
+
78
+
/* Squelch Threshold */
79
+
#define USB_CTL0_SQRXTUNE0_MASK GENMASK(2, 0)
80
+
81
+
/* USB control register 1 in HiSysConfig system controller */
82
+
/* Data Detect Voltage */
83
+
#define USB_CTL1_VDATREFTUNE0_MASK GENMASK(23, 22)
84
+
85
+
/* VBUS Valid Threshold */
86
+
#define USB_CTL1_OTGTUNE0_MASK GENMASK(21, 19)
87
+
88
+
/* Transmitter High-Speed Crossover */
89
+
#define USB_CTL1_TXHSXVTUNE0_MASK GENMASK(18, 17)
90
+
91
+
/* FS/LS Source Impedance */
92
+
#define USB_CTL1_TXFSLSTUNE0_MASK GENMASK(16, 13)
93
+
94
+
/* HS DC Voltage Level */
95
+
#define USB_CTL1_TXVREFTUNE0_MASK GENMASK(12, 9)
96
+
97
+
/* HS Transmitter Rise/Fall Time */
98
+
#define USB_CTL1_TXRISETUNE0_MASK GENMASK(8, 7)
99
+
100
+
/* USB Source Impedance */
101
+
#define USB_CTL1_TXRESTUNE0_MASK GENMASK(6, 5)
102
+
103
+
/* HS Transmitter Pre-Emphasis Current Control */
104
+
#define USB_CTL1_TXPREEMPAMPTUNE0_MASK GENMASK(4, 3)
105
+
106
+
/* HS Transmitter Pre-Emphasis Duration Control */
107
+
#define USB_CTL1_TXPREEMPPULSETUNE0_MASK GENMASK(2, 2)
108
+
109
+
/* charging detection */
110
+
#define USB_CTL1_CHRGSRCPUENB0_MASK GENMASK(1, 0)
111
+
112
+
#define K230_PHY_CTL0_VAL \
113
+
( \
114
+
FIELD_PREP(USB_CTL0_PLLITUNE_MASK, 0x0) | \
115
+
FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xc) | \
116
+
FIELD_PREP(USB_CTL0_PLLBTUNE_MASK, 0x1) | \
117
+
FIELD_PREP(USB_CTL0_VREGBYPASS_MASK, 0x1) | \
118
+
FIELD_PREP(USB_CTL0_RETENABLEN_MASK, 0x1) | \
119
+
FIELD_PREP(USB_CTL0_RESREQIN_MASK, 0x0) | \
120
+
FIELD_PREP(USB_CTL0_VBUSVLDEXTSEL0_MASK, 0x0) | \
121
+
FIELD_PREP(USB_CTL0_OTGDISABLE0_MASK, 0x0) | \
122
+
FIELD_PREP(USB_CTL0_DRVVBUS0_MASK, 0x1) | \
123
+
FIELD_PREP(USB_CTL0_AUTORSMENB0_MASK, 0x0) | \
124
+
FIELD_PREP(USB_CTL0_HSXCVREXTCTL0_MASK, 0x0) | \
125
+
FIELD_PREP(USB_CTL0_FSDATAEXT0_MASK, 0x0) | \
126
+
FIELD_PREP(USB_CTL0_FSSE0EXT0_MASK, 0x0) | \
127
+
FIELD_PREP(USB_CTL0_TXENABLEN0_MASK, 0x0) | \
128
+
FIELD_PREP(USB_CTL0_COMPDISTUNE0_MASK, 0x3) | \
129
+
FIELD_PREP(USB_CTL0_SQRXTUNE0_MASK, 0x3) \
130
+
)
131
+
132
+
#define K230_PHY_CTL1_VAL \
133
+
( \
134
+
FIELD_PREP(USB_CTL1_VDATREFTUNE0_MASK, 0x1) | \
135
+
FIELD_PREP(USB_CTL1_OTGTUNE0_MASK, 0x3) | \
136
+
FIELD_PREP(USB_CTL1_TXHSXVTUNE0_MASK, 0x3) | \
137
+
FIELD_PREP(USB_CTL1_TXFSLSTUNE0_MASK, 0x3) | \
138
+
FIELD_PREP(USB_CTL1_TXVREFTUNE0_MASK, 0x3) | \
139
+
FIELD_PREP(USB_CTL1_TXRISETUNE0_MASK, 0x1) | \
140
+
FIELD_PREP(USB_CTL1_TXRESTUNE0_MASK, 0x1) | \
141
+
FIELD_PREP(USB_CTL1_TXPREEMPAMPTUNE0_MASK, 0x0) | \
142
+
FIELD_PREP(USB_CTL1_TXPREEMPPULSETUNE0_MASK, 0x0) | \
143
+
FIELD_PREP(USB_CTL1_CHRGSRCPUENB0_MASK, 0x0) \
144
+
)
145
+
146
+
struct k230_usb_phy_instance {
147
+
struct k230_usb_phy_global *global;
148
+
struct phy *phy;
149
+
u32 test_offset;
150
+
u32 ctl_offset;
151
+
int index;
152
+
};
153
+
154
+
struct k230_usb_phy_global {
155
+
struct k230_usb_phy_instance phys[MAX_PHYS];
156
+
void __iomem *base;
157
+
};
158
+
159
+
static int k230_usb_phy_power_on(struct phy *phy)
160
+
{
161
+
struct k230_usb_phy_instance *inst = phy_get_drvdata(phy);
162
+
struct k230_usb_phy_global *global = inst->global;
163
+
void __iomem *base = global->base;
164
+
u32 val;
165
+
166
+
/* Apply recommended settings */
167
+
writel(K230_PHY_CTL0_VAL, base + inst->ctl_offset + CTL0_OFFSET);
168
+
writel(K230_PHY_CTL1_VAL, base + inst->ctl_offset + CTL1_OFFSET);
169
+
170
+
/* Configure test register (pull-ups/pull-downs) */
171
+
val = readl(base + inst->test_offset + TEST_CTL3_OFFSET);
172
+
val |= USB_IDPULLUP0;
173
+
174
+
if (inst->index == 1)
175
+
val |= (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
176
+
else
177
+
val &= ~(USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
178
+
179
+
writel(val, base + inst->test_offset + TEST_CTL3_OFFSET);
180
+
181
+
return 0;
182
+
}
183
+
184
+
static int k230_usb_phy_power_off(struct phy *phy)
185
+
{
186
+
struct k230_usb_phy_instance *inst = phy_get_drvdata(phy);
187
+
struct k230_usb_phy_global *global = inst->global;
188
+
void __iomem *base = global->base;
189
+
u32 val;
190
+
191
+
val = readl(base + inst->test_offset + TEST_CTL3_OFFSET);
192
+
val &= ~(USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
193
+
writel(val, base + inst->test_offset + TEST_CTL3_OFFSET);
194
+
195
+
return 0;
196
+
}
197
+
198
+
static const struct phy_ops k230_usb_phy_ops = {
199
+
.power_on = k230_usb_phy_power_on,
200
+
.power_off = k230_usb_phy_power_off,
201
+
.owner = THIS_MODULE,
202
+
};
203
+
204
+
static struct phy *k230_usb_phy_xlate(struct device *dev,
205
+
const struct of_phandle_args *args)
206
+
{
207
+
struct k230_usb_phy_global *global = dev_get_drvdata(dev);
208
+
unsigned int idx = args->args[0];
209
+
210
+
if (idx >= MAX_PHYS)
211
+
return ERR_PTR(-EINVAL);
212
+
213
+
return global->phys[idx].phy;
214
+
}
215
+
216
+
static int k230_usb_phy_probe(struct platform_device *pdev)
217
+
{
218
+
struct k230_usb_phy_global *global;
219
+
struct device *dev = &pdev->dev;
220
+
struct phy_provider *provider;
221
+
int i;
222
+
223
+
global = devm_kzalloc(dev, sizeof(*global), GFP_KERNEL);
224
+
if (!global)
225
+
return -ENOMEM;
226
+
dev_set_drvdata(dev, global);
227
+
228
+
global->base = devm_platform_ioremap_resource(pdev, 0);
229
+
if (IS_ERR(global->base))
230
+
return dev_err_probe(dev, PTR_ERR(global->base),
231
+
"failed to map registers\n");
232
+
233
+
static const struct {
234
+
u32 test_offset;
235
+
u32 ctl_offset;
236
+
} phy_reg_info[MAX_PHYS] = {
237
+
[0] = { K230_USB0_TEST_REG_BASE, K230_USB0_CTL_REG_BASE },
238
+
[1] = { K230_USB1_TEST_REG_BASE, K230_USB1_CTL_REG_BASE },
239
+
};
240
+
241
+
for (i = 0; i < MAX_PHYS; i++) {
242
+
struct k230_usb_phy_instance *inst = &global->phys[i];
243
+
struct phy *phy;
244
+
245
+
inst->global = global;
246
+
inst->index = i;
247
+
inst->test_offset = phy_reg_info[i].test_offset;
248
+
inst->ctl_offset = phy_reg_info[i].ctl_offset;
249
+
250
+
phy = devm_phy_create(dev, NULL, &k230_usb_phy_ops);
251
+
if (IS_ERR(phy)) {
252
+
dev_err(dev, "failed to create phy%d\n", i);
253
+
return PTR_ERR(phy);
254
+
}
255
+
256
+
phy_set_drvdata(phy, inst);
257
+
inst->phy = phy;
258
+
}
259
+
260
+
provider = devm_of_phy_provider_register(dev, k230_usb_phy_xlate);
261
+
if (IS_ERR(provider))
262
+
return PTR_ERR(provider);
263
+
264
+
return 0;
265
+
}
266
+
267
+
static const struct of_device_id k230_usb_phy_of_match[] = {
268
+
{ .compatible = "canaan,k230-usb-phy" },
269
+
{}
270
+
};
271
+
MODULE_DEVICE_TABLE(of, k230_usb_phy_of_match);
272
+
273
+
static struct platform_driver k230_usb_phy_driver = {
274
+
.probe = k230_usb_phy_probe,
275
+
.driver = {
276
+
.name = "k230-usb-phy",
277
+
.of_match_table = k230_usb_phy_of_match,
278
+
},
279
+
};
280
+
module_platform_driver(k230_usb_phy_driver);
281
+
282
+
MODULE_DESCRIPTION("Canaan Kendryte K230 USB 2.0 PHY driver");
283
+
MODULE_AUTHOR("Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>");
284
+
MODULE_LICENSE("GPL");
+14
drivers/phy/eswin/Kconfig
+14
drivers/phy/eswin/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
#
3
+
# Phy drivers for ESWIN platforms
4
+
#
5
+
config PHY_EIC7700_SATA
6
+
tristate "eic7700 Sata SerDes/PHY driver"
7
+
depends on ARCH_ESWIN || COMPILE_TEST
8
+
depends on HAS_IOMEM
9
+
select GENERIC_PHY
10
+
help
11
+
Enable this to support SerDes/Phy found on ESWIN's
12
+
EIC7700 SoC. This Phy supports SATA 1.5 Gb/s,
13
+
SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
14
+
It supports one SATA host port to accept one SATA device.
+2
drivers/phy/eswin/Makefile
+2
drivers/phy/eswin/Makefile
+273
drivers/phy/eswin/phy-eic7700-sata.c
+273
drivers/phy/eswin/phy-eic7700-sata.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* ESWIN SATA PHY driver
4
+
*
5
+
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
6
+
* All rights reserved.
7
+
*
8
+
* Authors: Yulin Lu <luyulin@eswincomputing.com>
9
+
*/
10
+
11
+
#include <linux/bitfield.h>
12
+
#include <linux/clk.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/io.h>
15
+
#include <linux/kernel.h>
16
+
#include <linux/module.h>
17
+
#include <linux/phy/phy.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/reset.h>
21
+
22
+
#define SATA_AXI_LP_CTRL 0x08
23
+
#define SATA_MPLL_CTRL 0x20
24
+
#define SATA_P0_PHY_STAT 0x24
25
+
#define SATA_PHY_CTRL0 0x28
26
+
#define SATA_PHY_CTRL1 0x2c
27
+
#define SATA_REF_CTRL 0x34
28
+
#define SATA_REF_CTRL1 0x38
29
+
#define SATA_LOS_IDEN 0x3c
30
+
31
+
#define SATA_CLK_RST_SOURCE_PHY BIT(0)
32
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
33
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT 0x42
34
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8)
35
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT 0x46
36
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16)
37
+
#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT 0x73
38
+
#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
39
+
#define SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT 0x5
40
+
#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8)
41
+
#define SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT 0x5
42
+
#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16)
43
+
#define SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT 0x23
44
+
#define SATA_LOS_LEVEL_MASK GENMASK(4, 0)
45
+
#define SATA_LOS_BIAS_MASK GENMASK(18, 16)
46
+
#define SATA_M_CSYSREQ BIT(0)
47
+
#define SATA_S_CSYSREQ BIT(16)
48
+
#define SATA_REF_REPEATCLK_EN BIT(0)
49
+
#define SATA_REF_USE_PAD BIT(20)
50
+
#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16)
51
+
#define SATA_P0_PHY_READY BIT(0)
52
+
53
+
#define PLL_LOCK_SLEEP_US 10
54
+
#define PLL_LOCK_TIMEOUT_US 1000
55
+
56
+
struct eic7700_sata_phy {
57
+
u32 tx_amplitude_tuning_val[3];
58
+
u32 tx_preemph_tuning_val[3];
59
+
struct reset_control *rst;
60
+
struct regmap *regmap;
61
+
struct clk *clk;
62
+
struct phy *phy;
63
+
};
64
+
65
+
static const struct regmap_config eic7700_sata_phy_regmap_config = {
66
+
.reg_bits = 32,
67
+
.val_bits = 32,
68
+
.reg_stride = 4,
69
+
.max_register = SATA_LOS_IDEN,
70
+
};
71
+
72
+
static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
73
+
u32 status)
74
+
{
75
+
u32 val;
76
+
int ret;
77
+
78
+
ret = regmap_read_poll_timeout(regmap, reg, val,
79
+
(val & checkbit) == status,
80
+
PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);
81
+
82
+
return ret;
83
+
}
84
+
85
+
static int eic7700_sata_phy_init(struct phy *phy)
86
+
{
87
+
struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
88
+
u32 val;
89
+
int ret;
90
+
91
+
ret = clk_prepare_enable(sata_phy->clk);
92
+
if (ret)
93
+
return ret;
94
+
95
+
regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
96
+
97
+
val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK,
98
+
sata_phy->tx_amplitude_tuning_val[0]) |
99
+
FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK,
100
+
sata_phy->tx_amplitude_tuning_val[1]) |
101
+
FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK,
102
+
sata_phy->tx_amplitude_tuning_val[2]);
103
+
regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
104
+
105
+
val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK,
106
+
sata_phy->tx_preemph_tuning_val[0]) |
107
+
FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK,
108
+
sata_phy->tx_preemph_tuning_val[1]) |
109
+
FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK,
110
+
sata_phy->tx_preemph_tuning_val[2]);
111
+
regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
112
+
113
+
val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
114
+
FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
115
+
regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
116
+
117
+
val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
118
+
regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
119
+
120
+
val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
121
+
regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
122
+
123
+
val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
124
+
regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
125
+
126
+
usleep_range(15, 20);
127
+
128
+
ret = reset_control_deassert(sata_phy->rst);
129
+
if (ret)
130
+
goto disable_clk;
131
+
132
+
ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
133
+
SATA_P0_PHY_READY, 1);
134
+
if (ret < 0) {
135
+
dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
136
+
goto disable_clk;
137
+
}
138
+
139
+
return 0;
140
+
141
+
disable_clk:
142
+
clk_disable_unprepare(sata_phy->clk);
143
+
return ret;
144
+
}
145
+
146
+
static int eic7700_sata_phy_exit(struct phy *phy)
147
+
{
148
+
struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
149
+
int ret;
150
+
151
+
ret = reset_control_assert(sata_phy->rst);
152
+
if (ret)
153
+
return ret;
154
+
155
+
clk_disable_unprepare(sata_phy->clk);
156
+
157
+
return 0;
158
+
}
159
+
160
+
static const struct phy_ops eic7700_sata_phy_ops = {
161
+
.init = eic7700_sata_phy_init,
162
+
.exit = eic7700_sata_phy_exit,
163
+
.owner = THIS_MODULE,
164
+
};
165
+
166
+
static void eic7700_get_tuning_param(struct device_node *np,
167
+
struct eic7700_sata_phy *sata_phy)
168
+
{
169
+
if (of_property_read_u32_array
170
+
(np, "eswin,tx-amplitude-tuning",
171
+
sata_phy->tx_amplitude_tuning_val,
172
+
ARRAY_SIZE(sata_phy->tx_amplitude_tuning_val))) {
173
+
sata_phy->tx_amplitude_tuning_val[0] =
174
+
SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT;
175
+
sata_phy->tx_amplitude_tuning_val[1] =
176
+
SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT;
177
+
sata_phy->tx_amplitude_tuning_val[2] =
178
+
SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT;
179
+
}
180
+
181
+
if (of_property_read_u32_array
182
+
(np, "eswin,tx-preemph-tuning",
183
+
sata_phy->tx_preemph_tuning_val,
184
+
ARRAY_SIZE(sata_phy->tx_preemph_tuning_val))) {
185
+
sata_phy->tx_preemph_tuning_val[0] =
186
+
SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT;
187
+
sata_phy->tx_preemph_tuning_val[1] =
188
+
SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT;
189
+
sata_phy->tx_preemph_tuning_val[2] =
190
+
SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT;
191
+
}
192
+
}
193
+
194
+
static int eic7700_sata_phy_probe(struct platform_device *pdev)
195
+
{
196
+
struct eic7700_sata_phy *sata_phy;
197
+
struct phy_provider *phy_provider;
198
+
struct device *dev = &pdev->dev;
199
+
struct device_node *np = dev->of_node;
200
+
struct resource *res;
201
+
void __iomem *regs;
202
+
203
+
sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
204
+
if (!sata_phy)
205
+
return -ENOMEM;
206
+
207
+
/*
208
+
* Map the I/O resource with platform_get_resource and devm_ioremap
209
+
* instead of the devm_platform_ioremap_resource API, because the
210
+
* address region of the SATA-PHY falls into the region of the HSP
211
+
* clock & reset that has already been obtained by the HSP
212
+
* clock-and-reset driver.
213
+
*/
214
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215
+
if (!res)
216
+
return -ENOENT;
217
+
218
+
regs = devm_ioremap(dev, res->start, resource_size(res));
219
+
if (IS_ERR(regs))
220
+
return PTR_ERR(regs);
221
+
222
+
sata_phy->regmap = devm_regmap_init_mmio
223
+
(dev, regs, &eic7700_sata_phy_regmap_config);
224
+
if (IS_ERR(sata_phy->regmap))
225
+
return dev_err_probe(dev, PTR_ERR(sata_phy->regmap),
226
+
"failed to init regmap\n");
227
+
228
+
dev_set_drvdata(dev, sata_phy);
229
+
230
+
eic7700_get_tuning_param(np, sata_phy);
231
+
232
+
sata_phy->clk = devm_clk_get(dev, "phy");
233
+
if (IS_ERR(sata_phy->clk))
234
+
return PTR_ERR(sata_phy->clk);
235
+
236
+
sata_phy->rst = devm_reset_control_array_get_exclusive(dev);
237
+
if (IS_ERR(sata_phy->rst))
238
+
return dev_err_probe(dev, PTR_ERR(sata_phy->rst),
239
+
"failed to get reset control\n");
240
+
241
+
sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops);
242
+
if (IS_ERR(sata_phy->phy))
243
+
return dev_err_probe(dev, PTR_ERR(sata_phy->phy),
244
+
"failed to create PHY\n");
245
+
246
+
phy_set_drvdata(sata_phy->phy, sata_phy);
247
+
248
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
249
+
if (IS_ERR(phy_provider))
250
+
return dev_err_probe(dev, PTR_ERR(phy_provider),
251
+
"failed to register PHY provider\n");
252
+
253
+
return 0;
254
+
}
255
+
256
+
static const struct of_device_id eic7700_sata_phy_of_match[] = {
257
+
{ .compatible = "eswin,eic7700-sata-phy" },
258
+
{ },
259
+
};
260
+
MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match);
261
+
262
+
static struct platform_driver eic7700_sata_phy_driver = {
263
+
.probe = eic7700_sata_phy_probe,
264
+
.driver = {
265
+
.of_match_table = eic7700_sata_phy_of_match,
266
+
.name = "eic7700-sata-phy",
267
+
}
268
+
};
269
+
module_platform_driver(eic7700_sata_phy_driver);
270
+
271
+
MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC");
272
+
MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
273
+
MODULE_LICENSE("GPL");
+16
-8
drivers/phy/marvell/phy-mmp3-hsic.c
+16
-8
drivers/phy/marvell/phy-mmp3-hsic.c
···
14
14
#define HSIC_ENABLE BIT(7)
15
15
#define PLL_BYPASS BIT(4)
16
16
17
+
struct mmp3_hsic_data {
18
+
void __iomem *base;
19
+
};
20
+
17
21
static int mmp3_hsic_phy_init(struct phy *phy)
18
22
{
19
-
void __iomem *base = (void __iomem *)phy_get_drvdata(phy);
23
+
struct mmp3_hsic_data *mmp3 = phy_get_drvdata(phy);
20
24
u32 hsic_ctrl;
21
25
22
-
hsic_ctrl = readl_relaxed(base + HSIC_CTRL);
26
+
hsic_ctrl = readl_relaxed(mmp3->base + HSIC_CTRL);
23
27
hsic_ctrl |= HSIC_ENABLE;
24
28
hsic_ctrl |= PLL_BYPASS;
25
-
writel_relaxed(hsic_ctrl, base + HSIC_CTRL);
29
+
writel_relaxed(hsic_ctrl, mmp3->base + HSIC_CTRL);
26
30
27
31
return 0;
28
32
}
···
45
41
static int mmp3_hsic_phy_probe(struct platform_device *pdev)
46
42
{
47
43
struct device *dev = &pdev->dev;
44
+
struct mmp3_hsic_data *mmp3;
48
45
struct phy_provider *provider;
49
-
void __iomem *base;
50
46
struct phy *phy;
51
47
52
-
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
53
-
if (IS_ERR(base))
54
-
return PTR_ERR(base);
48
+
mmp3 = devm_kzalloc(dev, sizeof(*mmp3), GFP_KERNEL);
49
+
if (!mmp3)
50
+
return -ENOMEM;
51
+
52
+
mmp3->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
53
+
if (IS_ERR(mmp3->base))
54
+
return PTR_ERR(mmp3->base);
55
55
56
56
phy = devm_phy_create(dev, NULL, &mmp3_hsic_phy_ops);
57
57
if (IS_ERR(phy)) {
···
63
55
return PTR_ERR(phy);
64
56
}
65
57
66
-
phy_set_drvdata(phy, (void *)base);
58
+
phy_set_drvdata(phy, mmp3);
67
59
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
68
60
if (IS_ERR(provider)) {
69
61
dev_err(dev, "failed to register PHY provider\n");
+2
-2
drivers/phy/mediatek/phy-mtk-tphy.c
+2
-2
drivers/phy/mediatek/phy-mtk-tphy.c
···
276
276
};
277
277
278
278
/**
279
-
* mtk_phy_pdata - SoC specific platform data
279
+
* struct mtk_phy_pdata - SoC specific platform data
280
280
* @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only)
281
281
* @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from
282
282
* fractional mode to integer to output 26MHz for U2PHY
283
283
* @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values
284
284
* read from different nvmem (usually different eFuse array)
285
285
* that is pointed at in the device tree node for this PHY
286
-
* @slew_ref_clk_mhz: Default reference clock (in MHz) for slew rate calibration
286
+
* @slew_ref_clock_mhz: Default reference clock (in MHz) for slew rate calibration
287
287
* @slew_rate_coefficient: Coefficient for slew rate calibration
288
288
* @version: PHY IP Version
289
289
*/
drivers/phy/phy-spacemit-k1-pcie.c
drivers/phy/spacemit/phy-k1-pcie.c
drivers/phy/phy-spacemit-k1-pcie.c
drivers/phy/spacemit/phy-k1-pcie.c
+1
-1
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
+1
-1
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
···
83
83
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
84
84
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
85
85
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1),
86
-
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
86
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 0),
87
87
M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
88
88
};
89
89
+3
-3
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+3
-3
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
···
1679
1679
if (ret)
1680
1680
return ret;
1681
1681
1682
-
if (qmp->dp_serdes != 0) {
1682
+
if (qmp->dp_serdes) {
1683
1683
ret = phy_dp_clks_register(qmp, np);
1684
1684
if (ret)
1685
1685
return ret;
···
1833
1833
if (IS_ERR(base))
1834
1834
return PTR_ERR(base);
1835
1835
1836
-
if (offs->dp_serdes != 0) {
1836
+
if (offs->dp_serdes) {
1837
1837
qmp->dp_serdes = base + offs->dp_serdes;
1838
1838
qmp->dp_tx = base + offs->dp_txa;
1839
1839
qmp->dp_tx2 = base + offs->dp_txb;
···
1982
1982
1983
1983
phy_set_drvdata(qmp->usb_phy, qmp);
1984
1984
1985
-
if (qmp->dp_serdes != 0) {
1985
+
if (qmp->dp_serdes) {
1986
1986
qmp->dp_phy = devm_phy_create(dev, np, &qmp_usbc_dp_phy_ops);
1987
1987
if (IS_ERR(qmp->dp_phy)) {
1988
1988
ret = PTR_ERR(qmp->dp_phy);
+12
drivers/phy/spacemit/Kconfig
+12
drivers/phy/spacemit/Kconfig
···
2
2
#
3
3
# Phy drivers for SpacemiT platforms
4
4
#
5
+
config PHY_SPACEMIT_K1_PCIE
6
+
tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
7
+
depends on ARCH_SPACEMIT || COMPILE_TEST
8
+
depends on COMMON_CLK
9
+
depends on HAS_IOMEM
10
+
depends on OF
11
+
select GENERIC_PHY
12
+
default ARCH_SPACEMIT
13
+
help
14
+
Enable support for the PCIe and USB 3 combo PHY and two
15
+
PCIe-only PHYs used in the SpacemiT K1 SoC.
16
+
5
17
config PHY_SPACEMIT_K1_USB2
6
18
tristate "SpacemiT K1 USB 2.0 PHY support"
7
19
depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF