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Merge tag 'drm-fixes-2019-07-05-1' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"I skipped last week because there wasn't much worth doing, this week
got a few more fixes in.

amdgpu:
- default register value change
- runpm regression fix
- fan control fix

i915:
- fix Ironlake regression

panfrost:
- fix a double free

virtio:
- fix a locking bug

imx:
- crtc disable fixes"

* tag 'drm-fixes-2019-07-05-1' of git://anongit.freedesktop.org/drm/drm:
drm/imx: only send event on crtc disable if kept disabled
drm/imx: notify drm core before sending event during crtc disable
drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
drm/amdgpu: Don't skip display settings in hwmgr_resume()
drm/amd/powerplay: use hardware fan control if no powerplay fan table
drm/panfrost: Fix a double-free error
drm/etnaviv: add missing failure path to destroy suballoc
drm/virtio: move drm_connector_update_edid_property() call

+22 -31
-19
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 1959 1959 mutex_unlock(&adev->srbm_mutex); 1960 1960 1961 1961 gfx_v9_0_init_compute_vmid(adev); 1962 - 1963 - mutex_lock(&adev->grbm_idx_mutex); 1964 - /* 1965 - * making sure that the following register writes will be broadcasted 1966 - * to all the shaders 1967 - */ 1968 - gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1969 - 1970 - WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1971 - (adev->gfx.config.sc_prim_fifo_size_frontend << 1972 - PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1973 - (adev->gfx.config.sc_prim_fifo_size_backend << 1974 - PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1975 - (adev->gfx.config.sc_hiz_tile_fifo_size << 1976 - PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1977 - (adev->gfx.config.sc_earlyz_tile_fifo_size << 1978 - PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1979 - mutex_unlock(&adev->grbm_idx_mutex); 1980 - 1981 1962 } 1982 1963 1983 1964 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 326 326 if (ret) 327 327 return ret; 328 328 329 - ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); 329 + ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); 330 330 331 331 return ret; 332 332 }
+3 -1
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
··· 916 916 PHM_PlatformCaps_ThermalController 917 917 ); 918 918 919 - if (0 == powerplay_table->usFanTableOffset) 919 + if (0 == powerplay_table->usFanTableOffset) { 920 + hwmgr->thermal_controller.use_hw_fan_control = 1; 920 921 return 0; 922 + } 921 923 922 924 fan_table = (const PPTable_Generic_SubTable_Header *) 923 925 (((unsigned long)powerplay_table) +
+1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
··· 694 694 uint8_t ucType; 695 695 uint8_t ucI2cLine; 696 696 uint8_t ucI2cAddress; 697 + uint8_t use_hw_fan_control; 697 698 struct pp_fan_info fanInfo; 698 699 struct pp_advance_fan_control_parameters advanceFanControlParameters; 699 700 };
+4
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
··· 2092 2092 return 0; 2093 2093 } 2094 2094 2095 + /* use hardware fan control */ 2096 + if (hwmgr->thermal_controller.use_hw_fan_control) 2097 + return 0; 2098 + 2095 2099 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. 2096 2100 usPWMMin * duty100; 2097 2101 do_div(tmp64, 10000);
+5 -2
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
··· 760 760 if (IS_ERR(gpu->cmdbuf_suballoc)) { 761 761 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n"); 762 762 ret = PTR_ERR(gpu->cmdbuf_suballoc); 763 - goto fail; 763 + goto destroy_iommu; 764 764 } 765 765 766 766 /* Create buffer: */ ··· 768 768 PAGE_SIZE); 769 769 if (ret) { 770 770 dev_err(gpu->dev, "could not create command buffer\n"); 771 - goto destroy_iommu; 771 + goto destroy_suballoc; 772 772 } 773 773 774 774 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 && ··· 800 800 free_buffer: 801 801 etnaviv_cmdbuf_free(&gpu->buffer); 802 802 gpu->buffer.suballoc = NULL; 803 + destroy_suballoc: 804 + etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc); 805 + gpu->cmdbuf_suballoc = NULL; 803 806 destroy_iommu: 804 807 etnaviv_iommu_destroy(gpu->mmu); 805 808 gpu->mmu = NULL;
+3 -3
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 1888 1888 */ 1889 1889 request->reserved_space += LEGACY_REQUEST_SIZE; 1890 1890 1891 - ret = switch_context(request); 1891 + /* Unconditionally invalidate GPU caches and TLBs. */ 1892 + ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1892 1893 if (ret) 1893 1894 return ret; 1894 1895 1895 - /* Unconditionally invalidate GPU caches and TLBs. */ 1896 - ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1896 + ret = switch_context(request); 1897 1897 if (ret) 1898 1898 return ret; 1899 1899
+3 -3
drivers/gpu/drm/imx/ipuv3-crtc.c
··· 91 91 ipu_dc_disable(ipu); 92 92 ipu_prg_disable(ipu); 93 93 94 + drm_crtc_vblank_off(crtc); 95 + 94 96 spin_lock_irq(&crtc->dev->event_lock); 95 - if (crtc->state->event) { 97 + if (crtc->state->event && !crtc->state->active) { 96 98 drm_crtc_send_vblank_event(crtc, crtc->state->event); 97 99 crtc->state->event = NULL; 98 100 } 99 101 spin_unlock_irq(&crtc->dev->event_lock); 100 - 101 - drm_crtc_vblank_off(crtc); 102 102 } 103 103 104 104 static void imx_drm_crtc_reset(struct drm_crtc *crtc)
+1 -1
drivers/gpu/drm/panfrost/panfrost_drv.c
··· 63 63 return 0; 64 64 65 65 err_free: 66 - drm_gem_object_put_unlocked(&shmem->base); 66 + drm_gem_handle_delete(file, args->handle); 67 67 return ret; 68 68 } 69 69
+1 -1
drivers/gpu/drm/virtio/virtgpu_vq.c
··· 619 619 output = vgdev->outputs + scanout; 620 620 621 621 new_edid = drm_do_get_edid(&output->conn, virtio_get_edid_block, resp); 622 + drm_connector_update_edid_property(&output->conn, new_edid); 622 623 623 624 spin_lock(&vgdev->display_info_lock); 624 625 old_edid = output->edid; 625 626 output->edid = new_edid; 626 - drm_connector_update_edid_property(&output->conn, output->edid); 627 627 spin_unlock(&vgdev->display_info_lock); 628 628 629 629 kfree(old_edid);