Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Another set of five fixes. The most interesting one is a fix for race
condition in the local_irq_disable() implementation used by .S code
for pre-MIPS R2 processors only. It leaves a race that's hard but not
impossible to hit; the others fairly obvious"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Make local_irq_disable macro safe for non-Mipsr2
MIPS: Octeon: Fix warning in of_device_alloc on cn3xxx
MIPS: ftrace: Tweak safe_load()/safe_store() macros
MIPS: BCM47XX: Check all (32) GPIOs when looking for a pin
MIPS: Fix possible build error with transparent hugepages enabled
+40
-27
+6
-6
arch/mips/Kconfig
+6
-6
arch/mips/Kconfig
···
1776
1776
1777
1777
config FORCE_MAX_ZONEORDER
1778
1778
int "Maximum zone order"
1779
-
range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB
1780
-
default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB
1781
-
range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB
1782
-
default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB
1783
-
range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB
1784
-
default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB
1779
+
range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1780
+
default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1781
+
range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1782
+
default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1783
+
range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1784
+
default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1785
1785
range 11 64
1786
1786
default "11"
1787
1787
help
+1
-1
arch/mips/bcm47xx/nvram.c
+1
-1
arch/mips/bcm47xx/nvram.c
+12
-10
arch/mips/cavium-octeon/octeon-irq.c
+12
-10
arch/mips/cavium-octeon/octeon-irq.c
···
975
975
if (ciu > 1 || bit > 63)
976
976
return -EINVAL;
977
977
978
-
/* These are the GPIO lines */
979
-
if (ciu == 0 && bit >= 16 && bit < 32)
980
-
return -EINVAL;
981
-
982
978
*out_hwirq = (ciu << 6) | bit;
983
979
*out_type = 0;
984
980
···
1002
1006
1003
1007
if (!octeon_irq_virq_in_range(virq))
1004
1008
return -EINVAL;
1009
+
1010
+
/* Don't map irq if it is reserved for GPIO. */
1011
+
if (line == 0 && bit >= 16 && bit <32)
1012
+
return 0;
1005
1013
1006
1014
if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1007
1015
return -EINVAL;
···
1525
1525
ciu = intspec[0];
1526
1526
bit = intspec[1];
1527
1527
1528
-
/* Line 7 are the GPIO lines */
1529
-
if (ciu > 6 || bit > 63)
1530
-
return -EINVAL;
1531
-
1532
1528
*out_hwirq = (ciu << 6) | bit;
1533
1529
*out_type = 0;
1534
1530
···
1566
1570
if (!octeon_irq_virq_in_range(virq))
1567
1571
return -EINVAL;
1568
1572
1569
-
/* Line 7 are the GPIO lines */
1570
-
if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0)
1573
+
/*
1574
+
* Don't map irq if it is reserved for GPIO.
1575
+
* (Line 7 are the GPIO lines.)
1576
+
*/
1577
+
if (line == 7)
1578
+
return 0;
1579
+
1580
+
if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1571
1581
return -EINVAL;
1572
1582
1573
1583
if (octeon_irq_ciu2_is_edge(line, bit))
+11
arch/mips/include/asm/asmmacro.h
+11
arch/mips/include/asm/asmmacro.h
···
9
9
#define _ASM_ASMMACRO_H
10
10
11
11
#include <asm/hazards.h>
12
+
#include <asm/asm-offsets.h>
12
13
13
14
#ifdef CONFIG_32BIT
14
15
#include <asm/asmmacro-32.h>
···
55
54
.endm
56
55
57
56
.macro local_irq_disable reg=t0
57
+
#ifdef CONFIG_PREEMPT
58
+
lw \reg, TI_PRE_COUNT($28)
59
+
addi \reg, \reg, 1
60
+
sw \reg, TI_PRE_COUNT($28)
61
+
#endif
58
62
mfc0 \reg, CP0_STATUS
59
63
ori \reg, \reg, 1
60
64
xori \reg, \reg, 1
61
65
mtc0 \reg, CP0_STATUS
62
66
irq_disable_hazard
67
+
#ifdef CONFIG_PREEMPT
68
+
lw \reg, TI_PRE_COUNT($28)
69
+
addi \reg, \reg, -1
70
+
sw \reg, TI_PRE_COUNT($28)
71
+
#endif
63
72
.endm
64
73
#endif /* CONFIG_MIPS_MT_SMTC */
65
74
+10
-10
arch/mips/include/asm/ftrace.h
+10
-10
arch/mips/include/asm/ftrace.h
···
22
22
#define safe_load(load, src, dst, error) \
23
23
do { \
24
24
asm volatile ( \
25
-
"1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26
-
" li %[" STR(error) "], 0\n" \
25
+
"1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26
+
" li %[tmp_err], 0\n" \
27
27
"2:\n" \
28
28
\
29
29
".section .fixup, \"ax\"\n" \
30
-
"3: li %[" STR(error) "], 1\n" \
30
+
"3: li %[tmp_err], 1\n" \
31
31
" j 2b\n" \
32
32
".previous\n" \
33
33
\
···
35
35
STR(PTR) "\t1b, 3b\n\t" \
36
36
".previous\n" \
37
37
\
38
-
: [dst] "=&r" (dst), [error] "=r" (error)\
39
-
: [src] "r" (src) \
38
+
: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
39
+
: [tmp_src] "r" (src) \
40
40
: "memory" \
41
41
); \
42
42
} while (0)
···
44
44
#define safe_store(store, src, dst, error) \
45
45
do { \
46
46
asm volatile ( \
47
-
"1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48
-
" li %[" STR(error) "], 0\n" \
47
+
"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48
+
" li %[tmp_err], 0\n" \
49
49
"2:\n" \
50
50
\
51
51
".section .fixup, \"ax\"\n" \
52
-
"3: li %[" STR(error) "], 1\n" \
52
+
"3: li %[tmp_err], 1\n" \
53
53
" j 2b\n" \
54
54
".previous\n" \
55
55
\
···
57
57
STR(PTR) "\t1b, 3b\n\t" \
58
58
".previous\n" \
59
59
\
60
-
: [error] "=r" (error) \
61
-
: [dst] "r" (dst), [src] "r" (src)\
60
+
: [tmp_err] "=r" (error) \
61
+
: [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
62
62
: "memory" \
63
63
); \
64
64
} while (0)