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drm/i915/psr: Introduce helper intel_psr_set_non_psr_pipes()

Add a function to set non-psr pipes in crtc_state based on psr features.
This will help to move this part later where we re-evaluate psr features
and update the non-psr pipes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20251016055415.2101347-7-ankit.k.nautiyal@intel.com

+29 -20
+29 -20
drivers/gpu/drm/i915/display/intel_psr.c
··· 1711 1711 !crtc_state->has_sel_update); 1712 1712 } 1713 1713 1714 + static 1715 + void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1716 + struct intel_crtc_state *crtc_state) 1717 + { 1718 + struct intel_display *display = to_intel_display(intel_dp); 1719 + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1720 + struct intel_crtc *crtc; 1721 + u8 active_pipes = 0; 1722 + 1723 + /* Wa_16025596647 */ 1724 + if (DISPLAY_VER(display) != 20 && 1725 + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 1726 + return; 1727 + 1728 + /* Not needed by Panel Replay */ 1729 + if (crtc_state->has_panel_replay) 1730 + return; 1731 + 1732 + /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1733 + for_each_intel_crtc(display->drm, crtc) 1734 + active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1735 + 1736 + active_pipes = intel_calc_active_pipes(state, active_pipes); 1737 + 1738 + crtc_state->active_non_psr_pipes = active_pipes & 1739 + ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1740 + } 1741 + 1714 1742 void intel_psr_compute_config(struct intel_dp *intel_dp, 1715 1743 struct intel_crtc_state *crtc_state, 1716 1744 struct drm_connector_state *conn_state) 1717 1745 { 1718 1746 struct intel_display *display = to_intel_display(intel_dp); 1719 1747 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1720 - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1721 - struct intel_crtc *crtc; 1722 - u8 active_pipes = 0; 1723 1748 1724 1749 if (!psr_global_enabled(intel_dp)) { 1725 1750 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); ··· 1793 1768 "PSR disabled to workaround PSR FSM hang issue\n"); 1794 1769 } 1795 1770 1796 - /* Rest is for Wa_16025596647 */ 1797 - if (DISPLAY_VER(display) != 20 && 1798 - !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 1799 - return; 1800 - 1801 - /* Not needed by Panel Replay */ 1802 - if (crtc_state->has_panel_replay) 1803 - return; 1804 - 1805 - /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1806 - for_each_intel_crtc(display->drm, crtc) 1807 - active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1808 - 1809 - active_pipes = intel_calc_active_pipes(state, active_pipes); 1810 - 1811 - crtc_state->active_non_psr_pipes = active_pipes & 1812 - ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1771 + intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 1813 1772 } 1814 1773 1815 1774 void intel_psr_get_config(struct intel_encoder *encoder,