dpll: add frequency monitoring to netlink spec

+20

Documentation/driver-api/dpll.rst

··· 250 250 ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature 251 251 =============================== ======================== 252 252 253 + Frequency monitor 254 + ================= 255 + 256 + Some DPLL devices may offer the capability to measure the actual 257 + frequency of all available input pins. The attribute and current feature state 258 + shall be included in the response message of the ``DPLL_CMD_DEVICE_GET`` 259 + command for supported DPLL devices. In such cases, users can also control 260 + the feature using the ``DPLL_CMD_DEVICE_SET`` command by setting the 261 + ``enum dpll_feature_state`` values for the attribute. 262 + Once enabled the measured input frequency for each input pin shall be 263 + returned in the ``DPLL_A_PIN_MEASURED_FREQUENCY`` attribute. The value 264 + is in millihertz (mHz), using ``DPLL_PIN_MEASURED_FREQUENCY_DIVIDER`` 265 + as the divider. 266 + 267 + =============================== ======================== 268 + ``DPLL_A_FREQUENCY_MONITOR`` attr state of a feature 269 + =============================== ======================== 270 + 253 271 Embedded SYNC 254 272 ============= 255 273 ··· 429 411 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 430 412 pin 431 413 ``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities 414 + ``DPLL_A_PIN_MEASURED_FREQUENCY`` attr measured frequency of 415 + an input pin in mHz 432 416 ==================================== ================================== 433 417 434 418 ==================================== =================================

+35

Documentation/netlink/specs/dpll.yaml

··· 241 241 Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a 242 242 fractional part of a measured phase offset value. 243 243 - 244 + type: const 245 + name: pin-measured-frequency-divider 246 + value: 1000 247 + doc: | 248 + pin measured frequency divider allows userspace to calculate 249 + a value of measured input frequency as a fractional value with 250 + three digit decimal precision (millihertz). 251 + Value of (DPLL_A_PIN_MEASURED_FREQUENCY / 252 + DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is an integer part of 253 + a measured frequency value. 254 + Value of (DPLL_A_PIN_MEASURED_FREQUENCY % 255 + DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is a fractional part of 256 + a measured frequency value. 257 + - 244 258 type: enum 245 259 name: feature-state 246 260 doc: | ··· 333 319 name: phase-offset-avg-factor 334 320 type: u32 335 321 doc: Averaging factor applied to calculation of reported phase offset. 322 + - 323 + name: frequency-monitor 324 + type: u32 325 + enum: feature-state 326 + doc: Current or desired state of the frequency monitor feature. 327 + If enabled, dpll device shall measure all currently available 328 + inputs for their actual input frequency. 336 329 - 337 330 name: pin 338 331 enum-name: dpll_a_pin ··· 477 456 Value is in PPT (parts per trillion, 10^-12). 478 457 Note: This attribute provides higher resolution than the standard 479 458 fractional-frequency-offset (which is in PPM). 459 + - 460 + name: measured-frequency 461 + type: u64 462 + doc: | 463 + The measured frequency of the input pin in millihertz (mHz). 464 + Value of (DPLL_A_PIN_MEASURED_FREQUENCY / 465 + DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is an integer part (Hz) 466 + of a measured frequency value. 467 + Value of (DPLL_A_PIN_MEASURED_FREQUENCY % 468 + DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is a fractional part 469 + of a measured frequency value. 480 470 481 471 - 482 472 name: pin-parent-device ··· 576 544 - type 577 545 - phase-offset-monitor 578 546 - phase-offset-avg-factor 547 + - frequency-monitor 579 548 580 549 dump: 581 550 reply: *dev-attrs ··· 596 563 - mode 597 564 - phase-offset-monitor 598 565 - phase-offset-avg-factor 566 + - frequency-monitor 599 567 - 600 568 name: device-create-ntf 601 569 doc: Notification about device appearing ··· 677 643 - esync-frequency-supported 678 644 - esync-pulse 679 645 - reference-sync 646 + - measured-frequency 680 647 681 648 dump: 682 649 request:

+3 -2

drivers/dpll/dpll_nl.c

··· 43 43 }; 44 44 45 45 /* DPLL_CMD_DEVICE_SET - do */ 46 - static const struct nla_policy dpll_device_set_nl_policy[DPLL_A_PHASE_OFFSET_AVG_FACTOR + 1] = { 46 + static const struct nla_policy dpll_device_set_nl_policy[DPLL_A_FREQUENCY_MONITOR + 1] = { 47 47 [DPLL_A_ID] = { .type = NLA_U32, }, 48 48 [DPLL_A_MODE] = NLA_POLICY_RANGE(NLA_U32, 1, 2), 49 49 [DPLL_A_PHASE_OFFSET_MONITOR] = NLA_POLICY_MAX(NLA_U32, 1), 50 50 [DPLL_A_PHASE_OFFSET_AVG_FACTOR] = { .type = NLA_U32, }, 51 + [DPLL_A_FREQUENCY_MONITOR] = NLA_POLICY_MAX(NLA_U32, 1), 51 52 }; 52 53 53 54 /* DPLL_CMD_PIN_ID_GET - do */ ··· 116 115 .doit = dpll_nl_device_set_doit, 117 116 .post_doit = dpll_post_doit, 118 117 .policy = dpll_device_set_nl_policy, 119 - .maxattr = DPLL_A_PHASE_OFFSET_AVG_FACTOR, 118 + .maxattr = DPLL_A_FREQUENCY_MONITOR, 120 119 .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, 121 120 }, 122 121 {

+4 -1

include/uapi/linux/dpll.h

··· 191 191 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4, 192 192 }; 193 193 194 - #define DPLL_PHASE_OFFSET_DIVIDER 1000 194 + #define DPLL_PHASE_OFFSET_DIVIDER 1000 195 + #define DPLL_PIN_MEASURED_FREQUENCY_DIVIDER 1000 195 196 196 197 /** 197 198 * enum dpll_feature_state - Allow control (enable/disable) and status checking ··· 219 218 DPLL_A_CLOCK_QUALITY_LEVEL, 220 219 DPLL_A_PHASE_OFFSET_MONITOR, 221 220 DPLL_A_PHASE_OFFSET_AVG_FACTOR, 221 + DPLL_A_FREQUENCY_MONITOR, 222 222 223 223 __DPLL_A_MAX, 224 224 DPLL_A_MAX = (__DPLL_A_MAX - 1) ··· 256 254 DPLL_A_PIN_REFERENCE_SYNC, 257 255 DPLL_A_PIN_PHASE_ADJUST_GRAN, 258 256 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 257 + DPLL_A_PIN_MEASURED_FREQUENCY, 259 258 260 259 __DPLL_A_PIN_MAX, 261 260 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)

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