Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Since we didn't get around to collect fixes in time for -rc2 over the
easter vacation, this one is unfortunately a bit larger than we'd like
for an -rc3 merge.
A large set of the changes is in the device tree sources, so I'm
splitting out the description between code changes and DT changes.
Aside from omap and versatile express, the actual code bugs are and
trivial. Here is an overview:
imx:
- fix video clock settings
- fix one clock refcounting bug
omap:
- update defconfig for renamed USB PHY driver
- fix error handling in gpmc
- fix N900 video initialization regression
- fix reression in hwmod code from missing braces
- fix am43xx and omap3 clocks
- remove bogus write to voltage control register
pxa:
- fix build regression from 3.13 header cleanup
rockchip:
- fix a misleading printk string
shmobile:
- fix incorrect sound setting on multiple machines
spear:
- remove incorrect __init section annotation
tegra:
- remove a stale Kconfig entry
u300:
- update defconfig
ux500:
- enable common wireless and sensor drivers in defconfig
- more defconfig updates
vexpress:
- fix voltage calculation for opp
- fix reboot hang and warning
- fix out-of-bounds array access
- improve error handling in clock driver
overall:
- always select CLKSRC_OF in multiplatform builds
And these are the devicetree related changes:
imx:
- add missing #clock-cell properties
- fix pinctrl setting in imx6sl-evk
- fix video endpoint on imx53
- remove obsolete lvds-channel nodes (multiple patches)
- add missing second stmpe node
- fix usb host mode on dmo-edmqmx6 (multiple patches)
- fix gic node #address-cells to match usage
- add missing legacy IRQ map for PCIe
- fix microsom pincontrol setting for rgmii
- fix fatal typo in touchscreen DT usage for mx5
- list all RAM present on m53evk and mx53qsb
omap:
- fix bug in DT handling of gpmc external bus
- add DT for older revision of beagleboard
- fix regression after DT node name fixes
- remove obsolete properties for gpmc
- fix pinmux comment to match DT it refers to
- fix newly added dra7xx clock node data
- add missing clock for USB PHY
mvebu:
- add missing clock for mdio node
- fix nonstandard vendor prefixes on i2c nodes
rockchip:
- fix pin control setting for uart
shmobile:
- fix typo in DT data for pin control (multiple patches)
- fix gic node #address-cells to match usage
tegra:
- fix clock and uart DT representation to match hardware
zynq:
- add DT nodes for newly added driver
- add DT properties required for cpufreq-ondemand
overall:
- restore alphabetic order in Makefile
- grammar fixes in bindings"
* tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (66 commits)
ARM: vexpress/TC2: Convert OPP voltage to uV before storing
power/reset: vexpress: Fix restart/power off operation
dt: tegra: remove non-existent clock IDs
clk: tegra: remove non-existent clocks
ARM: tegra: remove UART5/UARTE from tegra124.dtsi
ARM: tegra: remove TEGRA_EMC_SCALING_ENABLE
ARM: Tidy up DTB Makefile entries
ARM: fix missing CLKSRC_OF on multi-platform
ARM: spear: add __init to spear_clocksource_init()
ARM: pxa: hx4700.h: include "irqs.h" for PXA_NR_BUILTIN_GPIO
arm/mach-vexpress: array accessed out of bounds
clk: vexpress: NULL dereference on error path
ARM: OMAP2+: Fix GPMC remap for devices using an offset
ARM: zynq: dt: Add I2C nodes to Zynq device tree
ARM: zynq: DT: Add 'clock-latency' property
ARM: OMAP2+: Fix oops for GPMC free
ARM: dts: Add support for the BeagleBoard xM A/B
ARM: dts: Grammar /that will/it will/
ARM: dts: Grammar /is uses/ is used/
ARM: OMAP2+: Fix config name for USB3 PHY
...
+430
-181
+1
arch/arm/Kconfig
+1
arch/arm/Kconfig
+10
-10
arch/arm/boot/dts/Makefile
+10
-10
arch/arm/boot/dts/Makefile
···
51
51
52
52
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
53
53
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
54
+
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
54
55
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
55
56
bcm21664-garnet.dtb
56
-
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
57
-
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
58
57
dtb-$(CONFIG_ARCH_BERLIN) += \
59
58
berlin2-sony-nsz-gs7.dtb \
60
59
berlin2cd-google-chromecast.dtb
···
245
246
omap3-sbc-t3730.dtb \
246
247
omap3-devkit8000.dtb \
247
248
omap3-beagle-xm.dtb \
249
+
omap3-beagle-xm-ab.dtb \
248
250
omap3-evm.dtb \
249
251
omap3-evm-37xx.dtb \
250
252
omap3-ldp.dtb \
···
294
294
dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
295
295
qcom-msm8960-cdp.dtb \
296
296
qcom-apq8074-dragonboard.dtb
297
-
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
298
-
ste-hrefprev60-stuib.dtb \
299
-
ste-hrefprev60-tvk.dtb \
300
-
ste-hrefv60plus-stuib.dtb \
301
-
ste-hrefv60plus-tvk.dtb \
302
-
ste-ccu8540.dtb \
303
-
ste-ccu9540.dtb
304
297
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
305
298
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
306
299
s3c6410-smdk6410.dtb
···
362
369
tegra30-cardhu-a04.dtb \
363
370
tegra114-dalmore.dtb \
364
371
tegra124-venice2.dtb
372
+
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
373
+
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
374
+
ste-hrefprev60-stuib.dtb \
375
+
ste-hrefprev60-tvk.dtb \
376
+
ste-hrefv60plus-stuib.dtb \
377
+
ste-hrefv60plus-tvk.dtb \
378
+
ste-ccu8540.dtb \
379
+
ste-ccu9540.dtb
365
380
dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
366
381
versatile-pb.dtb
367
-
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
368
382
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
369
383
vexpress-v2p-ca9.dtb \
370
384
vexpress-v2p-ca15-tc1.dtb \
+2
-2
arch/arm/boot/dts/am335x-bone-common.dtsi
+2
-2
arch/arm/boot/dts/am335x-bone-common.dtsi
···
183
183
&usb {
184
184
status = "okay";
185
185
186
-
control@44e10000 {
186
+
control@44e10620 {
187
187
status = "okay";
188
188
};
189
189
···
204
204
dr_mode = "host";
205
205
};
206
206
207
-
dma-controller@07402000 {
207
+
dma-controller@47402000 {
208
208
status = "okay";
209
209
};
210
210
};
+4
-4
arch/arm/boot/dts/am335x-evm.dts
+4
-4
arch/arm/boot/dts/am335x-evm.dts
···
301
301
302
302
am335x_evm_audio_pins: am335x_evm_audio_pins {
303
303
pinctrl-single,pins = <
304
-
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
305
-
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
304
+
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
305
+
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
306
306
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
307
307
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
308
308
>;
···
331
331
&usb {
332
332
status = "okay";
333
333
334
-
control@44e10000 {
334
+
control@44e10620 {
335
335
status = "okay";
336
336
};
337
337
···
352
352
dr_mode = "host";
353
353
};
354
354
355
-
dma-controller@07402000 {
355
+
dma-controller@47402000 {
356
356
status = "okay";
357
357
};
358
358
};
+2
-2
arch/arm/boot/dts/am335x-evmsk.dts
+2
-2
arch/arm/boot/dts/am335x-evmsk.dts
···
364
364
&usb {
365
365
status = "okay";
366
366
367
-
control@44e10000 {
367
+
control@44e10620 {
368
368
status = "okay";
369
369
};
370
370
···
385
385
dr_mode = "host";
386
386
};
387
387
388
-
dma-controller@07402000 {
388
+
dma-controller@47402000 {
389
389
status = "okay";
390
390
};
391
391
};
+2
-3
arch/arm/boot/dts/am335x-igep0033.dtsi
+2
-3
arch/arm/boot/dts/am335x-igep0033.dtsi
···
118
118
reg = <0 0 0>; /* CS0, offset 0 */
119
119
nand-bus-width = <8>;
120
120
ti,nand-ecc-opt = "bch8";
121
-
gpmc,device-nand = "true";
122
121
gpmc,device-width = <1>;
123
122
gpmc,sync-clk-ps = <0>;
124
123
gpmc,cs-on-ns = <0>;
···
201
202
&usb {
202
203
status = "okay";
203
204
204
-
control@44e10000 {
205
+
control@44e10620 {
205
206
status = "okay";
206
207
};
207
208
···
222
223
dr_mode = "host";
223
224
};
224
225
225
-
dma-controller@07402000 {
226
+
dma-controller@47402000 {
226
227
status = "okay";
227
228
};
228
229
};
+3
-3
arch/arm/boot/dts/am33xx.dtsi
+3
-3
arch/arm/boot/dts/am33xx.dtsi
···
72
72
};
73
73
74
74
/*
75
-
* The soc node represents the soc top level view. It is uses for IPs
75
+
* The soc node represents the soc top level view. It is used for IPs
76
76
* that are not memory mapped in the MPU view or for the MPU itself.
77
77
*/
78
78
soc {
···
94
94
95
95
/*
96
96
* XXX: Use a flat representation of the AM33XX interconnect.
97
-
* The real AM33XX interconnect network is quite complex.Since
98
-
* that will not bring real advantage to represent that in DT
97
+
* The real AM33XX interconnect network is quite complex. Since
98
+
* it will not bring real advantage to represent that in DT
99
99
* for the moment, just use a fake OCP bus entry to represent
100
100
* the whole bus hierarchy.
101
101
*/
+1
arch/arm/boot/dts/armada-370-xp.dtsi
+1
arch/arm/boot/dts/armada-370-xp.dtsi
+1
arch/arm/boot/dts/armada-38x.dtsi
+1
arch/arm/boot/dts/armada-38x.dtsi
+2
-2
arch/arm/boot/dts/dra7.dtsi
+2
-2
arch/arm/boot/dts/dra7.dtsi
···
80
80
};
81
81
82
82
/*
83
-
* The soc node represents the soc top level view. It is uses for IPs
83
+
* The soc node represents the soc top level view. It is used for IPs
84
84
* that are not memory mapped in the MPU view or for the MPU itself.
85
85
*/
86
86
soc {
···
94
94
/*
95
95
* XXX: Use a flat representation of the SOC interconnect.
96
96
* The real OMAP interconnect network is quite complex.
97
-
* Since that will not bring real advantage to represent that in DT for
97
+
* Since it will not bring real advantage to represent that in DT for
98
98
* the moment, just use a fake OCP bus entry to represent the whole bus
99
99
* hierarchy.
100
100
*/
+1
-1
arch/arm/boot/dts/dra7xx-clocks.dtsi
+1
-1
arch/arm/boot/dts/dra7xx-clocks.dtsi
···
1640
1640
#clock-cells = <0>;
1641
1641
compatible = "ti,mux-clock";
1642
1642
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1643
-
ti,bit-shift = <28>;
1643
+
ti,bit-shift = <24>;
1644
1644
reg = <0x1860>;
1645
1645
};
1646
1646
+1
arch/arm/boot/dts/imx25.dtsi
+1
arch/arm/boot/dts/imx25.dtsi
+1
arch/arm/boot/dts/imx27-apf27.dts
+1
arch/arm/boot/dts/imx27-apf27.dts
+1
arch/arm/boot/dts/imx27.dtsi
+1
arch/arm/boot/dts/imx27.dtsi
+4
arch/arm/boot/dts/imx50.dtsi
+4
arch/arm/boot/dts/imx50.dtsi
···
53
53
54
54
ckil {
55
55
compatible = "fsl,imx-ckil", "fixed-clock";
56
+
#clock-cells = <0>;
56
57
clock-frequency = <32768>;
57
58
};
58
59
59
60
ckih1 {
60
61
compatible = "fsl,imx-ckih1", "fixed-clock";
62
+
#clock-cells = <0>;
61
63
clock-frequency = <22579200>;
62
64
};
63
65
64
66
ckih2 {
65
67
compatible = "fsl,imx-ckih2", "fixed-clock";
68
+
#clock-cells = <0>;
66
69
clock-frequency = <0>;
67
70
};
68
71
69
72
osc {
70
73
compatible = "fsl,imx-osc", "fixed-clock";
74
+
#clock-cells = <0>;
71
75
clock-frequency = <24000000>;
72
76
};
73
77
};
+4
arch/arm/boot/dts/imx51.dtsi
+4
arch/arm/boot/dts/imx51.dtsi
···
50
50
51
51
ckil {
52
52
compatible = "fsl,imx-ckil", "fixed-clock";
53
+
#clock-cells = <0>;
53
54
clock-frequency = <32768>;
54
55
};
55
56
56
57
ckih1 {
57
58
compatible = "fsl,imx-ckih1", "fixed-clock";
59
+
#clock-cells = <0>;
58
60
clock-frequency = <0>;
59
61
};
60
62
61
63
ckih2 {
62
64
compatible = "fsl,imx-ckih2", "fixed-clock";
65
+
#clock-cells = <0>;
63
66
clock-frequency = <0>;
64
67
};
65
68
66
69
osc {
67
70
compatible = "fsl,imx-osc", "fixed-clock";
71
+
#clock-cells = <0>;
68
72
clock-frequency = <24000000>;
69
73
};
70
74
};
+12
-11
arch/arm/boot/dts/imx53-m53evk.dts
+12
-11
arch/arm/boot/dts/imx53-m53evk.dts
···
17
17
compatible = "denx,imx53-m53evk", "fsl,imx53";
18
18
19
19
memory {
20
-
reg = <0x70000000 0x20000000>;
20
+
reg = <0x70000000 0x20000000>,
21
+
<0xb0000000 0x20000000>;
21
22
};
22
23
23
24
soc {
···
194
193
irq-trigger = <0x1>;
195
194
196
195
stmpe_touchscreen {
197
-
compatible = "stmpe,ts";
196
+
compatible = "st,stmpe-ts";
198
197
reg = <0>;
199
-
ts,sample-time = <4>;
200
-
ts,mod-12b = <1>;
201
-
ts,ref-sel = <0>;
202
-
ts,adc-freq = <1>;
203
-
ts,ave-ctrl = <3>;
204
-
ts,touch-det-delay = <3>;
205
-
ts,settling = <4>;
206
-
ts,fraction-z = <7>;
207
-
ts,i-drive = <1>;
198
+
st,sample-time = <4>;
199
+
st,mod-12b = <1>;
200
+
st,ref-sel = <0>;
201
+
st,adc-freq = <1>;
202
+
st,ave-ctrl = <3>;
203
+
st,touch-det-delay = <3>;
204
+
st,settling = <4>;
205
+
st,fraction-z = <7>;
206
+
st,i-drive = <1>;
208
207
};
209
208
};
210
209
+2
-1
arch/arm/boot/dts/imx53-qsb-common.dtsi
+2
-1
arch/arm/boot/dts/imx53-qsb-common.dtsi
+10
-1
arch/arm/boot/dts/imx53-tx53-x03x.dts
+10
-1
arch/arm/boot/dts/imx53-tx53-x03x.dts
···
25
25
soc {
26
26
display: display@di0 {
27
27
compatible = "fsl,imx-parallel-display";
28
-
crtcs = <&ipu 0>;
29
28
interface-pix-fmt = "rgb24";
30
29
pinctrl-names = "default";
31
30
pinctrl-0 = <&pinctrl_rgb24_vga1>;
32
31
status = "okay";
32
+
33
+
port {
34
+
display0_in: endpoint {
35
+
remote-endpoint = <&ipu_di0_disp0>;
36
+
};
37
+
};
33
38
34
39
display-timings {
35
40
VGA {
···
296
291
>;
297
292
};
298
293
};
294
+
};
295
+
296
+
&ipu_di0_disp0 {
297
+
remote-endpoint = <&display0_in>;
299
298
};
300
299
301
300
&kpp {
+5
-1
arch/arm/boot/dts/imx53.dtsi
+5
-1
arch/arm/boot/dts/imx53.dtsi
···
70
70
71
71
ckil {
72
72
compatible = "fsl,imx-ckil", "fixed-clock";
73
+
#clock-cells = <0>;
73
74
clock-frequency = <32768>;
74
75
};
75
76
76
77
ckih1 {
77
78
compatible = "fsl,imx-ckih1", "fixed-clock";
79
+
#clock-cells = <0>;
78
80
clock-frequency = <22579200>;
79
81
};
80
82
81
83
ckih2 {
82
84
compatible = "fsl,imx-ckih2", "fixed-clock";
85
+
#clock-cells = <0>;
83
86
clock-frequency = <0>;
84
87
};
85
88
86
89
osc {
87
90
compatible = "fsl,imx-osc", "fixed-clock";
91
+
#clock-cells = <0>;
88
92
clock-frequency = <24000000>;
89
93
};
90
94
};
···
434
430
435
431
port {
436
432
lvds1_in: endpoint {
437
-
remote-endpoint = <&ipu_di0_lvds0>;
433
+
remote-endpoint = <&ipu_di1_lvds1>;
438
434
};
439
435
};
440
436
};
+35
-13
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+35
-13
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
···
19
19
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
20
20
21
21
aliases {
22
-
gpio7 = &stmpe_gpio;
22
+
gpio7 = &stmpe_gpio1;
23
+
gpio8 = &stmpe_gpio2;
24
+
stmpe-i2c0 = &stmpe1;
25
+
stmpe-i2c1 = &stmpe2;
23
26
};
24
27
25
28
memory {
···
43
40
regulator-always-on;
44
41
};
45
42
46
-
reg_usb_otg_vbus: regulator@1 {
43
+
reg_usb_otg_switch: regulator@1 {
47
44
compatible = "regulator-fixed";
48
45
reg = <1>;
49
-
regulator-name = "usb_otg_vbus";
46
+
regulator-name = "usb_otg_switch";
50
47
regulator-min-microvolt = <5000000>;
51
48
regulator-max-microvolt = <5000000>;
52
49
gpio = <&gpio7 12 0>;
50
+
regulator-boot-on;
51
+
regulator-always-on;
53
52
};
54
53
55
54
reg_usb_host1: regulator@2 {
···
70
65
71
66
led-blue {
72
67
label = "blue";
73
-
gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
68
+
gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
74
69
linux,default-trigger = "heartbeat";
75
70
};
76
71
77
72
led-green {
78
73
label = "green";
79
-
gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
74
+
gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
80
75
};
81
76
82
77
led-pink {
83
78
label = "pink";
84
-
gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
79
+
gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
85
80
};
86
81
87
82
led-red {
88
83
label = "red";
89
-
gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
84
+
gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
90
85
};
91
86
};
92
87
};
···
104
99
clock-frequency = <100000>;
105
100
pinctrl-names = "default";
106
101
pinctrl-0 = <&pinctrl_i2c2
107
-
&pinctrl_stmpe>;
102
+
&pinctrl_stmpe1
103
+
&pinctrl_stmpe2>;
108
104
status = "okay";
109
105
110
106
pmic: pfuze100@08 {
···
211
205
};
212
206
};
213
207
214
-
stmpe: stmpe1601@40 {
208
+
stmpe1: stmpe1601@40 {
215
209
compatible = "st,stmpe1601";
216
210
reg = <0x40>;
217
211
interrupts = <30 0>;
218
212
interrupt-parent = <&gpio3>;
219
213
220
-
stmpe_gpio: stmpe_gpio {
214
+
stmpe_gpio1: stmpe_gpio {
215
+
#gpio-cells = <2>;
216
+
compatible = "st,stmpe-gpio";
217
+
};
218
+
};
219
+
220
+
stmpe2: stmpe1601@44 {
221
+
compatible = "st,stmpe1601";
222
+
reg = <0x44>;
223
+
interrupts = <2 0>;
224
+
interrupt-parent = <&gpio5>;
225
+
226
+
stmpe_gpio2: stmpe_gpio {
221
227
#gpio-cells = <2>;
222
228
compatible = "st,stmpe-gpio";
223
229
};
···
291
273
>;
292
274
};
293
275
294
-
pinctrl_stmpe: stmpegrp {
276
+
pinctrl_stmpe1: stmpe1grp {
295
277
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
278
+
};
279
+
280
+
pinctrl_stmpe2: stmpe2grp {
281
+
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
296
282
};
297
283
298
284
pinctrl_uart1: uart1grp {
···
315
293
316
294
pinctrl_usbotg: usbotggrp {
317
295
fsl,pins = <
318
-
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
296
+
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
319
297
>;
320
298
};
321
299
···
366
344
&usbh1 {
367
345
vbus-supply = <®_usb_host1>;
368
346
disable-over-current;
347
+
dr_mode = "host";
369
348
status = "okay";
370
349
};
371
350
372
351
&usbotg {
373
-
vbus-supply = <®_usb_otg_vbus>;
374
352
pinctrl-names = "default";
375
353
pinctrl-0 = <&pinctrl_usbotg>;
376
354
disable-over-current;
-3
arch/arm/boot/dts/imx6q-gw5400-a.dts
-3
arch/arm/boot/dts/imx6q-gw5400-a.dts
-3
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
-3
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+11
-11
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+11
-11
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
···
26
26
/* GPIO16 -> AR8035 25MHz */
27
27
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
28
28
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
29
-
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
30
-
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
31
-
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
32
-
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
33
-
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
29
+
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
30
+
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
31
+
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
32
+
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
33
+
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
34
34
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
35
35
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
36
36
/* AR8035 pin strapping: IO voltage: pull up */
37
-
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
37
+
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
38
38
/* AR8035 pin strapping: PHYADDR#0: pull down */
39
-
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
39
+
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
40
40
/* AR8035 pin strapping: PHYADDR#1: pull down */
41
-
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
41
+
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
42
42
/* AR8035 pin strapping: MODE#1: pull up */
43
-
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
43
+
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
44
44
/* AR8035 pin strapping: MODE#3: pull up */
45
-
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
45
+
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
46
46
/* AR8035 pin strapping: MODE#0: pull down */
47
-
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
47
+
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
48
48
49
49
/*
50
50
* As the RMII pins are also connected to RGMII
+11
-2
arch/arm/boot/dts/imx6qdl.dtsi
+11
-2
arch/arm/boot/dts/imx6qdl.dtsi
···
10
10
* http://www.gnu.org/copyleft/gpl.html
11
11
*/
12
12
13
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
14
+
13
15
#include "skeleton.dtsi"
14
16
15
17
/ {
···
48
46
intc: interrupt-controller@00a01000 {
49
47
compatible = "arm,cortex-a9-gic";
50
48
#interrupt-cells = <3>;
51
-
#address-cells = <1>;
52
-
#size-cells = <1>;
53
49
interrupt-controller;
54
50
reg = <0x00a01000 0x1000>,
55
51
<0x00a00100 0x100>;
···
59
59
60
60
ckil {
61
61
compatible = "fsl,imx-ckil", "fixed-clock";
62
+
#clock-cells = <0>;
62
63
clock-frequency = <32768>;
63
64
};
64
65
65
66
ckih1 {
66
67
compatible = "fsl,imx-ckih1", "fixed-clock";
68
+
#clock-cells = <0>;
67
69
clock-frequency = <0>;
68
70
};
69
71
70
72
osc {
71
73
compatible = "fsl,imx-osc", "fixed-clock";
74
+
#clock-cells = <0>;
72
75
clock-frequency = <24000000>;
73
76
};
74
77
};
···
141
138
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
142
139
num-lanes = <1>;
143
140
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
141
+
#interrupt-cells = <1>;
142
+
interrupt-map-mask = <0 0 0 0x7>;
143
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
144
+
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
145
+
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
146
+
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
144
147
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
145
148
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
146
149
status = "disabled";
+1
arch/arm/boot/dts/imx6sl-evk.dts
+1
arch/arm/boot/dts/imx6sl-evk.dts
+2
-2
arch/arm/boot/dts/imx6sl.dtsi
+2
-2
arch/arm/boot/dts/imx6sl.dtsi
···
68
68
intc: interrupt-controller@00a01000 {
69
69
compatible = "arm,cortex-a9-gic";
70
70
#interrupt-cells = <3>;
71
-
#address-cells = <1>;
72
-
#size-cells = <1>;
73
71
interrupt-controller;
74
72
reg = <0x00a01000 0x1000>,
75
73
<0x00a00100 0x100>;
···
79
81
80
82
ckil {
81
83
compatible = "fixed-clock";
84
+
#clock-cells = <0>;
82
85
clock-frequency = <32768>;
83
86
};
84
87
85
88
osc {
86
89
compatible = "fixed-clock";
90
+
#clock-cells = <0>;
87
91
clock-frequency = <24000000>;
88
92
};
89
93
};
+1
-1
arch/arm/boot/dts/kirkwood-b3.dts
+1
-1
arch/arm/boot/dts/kirkwood-b3.dts
+1
-1
arch/arm/boot/dts/kirkwood-cloudbox.dts
+1
-1
arch/arm/boot/dts/kirkwood-cloudbox.dts
+1
-1
arch/arm/boot/dts/kirkwood-dreamplug.dts
+1
-1
arch/arm/boot/dts/kirkwood-dreamplug.dts
+1
-1
arch/arm/boot/dts/kirkwood-laplug.dts
+1
-1
arch/arm/boot/dts/kirkwood-laplug.dts
+1
-1
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+1
-1
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+2
-2
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+2
-2
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
···
32
32
flash@0 {
33
33
#address-cells = <1>;
34
34
#size-cells = <1>;
35
-
compatible = "mx25l4005a";
35
+
compatible = "mxicy,mx25l4005a";
36
36
reg = <0>;
37
37
spi-max-frequency = <20000000>;
38
38
mode = <0>;
···
50
50
status = "okay";
51
51
52
52
eeprom@50 {
53
-
compatible = "at,24c04";
53
+
compatible = "atmel,24c04";
54
54
pagesize = <16>;
55
55
reg = <0x50>;
56
56
};
+1
-1
arch/arm/boot/dts/kirkwood-nsa310.dts
+1
-1
arch/arm/boot/dts/kirkwood-nsa310.dts
+1
-1
arch/arm/boot/dts/kirkwood-nsa310a.dts
+1
-1
arch/arm/boot/dts/kirkwood-nsa310a.dts
+1
-1
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+1
-1
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+1
-1
arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+1
-1
arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+16
arch/arm/boot/dts/omap3-beagle-xm-ab.dts
+16
arch/arm/boot/dts/omap3-beagle-xm-ab.dts
···
1
+
/*
2
+
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*/
8
+
9
+
#include "omap3-beagle-xm.dts"
10
+
11
+
/ {
12
+
/* HS USB Port 2 Power enable was inverted with the xM C */
13
+
hsusb2_power: hsusb2_power_reg {
14
+
enable-active-high;
15
+
};
16
+
};
-1
arch/arm/boot/dts/omap3-devkit8000.dts
-1
arch/arm/boot/dts/omap3-devkit8000.dts
-1
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
-1
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+1
-1
arch/arm/boot/dts/omap3.dtsi
+1
-1
arch/arm/boot/dts/omap3.dtsi
···
74
74
/*
75
75
* XXX: Use a flat representation of the OMAP3 interconnect.
76
76
* The real OMAP interconnect network is quite complex.
77
-
* Since that will not bring real advantage to represent that in DT for
77
+
* Since it will not bring real advantage to represent that in DT for
78
78
* the moment, just use a fake OCP bus entry to represent the whole bus
79
79
* hierarchy.
80
80
*/
+2
-2
arch/arm/boot/dts/omap4.dtsi
+2
-2
arch/arm/boot/dts/omap4.dtsi
···
72
72
};
73
73
74
74
/*
75
-
* The soc node represents the soc top level view. It is uses for IPs
75
+
* The soc node represents the soc top level view. It is used for IPs
76
76
* that are not memory mapped in the MPU view or for the MPU itself.
77
77
*/
78
78
soc {
···
96
96
/*
97
97
* XXX: Use a flat representation of the OMAP4 interconnect.
98
98
* The real OMAP interconnect network is quite complex.
99
-
* Since that will not bring real advantage to represent that in DT for
99
+
* Since it will not bring real advantage to represent that in DT for
100
100
* the moment, just use a fake OCP bus entry to represent the whole bus
101
101
* hierarchy.
102
102
*/
+8
-2
arch/arm/boot/dts/omap5.dtsi
+8
-2
arch/arm/boot/dts/omap5.dtsi
···
93
93
};
94
94
95
95
/*
96
-
* The soc node represents the soc top level view. It is uses for IPs
96
+
* The soc node represents the soc top level view. It is used for IPs
97
97
* that are not memory mapped in the MPU view or for the MPU itself.
98
98
*/
99
99
soc {
···
107
107
/*
108
108
* XXX: Use a flat representation of the OMAP3 interconnect.
109
109
* The real OMAP interconnect network is quite complex.
110
-
* Since that will not bring real advantage to represent that in DT for
110
+
* Since it will not bring real advantage to represent that in DT for
111
111
* the moment, just use a fake OCP bus entry to represent the whole bus
112
112
* hierarchy.
113
113
*/
···
813
813
<0x4a084c00 0x40>;
814
814
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
815
815
ctrl-module = <&omap_control_usb3phy>;
816
+
clocks = <&usb_phy_cm_clk32k>,
817
+
<&sys_clkin>,
818
+
<&usb_otg_ss_refclk960m>;
819
+
clock-names = "wkupclk",
820
+
"sysclk",
821
+
"refclk";
816
822
#phy-cells = <0>;
817
823
};
818
824
};
-1
arch/arm/boot/dts/r8a7740.dtsi
-1
arch/arm/boot/dts/r8a7740.dtsi
+2
-2
arch/arm/boot/dts/r8a7790-lager.dts
+2
-2
arch/arm/boot/dts/r8a7790-lager.dts
···
141
141
};
142
142
143
143
sdhi0_pins: sd0 {
144
-
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
144
+
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
145
145
renesas,function = "sdhi0";
146
146
};
147
147
148
148
sdhi2_pins: sd2 {
149
-
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
149
+
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
150
150
renesas,function = "sdhi2";
151
151
};
152
152
+3
-3
arch/arm/boot/dts/r8a7791-koelsch.dts
+3
-3
arch/arm/boot/dts/r8a7791-koelsch.dts
···
230
230
};
231
231
232
232
sdhi0_pins: sd0 {
233
-
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
233
+
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
234
234
renesas,function = "sdhi0";
235
235
};
236
236
237
237
sdhi1_pins: sd1 {
238
-
renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
238
+
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
239
239
renesas,function = "sdhi1";
240
240
};
241
241
242
242
sdhi2_pins: sd2 {
243
-
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
243
+
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
244
244
renesas,function = "sdhi2";
245
245
};
246
246
+4
-4
arch/arm/boot/dts/rk3188.dtsi
+4
-4
arch/arm/boot/dts/rk3188.dtsi
···
149
149
150
150
uart0 {
151
151
uart0_xfer: uart0-xfer {
152
-
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
152
+
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
153
153
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
154
154
};
155
155
···
164
164
165
165
uart1 {
166
166
uart1_xfer: uart1-xfer {
167
-
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
167
+
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
168
168
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
169
169
};
170
170
···
179
179
180
180
uart2 {
181
181
uart2_xfer: uart2-xfer {
182
-
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
182
+
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
183
183
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
184
184
};
185
185
/* no rts / cts for uart2 */
···
187
187
188
188
uart3 {
189
189
uart3_xfer: uart3-xfer {
190
-
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
190
+
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
191
191
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
192
192
};
193
193
-1
arch/arm/boot/dts/sh73a0.dtsi
-1
arch/arm/boot/dts/sh73a0.dtsi
-13
arch/arm/boot/dts/tegra124.dtsi
-13
arch/arm/boot/dts/tegra124.dtsi
···
233
233
status = "disabled";
234
234
};
235
235
236
-
serial@0,70006400 {
237
-
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
238
-
reg = <0x0 0x70006400 0x0 0x40>;
239
-
reg-shift = <2>;
240
-
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
241
-
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
242
-
resets = <&tegra_car 66>;
243
-
reset-names = "serial";
244
-
dmas = <&apbdma 20>, <&apbdma 20>;
245
-
dma-names = "rx", "tx";
246
-
status = "disabled";
247
-
};
248
-
249
236
pwm@0,7000a000 {
250
237
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
251
238
reg = <0x0 0x7000a000 0x0 0x100>;
+2
arch/arm/boot/dts/vf610-twr.dts
+2
arch/arm/boot/dts/vf610-twr.dts
+2
-2
arch/arm/boot/dts/vf610.dtsi
+2
-2
arch/arm/boot/dts/vf610.dtsi
···
45
45
46
46
sxosc {
47
47
compatible = "fixed-clock";
48
+
#clock-cells = <0>;
48
49
clock-frequency = <32768>;
49
50
};
50
51
51
52
fxosc {
52
53
compatible = "fixed-clock";
54
+
#clock-cells = <0>;
53
55
clock-frequency = <24000000>;
54
56
};
55
57
};
···
74
72
intc: interrupt-controller@40002000 {
75
73
compatible = "arm,cortex-a9-gic";
76
74
#interrupt-cells = <3>;
77
-
#address-cells = <1>;
78
-
#size-cells = <1>;
79
75
interrupt-controller;
80
76
reg = <0x40003000 0x1000>,
81
77
<0x40002100 0x100>;
+23
arch/arm/boot/dts/zynq-7000.dtsi
+23
arch/arm/boot/dts/zynq-7000.dtsi
···
24
24
device_type = "cpu";
25
25
reg = <0>;
26
26
clocks = <&clkc 3>;
27
+
clock-latency = <1000>;
27
28
operating-points = <
28
29
/* kHz uV */
29
30
666667 1000000
···
54
53
#size-cells = <1>;
55
54
interrupt-parent = <&intc>;
56
55
ranges;
56
+
57
+
i2c0: zynq-i2c@e0004000 {
58
+
compatible = "cdns,i2c-r1p10";
59
+
status = "disabled";
60
+
clocks = <&clkc 38>;
61
+
interrupt-parent = <&intc>;
62
+
interrupts = <0 25 4>;
63
+
reg = <0xe0004000 0x1000>;
64
+
#address-cells = <1>;
65
+
#size-cells = <0>;
66
+
};
67
+
68
+
i2c1: zynq-i2c@e0005000 {
69
+
compatible = "cdns,i2c-r1p10";
70
+
status = "disabled";
71
+
clocks = <&clkc 39>;
72
+
interrupt-parent = <&intc>;
73
+
interrupts = <0 48 4>;
74
+
reg = <0xe0005000 0x1000>;
75
+
#address-cells = <1>;
76
+
#size-cells = <0>;
77
+
};
57
78
58
79
intc: interrupt-controller@f8f01000 {
59
80
compatible = "arm,cortex-a9-gic";
+76
arch/arm/boot/dts/zynq-zc702.dts
+76
arch/arm/boot/dts/zynq-zc702.dts
···
34
34
phy-mode = "rgmii";
35
35
};
36
36
37
+
&i2c0 {
38
+
status = "okay";
39
+
clock-frequency = <400000>;
40
+
41
+
i2cswitch@74 {
42
+
compatible = "nxp,pca9548";
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
45
+
reg = <0x74>;
46
+
47
+
i2c@0 {
48
+
#address-cells = <1>;
49
+
#size-cells = <0>;
50
+
reg = <0>;
51
+
si570: clock-generator@5d {
52
+
#clock-cells = <0>;
53
+
compatible = "silabs,si570";
54
+
temperature-stability = <50>;
55
+
reg = <0x5d>;
56
+
factory-fout = <156250000>;
57
+
clock-frequency = <148500000>;
58
+
};
59
+
};
60
+
61
+
i2c@2 {
62
+
#address-cells = <1>;
63
+
#size-cells = <0>;
64
+
reg = <2>;
65
+
eeprom@54 {
66
+
compatible = "at,24c08";
67
+
reg = <0x54>;
68
+
};
69
+
};
70
+
71
+
i2c@3 {
72
+
#address-cells = <1>;
73
+
#size-cells = <0>;
74
+
reg = <3>;
75
+
gpio@21 {
76
+
compatible = "ti,tca6416";
77
+
reg = <0x21>;
78
+
gpio-controller;
79
+
#gpio-cells = <2>;
80
+
};
81
+
};
82
+
83
+
i2c@4 {
84
+
#address-cells = <1>;
85
+
#size-cells = <0>;
86
+
reg = <4>;
87
+
rtc@51 {
88
+
compatible = "nxp,pcf8563";
89
+
reg = <0x51>;
90
+
};
91
+
};
92
+
93
+
i2c@7 {
94
+
#address-cells = <1>;
95
+
#size-cells = <0>;
96
+
reg = <7>;
97
+
hwmon@52 {
98
+
compatible = "ti,ucd9248";
99
+
reg = <52>;
100
+
};
101
+
hwmon@53 {
102
+
compatible = "ti,ucd9248";
103
+
reg = <53>;
104
+
};
105
+
hwmon@54 {
106
+
compatible = "ti,ucd9248";
107
+
reg = <54>;
108
+
};
109
+
};
110
+
};
111
+
};
112
+
37
113
&sdhci0 {
38
114
status = "okay";
39
115
};
+68
arch/arm/boot/dts/zynq-zc706.dts
+68
arch/arm/boot/dts/zynq-zc706.dts
···
35
35
phy-mode = "rgmii";
36
36
};
37
37
38
+
&i2c0 {
39
+
status = "okay";
40
+
clock-frequency = <400000>;
41
+
42
+
i2cswitch@74 {
43
+
compatible = "nxp,pca9548";
44
+
#address-cells = <1>;
45
+
#size-cells = <0>;
46
+
reg = <0x74>;
47
+
48
+
i2c@0 {
49
+
#address-cells = <1>;
50
+
#size-cells = <0>;
51
+
reg = <0>;
52
+
si570: clock-generator@5d {
53
+
#clock-cells = <0>;
54
+
compatible = "silabs,si570";
55
+
temperature-stability = <50>;
56
+
reg = <0x5d>;
57
+
factory-fout = <156250000>;
58
+
clock-frequency = <148500000>;
59
+
};
60
+
};
61
+
62
+
i2c@2 {
63
+
#address-cells = <1>;
64
+
#size-cells = <0>;
65
+
reg = <2>;
66
+
eeprom@54 {
67
+
compatible = "at,24c08";
68
+
reg = <0x54>;
69
+
};
70
+
};
71
+
72
+
i2c@3 {
73
+
#address-cells = <1>;
74
+
#size-cells = <0>;
75
+
reg = <3>;
76
+
gpio@21 {
77
+
compatible = "ti,tca6416";
78
+
reg = <0x21>;
79
+
gpio-controller;
80
+
#gpio-cells = <2>;
81
+
};
82
+
};
83
+
84
+
i2c@4 {
85
+
#address-cells = <1>;
86
+
#size-cells = <0>;
87
+
reg = <4>;
88
+
rtc@51 {
89
+
compatible = "nxp,pcf8563";
90
+
reg = <0x51>;
91
+
};
92
+
};
93
+
94
+
i2c@7 {
95
+
#address-cells = <1>;
96
+
#size-cells = <0>;
97
+
reg = <7>;
98
+
ucd90120@65 {
99
+
compatible = "ti,ucd90120";
100
+
reg = <0x65>;
101
+
};
102
+
};
103
+
};
104
+
};
105
+
38
106
&sdhci0 {
39
107
status = "okay";
40
108
};
+1
-1
arch/arm/configs/omap2plus_defconfig
+1
-1
arch/arm/configs/omap2plus_defconfig
+2
-2
arch/arm/configs/u300_defconfig
+2
-2
arch/arm/configs/u300_defconfig
···
11
11
CONFIG_MODULE_UNLOAD=y
12
12
# CONFIG_LBDAF is not set
13
13
# CONFIG_BLK_DEV_BSG is not set
14
+
CONFIG_PARTITION_ADVANCED=y
14
15
# CONFIG_IOSCHED_CFQ is not set
15
16
# CONFIG_ARCH_MULTI_V7 is not set
16
17
CONFIG_ARCH_U300=y
···
22
21
CONFIG_ZBOOT_ROM_BSS=0x0
23
22
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
24
23
CONFIG_CPU_IDLE=y
25
-
CONFIG_FPE_NWFPE=y
26
24
# CONFIG_SUSPEND is not set
27
25
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
28
26
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
···
64
64
CONFIG_NLS_CODEPAGE_437=y
65
65
CONFIG_NLS_ISO8859_1=y
66
66
CONFIG_PRINTK_TIME=y
67
+
CONFIG_DEBUG_INFO=y
67
68
CONFIG_DEBUG_FS=y
68
69
# CONFIG_SCHED_DEBUG is not set
69
70
CONFIG_TIMER_STATS=y
70
71
# CONFIG_DEBUG_PREEMPT is not set
71
-
CONFIG_DEBUG_INFO=y
+15
-9
arch/arm/configs/u8500_defconfig
+15
-9
arch/arm/configs/u8500_defconfig
···
1
1
# CONFIG_SWAP is not set
2
2
CONFIG_SYSVIPC=y
3
-
CONFIG_NO_HZ=y
3
+
CONFIG_NO_HZ_IDLE=y
4
4
CONFIG_HIGH_RES_TIMERS=y
5
5
CONFIG_BLK_DEV_INITRD=y
6
6
CONFIG_KALLSYMS_ALL=y
7
7
CONFIG_MODULES=y
8
8
CONFIG_MODULE_UNLOAD=y
9
9
# CONFIG_BLK_DEV_BSG is not set
10
+
CONFIG_PARTITION_ADVANCED=y
10
11
CONFIG_ARCH_U8500=y
11
12
CONFIG_MACH_HREFV60=y
12
13
CONFIG_MACH_SNOWBALL=y
13
-
CONFIG_MACH_UX500_DT=y
14
14
CONFIG_SMP=y
15
15
CONFIG_NR_CPUS=2
16
16
CONFIG_PREEMPT=y
···
34
34
CONFIG_IP_PNP_DHCP=y
35
35
CONFIG_NETFILTER=y
36
36
CONFIG_PHONET=y
37
-
# CONFIG_WIRELESS is not set
37
+
CONFIG_CFG80211=y
38
+
CONFIG_CFG80211_DEBUGFS=y
39
+
CONFIG_MAC80211=y
40
+
CONFIG_MAC80211_LEDS=y
38
41
CONFIG_CAIF=y
39
42
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
43
+
CONFIG_DEVTMPFS=y
44
+
CONFIG_DEVTMPFS_MOUNT=y
40
45
CONFIG_BLK_DEV_RAM=y
41
46
CONFIG_BLK_DEV_RAM_SIZE=65536
42
47
CONFIG_SENSORS_BH1780=y
43
48
CONFIG_NETDEVICES=y
44
49
CONFIG_SMSC911X=y
45
50
CONFIG_SMSC_PHY=y
46
-
# CONFIG_WLAN is not set
51
+
CONFIG_CW1200=y
52
+
CONFIG_CW1200_WLAN_SDIO=y
47
53
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
48
54
CONFIG_INPUT_EVDEV=y
49
55
# CONFIG_KEYBOARD_ATKBD is not set
···
91
85
CONFIG_USB_GADGET=y
92
86
CONFIG_USB_ETH=m
93
87
CONFIG_MMC=y
94
-
CONFIG_MMC_UNSAFE_RESUME=y
95
-
# CONFIG_MMC_BLOCK_BOUNCE is not set
96
88
CONFIG_MMC_ARMMMCI=y
97
89
CONFIG_NEW_LEDS=y
98
90
CONFIG_LEDS_CLASS=y
99
91
CONFIG_LEDS_LM3530=y
100
92
CONFIG_LEDS_GPIO=y
101
93
CONFIG_LEDS_LP5521=y
102
-
CONFIG_LEDS_TRIGGERS=y
103
94
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
104
95
CONFIG_RTC_CLASS=y
105
96
CONFIG_RTC_DRV_AB8500=y
···
106
103
CONFIG_STAGING=y
107
104
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
108
105
CONFIG_HSEM_U8500=y
106
+
CONFIG_IIO=y
107
+
CONFIG_IIO_ST_ACCEL_3AXIS=y
108
+
CONFIG_IIO_ST_GYRO_3AXIS=y
109
+
CONFIG_IIO_ST_MAGN_3AXIS=y
110
+
CONFIG_IIO_ST_PRESS=y
109
111
CONFIG_EXT2_FS=y
110
112
CONFIG_EXT2_FS_XATTR=y
111
113
CONFIG_EXT2_FS_POSIX_ACL=y
···
118
110
CONFIG_EXT3_FS=y
119
111
CONFIG_EXT4_FS=y
120
112
CONFIG_VFAT_FS=y
121
-
CONFIG_DEVTMPFS=y
122
-
CONFIG_DEVTMPFS_MOUNT=y
123
113
CONFIG_TMPFS=y
124
114
CONFIG_TMPFS_POSIX_ACL=y
125
115
# CONFIG_MISC_FILESYSTEMS is not set
+19
-10
arch/arm/mach-imx/clk-imx6q.c
+19
-10
arch/arm/mach-imx/clk-imx6q.c
···
208
208
* the "output_enable" bit as a gate, even though it's really just
209
209
* enabling clock output.
210
210
*/
211
-
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
212
-
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
211
+
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
212
+
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
213
213
214
214
/* name parent_name reg idx */
215
215
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
···
258
258
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
259
259
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
260
260
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
261
-
clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
262
-
clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
263
-
clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
264
-
clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
265
-
clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
266
-
clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
267
-
clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
268
-
clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
261
+
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
262
+
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
263
+
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
264
+
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
265
+
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
266
+
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
267
+
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
268
+
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
269
269
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
270
270
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
271
271
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
···
444
444
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
445
445
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
446
446
}
447
+
448
+
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
449
+
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
450
+
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
451
+
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
452
+
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
453
+
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
454
+
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
455
+
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
447
456
448
457
/*
449
458
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
+1
-1
arch/arm/mach-omap2/board-rx51-video.c
+1
-1
arch/arm/mach-omap2/board-rx51-video.c
+2
-2
arch/arm/mach-omap2/clkt_dpll.c
+2
-2
arch/arm/mach-omap2/clkt_dpll.c
···
209
209
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
210
210
v == OMAP3XXX_EN_DPLL_FRBYPASS)
211
211
return 1;
212
-
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
212
+
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
213
213
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
214
214
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
215
215
v == OMAP4XXX_EN_DPLL_MNBYPASS)
···
255
255
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
256
256
v == OMAP3XXX_EN_DPLL_FRBYPASS)
257
257
return __clk_get_rate(dd->clk_bypass);
258
-
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
258
+
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
259
259
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
260
260
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
261
261
v == OMAP4XXX_EN_DPLL_MNBYPASS)
+13
-2
arch/arm/mach-omap2/gpmc.c
+13
-2
arch/arm/mach-omap2/gpmc.c
···
501
501
int r;
502
502
503
503
spin_lock(&gpmc_mem_lock);
504
-
r = release_resource(&gpmc_cs_mem[cs]);
504
+
r = release_resource(res);
505
505
res->start = 0;
506
506
res->end = 0;
507
507
spin_unlock(&gpmc_mem_lock);
···
527
527
pr_err("%s: requested chip-select is disabled\n", __func__);
528
528
return -ENODEV;
529
529
}
530
+
531
+
/*
532
+
* Make sure we ignore any device offsets from the GPMC partition
533
+
* allocated for the chip select and that the new base confirms
534
+
* to the GPMC 16MB minimum granularity.
535
+
*/
536
+
base &= ~(SZ_16M - 1);
537
+
530
538
gpmc_cs_get_memconf(cs, &old_base, &size);
531
539
if (base == old_base)
532
540
return 0;
···
594
586
595
587
void gpmc_cs_free(int cs)
596
588
{
589
+
struct resource *res = &gpmc_cs_mem[cs];
590
+
597
591
spin_lock(&gpmc_mem_lock);
598
592
if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
599
593
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
···
604
594
return;
605
595
}
606
596
gpmc_cs_disable_mem(cs);
607
-
release_resource(&gpmc_cs_mem[cs]);
597
+
if (res->flags)
598
+
release_resource(res);
608
599
gpmc_cs_set_reserved(cs, 0);
609
600
spin_unlock(&gpmc_mem_lock);
610
601
}
+2
-1
arch/arm/mach-omap2/omap_hwmod.c
+2
-1
arch/arm/mach-omap2/omap_hwmod.c
···
2546
2546
return -EINVAL;
2547
2547
}
2548
2548
2549
-
if (np)
2549
+
if (np) {
2550
2550
if (of_find_property(np, "ti,no-reset-on-init", NULL))
2551
2551
oh->flags |= HWMOD_INIT_NO_RESET;
2552
2552
if (of_find_property(np, "ti,no-idle-on-init", NULL))
2553
2553
oh->flags |= HWMOD_INIT_NO_IDLE;
2554
+
}
2554
2555
2555
2556
oh->_state = _HWMOD_STATE_INITIALIZED;
2556
2557
+2
-2
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+2
-2
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
···
1964
1964
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1965
1965
.name = "usb_host_hs",
1966
1966
.class = &omap3xxx_usb_host_hs_hwmod_class,
1967
-
.clkdm_name = "l3_init_clkdm",
1967
+
.clkdm_name = "usbhost_clkdm",
1968
1968
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
1969
1969
.main_clk = "usbhost_48m_fck",
1970
1970
.prcm = {
···
2047
2047
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2048
2048
.name = "usb_tll_hs",
2049
2049
.class = &omap3xxx_usb_tll_hs_hwmod_class,
2050
-
.clkdm_name = "l3_init_clkdm",
2050
+
.clkdm_name = "core_l4_clkdm",
2051
2051
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2052
2052
.main_clk = "usbtll_fck",
2053
2053
.prcm = {
-4
arch/arm/mach-omap2/pm34xx.c
-4
arch/arm/mach-omap2/pm34xx.c
···
330
330
omap3_sram_restore_context();
331
331
omap2_sms_restore_context();
332
332
}
333
-
if (core_next_state == PWRDM_POWER_OFF)
334
-
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
335
-
OMAP3430_GR_MOD,
336
-
OMAP3_PRM_VOLTCTRL_OFFSET);
337
333
}
338
334
omap3_intc_resume_idle();
339
335
+1
arch/arm/mach-pxa/include/mach/hx4700.h
+1
arch/arm/mach-pxa/include/mach/hx4700.h
+1
-1
arch/arm/mach-rockchip/platsmp.c
+1
-1
arch/arm/mach-rockchip/platsmp.c
+1
arch/arm/mach-shmobile/board-armadillo800eva.c
+1
arch/arm/mach-shmobile/board-armadillo800eva.c
+1
-3
arch/arm/mach-shmobile/board-lager.c
+1
-3
arch/arm/mach-shmobile/board-lager.c
···
588
588
.card = "SSI01-AK4643",
589
589
.codec = "ak4642-codec.2-0012",
590
590
.platform = "rcar_sound",
591
-
.daifmt = SND_SOC_DAIFMT_LEFT_J,
591
+
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
592
592
.cpu_dai = {
593
593
.name = "rcar_sound",
594
-
.fmt = SND_SOC_DAIFMT_CBS_CFS,
595
594
},
596
595
.codec_dai = {
597
596
.name = "ak4642-hifi",
598
-
.fmt = SND_SOC_DAIFMT_CBM_CFM,
599
597
.sysclk = 11289600,
600
598
},
601
599
};
+1
-1
arch/arm/mach-spear/time.c
+1
-1
arch/arm/mach-spear/time.c
-3
arch/arm/mach-tegra/Kconfig
-3
arch/arm/mach-tegra/Kconfig
+5
-2
arch/arm/mach-vexpress/dcscb.c
+5
-2
arch/arm/mach-vexpress/dcscb.c
···
51
51
static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
52
52
{
53
53
unsigned int rst_hold, cpumask = (1 << cpu);
54
-
unsigned int all_mask = dcscb_allcpus_mask[cluster];
54
+
unsigned int all_mask;
55
55
56
56
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
57
57
if (cpu >= 4 || cluster >= 2)
58
58
return -EINVAL;
59
+
60
+
all_mask = dcscb_allcpus_mask[cluster];
59
61
60
62
/*
61
63
* Since this is called with IRQs enabled, and no arch_spin_lock_irq
···
103
101
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
104
102
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
105
103
cpumask = (1 << cpu);
106
-
all_mask = dcscb_allcpus_mask[cluster];
107
104
108
105
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
109
106
BUG_ON(cpu >= 4 || cluster >= 2);
107
+
108
+
all_mask = dcscb_allcpus_mask[cluster];
110
109
111
110
__mcpm_cpu_going_down(cpu, cluster);
112
111
+2
-2
arch/arm/mach-vexpress/spc.c
+2
-2
arch/arm/mach-vexpress/spc.c
···
392
392
* +--------------------------+
393
393
* | 31 20 | 19 0 |
394
394
* +--------------------------+
395
-
* | u_volt | freq(kHz) |
395
+
* | m_volt | freq(kHz) |
396
396
* +--------------------------+
397
397
*/
398
398
#define MULT_FACTOR 20
···
414
414
ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
415
415
if (!ret) {
416
416
opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
417
-
opps->u_volt = data >> VOLT_SHIFT;
417
+
opps->u_volt = (data >> VOLT_SHIFT) * 1000;
418
418
} else {
419
419
break;
420
420
}
-3
drivers/clk/tegra/clk-tegra124.c
-3
drivers/clk/tegra/clk-tegra124.c
···
764
764
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
765
765
[tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
766
766
[tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
767
-
[tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
768
767
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
769
768
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
770
769
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
···
808
809
[tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
809
810
[tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
810
811
[tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
811
-
[tegra_clk_ndspeed] = { .dt_id = TEGRA124_CLK_NDSPEED, .present = true },
812
812
[tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
813
813
[tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
814
814
[tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
···
950
952
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
951
953
[tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
952
954
[tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
953
-
[tegra_clk_uarte] = { .dt_id = TEGRA124_CLK_UARTE, .present = true },
954
955
};
955
956
956
957
static struct tegra_devclk devclks[] __initdata = {
+1
-1
drivers/clk/versatile/clk-vexpress-osc.c
+1
-1
drivers/clk/versatile/clk-vexpress-osc.c
+10
-9
drivers/power/reset/vexpress-poweroff.c
+10
-9
drivers/power/reset/vexpress-poweroff.c
···
11
11
* Copyright (C) 2012 ARM Limited
12
12
*/
13
13
14
-
#include <linux/jiffies.h>
14
+
#include <linux/delay.h>
15
15
#include <linux/of.h>
16
16
#include <linux/of_device.h>
17
17
#include <linux/platform_device.h>
···
23
23
static void vexpress_reset_do(struct device *dev, const char *what)
24
24
{
25
25
int err = -ENOENT;
26
-
struct vexpress_config_func *func =
27
-
vexpress_config_func_get_by_dev(dev);
26
+
struct vexpress_config_func *func = dev_get_drvdata(dev);
28
27
29
28
if (func) {
30
-
unsigned long timeout;
31
-
32
29
err = vexpress_config_write(func, 0, 0);
33
-
34
-
timeout = jiffies + HZ;
35
-
while (time_before(jiffies, timeout))
36
-
cpu_relax();
30
+
if (!err)
31
+
mdelay(1000);
37
32
}
38
33
39
34
dev_emerg(dev, "Unable to %s (%d)\n", what, err);
···
91
96
enum vexpress_reset_func func;
92
97
const struct of_device_id *match =
93
98
of_match_device(vexpress_reset_of_match, &pdev->dev);
99
+
struct vexpress_config_func *config_func;
94
100
95
101
if (match)
96
102
func = (enum vexpress_reset_func)match->data;
97
103
else
98
104
func = pdev->id_entry->driver_data;
105
+
106
+
config_func = vexpress_config_func_get_by_dev(&pdev->dev);
107
+
if (!config_func)
108
+
return -EINVAL;
109
+
dev_set_drvdata(&pdev->dev, config_func);
99
110
100
111
switch (func) {
101
112
case FUNC_SHUTDOWN:
+3
-3
include/dt-bindings/clock/tegra124-car.h
+3
-3
include/dt-bindings/clock/tegra124-car.h
···
29
29
/* 10 (register bit affects spdif_in and spdif_out) */
30
30
#define TEGRA124_CLK_I2S1 11
31
31
#define TEGRA124_CLK_I2C1 12
32
-
#define TEGRA124_CLK_NDFLASH 13
32
+
/* 13 */
33
33
#define TEGRA124_CLK_SDMMC1 14
34
34
#define TEGRA124_CLK_SDMMC4 15
35
35
/* 16 */
···
83
83
84
84
/* 64 */
85
85
#define TEGRA124_CLK_UARTD 65
86
-
#define TEGRA124_CLK_UARTE 66
86
+
/* 66 */
87
87
#define TEGRA124_CLK_I2C3 67
88
88
#define TEGRA124_CLK_SBC4 68
89
89
#define TEGRA124_CLK_SDMMC3 69
···
97
97
#define TEGRA124_CLK_TRACE 77
98
98
#define TEGRA124_CLK_SOC_THERM 78
99
99
#define TEGRA124_CLK_DTV 79
100
-
#define TEGRA124_CLK_NDSPEED 80
100
+
/* 80 */
101
101
#define TEGRA124_CLK_I2CSLOW 81
102
102
#define TEGRA124_CLK_DSIB 82
103
103
#define TEGRA124_CLK_TSEC 83