-3

Documentation/devicetree/bindings/iio/addac/adi,ad74115.yaml

reviewed

··· 216 216 description: Whether to enable burnout current for EXT1. 217 217 218 218 adi,ext1-burnout-current-nanoamp: 219 219 - $ref: /schemas/types.yaml#/definitions/uint32 220 219 description: 221 220 Burnout current in nanoamps to be applied to EXT1. 222 221 enum: [0, 50, 500, 1000, 10000] ··· 232 233 description: Whether to enable burnout current for EXT2. 233 234 234 235 adi,ext2-burnout-current-nanoamp: 235 235 - $ref: /schemas/types.yaml#/definitions/uint32 236 236 description: Burnout current in nanoamps to be applied to EXT2. 237 237 enum: [0, 50, 500, 1000, 10000] 238 238 default: 0 ··· 247 249 description: Whether to enable burnout current for VIOUT. 248 250 249 251 adi,viout-burnout-current-nanoamp: 250 250 - $ref: /schemas/types.yaml#/definitions/uint32 251 252 description: Burnout current in nanoamps to be applied to VIOUT. 252 253 enum: [0, 1000, 10000] 253 254 default: 0

+1

drivers/android/binder.c

reviewed

··· 6617 6617 6618 6618 err_alloc_device_names_failed: 6619 6619 debugfs_remove_recursive(binder_debugfs_dir_entry_root); 6620 6620 + binder_alloc_shrinker_exit(); 6620 6621 6621 6622 return ret; 6622 6623 }

+6

drivers/android/binder_alloc.c

reviewed

··· 1087 1087 return ret; 1088 1088 } 1089 1089 1090 1090 + void binder_alloc_shrinker_exit(void) 1091 1091 + { 1092 1092 + unregister_shrinker(&binder_shrinker); 1093 1093 + list_lru_destroy(&binder_alloc_lru); 1094 1094 + } 1095 1095 + 1090 1096 /** 1091 1097 * check_buffer() - verify that buffer/offset is safe to access 1092 1098 * @alloc: binder_alloc for this proc

+1

drivers/android/binder_alloc.h

reviewed

··· 129 129 int pid); 130 130 extern void binder_alloc_init(struct binder_alloc *alloc); 131 131 extern int binder_alloc_shrinker_init(void); 132 132 + extern void binder_alloc_shrinker_exit(void); 132 133 extern void binder_alloc_vma_close(struct binder_alloc *alloc); 133 134 extern struct binder_buffer * 134 135 binder_alloc_prepare_to_free(struct binder_alloc *alloc,

+7 -7

drivers/counter/Kconfig

reviewed

··· 3 3 # Counter devices 4 4 # 5 5 6 6 - menuconfig COUNTER 7 7 - tristate "Counter support" 8 8 - help 9 9 - This enables counter device support through the Generic Counter 10 10 - interface. You only need to enable this, if you also want to enable 11 11 - one or more of the counter device drivers below. 12 12 - 13 6 config I8254 14 7 tristate 15 8 select COUNTER ··· 17 24 components. 18 25 19 26 If built as a module its name will be i8254. 27 27 + 28 28 + menuconfig COUNTER 29 29 + tristate "Counter support" 30 30 + help 31 31 + This enables counter device support through the Generic Counter 32 32 + interface. You only need to enable this, if you also want to enable 33 33 + one or more of the counter device drivers below. 20 34 21 35 if COUNTER 22 36

+8 -8

drivers/iio/adc/ad7192.c

reviewed

··· 62 62 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 63 63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 64 64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 65 65 - #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ 66 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 67 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 68 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ ··· 90 91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92 92 93 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 94 94 + #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 93 95 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 94 96 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 95 97 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ ··· 472 472 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 473 473 struct ad7192_state *st = iio_priv(indio_dev); 474 474 475 475 - return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); 475 475 + return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX)); 476 476 } 477 477 478 478 static ssize_t ad7192_show_bridge_switch(struct device *dev, ··· 513 513 514 514 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 515 515 break; 516 516 - case AD7192_REG_MODE: 516 516 + case AD7192_REG_CONF: 517 517 if (val) 518 518 - st->mode |= AD7192_MODE_ACX; 518 518 + st->conf |= AD7192_CONF_ACX; 519 519 else 520 520 - st->mode &= ~AD7192_MODE_ACX; 520 520 + st->conf &= ~AD7192_CONF_ACX; 521 521 522 522 - ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 522 522 + ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 523 523 break; 524 524 default: 525 525 ret = -EINVAL; ··· 579 579 580 580 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 581 581 ad7192_show_ac_excitation, ad7192_set, 582 582 - AD7192_REG_MODE); 582 582 + AD7192_REG_CONF); 583 583 584 584 static struct attribute *ad7192_attributes[] = { 585 585 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 586 586 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 587 587 - &iio_dev_attr_ac_excitation_en.dev_attr.attr, 588 587 NULL 589 588 }; 590 589 ··· 594 595 static struct attribute *ad7195_attributes[] = { 595 596 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 596 597 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 598 598 + &iio_dev_attr_ac_excitation_en.dev_attr.attr, 597 599 NULL 598 600 }; 599 601

+6 -3

drivers/iio/adc/ina2xx-adc.c

reviewed

··· 124 124 enum ina2xx_ids { ina219, ina226 }; 125 125 126 126 struct ina2xx_config { 127 127 + const char *name; 127 128 u16 config_default; 128 129 int calibration_value; 129 130 int shunt_voltage_lsb; /* nV */ ··· 156 155 157 156 static const struct ina2xx_config ina2xx_config[] = { 158 157 [ina219] = { 158 158 + .name = "ina219", 159 159 .config_default = INA219_CONFIG_DEFAULT, 160 160 .calibration_value = 4096, 161 161 .shunt_voltage_lsb = 10000, ··· 166 164 .chip_id = ina219, 167 165 }, 168 166 [ina226] = { 167 167 + .name = "ina226", 169 168 .config_default = INA226_CONFIG_DEFAULT, 170 169 .calibration_value = 2048, 171 170 .shunt_voltage_lsb = 2500, ··· 999 996 /* Patch the current config register with default. */ 1000 997 val = chip->config->config_default; 1001 998 1002 1002 - if (id->driver_data == ina226) { 999 999 + if (type == ina226) { 1003 1000 ina226_set_average(chip, INA226_DEFAULT_AVG, &val); 1004 1001 ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); 1005 1002 ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); ··· 1018 1015 } 1019 1016 1020 1017 indio_dev->modes = INDIO_DIRECT_MODE; 1021 1021 - if (id->driver_data == ina226) { 1018 1018 + if (type == ina226) { 1022 1019 indio_dev->channels = ina226_channels; 1023 1020 indio_dev->num_channels = ARRAY_SIZE(ina226_channels); 1024 1021 indio_dev->info = &ina226_info; ··· 1027 1024 indio_dev->num_channels = ARRAY_SIZE(ina219_channels); 1028 1025 indio_dev->info = &ina219_info; 1029 1026 } 1030 1030 - indio_dev->name = id->name; 1027 1027 + indio_dev->name = id ? id->name : chip->config->name; 1031 1028 1032 1029 ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev, 1033 1030 &ina2xx_setup_ops);

+12 -11

drivers/iio/adc/meson_saradc.c

reviewed

··· 916 916 goto err_vref; 917 917 } 918 918 919 919 - ret = clk_prepare_enable(priv->core_clk); 920 920 - if (ret) { 921 921 - dev_err(dev, "failed to enable core clk\n"); 922 922 - goto err_core_clk; 923 923 - } 924 924 - 925 919 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); 926 920 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 927 921 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); ··· 942 948 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 943 949 MESON_SAR_ADC_REG3_ADC_EN, 0); 944 950 meson_sar_adc_set_bandgap(indio_dev, false); 945 945 - clk_disable_unprepare(priv->core_clk); 946 946 - err_core_clk: 947 951 regulator_disable(priv->vref); 948 952 err_vref: 949 953 meson_sar_adc_unlock(indio_dev); ··· 968 976 MESON_SAR_ADC_REG3_ADC_EN, 0); 969 977 970 978 meson_sar_adc_set_bandgap(indio_dev, false); 971 971 - 972 972 - clk_disable_unprepare(priv->core_clk); 973 979 974 980 regulator_disable(priv->vref); 975 981 ··· 1201 1211 if (IS_ERR(priv->clkin)) 1202 1212 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); 1203 1213 1204 1204 - priv->core_clk = devm_clk_get(dev, "core"); 1214 1214 + priv->core_clk = devm_clk_get_enabled(dev, "core"); 1205 1215 if (IS_ERR(priv->core_clk)) 1206 1216 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); 1207 1217 ··· 1284 1294 static int meson_sar_adc_suspend(struct device *dev) 1285 1295 { 1286 1296 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1297 1297 + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1287 1298 1288 1299 meson_sar_adc_hw_disable(indio_dev); 1300 1300 + 1301 1301 + clk_disable_unprepare(priv->core_clk); 1289 1302 1290 1303 return 0; 1291 1304 } ··· 1296 1303 static int meson_sar_adc_resume(struct device *dev) 1297 1304 { 1298 1305 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1306 1306 + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1307 1307 + int ret; 1308 1308 + 1309 1309 + ret = clk_prepare_enable(priv->core_clk); 1310 1310 + if (ret) { 1311 1311 + dev_err(dev, "failed to enable core clk\n"); 1312 1312 + return ret; 1313 1313 + } 1299 1314 1300 1315 return meson_sar_adc_hw_enable(indio_dev); 1301 1316 }

+1 -1

drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c

reviewed

··· 253 253 platform_set_drvdata(pdev, indio_dev); 254 254 255 255 state->ec = ec->ec_dev; 256 256 - state->msg = devm_kzalloc(&pdev->dev, 256 256 + state->msg = devm_kzalloc(&pdev->dev, sizeof(*state->msg) + 257 257 max((u16)sizeof(struct ec_params_motion_sense), 258 258 state->ec->max_response), GFP_KERNEL); 259 259 if (!state->msg)

+4 -1

drivers/iio/frequency/admv1013.c

reviewed

··· 344 344 345 345 static int admv1013_update_mixer_vgate(struct admv1013_state *st) 346 346 { 347 347 - unsigned int vcm, mixer_vgate; 347 347 + unsigned int mixer_vgate; 348 348 + int vcm; 348 349 349 350 vcm = regulator_get_voltage(st->reg); 351 351 + if (vcm < 0) 352 352 + return vcm; 350 353 351 354 if (vcm < 1800000) 352 355 mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;

+1 -1

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c

reviewed

··· 2687 2687 static int lsm6dsx_get_acpi_mount_matrix(struct device *dev, 2688 2688 struct iio_mount_matrix *orientation) 2689 2689 { 2690 2690 - return false; 2690 2690 + return -EOPNOTSUPP; 2691 2691 } 2692 2692 2693 2693 #endif

+3 -2

drivers/iio/industrialio-core.c

reviewed

··· 1888 1888 int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod) 1889 1889 { 1890 1890 struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); 1891 1891 - struct fwnode_handle *fwnode; 1891 1891 + struct fwnode_handle *fwnode = NULL; 1892 1892 int ret; 1893 1893 1894 1894 if (!indio_dev->info) ··· 1899 1899 /* If the calling driver did not initialize firmware node, do it here */ 1900 1900 if (dev_fwnode(&indio_dev->dev)) 1901 1901 fwnode = dev_fwnode(&indio_dev->dev); 1902 1902 - else 1902 1902 + /* The default dummy IIO device has no parent */ 1903 1903 + else if (indio_dev->dev.parent) 1903 1904 fwnode = dev_fwnode(indio_dev->dev.parent); 1904 1905 device_set_node(&indio_dev->dev, fwnode); 1905 1906

+19 -3

drivers/iio/light/rohm-bu27008.c

reviewed

··· 190 190 .address = BU27008_REG_##data##_LO, \ 191 191 .scan_index = BU27008_##color, \ 192 192 .scan_type = { \ 193 193 - .sign = 's', \ 193 193 + .sign = 'u', \ 194 194 .realbits = 16, \ 195 195 .storagebits = 16, \ 196 196 .endianness = IIO_LE, \ ··· 633 633 for (i = 0; i < data->gts.num_itime; i++) { 634 634 new_time_sel = data->gts.itime_table[i].sel; 635 635 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, 636 636 - new_time_sel, val, val2 * 1000, gain_sel); 636 636 + new_time_sel, val, val2, gain_sel); 637 637 if (!ret) 638 638 break; 639 639 } ··· 662 662 goto unlock_out; 663 663 664 664 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel, 665 665 - val, val2 * 1000, &gain_sel); 665 665 + val, val2, &gain_sel); 666 666 if (ret) { 667 667 ret = bu27008_try_find_new_time_gain(data, val, val2, &gain_sel); 668 668 if (ret) ··· 675 675 mutex_unlock(&data->mutex); 676 676 677 677 return ret; 678 678 + } 679 679 + 680 680 + static int bu27008_write_raw_get_fmt(struct iio_dev *indio_dev, 681 681 + struct iio_chan_spec const *chan, 682 682 + long mask) 683 683 + { 684 684 + 685 685 + switch (mask) { 686 686 + case IIO_CHAN_INFO_SCALE: 687 687 + return IIO_VAL_INT_PLUS_NANO; 688 688 + case IIO_CHAN_INFO_INT_TIME: 689 689 + return IIO_VAL_INT_PLUS_MICRO; 690 690 + default: 691 691 + return -EINVAL; 692 692 + } 678 693 } 679 694 680 695 static int bu27008_write_raw(struct iio_dev *idev, ··· 771 756 static const struct iio_info bu27008_info = { 772 757 .read_raw = &bu27008_read_raw, 773 758 .write_raw = &bu27008_write_raw, 759 759 + .write_raw_get_fmt = &bu27008_write_raw_get_fmt, 774 760 .read_avail = &bu27008_read_avail, 775 761 .update_scan_mode = bu27008_update_scan_mode, 776 762 .validate_trigger = iio_validate_own_trigger,

+19 -3

drivers/iio/light/rohm-bu27034.c

reviewed

··· 575 575 return -EINVAL; 576 576 577 577 if (chan == BU27034_CHAN_ALS) { 578 578 - if (val == 0 && val2 == 1000) 578 578 + if (val == 0 && val2 == 1000000) 579 579 return 0; 580 580 581 581 return -EINVAL; ··· 587 587 goto unlock_out; 588 588 589 589 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel, 590 590 - val, val2 * 1000, &gain_sel); 590 590 + val, val2, &gain_sel); 591 591 if (ret) { 592 592 /* 593 593 * Could not support scale with given time. Need to change time. ··· 624 624 625 625 /* Can we provide requested scale with this time? */ 626 626 ret = iio_gts_find_gain_sel_for_scale_using_time( 627 627 - &data->gts, new_time_sel, val, val2 * 1000, 627 627 + &data->gts, new_time_sel, val, val2, 628 628 &gain_sel); 629 629 if (ret) 630 630 continue; ··· 1217 1217 } 1218 1218 } 1219 1219 1220 1220 + static int bu27034_write_raw_get_fmt(struct iio_dev *indio_dev, 1221 1221 + struct iio_chan_spec const *chan, 1222 1222 + long mask) 1223 1223 + { 1224 1224 + 1225 1225 + switch (mask) { 1226 1226 + case IIO_CHAN_INFO_SCALE: 1227 1227 + return IIO_VAL_INT_PLUS_NANO; 1228 1228 + case IIO_CHAN_INFO_INT_TIME: 1229 1229 + return IIO_VAL_INT_PLUS_MICRO; 1230 1230 + default: 1231 1231 + return -EINVAL; 1232 1232 + } 1233 1233 + } 1234 1234 + 1220 1235 static int bu27034_write_raw(struct iio_dev *idev, 1221 1236 struct iio_chan_spec const *chan, 1222 1237 int val, int val2, long mask) ··· 1282 1267 static const struct iio_info bu27034_info = { 1283 1268 .read_raw = &bu27034_read_raw, 1284 1269 .write_raw = &bu27034_write_raw, 1270 1270 + .write_raw_get_fmt = &bu27034_write_raw_get_fmt, 1285 1271 .read_avail = &bu27034_read_avail, 1286 1272 }; 1287 1273

+5

drivers/interconnect/qcom/bcm-voter.c

reviewed

··· 83 83 84 84 temp = agg_peak[bucket] * bcm->vote_scale; 85 85 bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit); 86 86 + 87 87 + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) { 88 88 + bcm->vote_x[bucket] = 0; 89 89 + bcm->vote_y[bucket] = bcm->enable_mask; 90 90 + } 86 91 } 87 92 88 93 if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&

+2

drivers/interconnect/qcom/icc-rpmh.h

reviewed

··· 81 81 * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm 82 82 * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm 83 83 * @vote_scale: scaling factor for vote_x and vote_y 84 84 + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y 84 85 * @dirty: flag used to indicate whether the bcm needs to be committed 85 86 * @keepalive: flag used to indicate whether a keepalive is required 86 87 * @aux_data: auxiliary data used when calculating threshold values and ··· 98 97 u64 vote_x[QCOM_ICC_NUM_BUCKETS]; 99 98 u64 vote_y[QCOM_ICC_NUM_BUCKETS]; 100 99 u64 vote_scale; 100 100 + u32 enable_mask; 101 101 bool dirty; 102 102 bool keepalive; 103 103 struct bcm_db aux_data;

+1

drivers/interconnect/qcom/sa8775p.c

reviewed

··· 1873 1873 1874 1874 static struct qcom_icc_bcm bcm_acv = { 1875 1875 .name = "ACV", 1876 1876 + .enable_mask = 0x8, 1876 1877 .num_nodes = 1, 1877 1878 .nodes = { &ebi }, 1878 1879 };

+9

drivers/interconnect/qcom/sm8450.c

reviewed

··· 1337 1337 1338 1338 static struct qcom_icc_bcm bcm_acv = { 1339 1339 .name = "ACV", 1340 1340 + .enable_mask = 0x8, 1340 1341 .num_nodes = 1, 1341 1342 .nodes = { &ebi }, 1342 1343 }; ··· 1350 1349 1351 1350 static struct qcom_icc_bcm bcm_cn0 = { 1352 1351 .name = "CN0", 1352 1352 + .enable_mask = 0x1, 1353 1353 .keepalive = true, 1354 1354 .num_nodes = 55, 1355 1355 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, ··· 1385 1383 1386 1384 static struct qcom_icc_bcm bcm_co0 = { 1387 1385 .name = "CO0", 1386 1386 + .enable_mask = 0x1, 1388 1387 .num_nodes = 2, 1389 1388 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1390 1389 }; ··· 1406 1403 1407 1404 static struct qcom_icc_bcm bcm_mm1 = { 1408 1405 .name = "MM1", 1406 1406 + .enable_mask = 0x1, 1409 1407 .num_nodes = 12, 1410 1408 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1411 1409 &qnm_camnoc_sf, &qnm_mdp, ··· 1449 1445 1450 1446 static struct qcom_icc_bcm bcm_sh1 = { 1451 1447 .name = "SH1", 1448 1448 + .enable_mask = 0x1, 1452 1449 .num_nodes = 7, 1453 1450 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1454 1451 &qnm_nsp_gemnoc, &qnm_pcie, ··· 1466 1461 1467 1462 static struct qcom_icc_bcm bcm_sn1 = { 1468 1463 .name = "SN1", 1464 1464 + .enable_mask = 0x1, 1469 1465 .num_nodes = 4, 1470 1466 .nodes = { &qhm_gic, &qxm_pimem, 1471 1467 &xm_gic, &qns_gemnoc_gc }, ··· 1498 1492 1499 1493 static struct qcom_icc_bcm bcm_acv_disp = { 1500 1494 .name = "ACV", 1495 1495 + .enable_mask = 0x1, 1501 1496 .num_nodes = 1, 1502 1497 .nodes = { &ebi_disp }, 1503 1498 }; ··· 1517 1510 1518 1511 static struct qcom_icc_bcm bcm_mm1_disp = { 1519 1512 .name = "MM1", 1513 1513 + .enable_mask = 0x1, 1520 1514 .num_nodes = 3, 1521 1515 .nodes = { &qnm_mdp_disp, &qnm_rot_disp, 1522 1516 &qns_mem_noc_sf_disp }, ··· 1531 1523 1532 1524 static struct qcom_icc_bcm bcm_sh1_disp = { 1533 1525 .name = "SH1", 1526 1526 + .enable_mask = 0x1, 1534 1527 .num_nodes = 1, 1535 1528 .nodes = { &qnm_pcie_disp }, 1536 1529 };

+17

drivers/interconnect/qcom/sm8550.c

reviewed

··· 1473 1473 1474 1474 static struct qcom_icc_bcm bcm_acv = { 1475 1475 .name = "ACV", 1476 1476 + .enable_mask = 0x8, 1476 1477 .num_nodes = 1, 1477 1478 .nodes = { &ebi }, 1478 1479 }; ··· 1486 1485 1487 1486 static struct qcom_icc_bcm bcm_cn0 = { 1488 1487 .name = "CN0", 1488 1488 + .enable_mask = 0x1, 1489 1489 .keepalive = true, 1490 1490 .num_nodes = 54, 1491 1491 .nodes = { &qsm_cfg, &qhs_ahb2phy0, ··· 1526 1524 1527 1525 static struct qcom_icc_bcm bcm_co0 = { 1528 1526 .name = "CO0", 1527 1527 + .enable_mask = 0x1, 1529 1528 .num_nodes = 2, 1530 1529 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1531 1530 }; ··· 1552 1549 1553 1550 static struct qcom_icc_bcm bcm_mm1 = { 1554 1551 .name = "MM1", 1552 1552 + .enable_mask = 0x1, 1555 1553 .num_nodes = 8, 1556 1554 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1557 1555 &qnm_camnoc_sf, &qnm_vapss_hcp, ··· 1593 1589 1594 1590 static struct qcom_icc_bcm bcm_sh1 = { 1595 1591 .name = "SH1", 1592 1592 + .enable_mask = 0x1, 1596 1593 .num_nodes = 13, 1597 1594 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1598 1595 &chm_apps, &qnm_gpu, ··· 1613 1608 1614 1609 static struct qcom_icc_bcm bcm_sn1 = { 1615 1610 .name = "SN1", 1611 1611 + .enable_mask = 0x1, 1616 1612 .num_nodes = 3, 1617 1613 .nodes = { &qhm_gic, &xm_gic, 1618 1614 &qns_gemnoc_gc }, ··· 1639 1633 1640 1634 static struct qcom_icc_bcm bcm_acv_disp = { 1641 1635 .name = "ACV", 1636 1636 + .enable_mask = 0x1, 1642 1637 .num_nodes = 1, 1643 1638 .nodes = { &ebi_disp }, 1644 1639 }; ··· 1664 1657 1665 1658 static struct qcom_icc_bcm bcm_sh1_disp = { 1666 1659 .name = "SH1", 1660 1660 + .enable_mask = 0x1, 1667 1661 .num_nodes = 2, 1668 1662 .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, 1669 1663 }; 1670 1664 1671 1665 static struct qcom_icc_bcm bcm_acv_cam_ife_0 = { 1672 1666 .name = "ACV", 1667 1667 + .enable_mask = 0x0, 1673 1668 .num_nodes = 1, 1674 1669 .nodes = { &ebi_cam_ife_0 }, 1675 1670 }; ··· 1690 1681 1691 1682 static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { 1692 1683 .name = "MM1", 1684 1684 + .enable_mask = 0x1, 1693 1685 .num_nodes = 4, 1694 1686 .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, 1695 1687 &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, ··· 1704 1694 1705 1695 static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { 1706 1696 .name = "SH1", 1697 1697 + .enable_mask = 0x1, 1707 1698 .num_nodes = 3, 1708 1699 .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, 1709 1700 &qnm_pcie_cam_ife_0 }, ··· 1712 1701 1713 1702 static struct qcom_icc_bcm bcm_acv_cam_ife_1 = { 1714 1703 .name = "ACV", 1704 1704 + .enable_mask = 0x0, 1715 1705 .num_nodes = 1, 1716 1706 .nodes = { &ebi_cam_ife_1 }, 1717 1707 }; ··· 1731 1719 1732 1720 static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { 1733 1721 .name = "MM1", 1722 1722 + .enable_mask = 0x1, 1734 1723 .num_nodes = 4, 1735 1724 .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, 1736 1725 &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, ··· 1745 1732 1746 1733 static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { 1747 1734 .name = "SH1", 1735 1735 + .enable_mask = 0x1, 1748 1736 .num_nodes = 3, 1749 1737 .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, 1750 1738 &qnm_pcie_cam_ife_1 }, ··· 1753 1739 1754 1740 static struct qcom_icc_bcm bcm_acv_cam_ife_2 = { 1755 1741 .name = "ACV", 1742 1742 + .enable_mask = 0x0, 1756 1743 .num_nodes = 1, 1757 1744 .nodes = { &ebi_cam_ife_2 }, 1758 1745 }; ··· 1772 1757 1773 1758 static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { 1774 1759 .name = "MM1", 1760 1760 + .enable_mask = 0x1, 1775 1761 .num_nodes = 4, 1776 1762 .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, 1777 1763 &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, ··· 1786 1770 1787 1771 static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = { 1788 1772 .name = "SH1", 1773 1773 + .enable_mask = 0x1, 1789 1774 .num_nodes = 3, 1790 1775 .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, 1791 1776 &qnm_pcie_cam_ife_2 },

+1 -1

drivers/misc/cardreader/rts5227.c

reviewed

··· 195 195 } 196 196 } 197 197 198 198 - if (option->force_clkreq_0) 198 198 + if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) 199 199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 200 200 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 201 201 else

-18

drivers/misc/cardreader/rts5228.c

reviewed

··· 435 435 option->ltr_enabled = false; 436 436 } 437 437 } 438 438 - 439 439 - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 440 440 - | PM_L1_1_EN | PM_L1_2_EN)) 441 441 - option->force_clkreq_0 = false; 442 442 - else 443 443 - option->force_clkreq_0 = true; 444 438 } 445 439 446 440 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) 447 441 { 448 448 - struct rtsx_cr_option *option = &pcr->option; 449 442 450 443 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, 451 444 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); ··· 468 475 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 469 476 else 470 477 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); 471 471 - 472 472 - /* 473 473 - * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 474 474 - * to drive low, and we forcibly request clock. 475 475 - */ 476 476 - if (option->force_clkreq_0) 477 477 - rtsx_pci_write_register(pcr, PETXCFG, 478 478 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 479 479 - else 480 480 - rtsx_pci_write_register(pcr, PETXCFG, 481 481 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 482 478 483 479 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 484 480

+1 -2

drivers/misc/cardreader/rts5249.c

reviewed

··· 327 327 } 328 328 } 329 329 330 330 - 331 330 /* 332 331 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 333 332 * to drive low, and we forcibly request clock. 334 333 */ 335 335 - if (option->force_clkreq_0) 334 334 + if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG) 336 335 rtsx_pci_write_register(pcr, PETXCFG, 337 336 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 338 337 else

-18

drivers/misc/cardreader/rts5260.c

reviewed

··· 517 517 option->ltr_enabled = false; 518 518 } 519 519 } 520 520 - 521 521 - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 522 522 - | PM_L1_1_EN | PM_L1_2_EN)) 523 523 - option->force_clkreq_0 = false; 524 524 - else 525 525 - option->force_clkreq_0 = true; 526 520 } 527 521 528 522 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) 529 523 { 530 530 - struct rtsx_cr_option *option = &pcr->option; 531 524 532 525 /* Set mcu_cnt to 7 to ensure data can be sampled properly */ 533 526 rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07); ··· 538 545 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 539 546 540 547 rts5260_init_hw(pcr); 541 541 - 542 542 - /* 543 543 - * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 544 544 - * to drive low, and we forcibly request clock. 545 545 - */ 546 546 - if (option->force_clkreq_0) 547 547 - rtsx_pci_write_register(pcr, PETXCFG, 548 548 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 549 549 - else 550 550 - rtsx_pci_write_register(pcr, PETXCFG, 551 551 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 552 548 553 549 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 554 550

-18

drivers/misc/cardreader/rts5261.c

reviewed

··· 498 498 option->ltr_enabled = false; 499 499 } 500 500 } 501 501 - 502 502 - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 503 503 - | PM_L1_1_EN | PM_L1_2_EN)) 504 504 - option->force_clkreq_0 = false; 505 505 - else 506 506 - option->force_clkreq_0 = true; 507 501 } 508 502 509 503 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) 510 504 { 511 511 - struct rtsx_cr_option *option = &pcr->option; 512 505 u32 val; 513 506 514 507 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, ··· 546 553 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 547 554 else 548 555 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); 549 549 - 550 550 - /* 551 551 - * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 552 552 - * to drive low, and we forcibly request clock. 553 553 - */ 554 554 - if (option->force_clkreq_0) 555 555 - rtsx_pci_write_register(pcr, PETXCFG, 556 556 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 557 557 - else 558 558 - rtsx_pci_write_register(pcr, PETXCFG, 559 559 - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 560 556 561 557 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 562 558

+4 -1

drivers/misc/cardreader/rtsx_pcr.c

reviewed

··· 1326 1326 return err; 1327 1327 } 1328 1328 1329 1329 - if (pcr->aspm_mode == ASPM_MODE_REG) 1329 1329 + if (pcr->aspm_mode == ASPM_MODE_REG) { 1330 1330 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); 1331 1331 + rtsx_pci_write_register(pcr, PETXCFG, 1332 1332 + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 1333 1333 + } 1331 1334 1332 1335 /* No CD interrupt if probing driver with card inserted. 1333 1336 * So we need to initialize pcr->card_exist here.

+18 -1

drivers/misc/tps6594-esm.c

reviewed

··· 13 13 14 14 #include <linux/mfd/tps6594.h> 15 15 16 16 + #define TPS6594_DEV_REV_1 0x08 17 17 + 16 18 static irqreturn_t tps6594_esm_isr(int irq, void *dev_id) 17 19 { 18 20 struct platform_device *pdev = dev_id; ··· 34 32 { 35 33 struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent); 36 34 struct device *dev = &pdev->dev; 35 35 + unsigned int rev; 37 36 int irq; 38 37 int ret; 39 38 int i; 40 39 41 41 - for (i = 0 ; i < pdev->num_resources ; i++) { 40 40 + /* 41 41 + * Due to a bug in revision 1 of the PMIC, the GPIO3 used for the 42 42 + * SoC ESM function is used to power the load switch instead. 43 43 + * As a consequence, ESM can not be used on those PMIC. 44 44 + * Check the version and return an error in case of revision 1. 45 45 + */ 46 46 + ret = regmap_read(tps->regmap, TPS6594_REG_DEV_REV, &rev); 47 47 + if (ret) 48 48 + return dev_err_probe(dev, ret, 49 49 + "Failed to read PMIC revision\n"); 50 50 + if (rev == TPS6594_DEV_REV_1) 51 51 + return dev_err_probe(dev, -ENODEV, 52 52 + "ESM not supported for revision 1 PMIC\n"); 53 53 + 54 54 + for (i = 0; i < pdev->num_resources; i++) { 42 55 irq = platform_get_irq_byname(pdev, pdev->resource[i].name); 43 56 if (irq < 0) 44 57 return dev_err_probe(dev, irq, "Failed to get %s irq\n",

+2 -1

tools/counter/Makefile

reviewed

··· 40 40 clean: 41 41 rm -f $(ALL_PROGRAMS) 42 42 rm -rf $(OUTPUT)include/linux/counter.h 43 43 - rmdir -p $(OUTPUT)include/linux 43 43 + rm -df $(OUTPUT)include/linux 44 44 + rm -df $(OUTPUT)include 44 45 find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete 45 46 46 47 install: $(ALL_PROGRAMS)