Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dp: move link property handling to dp_panel
Instead of passing link properties through the separate struct, parse
them directly in the dp_panel.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576117/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-13-098d5f581dd3@linaro.org
+66
-67
-8
drivers/gpu/drm/msm/dp/dp_display.c
-8
drivers/gpu/drm/msm/dp/dp_display.c
···
357
357
int rc = 0;
358
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struct edid *edid;
359
359
360
-
dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
361
-
dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
362
-
363
-
drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
364
-
dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
365
-
366
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rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
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361
if (rc)
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goto end;
···
375
381
376
382
dp->audio_supported = drm_detect_monitor_audio(edid);
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dp_panel_handle_sink_request(dp->panel);
378
-
379
-
dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
380
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381
385
/*
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* set sink to normal operation mode -- D0
-1
drivers/gpu/drm/msm/dp/dp_display.h
-1
drivers/gpu/drm/msm/dp/dp_display.h
+66
drivers/gpu/drm/msm/dp/dp_panel.c
+66
drivers/gpu/drm/msm/dp/dp_panel.c
···
7
7
8
8
#include <drm/drm_connector.h>
9
9
#include <drm/drm_edid.h>
10
+
#include <drm/drm_of.h>
10
11
#include <drm/drm_print.h>
12
+
13
+
#define DP_MAX_NUM_DP_LANES 4
14
+
#define DP_LINK_RATE_HBR2 540000 /* kbytes */
11
15
12
16
struct dp_panel_private {
13
17
struct device *dev;
···
141
137
}
142
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panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
140
+
141
+
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
142
+
dp_panel->max_dp_lanes, dp_panel->max_dp_link_rate);
144
143
145
144
rc = dp_panel_read_dpcd(dp_panel);
146
145
if (rc) {
···
393
386
return 0;
394
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}
395
388
389
+
static u32 dp_panel_link_frequencies(struct device_node *of_node)
390
+
{
391
+
struct device_node *endpoint;
392
+
u64 frequency = 0;
393
+
int cnt;
394
+
395
+
endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
396
+
if (!endpoint)
397
+
return 0;
398
+
399
+
cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
400
+
401
+
if (cnt > 0)
402
+
of_property_read_u64_index(endpoint, "link-frequencies",
403
+
cnt - 1, &frequency);
404
+
of_node_put(endpoint);
405
+
406
+
do_div(frequency,
407
+
10 * /* from symbol rate to link rate */
408
+
1000); /* kbytes */
409
+
410
+
return frequency;
411
+
}
412
+
413
+
static int dp_panel_parse_dt(struct dp_panel *dp_panel)
414
+
{
415
+
struct dp_panel_private *panel;
416
+
struct device_node *of_node;
417
+
int cnt;
418
+
419
+
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
420
+
of_node = panel->dev->of_node;
421
+
422
+
/*
423
+
* data-lanes is the property of dp_out endpoint
424
+
*/
425
+
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
426
+
if (cnt < 0) {
427
+
/* legacy code, data-lanes is the property of mdss_dp node */
428
+
cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
429
+
}
430
+
431
+
if (cnt > 0)
432
+
dp_panel->max_dp_lanes = cnt;
433
+
else
434
+
dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
435
+
436
+
dp_panel->max_dp_link_rate = dp_panel_link_frequencies(of_node);
437
+
if (!dp_panel->max_dp_link_rate)
438
+
dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2;
439
+
440
+
return 0;
441
+
}
442
+
396
443
struct dp_panel *dp_panel_get(struct dp_panel_in *in)
397
444
{
398
445
struct dp_panel_private *panel;
399
446
struct dp_panel *dp_panel;
447
+
int ret;
400
448
401
449
if (!in->dev || !in->catalog || !in->aux || !in->link) {
402
450
DRM_ERROR("invalid input\n");
···
469
407
470
408
dp_panel = &panel->dp_panel;
471
409
dp_panel->max_bw_code = DP_LINK_BW_8_1;
410
+
411
+
ret = dp_panel_parse_dt(dp_panel);
412
+
if (ret)
413
+
return ERR_PTR(ret);
472
414
473
415
return dp_panel;
474
416
}
-54
drivers/gpu/drm/msm/dp/dp_parser.c
-54
drivers/gpu/drm/msm/dp/dp_parser.c
···
24
24
return 0;
25
25
}
26
26
27
-
static u32 dp_parser_link_frequencies(struct device_node *of_node)
28
-
{
29
-
struct device_node *endpoint;
30
-
u64 frequency = 0;
31
-
int cnt;
32
-
33
-
endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
34
-
if (!endpoint)
35
-
return 0;
36
-
37
-
cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
38
-
39
-
if (cnt > 0)
40
-
of_property_read_u64_index(endpoint, "link-frequencies",
41
-
cnt - 1, &frequency);
42
-
of_node_put(endpoint);
43
-
44
-
do_div(frequency,
45
-
10 * /* from symbol rate to link rate */
46
-
1000); /* kbytes */
47
-
48
-
return frequency;
49
-
}
50
-
51
-
static int dp_parser_misc(struct dp_parser *parser)
52
-
{
53
-
struct device_node *of_node = parser->pdev->dev.of_node;
54
-
int cnt;
55
-
56
-
/*
57
-
* data-lanes is the property of dp_out endpoint
58
-
*/
59
-
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
60
-
if (cnt < 0) {
61
-
/* legacy code, data-lanes is the property of mdss_dp node */
62
-
cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
63
-
}
64
-
65
-
if (cnt > 0)
66
-
parser->max_dp_lanes = cnt;
67
-
else
68
-
parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
69
-
70
-
parser->max_dp_link_rate = dp_parser_link_frequencies(of_node);
71
-
if (!parser->max_dp_link_rate)
72
-
parser->max_dp_link_rate = DP_LINK_RATE_HBR2;
73
-
74
-
return 0;
75
-
}
76
-
77
27
int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser)
78
28
{
79
29
struct platform_device *pdev = parser->pdev;
···
48
98
}
49
99
50
100
rc = dp_parser_ctrl_res(parser);
51
-
if (rc)
52
-
return rc;
53
-
54
-
rc = dp_parser_misc(parser);
55
101
if (rc)
56
102
return rc;
57
103
-4
drivers/gpu/drm/msm/dp/dp_parser.h
-4
drivers/gpu/drm/msm/dp/dp_parser.h
···
11
11
#include "msm_drv.h"
12
12
13
13
#define DP_MAX_PIXEL_CLK_KHZ 675000
14
-
#define DP_MAX_NUM_DP_LANES 4
15
-
#define DP_LINK_RATE_HBR2 540000 /* kbytes */
16
14
17
15
/**
18
16
* struct dp_parser - DP parser's data exposed to clients
···
21
23
struct dp_parser {
22
24
struct platform_device *pdev;
23
25
struct phy *phy;
24
-
u32 max_dp_lanes;
25
-
u32 max_dp_link_rate;
26
26
struct drm_bridge *next_bridge;
27
27
};
28
28