tjh.dev / kernel
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Merge tag 'pm+acpi-4.4-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull more power management and ACPI updates from Rafael Wysocki:
"These are mostly fixes and cleanups (ACPI core, PM core, cpufreq, ACPI
EC driver, device properties) including three reverts of recent
intel_pstate driver commits due to a regression introduced by one of
them plus support for Atom Airmont cores in intel_pstate (which really
boils down to adding new frequency tables for Airmont) and additional
turbostat updates.

Specifics:

- Revert three recent intel_pstate driver commits one of which
introduced a regression and the remaining two depend on the
problematic one (Rafael Wysocki).

- Fix breakage related to the recently introduced ACPI _CCA object
support in the PCI DMA setup code (Suravee Suthikulpanit).

- Fix up the recently introduced ACPI CPPC support to only use the
hardware-reduced version of the PCCT structure as the only
architecture to support it (ARM64) will only use hardware-reduced
ACPI anyway (Ashwin Chaugule).

- Fix a cpufreq mediatek driver build problem (Arnd Bergmann).

- Fix the SMBus transaction handling implementation in the ACPI core
to avoid re-entrant calls to wait_event_timeout() which makes
intermittent boot stalls related to the Smart Battery Subsystem
initialization go away and revert a workaround of another problem
with the same underlying root cause (Chris Bainbridge).

- Fix the generic wakeup interrupts framework to avoid using invalid
IRQ numbers (Dmitry Torokhov).

- Remove a redundant check from the ACPI EC driver (Markus Elfring).

- Modify the intel_pstate driver so it can support more Atom flavors
than just one (Baytrail) and add support for Atom Airmont cores
(which require new freqnency tables) to it (Philippe Longepe).

- Clean up MSR-related symbols in turbostat (Len Brown)"

* tag 'pm+acpi-4.4-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
PCI: Fix OF logic in pci_dma_configure()
Revert "Documentation: kernel_parameters for Intel P state driver"
cpufreq: mediatek: fix build error
cpufreq: intel_pstate: Add separate support for Airmont cores
cpufreq: intel_pstate: Replace BYT with ATOM
Revert "cpufreq: intel_pstate: Use ACPI perf configuration"
Revert "cpufreq: intel_pstate: Avoid calculation for max/min"
ACPI-EC: Drop unnecessary check made before calling acpi_ec_delete_query()
Revert "ACPI / SBS: Add 5 us delay to fix SBS hangs on MacBook"
ACPI / SMBus: Fix boot stalls / high CPU caused by reentrant code
PM / wakeirq: check that wake IRQ is valid before accepting it
ACPI / CPPC: Use h/w reduced version of the PCCT structure
x86: remove unused definition of MSR_NHM_PLATFORM_INFO
tools/power turbostat: use new name for MSR_PLATFORM_INFO

Linus Torvalds 400f3f25 2f255351

+96 -300
-3
Documentation/kernel-parameters.txt
··· 1583 1583 hwp_only 1584 1584 Only load intel_pstate on systems which support 1585 1585 hardware P state control (HWP) if available. 1586 - no_acpi 1587 - Don't use ACPI processor performance control objects 1588 - _PSS and _PPC specified limits. 1589 1586 1590 1587 intremap= [X86-64, Intel-IOMMU] 1591 1588 on enable Interrupt Remapping (default)
+1 -2
arch/x86/include/asm/msr-index.h
··· 35 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 36 #define MSR_IA32_PERFCTR1 0x000000c2 37 37 #define MSR_FSB_FREQ 0x000000cd 38 - #define MSR_NHM_PLATFORM_INFO 0x000000ce 38 + #define MSR_PLATFORM_INFO 0x000000ce 39 39 40 40 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 41 41 #define NHM_C3_AUTO_DEMOTE (1UL << 25) ··· 44 44 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45 45 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 46 46 47 - #define MSR_PLATFORM_INFO 0x000000ce 48 47 #define MSR_MTRRcap 0x000000fe 49 48 #define MSR_IA32_BBL_CR_CTL 0x00000119 50 49 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
+1 -1
drivers/acpi/cppc_acpi.c
··· 304 304 305 305 static int register_pcc_channel(int pcc_subspace_idx) 306 306 { 307 - struct acpi_pcct_subspace *cppc_ss; 307 + struct acpi_pcct_hw_reduced *cppc_ss; 308 308 unsigned int len; 309 309 310 310 if (pcc_subspace_idx >= 0) {
+1 -1
drivers/acpi/ec.c
··· 1103 1103 } 1104 1104 1105 1105 err_exit: 1106 - if (result && q) 1106 + if (result) 1107 1107 acpi_ec_delete_query(q); 1108 1108 if (data) 1109 1109 *data = value;
+7 -41
drivers/acpi/sbshc.c
··· 14 14 #include <linux/delay.h> 15 15 #include <linux/module.h> 16 16 #include <linux/interrupt.h> 17 - #include <linux/dmi.h> 18 17 #include "sbshc.h" 19 18 20 19 #define PREFIX "ACPI: " ··· 29 30 u8 query_bit; 30 31 smbus_alarm_callback callback; 31 32 void *context; 33 + bool done; 32 34 }; 33 35 34 36 static int acpi_smbus_hc_add(struct acpi_device *device); ··· 88 88 ACPI_SMB_ALARM_DATA = 0x26, /* 2 bytes alarm data */ 89 89 }; 90 90 91 - static bool macbook; 92 - 93 91 static inline int smb_hc_read(struct acpi_smb_hc *hc, u8 address, u8 *data) 94 92 { 95 93 return ec_read(hc->offset + address, data); ··· 98 100 return ec_write(hc->offset + address, data); 99 101 } 100 102 101 - static inline int smb_check_done(struct acpi_smb_hc *hc) 102 - { 103 - union acpi_smb_status status = {.raw = 0}; 104 - smb_hc_read(hc, ACPI_SMB_STATUS, &status.raw); 105 - return status.fields.done && (status.fields.status == SMBUS_OK); 106 - } 107 - 108 103 static int wait_transaction_complete(struct acpi_smb_hc *hc, int timeout) 109 104 { 110 - if (wait_event_timeout(hc->wait, smb_check_done(hc), 111 - msecs_to_jiffies(timeout))) 105 + if (wait_event_timeout(hc->wait, hc->done, msecs_to_jiffies(timeout))) 112 106 return 0; 113 - /* 114 - * After the timeout happens, OS will try to check the status of SMbus. 115 - * If the status is what OS expected, it will be regarded as the bogus 116 - * timeout. 117 - */ 118 - if (smb_check_done(hc)) 119 - return 0; 120 - else 121 - return -ETIME; 107 + return -ETIME; 122 108 } 123 109 124 110 static int acpi_smbus_transaction(struct acpi_smb_hc *hc, u8 protocol, ··· 117 135 } 118 136 119 137 mutex_lock(&hc->lock); 120 - if (macbook) 121 - udelay(5); 138 + hc->done = false; 122 139 if (smb_hc_read(hc, ACPI_SMB_PROTOCOL, &temp)) 123 140 goto end; 124 141 if (temp) { ··· 216 235 if (smb_hc_read(hc, ACPI_SMB_STATUS, &status.raw)) 217 236 return 0; 218 237 /* Check if it is only a completion notify */ 219 - if (status.fields.done) 238 + if (status.fields.done && status.fields.status == SMBUS_OK) { 239 + hc->done = true; 220 240 wake_up(&hc->wait); 241 + } 221 242 if (!status.fields.alarm) 222 243 return 0; 223 244 mutex_lock(&hc->lock); ··· 245 262 acpi_handle handle, acpi_ec_query_func func, 246 263 void *data); 247 264 248 - static int macbook_dmi_match(const struct dmi_system_id *d) 249 - { 250 - pr_debug("Detected MacBook, enabling workaround\n"); 251 - macbook = true; 252 - return 0; 253 - } 254 - 255 - static struct dmi_system_id acpi_smbus_dmi_table[] = { 256 - { macbook_dmi_match, "Apple MacBook", { 257 - DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), 258 - DMI_MATCH(DMI_PRODUCT_NAME, "MacBook") }, 259 - }, 260 - { }, 261 - }; 262 - 263 265 static int acpi_smbus_hc_add(struct acpi_device *device) 264 266 { 265 267 int status; 266 268 unsigned long long val; 267 269 struct acpi_smb_hc *hc; 268 - 269 - dmi_check_system(acpi_smbus_dmi_table); 270 270 271 271 if (!device) 272 272 return -EINVAL;
+6
drivers/base/power/wakeirq.c
··· 68 68 struct wake_irq *wirq; 69 69 int err; 70 70 71 + if (irq < 0) 72 + return -EINVAL; 73 + 71 74 wirq = kzalloc(sizeof(*wirq), GFP_KERNEL); 72 75 if (!wirq) 73 76 return -ENOMEM; ··· 169 166 { 170 167 struct wake_irq *wirq; 171 168 int err; 169 + 170 + if (irq < 0) 171 + return -EINVAL; 172 172 173 173 wirq = kzalloc(sizeof(*wirq), GFP_KERNEL); 174 174 if (!wirq)
+1
drivers/cpufreq/Kconfig.arm
··· 84 84 config ARM_MT8173_CPUFREQ 85 85 bool "Mediatek MT8173 CPUFreq support" 86 86 depends on ARCH_MEDIATEK && REGULATOR 87 + depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST) 87 88 depends on !CPU_THERMAL || THERMAL=y 88 89 select PM_OPP 89 90 help
-1
drivers/cpufreq/Kconfig.x86
··· 5 5 config X86_INTEL_PSTATE 6 6 bool "Intel P state control" 7 7 depends on X86 8 - select ACPI_PROCESSOR if ACPI 9 8 help 10 9 This driver provides a P state for Intel core processors. 11 10 The driver implements an internal governor and will become
+73 -245
drivers/cpufreq/intel_pstate.c
··· 34 34 #include <asm/cpu_device_id.h> 35 35 #include <asm/cpufeature.h> 36 36 37 - #if IS_ENABLED(CONFIG_ACPI) 38 - #include <acpi/processor.h> 39 - #endif 40 - 41 - #define BYT_RATIOS 0x66a 42 - #define BYT_VIDS 0x66b 43 - #define BYT_TURBO_RATIOS 0x66c 44 - #define BYT_TURBO_VIDS 0x66d 37 + #define ATOM_RATIOS 0x66a 38 + #define ATOM_VIDS 0x66b 39 + #define ATOM_TURBO_RATIOS 0x66c 40 + #define ATOM_TURBO_VIDS 0x66d 45 41 46 42 #define FRAC_BITS 8 47 43 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) ··· 113 117 u64 prev_mperf; 114 118 u64 prev_tsc; 115 119 struct sample sample; 116 - #if IS_ENABLED(CONFIG_ACPI) 117 - struct acpi_processor_performance acpi_perf_data; 118 - #endif 119 120 }; 120 121 121 122 static struct cpudata **all_cpu_data; ··· 143 150 static struct pstate_adjust_policy pid_params; 144 151 static struct pstate_funcs pstate_funcs; 145 152 static int hwp_active; 146 - static int no_acpi_perf; 147 153 148 154 struct perf_limits { 149 155 int no_turbo; ··· 155 163 int max_sysfs_pct; 156 164 int min_policy_pct; 157 165 int min_sysfs_pct; 158 - int max_perf_ctl; 159 - int min_perf_ctl; 160 166 }; 161 167 162 168 static struct perf_limits performance_limits = { ··· 181 191 .max_sysfs_pct = 100, 182 192 .min_policy_pct = 0, 183 193 .min_sysfs_pct = 0, 184 - .max_perf_ctl = 0, 185 - .min_perf_ctl = 0, 186 194 }; 187 195 188 196 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 189 197 static struct perf_limits *limits = &performance_limits; 190 198 #else 191 199 static struct perf_limits *limits = &powersave_limits; 192 - #endif 193 - 194 - #if IS_ENABLED(CONFIG_ACPI) 195 - /* 196 - * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and 197 - * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and 198 - * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state 199 - * ratio, out of it only high 8 bits are used. For example 0x1700 is setting 200 - * target ratio 0x17. The _PSS control value stores in a format which can be 201 - * directly written to PERF_CTL MSR. But in intel_pstate driver this shift 202 - * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()). 203 - * This function converts the _PSS control value to intel pstate driver format 204 - * for comparison and assignment. 205 - */ 206 - static int convert_to_native_pstate_format(struct cpudata *cpu, int index) 207 - { 208 - return cpu->acpi_perf_data.states[index].control >> 8; 209 - } 210 - 211 - static int intel_pstate_init_perf_limits(struct cpufreq_policy *policy) 212 - { 213 - struct cpudata *cpu; 214 - int ret; 215 - bool turbo_absent = false; 216 - int max_pstate_index; 217 - int min_pss_ctl, max_pss_ctl, turbo_pss_ctl; 218 - int i; 219 - 220 - cpu = all_cpu_data[policy->cpu]; 221 - 222 - pr_debug("intel_pstate: default limits 0x%x 0x%x 0x%x\n", 223 - cpu->pstate.min_pstate, cpu->pstate.max_pstate, 224 - cpu->pstate.turbo_pstate); 225 - 226 - if (!cpu->acpi_perf_data.shared_cpu_map && 227 - zalloc_cpumask_var_node(&cpu->acpi_perf_data.shared_cpu_map, 228 - GFP_KERNEL, cpu_to_node(policy->cpu))) { 229 - return -ENOMEM; 230 - } 231 - 232 - ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 233 - policy->cpu); 234 - if (ret) 235 - return ret; 236 - 237 - /* 238 - * Check if the control value in _PSS is for PERF_CTL MSR, which should 239 - * guarantee that the states returned by it map to the states in our 240 - * list directly. 241 - */ 242 - if (cpu->acpi_perf_data.control_register.space_id != 243 - ACPI_ADR_SPACE_FIXED_HARDWARE) 244 - return -EIO; 245 - 246 - pr_debug("intel_pstate: CPU%u - ACPI _PSS perf data\n", policy->cpu); 247 - for (i = 0; i < cpu->acpi_perf_data.state_count; i++) 248 - pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 249 - (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 250 - (u32) cpu->acpi_perf_data.states[i].core_frequency, 251 - (u32) cpu->acpi_perf_data.states[i].power, 252 - (u32) cpu->acpi_perf_data.states[i].control); 253 - 254 - /* 255 - * If there is only one entry _PSS, simply ignore _PSS and continue as 256 - * usual without taking _PSS into account 257 - */ 258 - if (cpu->acpi_perf_data.state_count < 2) 259 - return 0; 260 - 261 - turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0); 262 - min_pss_ctl = convert_to_native_pstate_format(cpu, 263 - cpu->acpi_perf_data.state_count - 1); 264 - /* Check if there is a turbo freq in _PSS */ 265 - if (turbo_pss_ctl <= cpu->pstate.max_pstate && 266 - turbo_pss_ctl > cpu->pstate.min_pstate) { 267 - pr_debug("intel_pstate: no turbo range exists in _PSS\n"); 268 - limits->no_turbo = limits->turbo_disabled = 1; 269 - cpu->pstate.turbo_pstate = cpu->pstate.max_pstate; 270 - turbo_absent = true; 271 - } 272 - 273 - /* Check if the max non turbo p state < Intel P state max */ 274 - max_pstate_index = turbo_absent ? 0 : 1; 275 - max_pss_ctl = convert_to_native_pstate_format(cpu, max_pstate_index); 276 - if (max_pss_ctl < cpu->pstate.max_pstate && 277 - max_pss_ctl > cpu->pstate.min_pstate) 278 - cpu->pstate.max_pstate = max_pss_ctl; 279 - 280 - /* check If min perf > Intel P State min */ 281 - if (min_pss_ctl > cpu->pstate.min_pstate && 282 - min_pss_ctl < cpu->pstate.max_pstate) { 283 - cpu->pstate.min_pstate = min_pss_ctl; 284 - policy->cpuinfo.min_freq = min_pss_ctl * cpu->pstate.scaling; 285 - } 286 - 287 - if (turbo_absent) 288 - policy->cpuinfo.max_freq = cpu->pstate.max_pstate * 289 - cpu->pstate.scaling; 290 - else { 291 - policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 292 - cpu->pstate.scaling; 293 - /* 294 - * The _PSS table doesn't contain whole turbo frequency range. 295 - * This just contains +1 MHZ above the max non turbo frequency, 296 - * with control value corresponding to max turbo ratio. But 297 - * when cpufreq set policy is called, it will call with this 298 - * max frequency, which will cause a reduced performance as 299 - * this driver uses real max turbo frequency as the max 300 - * frequeny. So correct this frequency in _PSS table to 301 - * correct max turbo frequency based on the turbo ratio. 302 - * Also need to convert to MHz as _PSS freq is in MHz. 303 - */ 304 - cpu->acpi_perf_data.states[0].core_frequency = 305 - turbo_pss_ctl * 100; 306 - } 307 - 308 - pr_debug("intel_pstate: Updated limits using _PSS 0x%x 0x%x 0x%x\n", 309 - cpu->pstate.min_pstate, cpu->pstate.max_pstate, 310 - cpu->pstate.turbo_pstate); 311 - pr_debug("intel_pstate: policy max_freq=%d Khz min_freq = %d KHz\n", 312 - policy->cpuinfo.max_freq, policy->cpuinfo.min_freq); 313 - 314 - return 0; 315 - } 316 - 317 - static int intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 318 - { 319 - struct cpudata *cpu; 320 - 321 - if (!no_acpi_perf) 322 - return 0; 323 - 324 - cpu = all_cpu_data[policy->cpu]; 325 - acpi_processor_unregister_performance(policy->cpu); 326 - return 0; 327 - } 328 - 329 - #else 330 - static int intel_pstate_init_perf_limits(struct cpufreq_policy *policy) 331 - { 332 - return 0; 333 - } 334 - 335 - static int intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 336 - { 337 - return 0; 338 - } 339 200 #endif 340 201 341 202 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, ··· 528 687 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 529 688 } 530 689 531 - static int byt_get_min_pstate(void) 690 + static int atom_get_min_pstate(void) 532 691 { 533 692 u64 value; 534 693 535 - rdmsrl(BYT_RATIOS, value); 694 + rdmsrl(ATOM_RATIOS, value); 536 695 return (value >> 8) & 0x7F; 537 696 } 538 697 539 - static int byt_get_max_pstate(void) 698 + static int atom_get_max_pstate(void) 540 699 { 541 700 u64 value; 542 701 543 - rdmsrl(BYT_RATIOS, value); 702 + rdmsrl(ATOM_RATIOS, value); 544 703 return (value >> 16) & 0x7F; 545 704 } 546 705 547 - static int byt_get_turbo_pstate(void) 706 + static int atom_get_turbo_pstate(void) 548 707 { 549 708 u64 value; 550 709 551 - rdmsrl(BYT_TURBO_RATIOS, value); 710 + rdmsrl(ATOM_TURBO_RATIOS, value); 552 711 return value & 0x7F; 553 712 } 554 713 555 - static void byt_set_pstate(struct cpudata *cpudata, int pstate) 714 + static void atom_set_pstate(struct cpudata *cpudata, int pstate) 556 715 { 557 716 u64 val; 558 717 int32_t vid_fp; ··· 577 736 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); 578 737 } 579 738 580 - #define BYT_BCLK_FREQS 5 581 - static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; 582 - 583 - static int byt_get_scaling(void) 739 + static int silvermont_get_scaling(void) 584 740 { 585 741 u64 value; 586 742 int i; 743 + /* Defined in Table 35-6 from SDM (Sept 2015) */ 744 + static int silvermont_freq_table[] = { 745 + 83300, 100000, 133300, 116700, 80000}; 587 746 588 747 rdmsrl(MSR_FSB_FREQ, value); 589 - i = value & 0x3; 748 + i = value & 0x7; 749 + WARN_ON(i > 4); 590 750 591 - BUG_ON(i > BYT_BCLK_FREQS); 592 - 593 - return byt_freq_table[i] * 100; 751 + return silvermont_freq_table[i]; 594 752 } 595 753 596 - static void byt_get_vid(struct cpudata *cpudata) 754 + static int airmont_get_scaling(void) 755 + { 756 + u64 value; 757 + int i; 758 + /* Defined in Table 35-10 from SDM (Sept 2015) */ 759 + static int airmont_freq_table[] = { 760 + 83300, 100000, 133300, 116700, 80000, 761 + 93300, 90000, 88900, 87500}; 762 + 763 + rdmsrl(MSR_FSB_FREQ, value); 764 + i = value & 0xF; 765 + WARN_ON(i > 8); 766 + 767 + return airmont_freq_table[i]; 768 + } 769 + 770 + static void atom_get_vid(struct cpudata *cpudata) 597 771 { 598 772 u64 value; 599 773 600 - rdmsrl(BYT_VIDS, value); 774 + rdmsrl(ATOM_VIDS, value); 601 775 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 602 776 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 603 777 cpudata->vid.ratio = div_fp( ··· 620 764 int_tofp(cpudata->pstate.max_pstate - 621 765 cpudata->pstate.min_pstate)); 622 766 623 - rdmsrl(BYT_TURBO_VIDS, value); 767 + rdmsrl(ATOM_TURBO_VIDS, value); 624 768 cpudata->vid.turbo = value & 0x7f; 625 769 } 626 770 ··· 741 885 }, 742 886 }; 743 887 744 - static struct cpu_defaults byt_params = { 888 + static struct cpu_defaults silvermont_params = { 745 889 .pid_policy = { 746 890 .sample_rate_ms = 10, 747 891 .deadband = 0, ··· 751 895 .i_gain_pct = 4, 752 896 }, 753 897 .funcs = { 754 - .get_max = byt_get_max_pstate, 755 - .get_max_physical = byt_get_max_pstate, 756 - .get_min = byt_get_min_pstate, 757 - .get_turbo = byt_get_turbo_pstate, 758 - .set = byt_set_pstate, 759 - .get_scaling = byt_get_scaling, 760 - .get_vid = byt_get_vid, 898 + .get_max = atom_get_max_pstate, 899 + .get_max_physical = atom_get_max_pstate, 900 + .get_min = atom_get_min_pstate, 901 + .get_turbo = atom_get_turbo_pstate, 902 + .set = atom_set_pstate, 903 + .get_scaling = silvermont_get_scaling, 904 + .get_vid = atom_get_vid, 905 + }, 906 + }; 907 + 908 + static struct cpu_defaults airmont_params = { 909 + .pid_policy = { 910 + .sample_rate_ms = 10, 911 + .deadband = 0, 912 + .setpoint = 60, 913 + .p_gain_pct = 14, 914 + .d_gain_pct = 0, 915 + .i_gain_pct = 4, 916 + }, 917 + .funcs = { 918 + .get_max = atom_get_max_pstate, 919 + .get_max_physical = atom_get_max_pstate, 920 + .get_min = atom_get_min_pstate, 921 + .get_turbo = atom_get_turbo_pstate, 922 + .set = atom_set_pstate, 923 + .get_scaling = airmont_get_scaling, 924 + .get_vid = atom_get_vid, 761 925 }, 762 926 }; 763 927 ··· 814 938 * policy, or by cpu specific default values determined through 815 939 * experimentation. 816 940 */ 817 - if (limits->max_perf_ctl && limits->max_sysfs_pct >= 818 - limits->max_policy_pct) { 819 - *max = limits->max_perf_ctl; 820 - } else { 821 - max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), 822 - limits->max_perf)); 823 - *max = clamp_t(int, max_perf_adj, cpu->pstate.min_pstate, 824 - cpu->pstate.turbo_pstate); 825 - } 941 + max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits->max_perf)); 942 + *max = clamp_t(int, max_perf_adj, 943 + cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 826 944 827 - if (limits->min_perf_ctl) { 828 - *min = limits->min_perf_ctl; 829 - } else { 830 - min_perf = fp_toint(mul_fp(int_tofp(max_perf), 831 - limits->min_perf)); 832 - *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 833 - } 945 + min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits->min_perf)); 946 + *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 834 947 } 835 948 836 949 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) ··· 1018 1153 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1019 1154 ICPU(0x2a, core_params), 1020 1155 ICPU(0x2d, core_params), 1021 - ICPU(0x37, byt_params), 1156 + ICPU(0x37, silvermont_params), 1022 1157 ICPU(0x3a, core_params), 1023 1158 ICPU(0x3c, core_params), 1024 1159 ICPU(0x3d, core_params), ··· 1027 1162 ICPU(0x45, core_params), 1028 1163 ICPU(0x46, core_params), 1029 1164 ICPU(0x47, core_params), 1030 - ICPU(0x4c, byt_params), 1165 + ICPU(0x4c, airmont_params), 1031 1166 ICPU(0x4e, core_params), 1032 1167 ICPU(0x4f, core_params), 1033 1168 ICPU(0x5e, core_params), ··· 1094 1229 1095 1230 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1096 1231 { 1097 - #if IS_ENABLED(CONFIG_ACPI) 1098 - struct cpudata *cpu; 1099 - int i; 1100 - #endif 1101 - pr_debug("intel_pstate: %s max %u policy->max %u\n", __func__, 1102 - policy->cpuinfo.max_freq, policy->max); 1103 1232 if (!policy->cpuinfo.max_freq) 1104 1233 return -ENODEV; 1105 1234 ··· 1128 1269 int_tofp(100)); 1129 1270 limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), 1130 1271 int_tofp(100)); 1131 - 1132 - #if IS_ENABLED(CONFIG_ACPI) 1133 - cpu = all_cpu_data[policy->cpu]; 1134 - for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 1135 - int control; 1136 - 1137 - control = convert_to_native_pstate_format(cpu, i); 1138 - if (control * cpu->pstate.scaling == policy->max) 1139 - limits->max_perf_ctl = control; 1140 - if (control * cpu->pstate.scaling == policy->min) 1141 - limits->min_perf_ctl = control; 1142 - } 1143 - 1144 - pr_debug("intel_pstate: max %u policy_max %u perf_ctl [0x%x-0x%x]\n", 1145 - policy->cpuinfo.max_freq, policy->max, limits->min_perf_ctl, 1146 - limits->max_perf_ctl); 1147 - #endif 1148 1272 1149 1273 if (hwp_active) 1150 1274 intel_pstate_hwp_set(); ··· 1183 1341 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1184 1342 policy->cpuinfo.max_freq = 1185 1343 cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1186 - if (!no_acpi_perf) 1187 - intel_pstate_init_perf_limits(policy); 1188 - /* 1189 - * If there is no acpi perf data or error, we ignore and use Intel P 1190 - * state calculated limits, So this is not fatal error. 1191 - */ 1192 1344 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1193 1345 cpumask_set_cpu(policy->cpu, policy->cpus); 1194 1346 1195 1347 return 0; 1196 - } 1197 - 1198 - static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1199 - { 1200 - return intel_pstate_exit_perf_limits(policy); 1201 1348 } 1202 1349 1203 1350 static struct cpufreq_driver intel_pstate_driver = { ··· 1195 1364 .setpolicy = intel_pstate_set_policy, 1196 1365 .get = intel_pstate_get, 1197 1366 .init = intel_pstate_cpu_init, 1198 - .exit = intel_pstate_cpu_exit, 1199 1367 .stop_cpu = intel_pstate_stop_cpu, 1200 1368 .name = "intel_pstate", 1201 1369 }; ··· 1236 1406 } 1237 1407 1238 1408 #if IS_ENABLED(CONFIG_ACPI) 1409 + #include <acpi/processor.h> 1239 1410 1240 1411 static bool intel_pstate_no_acpi_pss(void) 1241 1412 { ··· 1432 1601 force_load = 1; 1433 1602 if (!strcmp(str, "hwp_only")) 1434 1603 hwp_only = 1; 1435 - if (!strcmp(str, "no_acpi")) 1436 - no_acpi_perf = 1; 1437 - 1438 1604 return 0; 1439 1605 } 1440 1606 early_param("intel_pstate", intel_pstate_setup);
+2 -2
drivers/pci/probe.c
··· 1685 1685 { 1686 1686 struct device *bridge = pci_get_host_bridge_device(dev); 1687 1687 1688 - if (IS_ENABLED(CONFIG_OF) && dev->dev.of_node) { 1689 - if (bridge->parent) 1688 + if (IS_ENABLED(CONFIG_OF) && 1689 + bridge->parent && bridge->parent->of_node) { 1690 1690 of_dma_configure(&dev->dev, bridge->parent->of_node); 1691 1691 } else if (has_acpi_companion(bridge)) { 1692 1692 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
+4 -4
tools/power/x86/turbostat/turbostat.c
··· 1173 1173 unsigned long long msr; 1174 1174 unsigned int ratio; 1175 1175 1176 - get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr); 1176 + get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1177 1177 1178 - fprintf(stderr, "cpu%d: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1178 + fprintf(stderr, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1179 1179 1180 1180 ratio = (msr >> 40) & 0xFF; 1181 1181 fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency frequency\n", ··· 1807 1807 * 1808 1808 * MSR_SMI_COUNT 0x00000034 1809 1809 * 1810 - * MSR_NHM_PLATFORM_INFO 0x000000ce 1810 + * MSR_PLATFORM_INFO 0x000000ce 1811 1811 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 1812 1812 * 1813 1813 * MSR_PKG_C3_RESIDENCY 0x000003f8 ··· 1876 1876 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 1877 1877 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 1878 1878 1879 - get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr); 1879 + get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1880 1880 base_ratio = (msr >> 8) & 0xFF; 1881 1881 1882 1882 base_hz = base_ratio * bclk * 1000000;