Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'cxl-fixes-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Pull cxl fixes from Dave Jiang:
"The fixes address global persistent flush (GPF) changes and CXL
Features support changes that went in the 6.15 merge window. And also
a fix to an issue observed on CXL 1.1 platform during device
enumeration.
Summary:
- Fix using the wrong GPF DVSEC location:
- Fix caching of dport GPF DVSEC from the first endpoint
- Ensure that the GPF phase timeout is only updated once by first
endpoint
- Drop is_port parameter for cxl_gpf_get_dvsec()
- Fix the devm_* call host device for CXL fwctl setup
- Set the out_len in Set Features failure case
- Fix RCD initialization by skipping unneeded mem_en check"
* tag 'cxl-fixes-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
cxl/core/regs.c: Skip Memory Space Enable check for RCD and RCH Ports
cxl/feature: Update out_len in set feature failure case
cxl: Fix devm host device for CXL fwctl initialization
cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()
cxl/pci: Update Port GPF timeout only when the first EP attaching
cxl/core: Fix caching dport GPF DVSEC issue
+31
-30
+1
-1
drivers/cxl/core/core.h
+1
-1
drivers/cxl/core/core.h
···
119
119
120
120
int cxl_ras_init(void);
121
121
void cxl_ras_exit(void);
122
-
int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port);
122
+
int cxl_gpf_port_setup(struct cxl_dport *dport);
123
123
int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res,
124
124
int nid, resource_size_t *size);
125
125
+3
-3
drivers/cxl/core/features.c
+3
-3
drivers/cxl/core/features.c
···
528
528
rc = cxl_set_feature(cxl_mbox, &feat_in->uuid,
529
529
feat_in->version, feat_in->feat_data,
530
530
data_size, flags, offset, &return_code);
531
+
*out_len = sizeof(*rpc_out);
531
532
if (rc) {
532
533
rpc_out->retval = return_code;
533
534
return no_free_ptr(rpc_out);
534
535
}
535
536
536
537
rpc_out->retval = CXL_MBOX_CMD_RC_SUCCESS;
537
-
*out_len = sizeof(*rpc_out);
538
538
539
539
return no_free_ptr(rpc_out);
540
540
}
···
677
677
fwctl_put(fwctl_dev);
678
678
}
679
679
680
-
int devm_cxl_setup_fwctl(struct cxl_memdev *cxlmd)
680
+
int devm_cxl_setup_fwctl(struct device *host, struct cxl_memdev *cxlmd)
681
681
{
682
682
struct cxl_dev_state *cxlds = cxlmd->cxlds;
683
683
struct cxl_features_state *cxlfs;
···
700
700
if (rc)
701
701
return rc;
702
702
703
-
return devm_add_action_or_reset(&cxlmd->dev, free_memdev_fwctl,
703
+
return devm_add_action_or_reset(host, free_memdev_fwctl,
704
704
no_free_ptr(fwctl_dev));
705
705
}
706
706
EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_fwctl, "CXL");
+17
-13
drivers/cxl/core/pci.c
+17
-13
drivers/cxl/core/pci.c
···
1072
1072
#define GPF_TIMEOUT_BASE_MAX 2
1073
1073
#define GPF_TIMEOUT_SCALE_MAX 7 /* 10 seconds */
1074
1074
1075
-
u16 cxl_gpf_get_dvsec(struct device *dev, bool is_port)
1075
+
u16 cxl_gpf_get_dvsec(struct device *dev)
1076
1076
{
1077
+
struct pci_dev *pdev;
1078
+
bool is_port = true;
1077
1079
u16 dvsec;
1078
1080
1079
1081
if (!dev_is_pci(dev))
1080
1082
return 0;
1081
1083
1082
-
dvsec = pci_find_dvsec_capability(to_pci_dev(dev), PCI_VENDOR_ID_CXL,
1084
+
pdev = to_pci_dev(dev);
1085
+
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT)
1086
+
is_port = false;
1087
+
1088
+
dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
1083
1089
is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF);
1084
1090
if (!dvsec)
1085
1091
dev_warn(dev, "%s GPF DVSEC not present\n",
···
1134
1128
return rc;
1135
1129
}
1136
1130
1137
-
int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port)
1131
+
int cxl_gpf_port_setup(struct cxl_dport *dport)
1138
1132
{
1139
-
struct pci_dev *pdev;
1140
-
1141
-
if (!port)
1133
+
if (!dport)
1142
1134
return -EINVAL;
1143
1135
1144
-
if (!port->gpf_dvsec) {
1136
+
if (!dport->gpf_dvsec) {
1137
+
struct pci_dev *pdev;
1145
1138
int dvsec;
1146
1139
1147
-
dvsec = cxl_gpf_get_dvsec(dport_dev, true);
1140
+
dvsec = cxl_gpf_get_dvsec(dport->dport_dev);
1148
1141
if (!dvsec)
1149
1142
return -EINVAL;
1150
1143
1151
-
port->gpf_dvsec = dvsec;
1144
+
dport->gpf_dvsec = dvsec;
1145
+
pdev = to_pci_dev(dport->dport_dev);
1146
+
update_gpf_port_dvsec(pdev, dport->gpf_dvsec, 1);
1147
+
update_gpf_port_dvsec(pdev, dport->gpf_dvsec, 2);
1152
1148
}
1153
-
1154
-
pdev = to_pci_dev(dport_dev);
1155
-
update_gpf_port_dvsec(pdev, port->gpf_dvsec, 1);
1156
-
update_gpf_port_dvsec(pdev, port->gpf_dvsec, 2);
1157
1149
1158
1150
return 0;
1159
1151
}
+1
-1
drivers/cxl/core/port.c
+1
-1
drivers/cxl/core/port.c
-4
drivers/cxl/core/regs.c
-4
drivers/cxl/core/regs.c
···
581
581
resource_size_t rcrb = ri->base;
582
582
void __iomem *addr;
583
583
u32 bar0, bar1;
584
-
u16 cmd;
585
584
u32 id;
586
585
587
586
if (which == CXL_RCRB_UPSTREAM)
···
602
603
}
603
604
604
605
id = readl(addr + PCI_VENDOR_ID);
605
-
cmd = readw(addr + PCI_COMMAND);
606
606
bar0 = readl(addr + PCI_BASE_ADDRESS_0);
607
607
bar1 = readl(addr + PCI_BASE_ADDRESS_1);
608
608
iounmap(addr);
···
616
618
dev_err(dev, "Failed to access Downstream Port RCRB\n");
617
619
return CXL_RESOURCE_NONE;
618
620
}
619
-
if (!(cmd & PCI_COMMAND_MEMORY))
620
-
return CXL_RESOURCE_NONE;
621
621
/* The RCRB is a Memory Window, and the MEM_TYPE_1M bit is obsolete */
622
622
if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO))
623
623
return CXL_RESOURCE_NONE;
+3
-3
drivers/cxl/cxl.h
+3
-3
drivers/cxl/cxl.h
···
592
592
* @cdat: Cached CDAT data
593
593
* @cdat_available: Should a CDAT attribute be available in sysfs
594
594
* @pci_latency: Upstream latency in picoseconds
595
-
* @gpf_dvsec: Cached GPF port DVSEC
596
595
*/
597
596
struct cxl_port {
598
597
struct device dev;
···
615
616
} cdat;
616
617
bool cdat_available;
617
618
long pci_latency;
618
-
int gpf_dvsec;
619
619
};
620
620
621
621
/**
···
662
664
* @regs: Dport parsed register blocks
663
665
* @coord: access coordinates (bandwidth and latency performance attributes)
664
666
* @link_latency: calculated PCIe downstream latency
667
+
* @gpf_dvsec: Cached GPF port DVSEC
665
668
*/
666
669
struct cxl_dport {
667
670
struct device *dport_dev;
···
674
675
struct cxl_regs regs;
675
676
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
676
677
long link_latency;
678
+
int gpf_dvsec;
677
679
};
678
680
679
681
/**
···
910
910
#define __mock static
911
911
#endif
912
912
913
-
u16 cxl_gpf_get_dvsec(struct device *dev, bool is_port);
913
+
u16 cxl_gpf_get_dvsec(struct device *dev);
914
914
915
915
#endif /* __CXL_H__ */
+1
-1
drivers/cxl/pci.c
+1
-1
drivers/cxl/pci.c
+1
-1
drivers/cxl/pmem.c
+1
-1
drivers/cxl/pmem.c
+3
-2
include/cxl/features.h
+3
-2
include/cxl/features.h
···
66
66
#ifdef CONFIG_CXL_FEATURES
67
67
inline struct cxl_features_state *to_cxlfs(struct cxl_dev_state *cxlds);
68
68
int devm_cxl_setup_features(struct cxl_dev_state *cxlds);
69
-
int devm_cxl_setup_fwctl(struct cxl_memdev *cxlmd);
69
+
int devm_cxl_setup_fwctl(struct device *host, struct cxl_memdev *cxlmd);
70
70
#else
71
71
static inline struct cxl_features_state *to_cxlfs(struct cxl_dev_state *cxlds)
72
72
{
···
78
78
return -EOPNOTSUPP;
79
79
}
80
80
81
-
static inline int devm_cxl_setup_fwctl(struct cxl_memdev *cxlmd)
81
+
static inline int devm_cxl_setup_fwctl(struct device *host,
82
+
struct cxl_memdev *cxlmd)
82
83
{
83
84
return -EOPNOTSUPP;
84
85
}