tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'i3c/for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux

Pull i3c updates from Alexandre Belloni:
"Subsystem:
- add sysfs option to rescan bus via entdaa
- fix error code handling for send_ccc_cmd

Drivers:
- mipi-i3c-hci-pci: Intel Nova Lake-H I3C support"

* tag 'i3c/for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux: (22 commits)
i3c: mipi-i3c-hci: fix IBI payload length calculation for final status
i3c: master: adi: Fix error propagation for CCCs
i3c: master: Fix error codes at send_ccc_cmd
i3c: master: Move bus_init error suppression
i3c: master: Move entdaa error suppression
i3c: master: Move rstdaa error suppression
i3c: dw: Simplify xfer cleanup with __free(kfree)
i3c: dw: Fix memory leak in dw_i3c_master_i3c_xfers()
i3c: master: renesas: Use __free(kfree) for xfer cleanup in renesas_i3c_send_ccc_cmd()
i3c: master: renesas: Fix memory leak in renesas_i3c_i3c_xfers()
i3c: master: dw-i3c: Balance PM runtime usage count on probe failure
i3c: master: dw-i3c: Fix missing reset assertion in remove() callback
i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers
i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM
i3c: mipi-i3c-hci: Allow parent to manage runtime PM
i3c: mipi-i3c-hci: Add quirk to allow IBI while runtime suspended
i3c: mipi-i3c-hci-pci: Set d3hot_delay to 0 for Intel controllers
i3c: fix missing newline in dev_err messages
i3c: master: use kzalloc_flex
i3c: mipi-i3c-hci-pci: Add support for Intel Nova Lake-H I3C
...

Linus Torvalds 401b0e0b eb5249b1

+293 -100
+20
Documentation/ABI/testing/sysfs-bus-i3c
··· 172 172 the automatic retries. Exist only when I3C constroller supports 173 173 this retry on nack feature. 174 174 175 + What: /sys/bus/i3c/devices/i3c-<bus-id>/do_daa 176 + KernelVersion: 7.0 177 + Contact: linux-i3c@vger.kernel.org 178 + Description: 179 + Write-only attribute that triggers a Dynamic Address Assignment 180 + (DAA) procedure which discovers new I3C devices on the bus. 181 + Writing a boolean true value (1, y, yes, true, on) to this 182 + attribute causes the master controller to perform DAA, which 183 + includes broadcasting an ENTDAA (Enter Dynamic Address Assignment) 184 + Common Command Code (CCC) on the bus. Writing a false value 185 + returns -EINVAL. 186 + 187 + This is useful for discovering I3C devices that were not present 188 + during initial bus initialization and are unable to issue 189 + Hot-Join. Only devices without a currently assigned dynamic address 190 + will respond to the ENTDAA broadcast and be assigned addresses. 191 + 192 + Note that this mechanism is distinct from Hot-Join, since this is 193 + controller-initiated discovery, while Hot-Join is device-initiated 194 + method to provoke controller discovery procedure.
+70 -43
drivers/i3c/master.c
··· 758 758 759 759 static DEVICE_ATTR_RW(dev_nack_retry_count); 760 760 761 + static ssize_t do_daa_store(struct device *dev, 762 + struct device_attribute *attr, 763 + const char *buf, size_t count) 764 + { 765 + struct i3c_master_controller *master = dev_to_i3cmaster(dev); 766 + bool val; 767 + int ret; 768 + 769 + if (kstrtobool(buf, &val)) 770 + return -EINVAL; 771 + 772 + if (!val) 773 + return -EINVAL; 774 + 775 + if (!master->init_done) 776 + return -EAGAIN; 777 + 778 + ret = i3c_master_do_daa(master); 779 + if (ret) 780 + return ret; 781 + 782 + return count; 783 + } 784 + 785 + static DEVICE_ATTR_WO(do_daa); 786 + 761 787 static struct attribute *i3c_masterdev_attrs[] = { 762 788 &dev_attr_mode.attr, 763 789 &dev_attr_current_master.attr, ··· 795 769 &dev_attr_dynamic_address.attr, 796 770 &dev_attr_hdrcap.attr, 797 771 &dev_attr_hotjoin.attr, 772 + &dev_attr_do_daa.attr, 798 773 NULL, 799 774 }; 800 775 ATTRIBUTE_GROUPS(i3c_masterdev); ··· 925 898 cmd->err = I3C_ERROR_UNKNOWN; 926 899 } 927 900 901 + /** 902 + * i3c_master_send_ccc_cmd_locked() - send a CCC (Common Command Codes) 903 + * @master: master used to send frames on the bus 904 + * @cmd: command to send 905 + * 906 + * Return: 0 in case of success, or a negative error code otherwise. 907 + * I3C Mx error codes are stored in cmd->err. 908 + */ 928 909 static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master, 929 910 struct i3c_ccc_cmd *cmd) 930 911 { 931 - int ret; 932 - 933 912 if (!cmd || !master) 934 913 return -EINVAL; 935 914 ··· 953 920 !master->ops->supports_ccc_cmd(master, cmd)) 954 921 return -EOPNOTSUPP; 955 922 956 - ret = master->ops->send_ccc_cmd(master, cmd); 957 - if (ret) { 958 - if (cmd->err != I3C_ERROR_UNKNOWN) 959 - return cmd->err; 960 - 961 - return ret; 962 - } 963 - 964 - return 0; 923 + return master->ops->send_ccc_cmd(master, cmd); 965 924 } 966 925 967 926 static struct i2c_dev_desc * ··· 1041 1016 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1042 1017 i3c_ccc_cmd_dest_cleanup(&dest); 1043 1018 1019 + /* No active devices on the bus. */ 1020 + if (ret && cmd.err == I3C_ERROR_M2) 1021 + ret = 0; 1022 + 1044 1023 return ret; 1045 1024 } 1046 1025 ··· 1061 1032 * 1062 1033 * This function must be called with the bus lock held in write mode. 1063 1034 * 1064 - * Return: 0 in case of success, a positive I3C error code if the error is 1065 - * one of the official Mx error codes, and a negative error code otherwise. 1035 + * Return: 0 in case of success, or a negative error code otherwise. 1066 1036 */ 1067 1037 int i3c_master_entdaa_locked(struct i3c_master_controller *master) 1068 1038 { ··· 1074 1046 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1075 1047 i3c_ccc_cmd_dest_cleanup(&dest); 1076 1048 1049 + /* No active devices need an address. */ 1050 + if (ret && cmd.err == I3C_ERROR_M2) 1051 + ret = 0; 1052 + 1077 1053 return ret; 1078 1054 } 1079 1055 EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked); 1080 1056 1081 1057 static int i3c_master_enec_disec_locked(struct i3c_master_controller *master, 1082 - u8 addr, bool enable, u8 evts) 1058 + u8 addr, bool enable, u8 evts, 1059 + bool suppress_m2) 1083 1060 { 1084 1061 struct i3c_ccc_events *events; 1085 1062 struct i3c_ccc_cmd_dest dest; ··· 1104 1071 ret = i3c_master_send_ccc_cmd_locked(master, &cmd); 1105 1072 i3c_ccc_cmd_dest_cleanup(&dest); 1106 1073 1074 + if (suppress_m2 && ret && cmd.err == I3C_ERROR_M2) 1075 + ret = 0; 1076 + 1107 1077 return ret; 1108 1078 } 1109 1079 ··· 1121 1085 * 1122 1086 * This function must be called with the bus lock held in write mode. 1123 1087 * 1124 - * Return: 0 in case of success, a positive I3C error code if the error is 1125 - * one of the official Mx error codes, and a negative error code otherwise. 1088 + * Return: 0 in case of success, or a negative error code otherwise. 1126 1089 */ 1127 1090 int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr, 1128 1091 u8 evts) 1129 1092 { 1130 - return i3c_master_enec_disec_locked(master, addr, false, evts); 1093 + return i3c_master_enec_disec_locked(master, addr, false, evts, false); 1131 1094 } 1132 1095 EXPORT_SYMBOL_GPL(i3c_master_disec_locked); 1133 1096 ··· 1141 1106 * 1142 1107 * This function must be called with the bus lock held in write mode. 1143 1108 * 1144 - * Return: 0 in case of success, a positive I3C error code if the error is 1145 - * one of the official Mx error codes, and a negative error code otherwise. 1109 + * Return: 0 in case of success, or a negative error code otherwise. 1146 1110 */ 1147 1111 int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr, 1148 1112 u8 evts) 1149 1113 { 1150 - return i3c_master_enec_disec_locked(master, addr, true, evts); 1114 + return i3c_master_enec_disec_locked(master, addr, true, evts, false); 1151 1115 } 1152 1116 EXPORT_SYMBOL_GPL(i3c_master_enec_locked); 1153 1117 ··· 1166 1132 * 1167 1133 * This function must be called with the bus lock held in write mode. 1168 1134 * 1169 - * Return: 0 in case of success, a positive I3C error code if the error is 1170 - * one of the official Mx error codes, and a negative error code otherwise. 1135 + * Return: 0 in case of success, or a negative error code otherwise. 1171 1136 */ 1172 1137 int i3c_master_defslvs_locked(struct i3c_master_controller *master) 1173 1138 { ··· 1827 1794 1828 1795 i3c_bus_maintenance_lock(&master->bus); 1829 1796 1830 - if (rstdaa) { 1797 + if (rstdaa) 1831 1798 rstret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 1832 - if (rstret == I3C_ERROR_M2) 1833 - rstret = 0; 1834 - } 1835 1799 1836 1800 ret = master->ops->do_daa(master); 1837 1801 ··· 2123 2093 * (assigned by the bootloader for example). 2124 2094 */ 2125 2095 ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); 2126 - if (ret && ret != I3C_ERROR_M2) 2096 + if (ret) 2127 2097 goto err_bus_cleanup; 2128 2098 2129 2099 if (master->ops->set_speed) { ··· 2132 2102 goto err_bus_cleanup; 2133 2103 } 2134 2104 2135 - /* Disable all slave events before starting DAA. */ 2136 - ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR, 2137 - I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | 2138 - I3C_CCC_EVENT_HJ); 2139 - if (ret && ret != I3C_ERROR_M2) 2105 + /* 2106 + * Disable all slave events before starting DAA. When no active device 2107 + * is on the bus, returns Mx error code M2, this error is ignored. 2108 + */ 2109 + ret = i3c_master_enec_disec_locked(master, I3C_BROADCAST_ADDR, false, 2110 + I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | 2111 + I3C_CCC_EVENT_HJ, true); 2112 + if (ret) 2140 2113 goto err_bus_cleanup; 2141 2114 2142 2115 /* ··· 2429 2396 * DEFSLVS command. 2430 2397 */ 2431 2398 if (boardinfo->base.flags & I2C_CLIENT_TEN) { 2432 - dev_err(dev, "I2C device with 10 bit address not supported."); 2399 + dev_err(dev, "I2C device with 10 bit address not supported.\n"); 2433 2400 return -EOPNOTSUPP; 2434 2401 } 2435 2402 ··· 2826 2793 struct i3c_generic_ibi_pool { 2827 2794 spinlock_t lock; 2828 2795 unsigned int num_slots; 2829 - struct i3c_generic_ibi_slot *slots; 2830 2796 void *payload_buf; 2831 2797 struct list_head free_slots; 2832 2798 struct list_head pending; 2799 + struct i3c_generic_ibi_slot slots[] __counted_by(num_slots); 2833 2800 }; 2834 2801 2835 2802 /** ··· 2857 2824 WARN_ON(nslots != pool->num_slots); 2858 2825 2859 2826 kfree(pool->payload_buf); 2860 - kfree(pool->slots); 2861 2827 kfree(pool); 2862 2828 } 2863 2829 EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool); ··· 2879 2847 unsigned int i; 2880 2848 int ret; 2881 2849 2882 - pool = kzalloc_obj(*pool); 2850 + pool = kzalloc_flex(*pool, slots, req->num_slots); 2883 2851 if (!pool) 2884 2852 return ERR_PTR(-ENOMEM); 2853 + 2854 + pool->num_slots = req->num_slots; 2885 2855 2886 2856 spin_lock_init(&pool->lock); 2887 2857 INIT_LIST_HEAD(&pool->free_slots); 2888 2858 INIT_LIST_HEAD(&pool->pending); 2889 - 2890 - pool->slots = kzalloc_objs(*slot, req->num_slots); 2891 - if (!pool->slots) { 2892 - ret = -ENOMEM; 2893 - goto err_free_pool; 2894 - } 2895 2859 2896 2860 if (req->max_payload_len) { 2897 2861 pool->payload_buf = kcalloc(req->num_slots, ··· 2907 2879 (i * req->max_payload_len); 2908 2880 2909 2881 list_add_tail(&slot->node, &pool->free_slots); 2910 - pool->num_slots++; 2911 2882 } 2912 2883 2913 2884 return pool;
+2 -3
drivers/i3c/master/adi-i3c-master.c
··· 361 361 362 362 cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]); 363 363 364 - return 0; 364 + return xfer->ret; 365 365 } 366 366 367 367 static int adi_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, ··· 655 655 656 656 writel(irq_mask, master->regs + REG_IRQ_MASK); 657 657 658 - /* DAA always finishes with CE2_ERROR or NACK_RESP */ 659 - if (ret && ret != I3C_ERROR_M2) 658 + if (ret) 660 659 return ret; 661 660 662 661 /* Add I3C devices discovered */
+14 -37
drivers/i3c/master/dw-i3c-master.c
··· 7 7 8 8 #include <linux/bitfield.h> 9 9 #include <linux/bitops.h> 10 + #include <linux/cleanup.h> 10 11 #include <linux/clk.h> 11 12 #include <linux/completion.h> 12 13 #include <linux/err.h> ··· 394 393 return xfer; 395 394 } 396 395 397 - static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) 398 - { 399 - kfree(xfer); 400 - } 401 - 402 396 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) 403 397 { 404 398 struct dw_i3c_xfer *xfer = master->xferqueue.cur; ··· 711 715 static int dw_i3c_ccc_set(struct dw_i3c_master *master, 712 716 struct i3c_ccc_cmd *ccc) 713 717 { 714 - struct dw_i3c_xfer *xfer; 715 718 struct dw_i3c_cmd *cmd; 716 719 int ret, pos = 0; 717 720 ··· 720 725 return pos; 721 726 } 722 727 723 - xfer = dw_i3c_master_alloc_xfer(master, 1); 728 + struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 724 729 if (!xfer) 725 730 return -ENOMEM; 726 731 ··· 745 750 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 746 751 ccc->err = I3C_ERROR_M2; 747 752 748 - dw_i3c_master_free_xfer(xfer); 749 - 750 753 return ret; 751 754 } 752 755 753 756 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) 754 757 { 755 - struct dw_i3c_xfer *xfer; 756 758 struct dw_i3c_cmd *cmd; 757 759 int ret, pos; 758 760 ··· 757 765 if (pos < 0) 758 766 return pos; 759 767 760 - xfer = dw_i3c_master_alloc_xfer(master, 1); 768 + struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 761 769 if (!xfer) 762 770 return -ENOMEM; 763 771 ··· 782 790 ret = xfer->ret; 783 791 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 784 792 ccc->err = I3C_ERROR_M2; 785 - dw_i3c_master_free_xfer(xfer); 786 793 787 794 return ret; 788 795 } ··· 828 837 static int dw_i3c_master_daa(struct i3c_master_controller *m) 829 838 { 830 839 struct dw_i3c_master *master = to_dw_i3c_master(m); 831 - struct dw_i3c_xfer *xfer; 832 840 struct dw_i3c_cmd *cmd; 833 841 u32 olddevs, newdevs; 834 842 u8 last_addr = 0; 835 843 int ret, pos; 844 + 845 + struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1); 846 + if (!xfer) 847 + return -ENOMEM; 836 848 837 849 ret = pm_runtime_resume_and_get(master->dev); 838 850 if (ret < 0) { ··· 870 876 ret = 0; 871 877 } 872 878 873 - xfer = dw_i3c_master_alloc_xfer(master, 1); 874 - if (!xfer) { 875 - ret = -ENOMEM; 876 - goto rpm_out; 877 - } 878 - 879 879 pos = dw_i3c_master_get_free_pos(master); 880 880 if (pos < 0) { 881 - dw_i3c_master_free_xfer(xfer); 882 881 ret = pos; 883 882 goto rpm_out; 884 883 } ··· 896 909 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr); 897 910 } 898 911 899 - dw_i3c_master_free_xfer(xfer); 900 - 901 912 rpm_out: 902 913 pm_runtime_put_autosuspend(master->dev); 903 914 return ret; ··· 909 924 struct i3c_master_controller *m = i3c_dev_get_master(dev); 910 925 struct dw_i3c_master *master = to_dw_i3c_master(m); 911 926 unsigned int nrxwords = 0, ntxwords = 0; 912 - struct dw_i3c_xfer *xfer; 913 927 int i, ret = 0; 914 928 915 929 if (!i3c_nxfers) ··· 928 944 nrxwords > master->caps.datafifodepth) 929 945 return -EOPNOTSUPP; 930 946 931 - xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 947 + struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 932 948 if (!xfer) 933 949 return -ENOMEM; 934 950 ··· 979 995 } 980 996 981 997 ret = xfer->ret; 982 - dw_i3c_master_free_xfer(xfer); 983 998 984 999 pm_runtime_put_autosuspend(master->dev); 985 1000 return ret; ··· 1067 1084 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1068 1085 struct dw_i3c_master *master = to_dw_i3c_master(m); 1069 1086 unsigned int nrxwords = 0, ntxwords = 0; 1070 - struct dw_i3c_xfer *xfer; 1071 1087 int i, ret = 0; 1072 1088 1073 1089 if (!i2c_nxfers) ··· 1086 1104 nrxwords > master->caps.datafifodepth) 1087 1105 return -EOPNOTSUPP; 1088 1106 1089 - xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 1107 + struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 1090 1108 if (!xfer) 1091 1109 return -ENOMEM; 1092 1110 ··· 1095 1113 dev_err(master->dev, 1096 1114 "<%s> cannot resume i3c bus master, err: %d\n", 1097 1115 __func__, ret); 1098 - dw_i3c_master_free_xfer(xfer); 1099 1116 return ret; 1100 1117 } 1101 1118 ··· 1126 1145 dw_i3c_master_dequeue_xfer(master, xfer); 1127 1146 1128 1147 ret = xfer->ret; 1129 - dw_i3c_master_free_xfer(xfer); 1130 1148 1131 1149 pm_runtime_put_autosuspend(master->dev); 1132 1150 return ret; ··· 1586 1606 if (IS_ERR(master->pclk)) 1587 1607 return PTR_ERR(master->pclk); 1588 1608 1589 - master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 1590 - "core_rst"); 1609 + master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, 1610 + "core_rst"); 1591 1611 if (IS_ERR(master->core_rst)) 1592 1612 return PTR_ERR(master->core_rst); 1593 - 1594 - reset_control_deassert(master->core_rst); 1595 1613 1596 1614 spin_lock_init(&master->xferqueue.lock); 1597 1615 INIT_LIST_HEAD(&master->xferqueue.list); ··· 1602 1624 dw_i3c_master_irq_handler, 0, 1603 1625 dev_name(&pdev->dev), master); 1604 1626 if (ret) 1605 - goto err_assert_rst; 1627 + return ret; 1606 1628 1607 1629 platform_set_drvdata(pdev, master); 1608 1630 ··· 1647 1669 return 0; 1648 1670 1649 1671 err_disable_pm: 1672 + if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) 1673 + pm_runtime_put_noidle(&pdev->dev); 1650 1674 pm_runtime_disable(&pdev->dev); 1651 1675 pm_runtime_set_suspended(&pdev->dev); 1652 1676 pm_runtime_dont_use_autosuspend(&pdev->dev); 1653 - 1654 - err_assert_rst: 1655 - reset_control_assert(master->core_rst); 1656 1677 1657 1678 return ret; 1658 1679 }
+1 -1
drivers/i3c/master/i3c-master-cdns.c
··· 1143 1143 } 1144 1144 1145 1145 ret = i3c_master_entdaa_locked(&master->base); 1146 - if (ret && ret != I3C_ERROR_M2) 1146 + if (ret) 1147 1147 return ret; 1148 1148 1149 1149 newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
+30 -5
drivers/i3c/master/mipi-i3c-hci/core.c
··· 759 759 return 0; 760 760 } 761 761 762 - static int i3c_hci_runtime_suspend(struct device *dev) 762 + int i3c_hci_rpm_suspend(struct device *dev) 763 763 { 764 764 struct i3c_hci *hci = dev_get_drvdata(dev); 765 765 int ret; ··· 776 776 777 777 return 0; 778 778 } 779 + EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); 779 780 780 - static int i3c_hci_runtime_resume(struct device *dev) 781 + int i3c_hci_rpm_resume(struct device *dev) 781 782 { 782 783 struct i3c_hci *hci = dev_get_drvdata(dev); 783 784 int ret; ··· 800 799 reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE | HC_CONTROL_HOT_JOIN_CTRL); 801 800 802 801 return 0; 802 + } 803 + EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); 804 + 805 + static int i3c_hci_runtime_suspend(struct device *dev) 806 + { 807 + struct i3c_hci *hci = dev_get_drvdata(dev); 808 + 809 + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) 810 + return 0; 811 + 812 + return i3c_hci_rpm_suspend(dev); 813 + } 814 + 815 + static int i3c_hci_runtime_resume(struct device *dev) 816 + { 817 + struct i3c_hci *hci = dev_get_drvdata(dev); 818 + 819 + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) 820 + return 0; 821 + 822 + return i3c_hci_rpm_resume(dev); 803 823 } 804 824 805 825 static int i3c_hci_suspend(struct device *dev) ··· 865 843 { 866 844 return i3c_hci_resume_common(dev, true); 867 845 } 868 - 869 - #define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 870 846 871 847 static void i3c_hci_rpm_enable(struct device *dev) 872 848 { ··· 1016 996 if (hci->quirks & HCI_QUIRK_RPM_ALLOWED) 1017 997 i3c_hci_rpm_enable(&pdev->dev); 1018 998 999 + if (hci->quirks & HCI_QUIRK_RPM_IBI_ALLOWED) 1000 + hci->master.rpm_ibi_allowed = true; 1001 + 1019 1002 return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); 1020 1003 } 1021 1004 ··· 1042 1019 MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); 1043 1020 1044 1021 static const struct platform_device_id i3c_hci_driver_ids[] = { 1045 - { .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED }, 1022 + { .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | 1023 + HCI_QUIRK_RPM_IBI_ALLOWED | 1024 + HCI_QUIRK_RPM_PARENT_MANAGED }, 1046 1025 { /* sentinel */ } 1047 1026 }; 1048 1027 MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
+4 -1
drivers/i3c/master/mipi-i3c-hci/dma.c
··· 754 754 if (!(ibi_status & IBI_LAST_STATUS)) { 755 755 ibi_size += chunks * rh->ibi_chunk_sz; 756 756 } else { 757 - ibi_size += FIELD_GET(IBI_DATA_LENGTH, ibi_status); 757 + if (chunks) { 758 + ibi_size += (chunks - 1) * rh->ibi_chunk_sz; 759 + ibi_size += FIELD_GET(IBI_DATA_LENGTH, ibi_status); 760 + } 758 761 last_ptr = ptr; 759 762 break; 760 763 }
+7
drivers/i3c/master/mipi-i3c-hci/hci.h
··· 150 150 #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */ 151 151 #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */ 152 152 #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ 153 + #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed while runtime suspended */ 154 + #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by parent device */ 153 155 154 156 /* global functions */ 155 157 void mipi_i3c_hci_resume(struct i3c_hci *hci); ··· 161 159 void amd_set_resp_buf_thld(struct i3c_hci *hci); 162 160 void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); 163 161 int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n); 162 + 163 + #define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 164 + 165 + int i3c_hci_rpm_suspend(struct device *dev); 166 + int i3c_hci_rpm_resume(struct device *dev); 164 167 165 168 #endif
+138
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
··· 9 9 #include <linux/acpi.h> 10 10 #include <linux/bitfield.h> 11 11 #include <linux/debugfs.h> 12 + #include <linux/i3c/master.h> 12 13 #include <linux/idr.h> 13 14 #include <linux/iopoll.h> 14 15 #include <linux/kernel.h> ··· 21 20 #include <linux/pm_qos.h> 22 21 #include <linux/pm_runtime.h> 23 22 23 + #include "hci.h" 24 + 24 25 /* 25 26 * There can up to 15 instances, but implementations have at most 2 at this 26 27 * time. 27 28 */ 28 29 #define INST_MAX 2 29 30 31 + struct mipi_i3c_hci_pci_instance { 32 + struct device *dev; 33 + bool operational; 34 + }; 35 + 30 36 struct mipi_i3c_hci_pci { 31 37 struct pci_dev *pci; 32 38 void __iomem *base; 33 39 const struct mipi_i3c_hci_pci_info *info; 40 + struct mipi_i3c_hci_pci_instance instance[INST_MAX]; 34 41 void *private; 35 42 }; 36 43 ··· 49 40 int id[INST_MAX]; 50 41 u32 instance_offset[INST_MAX]; 51 42 int instance_count; 43 + bool control_instance_pm; 52 44 }; 53 45 54 46 #define INTEL_PRIV_OFFSET 0x2b0 ··· 174 164 dma_set_mask_and_coherent(&hci->pci->dev, DMA_BIT_MASK(64)); 175 165 176 166 hci->pci->d3cold_delay = 0; 167 + hci->pci->d3hot_delay = 0; 177 168 178 169 hci->private = host; 179 170 host->priv = priv; ··· 200 189 .id = {0, 1}, 201 190 .instance_offset = {0, 0x400}, 202 191 .instance_count = 2, 192 + .control_instance_pm = true, 203 193 }; 204 194 205 195 static const struct mipi_i3c_hci_pci_info intel_mi_2_info = { ··· 210 198 .id = {2, 3}, 211 199 .instance_offset = {0, 0x400}, 212 200 .instance_count = 2, 201 + .control_instance_pm = true, 213 202 }; 214 203 215 204 static const struct mipi_i3c_hci_pci_info intel_si_2_info = { ··· 220 207 .id = {2}, 221 208 .instance_offset = {0}, 222 209 .instance_count = 1, 210 + .control_instance_pm = true, 223 211 }; 212 + 213 + static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, struct device *dev) 214 + { 215 + for (int i = 0; i < INST_MAX; i++) { 216 + if (!hci->instance[i].dev) 217 + hci->instance[i].dev = dev; 218 + if (hci->instance[i].dev == dev) 219 + return i; 220 + } 221 + 222 + return -1; 223 + } 224 + 225 + #define HC_CONTROL 0x04 226 + #define HC_CONTROL_BUS_ENABLE BIT(31) 227 + 228 + static bool __mipi_i3c_hci_pci_is_operational(struct device *dev) 229 + { 230 + const struct mipi_i3c_hci_platform_data *pdata = dev->platform_data; 231 + u32 hc_control = readl(pdata->base_regs + HC_CONTROL); 232 + 233 + return hc_control & HC_CONTROL_BUS_ENABLE; 234 + } 235 + 236 + static bool mipi_i3c_hci_pci_is_operational(struct device *dev, bool update) 237 + { 238 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev->parent); 239 + int pos = mipi_i3c_hci_pci_find_instance(hci, dev); 240 + 241 + if (pos < 0) { 242 + dev_err(dev, "%s: I3C instance not found\n", __func__); 243 + return false; 244 + } 245 + 246 + if (update) 247 + hci->instance[pos].operational = __mipi_i3c_hci_pci_is_operational(dev); 248 + 249 + return hci->instance[pos].operational; 250 + } 251 + 252 + struct mipi_i3c_hci_pci_pm_data { 253 + struct device *dev[INST_MAX]; 254 + int dev_cnt; 255 + }; 256 + 257 + static bool mipi_i3c_hci_pci_is_mfd(struct device *dev) 258 + { 259 + return dev_is_platform(dev) && mfd_get_cell(to_platform_device(dev)); 260 + } 261 + 262 + static int mipi_i3c_hci_pci_suspend_instance(struct device *dev, void *data) 263 + { 264 + struct mipi_i3c_hci_pci_pm_data *pm_data = data; 265 + int ret; 266 + 267 + if (!mipi_i3c_hci_pci_is_mfd(dev) || 268 + !mipi_i3c_hci_pci_is_operational(dev, true)) 269 + return 0; 270 + 271 + ret = i3c_hci_rpm_suspend(dev); 272 + if (ret) 273 + return ret; 274 + 275 + pm_data->dev[pm_data->dev_cnt++] = dev; 276 + 277 + return 0; 278 + } 279 + 280 + static int mipi_i3c_hci_pci_resume_instance(struct device *dev, void *data) 281 + { 282 + struct mipi_i3c_hci_pci_pm_data *pm_data = data; 283 + int ret; 284 + 285 + if (!mipi_i3c_hci_pci_is_mfd(dev) || 286 + !mipi_i3c_hci_pci_is_operational(dev, false)) 287 + return 0; 288 + 289 + ret = i3c_hci_rpm_resume(dev); 290 + if (ret) 291 + return ret; 292 + 293 + pm_data->dev[pm_data->dev_cnt++] = dev; 294 + 295 + return 0; 296 + } 297 + 298 + static int mipi_i3c_hci_pci_suspend(struct device *dev) 299 + { 300 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev); 301 + struct mipi_i3c_hci_pci_pm_data pm_data = {}; 302 + int ret; 303 + 304 + if (!hci->info->control_instance_pm) 305 + return 0; 306 + 307 + ret = device_for_each_child_reverse(dev, &pm_data, mipi_i3c_hci_pci_suspend_instance); 308 + if (ret) 309 + for (int i = 0; i < pm_data.dev_cnt; i++) 310 + i3c_hci_rpm_resume(pm_data.dev[i]); 311 + 312 + return ret; 313 + } 314 + 315 + static int mipi_i3c_hci_pci_resume(struct device *dev) 316 + { 317 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev); 318 + struct mipi_i3c_hci_pci_pm_data pm_data = {}; 319 + int ret; 320 + 321 + if (!hci->info->control_instance_pm) 322 + return 0; 323 + 324 + ret = device_for_each_child(dev, &pm_data, mipi_i3c_hci_pci_resume_instance); 325 + if (ret) 326 + for (int i = 0; i < pm_data.dev_cnt; i++) 327 + i3c_hci_rpm_suspend(pm_data.dev[i]); 328 + 329 + return ret; 330 + } 224 331 225 332 static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) 226 333 { ··· 455 322 456 323 /* PM ops must exist for PCI to put a device to a low power state */ 457 324 static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops = { 325 + RUNTIME_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume, NULL) 326 + SYSTEM_SLEEP_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume) 458 327 }; 459 328 460 329 static const struct pci_device_id mipi_i3c_hci_pci_devices[] = { ··· 472 337 /* Nova Lake-S */ 473 338 { PCI_VDEVICE(INTEL, 0x6e2c), (kernel_ulong_t)&intel_mi_1_info}, 474 339 { PCI_VDEVICE(INTEL, 0x6e2d), (kernel_ulong_t)&intel_mi_2_info}, 340 + /* Nova Lake-H */ 341 + { PCI_VDEVICE(INTEL, 0xd37c), (kernel_ulong_t)&intel_mi_1_info}, 342 + { PCI_VDEVICE(INTEL, 0xd36f), (kernel_ulong_t)&intel_mi_2_info}, 475 343 { }, 476 344 }; 477 345 MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices);
+3 -6
drivers/i3c/master/renesas-i3c.c
··· 8 8 9 9 #include <linux/bitfield.h> 10 10 #include <linux/bitops.h> 11 + #include <linux/cleanup.h> 11 12 #include <linux/clk.h> 12 13 #include <linux/completion.h> 13 14 #include <linux/err.h> ··· 748 747 struct i3c_ccc_cmd *ccc) 749 748 { 750 749 struct renesas_i3c *i3c = to_renesas_i3c(m); 751 - struct renesas_i3c_xfer *xfer; 752 750 struct renesas_i3c_cmd *cmd; 753 751 int ret, pos = 0; 754 752 ··· 757 757 return pos; 758 758 } 759 759 760 - xfer = renesas_i3c_alloc_xfer(i3c, 1); 760 + struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 761 761 if (!xfer) 762 762 return -ENOMEM; 763 763 ··· 806 806 if (ret) 807 807 ccc->err = I3C_ERROR_M2; 808 808 809 - kfree(xfer); 810 - 811 809 return ret; 812 810 } 813 811 ··· 815 817 struct i3c_master_controller *m = i3c_dev_get_master(dev); 816 818 struct renesas_i3c *i3c = to_renesas_i3c(m); 817 819 struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 818 - struct renesas_i3c_xfer *xfer; 819 820 int i; 820 821 821 822 /* Enable I3C bus. */ 822 823 renesas_i3c_bus_enable(m, true); 823 824 824 - xfer = renesas_i3c_alloc_xfer(i3c, 1); 825 + struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1); 825 826 if (!xfer) 826 827 return -ENOMEM; 827 828
+4 -4
drivers/i3c/master/svc-i3c-master.c
··· 344 344 { 345 345 u32 reg; 346 346 347 - /* Set RX and TX tigger levels, flush FIFOs */ 347 + /* Set RX and TX trigger levels, flush FIFOs */ 348 348 reg = SVC_I3C_MDATACTRL_FLUSHTB | 349 349 SVC_I3C_MDATACTRL_FLUSHRB | 350 350 SVC_I3C_MDATACTRL_UNLOCK_TRIG | ··· 572 572 * 3. IBI isr writes an AutoIBI request. 573 573 * 4. The controller will not start AutoIBI process because SDA is not low. 574 574 * 5. IBIWON polling times out. 575 - * 6. Controller reamins in AutoIBI state and doesn't accept EmitStop request. 575 + * 6. Controller remains in AutoIBI state and doesn't accept EmitStop request. 576 576 */ 577 577 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 578 578 SVC_I3C_MCTRL_TYPE_I3C | ··· 774 774 775 775 /* 776 776 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a 777 - * duty-cycle tuned so that high levels are filetered out by 777 + * duty-cycle tuned so that high levels are filtered out by 778 778 * the 50ns filter (target being 40ns). 779 779 */ 780 780 odhpp = 1; ··· 1268 1268 /* Configure IBI auto-rules */ 1269 1269 ret = svc_i3c_update_ibirules(master); 1270 1270 if (ret) 1271 - dev_err(master->dev, "Cannot handle such a list of devices"); 1271 + dev_err(master->dev, "Cannot handle such a list of devices\n"); 1272 1272 1273 1273 rpm_out: 1274 1274 pm_runtime_put_autosuspend(master->dev);