Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v5.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A bunch of driver specific fixes, plus a fix for spi-mem's status
polling for devices that use GPIO chip selects and a DT bindings
examples fix that helps with the validation work"
* tag 'spi-fix-v5.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: rockchip: Unmask IRQ at the final to avoid preemption
spi: dt-bindings: Fix unevaluatedProperties warnings in examples
spi: spi-mem: Fix spi_mem_poll_status()
spi: cadence: Detect transmit FIFO depth
spi: spi-cadence: Fix SPI CS gets toggling sporadically
+39
-13
-1
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
-1
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
-1
Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
-1
Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+31
-6
drivers/spi/spi-cadence.c
+31
-6
drivers/spi/spi-cadence.c
···
69
69
#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
70
70
#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
71
71
#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
72
+
#define CDNS_SPI_NOSS 0x3C /* No Slave select */
72
73
73
74
/*
74
75
* SPI Interrupt Registers bit Masks
···
93
92
#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
94
93
#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
95
94
96
-
/* SPI FIFO depth in bytes */
97
-
#define CDNS_SPI_FIFO_DEPTH 128
98
-
99
95
/* Default number of chip select lines */
100
96
#define CDNS_SPI_DEFAULT_NUM_CS 4
101
97
···
108
110
* @rx_bytes: Number of bytes requested
109
111
* @dev_busy: Device busy flag
110
112
* @is_decoded_cs: Flag for decoder property set or not
113
+
* @tx_fifo_depth: Depth of the TX FIFO
111
114
*/
112
115
struct cdns_spi {
113
116
void __iomem *regs;
···
122
123
int rx_bytes;
123
124
u8 dev_busy;
124
125
u32 is_decoded_cs;
126
+
unsigned int tx_fifo_depth;
125
127
};
126
128
127
129
/* Macros for the SPI controller read/write */
···
304
304
{
305
305
unsigned long trans_cnt = 0;
306
306
307
-
while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
307
+
while ((trans_cnt < xspi->tx_fifo_depth) &&
308
308
(xspi->tx_bytes > 0)) {
309
309
310
310
/* When xspi in busy condition, bytes may send failed,
···
450
450
* @master: Pointer to the spi_master structure which provides
451
451
* information about the controller.
452
452
*
453
-
* This function disables the SPI master controller.
453
+
* This function disables the SPI master controller when no slave selected.
454
454
*
455
455
* Return: 0 always
456
456
*/
457
457
static int cdns_unprepare_transfer_hardware(struct spi_master *master)
458
458
{
459
459
struct cdns_spi *xspi = spi_master_get_devdata(master);
460
+
u32 ctrl_reg;
460
461
461
-
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
462
+
/* Disable the SPI if slave is deselected */
463
+
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
464
+
ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
465
+
if (ctrl_reg == CDNS_SPI_NOSS)
466
+
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
462
467
463
468
return 0;
469
+
}
470
+
471
+
/**
472
+
* cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
473
+
* @xspi: Pointer to the cdns_spi structure
474
+
*
475
+
* The depth of the TX FIFO is a synthesis configuration parameter of the SPI
476
+
* IP. The FIFO threshold register is sized so that its maximum value can be the
477
+
* FIFO size - 1. This is used to detect the size of the FIFO.
478
+
*/
479
+
static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
480
+
{
481
+
/* The MSBs will get truncated giving us the size of the FIFO */
482
+
cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
483
+
xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
484
+
485
+
/* Reset to default */
486
+
cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
464
487
}
465
488
466
489
/**
···
557
534
&xspi->is_decoded_cs);
558
535
if (ret < 0)
559
536
xspi->is_decoded_cs = 0;
537
+
538
+
cdns_spi_detect_fifo_depth(xspi);
560
539
561
540
/* SPI controller initializations */
562
541
cdns_spi_init_hw(xspi);
+1
-1
drivers/spi/spi-mem.c
+1
-1
drivers/spi/spi-mem.c
+7
-4
drivers/spi/spi-rockchip.c
+7
-4
drivers/spi/spi-rockchip.c
···
381
381
rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
382
382
rs->rx_left = xfer->len / rs->n_bytes;
383
383
384
-
if (rs->cs_inactive)
385
-
writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
386
-
else
387
-
writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
384
+
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
385
+
388
386
spi_enable_chip(rs, true);
389
387
390
388
if (rs->tx_left)
391
389
rockchip_spi_pio_writer(rs);
390
+
391
+
if (rs->cs_inactive)
392
+
writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
393
+
else
394
+
writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
392
395
393
396
/* 1 means the transfer is in progress */
394
397
return 1;