Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: airoha: generalize pins/group/function/confs handling
In preparation for support of Airoha AN7583, generalize
pins/group/function/confs handling and move them in match_data.
Inner function will base the values on the pinctrl priv struct instead of
relying on hardcoded struct.
This permits to use different PIN data while keeping the same logic.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Christian Marangi
and committed by
Linus Walleij
4043b0c4
9322da93
+317
-248
+317
-248
drivers/pinctrl/mediatek/pinctrl-airoha.c
+317
-248
drivers/pinctrl/mediatek/pinctrl-airoha.c
···
30
30
#include "../pinconf.h"
31
31
#include "../pinmux.h"
32
32
33
-
#define PINCTRL_PIN_GROUP(id) \
34
-
PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
33
+
#define PINCTRL_PIN_GROUP(id, table) \
34
+
PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
35
35
36
-
#define PINCTRL_FUNC_DESC(id) \
36
+
#define PINCTRL_FUNC_DESC(id, table) \
37
37
{ \
38
-
.desc = PINCTRL_PINFUNCTION(#id, id##_groups, \
39
-
ARRAY_SIZE(id##_groups)), \
40
-
.groups = id##_func_group, \
41
-
.group_size = ARRAY_SIZE(id##_func_group), \
38
+
.desc = PINCTRL_PINFUNCTION(#id, table##_groups, \
39
+
ARRAY_SIZE(table##_groups)),\
40
+
.groups = table##_func_group, \
41
+
.group_size = ARRAY_SIZE(table##_func_group), \
42
42
}
43
43
44
44
#define PINCTRL_CONF_DESC(p, offset, mask) \
···
357
357
u32 irq_type[AIROHA_NUM_PINS];
358
358
};
359
359
360
+
struct airoha_pinctrl_confs_info {
361
+
const struct airoha_pinctrl_conf *confs;
362
+
unsigned int num_confs;
363
+
};
364
+
365
+
enum airoha_pinctrl_confs_type {
366
+
AIROHA_PINCTRL_CONFS_PULLUP,
367
+
AIROHA_PINCTRL_CONFS_PULLDOWN,
368
+
AIROHA_PINCTRL_CONFS_DRIVE_E2,
369
+
AIROHA_PINCTRL_CONFS_DRIVE_E4,
370
+
AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
371
+
372
+
AIROHA_PINCTRL_CONFS_MAX,
373
+
};
374
+
360
375
struct airoha_pinctrl {
361
376
struct pinctrl_dev *ctrl;
377
+
378
+
struct pinctrl_desc desc;
379
+
const struct pingroup *grps;
380
+
const struct airoha_pinctrl_func *funcs;
381
+
const struct airoha_pinctrl_confs_info *confs_info;
362
382
363
383
struct regmap *chip_scu;
364
384
struct regmap *regmap;
···
386
366
struct airoha_pinctrl_gpiochip gpiochip;
387
367
};
388
368
389
-
static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
369
+
struct airoha_pinctrl_match_data {
370
+
const struct pinctrl_pin_desc *pins;
371
+
const unsigned int num_pins;
372
+
const struct pingroup *grps;
373
+
const unsigned int num_grps;
374
+
const struct airoha_pinctrl_func *funcs;
375
+
const unsigned int num_funcs;
376
+
const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
377
+
};
378
+
379
+
static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
390
380
PINCTRL_PIN(0, "uart1_txd"),
391
381
PINCTRL_PIN(1, "uart1_rxd"),
392
382
PINCTRL_PIN(2, "i2c_scl"),
···
457
427
PINCTRL_PIN(63, "pcie_reset2"),
458
428
};
459
429
460
-
static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
461
-
static const int pon_tod_1pps_pins[] = { 46 };
462
-
static const int gsw_tod_1pps_pins[] = { 46 };
463
-
static const int sipo_pins[] = { 16, 17 };
464
-
static const int sipo_rclk_pins[] = { 16, 17, 43 };
465
-
static const int mdio_pins[] = { 14, 15 };
466
-
static const int uart2_pins[] = { 48, 55 };
467
-
static const int uart2_cts_rts_pins[] = { 46, 47 };
468
-
static const int hsuart_pins[] = { 28, 29 };
469
-
static const int hsuart_cts_rts_pins[] = { 26, 27 };
470
-
static const int uart4_pins[] = { 38, 39 };
471
-
static const int uart5_pins[] = { 18, 19 };
472
-
static const int i2c0_pins[] = { 2, 3 };
473
-
static const int i2c1_pins[] = { 14, 15 };
474
-
static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
475
-
static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
476
-
static const int i2s_pins[] = { 26, 27, 28, 29 };
477
-
static const int pcm1_pins[] = { 22, 23, 24, 25 };
478
-
static const int pcm2_pins[] = { 18, 19, 20, 21 };
479
-
static const int spi_quad_pins[] = { 32, 33 };
480
-
static const int spi_pins[] = { 4, 5, 6, 7 };
481
-
static const int spi_cs1_pins[] = { 34 };
482
-
static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
483
-
static const int pcm_spi_int_pins[] = { 14 };
484
-
static const int pcm_spi_rst_pins[] = { 15 };
485
-
static const int pcm_spi_cs1_pins[] = { 43 };
486
-
static const int pcm_spi_cs2_pins[] = { 40 };
487
-
static const int pcm_spi_cs2_p128_pins[] = { 40 };
488
-
static const int pcm_spi_cs2_p156_pins[] = { 40 };
489
-
static const int pcm_spi_cs3_pins[] = { 41 };
490
-
static const int pcm_spi_cs4_pins[] = { 42 };
491
-
static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
492
-
static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
493
-
static const int gpio0_pins[] = { 13 };
494
-
static const int gpio1_pins[] = { 14 };
495
-
static const int gpio2_pins[] = { 15 };
496
-
static const int gpio3_pins[] = { 16 };
497
-
static const int gpio4_pins[] = { 17 };
498
-
static const int gpio5_pins[] = { 18 };
499
-
static const int gpio6_pins[] = { 19 };
500
-
static const int gpio7_pins[] = { 20 };
501
-
static const int gpio8_pins[] = { 21 };
502
-
static const int gpio9_pins[] = { 22 };
503
-
static const int gpio10_pins[] = { 23 };
504
-
static const int gpio11_pins[] = { 24 };
505
-
static const int gpio12_pins[] = { 25 };
506
-
static const int gpio13_pins[] = { 26 };
507
-
static const int gpio14_pins[] = { 27 };
508
-
static const int gpio15_pins[] = { 28 };
509
-
static const int gpio16_pins[] = { 29 };
510
-
static const int gpio17_pins[] = { 30 };
511
-
static const int gpio18_pins[] = { 31 };
512
-
static const int gpio19_pins[] = { 32 };
513
-
static const int gpio20_pins[] = { 33 };
514
-
static const int gpio21_pins[] = { 34 };
515
-
static const int gpio22_pins[] = { 35 };
516
-
static const int gpio23_pins[] = { 36 };
517
-
static const int gpio24_pins[] = { 37 };
518
-
static const int gpio25_pins[] = { 38 };
519
-
static const int gpio26_pins[] = { 39 };
520
-
static const int gpio27_pins[] = { 40 };
521
-
static const int gpio28_pins[] = { 41 };
522
-
static const int gpio29_pins[] = { 42 };
523
-
static const int gpio30_pins[] = { 43 };
524
-
static const int gpio31_pins[] = { 44 };
525
-
static const int gpio33_pins[] = { 46 };
526
-
static const int gpio34_pins[] = { 47 };
527
-
static const int gpio35_pins[] = { 48 };
528
-
static const int gpio36_pins[] = { 49 };
529
-
static const int gpio37_pins[] = { 50 };
530
-
static const int gpio38_pins[] = { 51 };
531
-
static const int gpio39_pins[] = { 52 };
532
-
static const int gpio40_pins[] = { 53 };
533
-
static const int gpio41_pins[] = { 54 };
534
-
static const int gpio42_pins[] = { 55 };
535
-
static const int gpio43_pins[] = { 56 };
536
-
static const int gpio44_pins[] = { 57 };
537
-
static const int gpio45_pins[] = { 58 };
538
-
static const int gpio46_pins[] = { 59 };
539
-
static const int pcie_reset0_pins[] = { 61 };
540
-
static const int pcie_reset1_pins[] = { 62 };
541
-
static const int pcie_reset2_pins[] = { 63 };
430
+
static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
431
+
static const int en7581_pon_tod_1pps_pins[] = { 46 };
432
+
static const int en7581_gsw_tod_1pps_pins[] = { 46 };
433
+
static const int en7581_sipo_pins[] = { 16, 17 };
434
+
static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
435
+
static const int en7581_mdio_pins[] = { 14, 15 };
436
+
static const int en7581_uart2_pins[] = { 48, 55 };
437
+
static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
438
+
static const int en7581_hsuart_pins[] = { 28, 29 };
439
+
static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
440
+
static const int en7581_uart4_pins[] = { 38, 39 };
441
+
static const int en7581_uart5_pins[] = { 18, 19 };
442
+
static const int en7581_i2c0_pins[] = { 2, 3 };
443
+
static const int en7581_i2c1_pins[] = { 14, 15 };
444
+
static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
445
+
static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
446
+
static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
447
+
static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
448
+
static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
449
+
static const int en7581_spi_quad_pins[] = { 32, 33 };
450
+
static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
451
+
static const int en7581_spi_cs1_pins[] = { 34 };
452
+
static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
453
+
static const int en7581_pcm_spi_int_pins[] = { 14 };
454
+
static const int en7581_pcm_spi_rst_pins[] = { 15 };
455
+
static const int en7581_pcm_spi_cs1_pins[] = { 43 };
456
+
static const int en7581_pcm_spi_cs2_pins[] = { 40 };
457
+
static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
458
+
static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
459
+
static const int en7581_pcm_spi_cs3_pins[] = { 41 };
460
+
static const int en7581_pcm_spi_cs4_pins[] = { 42 };
461
+
static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
462
+
static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
463
+
static const int en7581_gpio0_pins[] = { 13 };
464
+
static const int en7581_gpio1_pins[] = { 14 };
465
+
static const int en7581_gpio2_pins[] = { 15 };
466
+
static const int en7581_gpio3_pins[] = { 16 };
467
+
static const int en7581_gpio4_pins[] = { 17 };
468
+
static const int en7581_gpio5_pins[] = { 18 };
469
+
static const int en7581_gpio6_pins[] = { 19 };
470
+
static const int en7581_gpio7_pins[] = { 20 };
471
+
static const int en7581_gpio8_pins[] = { 21 };
472
+
static const int en7581_gpio9_pins[] = { 22 };
473
+
static const int en7581_gpio10_pins[] = { 23 };
474
+
static const int en7581_gpio11_pins[] = { 24 };
475
+
static const int en7581_gpio12_pins[] = { 25 };
476
+
static const int en7581_gpio13_pins[] = { 26 };
477
+
static const int en7581_gpio14_pins[] = { 27 };
478
+
static const int en7581_gpio15_pins[] = { 28 };
479
+
static const int en7581_gpio16_pins[] = { 29 };
480
+
static const int en7581_gpio17_pins[] = { 30 };
481
+
static const int en7581_gpio18_pins[] = { 31 };
482
+
static const int en7581_gpio19_pins[] = { 32 };
483
+
static const int en7581_gpio20_pins[] = { 33 };
484
+
static const int en7581_gpio21_pins[] = { 34 };
485
+
static const int en7581_gpio22_pins[] = { 35 };
486
+
static const int en7581_gpio23_pins[] = { 36 };
487
+
static const int en7581_gpio24_pins[] = { 37 };
488
+
static const int en7581_gpio25_pins[] = { 38 };
489
+
static const int en7581_gpio26_pins[] = { 39 };
490
+
static const int en7581_gpio27_pins[] = { 40 };
491
+
static const int en7581_gpio28_pins[] = { 41 };
492
+
static const int en7581_gpio29_pins[] = { 42 };
493
+
static const int en7581_gpio30_pins[] = { 43 };
494
+
static const int en7581_gpio31_pins[] = { 44 };
495
+
static const int en7581_gpio33_pins[] = { 46 };
496
+
static const int en7581_gpio34_pins[] = { 47 };
497
+
static const int en7581_gpio35_pins[] = { 48 };
498
+
static const int en7581_gpio36_pins[] = { 49 };
499
+
static const int en7581_gpio37_pins[] = { 50 };
500
+
static const int en7581_gpio38_pins[] = { 51 };
501
+
static const int en7581_gpio39_pins[] = { 52 };
502
+
static const int en7581_gpio40_pins[] = { 53 };
503
+
static const int en7581_gpio41_pins[] = { 54 };
504
+
static const int en7581_gpio42_pins[] = { 55 };
505
+
static const int en7581_gpio43_pins[] = { 56 };
506
+
static const int en7581_gpio44_pins[] = { 57 };
507
+
static const int en7581_gpio45_pins[] = { 58 };
508
+
static const int en7581_gpio46_pins[] = { 59 };
509
+
static const int en7581_pcie_reset0_pins[] = { 61 };
510
+
static const int en7581_pcie_reset1_pins[] = { 62 };
511
+
static const int en7581_pcie_reset2_pins[] = { 63 };
542
512
543
-
static const struct pingroup airoha_pinctrl_groups[] = {
544
-
PINCTRL_PIN_GROUP(pon),
545
-
PINCTRL_PIN_GROUP(pon_tod_1pps),
546
-
PINCTRL_PIN_GROUP(gsw_tod_1pps),
547
-
PINCTRL_PIN_GROUP(sipo),
548
-
PINCTRL_PIN_GROUP(sipo_rclk),
549
-
PINCTRL_PIN_GROUP(mdio),
550
-
PINCTRL_PIN_GROUP(uart2),
551
-
PINCTRL_PIN_GROUP(uart2_cts_rts),
552
-
PINCTRL_PIN_GROUP(hsuart),
553
-
PINCTRL_PIN_GROUP(hsuart_cts_rts),
554
-
PINCTRL_PIN_GROUP(uart4),
555
-
PINCTRL_PIN_GROUP(uart5),
556
-
PINCTRL_PIN_GROUP(i2c0),
557
-
PINCTRL_PIN_GROUP(i2c1),
558
-
PINCTRL_PIN_GROUP(jtag_udi),
559
-
PINCTRL_PIN_GROUP(jtag_dfd),
560
-
PINCTRL_PIN_GROUP(i2s),
561
-
PINCTRL_PIN_GROUP(pcm1),
562
-
PINCTRL_PIN_GROUP(pcm2),
563
-
PINCTRL_PIN_GROUP(spi),
564
-
PINCTRL_PIN_GROUP(spi_quad),
565
-
PINCTRL_PIN_GROUP(spi_cs1),
566
-
PINCTRL_PIN_GROUP(pcm_spi),
567
-
PINCTRL_PIN_GROUP(pcm_spi_int),
568
-
PINCTRL_PIN_GROUP(pcm_spi_rst),
569
-
PINCTRL_PIN_GROUP(pcm_spi_cs1),
570
-
PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
571
-
PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
572
-
PINCTRL_PIN_GROUP(pcm_spi_cs2),
573
-
PINCTRL_PIN_GROUP(pcm_spi_cs3),
574
-
PINCTRL_PIN_GROUP(pcm_spi_cs4),
575
-
PINCTRL_PIN_GROUP(emmc),
576
-
PINCTRL_PIN_GROUP(pnand),
577
-
PINCTRL_PIN_GROUP(gpio0),
578
-
PINCTRL_PIN_GROUP(gpio1),
579
-
PINCTRL_PIN_GROUP(gpio2),
580
-
PINCTRL_PIN_GROUP(gpio3),
581
-
PINCTRL_PIN_GROUP(gpio4),
582
-
PINCTRL_PIN_GROUP(gpio5),
583
-
PINCTRL_PIN_GROUP(gpio6),
584
-
PINCTRL_PIN_GROUP(gpio7),
585
-
PINCTRL_PIN_GROUP(gpio8),
586
-
PINCTRL_PIN_GROUP(gpio9),
587
-
PINCTRL_PIN_GROUP(gpio10),
588
-
PINCTRL_PIN_GROUP(gpio11),
589
-
PINCTRL_PIN_GROUP(gpio12),
590
-
PINCTRL_PIN_GROUP(gpio13),
591
-
PINCTRL_PIN_GROUP(gpio14),
592
-
PINCTRL_PIN_GROUP(gpio15),
593
-
PINCTRL_PIN_GROUP(gpio16),
594
-
PINCTRL_PIN_GROUP(gpio17),
595
-
PINCTRL_PIN_GROUP(gpio18),
596
-
PINCTRL_PIN_GROUP(gpio19),
597
-
PINCTRL_PIN_GROUP(gpio20),
598
-
PINCTRL_PIN_GROUP(gpio21),
599
-
PINCTRL_PIN_GROUP(gpio22),
600
-
PINCTRL_PIN_GROUP(gpio23),
601
-
PINCTRL_PIN_GROUP(gpio24),
602
-
PINCTRL_PIN_GROUP(gpio25),
603
-
PINCTRL_PIN_GROUP(gpio26),
604
-
PINCTRL_PIN_GROUP(gpio27),
605
-
PINCTRL_PIN_GROUP(gpio28),
606
-
PINCTRL_PIN_GROUP(gpio29),
607
-
PINCTRL_PIN_GROUP(gpio30),
608
-
PINCTRL_PIN_GROUP(gpio31),
609
-
PINCTRL_PIN_GROUP(gpio33),
610
-
PINCTRL_PIN_GROUP(gpio34),
611
-
PINCTRL_PIN_GROUP(gpio35),
612
-
PINCTRL_PIN_GROUP(gpio36),
613
-
PINCTRL_PIN_GROUP(gpio37),
614
-
PINCTRL_PIN_GROUP(gpio38),
615
-
PINCTRL_PIN_GROUP(gpio39),
616
-
PINCTRL_PIN_GROUP(gpio40),
617
-
PINCTRL_PIN_GROUP(gpio41),
618
-
PINCTRL_PIN_GROUP(gpio42),
619
-
PINCTRL_PIN_GROUP(gpio43),
620
-
PINCTRL_PIN_GROUP(gpio44),
621
-
PINCTRL_PIN_GROUP(gpio45),
622
-
PINCTRL_PIN_GROUP(gpio46),
623
-
PINCTRL_PIN_GROUP(pcie_reset0),
624
-
PINCTRL_PIN_GROUP(pcie_reset1),
625
-
PINCTRL_PIN_GROUP(pcie_reset2),
513
+
static const struct pingroup en7581_pinctrl_groups[] = {
514
+
PINCTRL_PIN_GROUP("pon", en7581_pon),
515
+
PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
516
+
PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
517
+
PINCTRL_PIN_GROUP("sipo", en7581_sipo),
518
+
PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
519
+
PINCTRL_PIN_GROUP("mdio", en7581_mdio),
520
+
PINCTRL_PIN_GROUP("uart2", en7581_uart2),
521
+
PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
522
+
PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
523
+
PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
524
+
PINCTRL_PIN_GROUP("uart4", en7581_uart4),
525
+
PINCTRL_PIN_GROUP("uart5", en7581_uart5),
526
+
PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
527
+
PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
528
+
PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
529
+
PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
530
+
PINCTRL_PIN_GROUP("i2s", en7581_i2s),
531
+
PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
532
+
PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
533
+
PINCTRL_PIN_GROUP("spi", en7581_spi),
534
+
PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
535
+
PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
536
+
PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
537
+
PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
538
+
PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
539
+
PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
540
+
PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
541
+
PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
542
+
PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
543
+
PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
544
+
PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
545
+
PINCTRL_PIN_GROUP("emmc", en7581_emmc),
546
+
PINCTRL_PIN_GROUP("pnand", en7581_pnand),
547
+
PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
548
+
PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
549
+
PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
550
+
PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
551
+
PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
552
+
PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
553
+
PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
554
+
PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
555
+
PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
556
+
PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
557
+
PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
558
+
PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
559
+
PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
560
+
PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
561
+
PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
562
+
PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
563
+
PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
564
+
PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
565
+
PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
566
+
PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
567
+
PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
568
+
PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
569
+
PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
570
+
PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
571
+
PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
572
+
PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
573
+
PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
574
+
PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
575
+
PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
576
+
PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
577
+
PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
578
+
PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
579
+
PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
580
+
PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
581
+
PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
582
+
PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
583
+
PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
584
+
PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
585
+
PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
586
+
PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
587
+
PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
588
+
PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
589
+
PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
590
+
PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
591
+
PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
592
+
PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
593
+
PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
594
+
PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
595
+
PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
626
596
};
627
597
628
598
static const char *const pon_groups[] = { "pon" };
···
1985
1955
},
1986
1956
};
1987
1957
1988
-
static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
1989
-
PINCTRL_FUNC_DESC(pon),
1990
-
PINCTRL_FUNC_DESC(tod_1pps),
1991
-
PINCTRL_FUNC_DESC(sipo),
1992
-
PINCTRL_FUNC_DESC(mdio),
1993
-
PINCTRL_FUNC_DESC(uart),
1994
-
PINCTRL_FUNC_DESC(i2c),
1995
-
PINCTRL_FUNC_DESC(jtag),
1996
-
PINCTRL_FUNC_DESC(pcm),
1997
-
PINCTRL_FUNC_DESC(spi),
1998
-
PINCTRL_FUNC_DESC(pcm_spi),
1999
-
PINCTRL_FUNC_DESC(i2s),
2000
-
PINCTRL_FUNC_DESC(emmc),
2001
-
PINCTRL_FUNC_DESC(pnand),
2002
-
PINCTRL_FUNC_DESC(pcie_reset),
2003
-
PINCTRL_FUNC_DESC(pwm),
2004
-
PINCTRL_FUNC_DESC(phy1_led0),
2005
-
PINCTRL_FUNC_DESC(phy2_led0),
2006
-
PINCTRL_FUNC_DESC(phy3_led0),
2007
-
PINCTRL_FUNC_DESC(phy4_led0),
2008
-
PINCTRL_FUNC_DESC(phy1_led1),
2009
-
PINCTRL_FUNC_DESC(phy2_led1),
2010
-
PINCTRL_FUNC_DESC(phy3_led1),
2011
-
PINCTRL_FUNC_DESC(phy4_led1),
1958
+
static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
1959
+
PINCTRL_FUNC_DESC("pon", pon),
1960
+
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
1961
+
PINCTRL_FUNC_DESC("sipo", sipo),
1962
+
PINCTRL_FUNC_DESC("mdio", mdio),
1963
+
PINCTRL_FUNC_DESC("uart", uart),
1964
+
PINCTRL_FUNC_DESC("i2c", i2c),
1965
+
PINCTRL_FUNC_DESC("jtag", jtag),
1966
+
PINCTRL_FUNC_DESC("pcm", pcm),
1967
+
PINCTRL_FUNC_DESC("spi", spi),
1968
+
PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
1969
+
PINCTRL_FUNC_DESC("i2s", i2s),
1970
+
PINCTRL_FUNC_DESC("emmc", emmc),
1971
+
PINCTRL_FUNC_DESC("pnand", pnand),
1972
+
PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
1973
+
PINCTRL_FUNC_DESC("pwm", pwm),
1974
+
PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
1975
+
PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
1976
+
PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
1977
+
PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
1978
+
PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
1979
+
PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
1980
+
PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
1981
+
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
2012
1982
};
2013
1983
2014
-
static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
1984
+
static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
2015
1985
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
2016
1986
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
2017
1987
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
···
2072
2042
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
2073
2043
};
2074
2044
2075
-
static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
2045
+
static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
2076
2046
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
2077
2047
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
2078
2048
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
···
2133
2103
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
2134
2104
};
2135
2105
2136
-
static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
2106
+
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
2137
2107
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
2138
2108
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
2139
2109
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
···
2194
2164
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
2195
2165
};
2196
2166
2197
-
static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
2167
+
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
2198
2168
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
2199
2169
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
2200
2170
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
···
2255
2225
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
2256
2226
};
2257
2227
2258
-
static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
2228
+
static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
2259
2229
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
2260
2230
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
2261
2231
PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
···
2576
2546
}
2577
2547
2578
2548
static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
2579
-
const struct airoha_pinctrl_conf *conf,
2580
-
int conf_size, int pin, u32 *val)
2549
+
enum airoha_pinctrl_confs_type conf_type,
2550
+
int pin, u32 *val)
2581
2551
{
2552
+
const struct airoha_pinctrl_confs_info *confs_info;
2582
2553
const struct airoha_pinctrl_reg *reg;
2583
2554
2584
-
reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
2555
+
confs_info = &pinctrl->confs_info[conf_type];
2556
+
2557
+
reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
2558
+
confs_info->num_confs,
2559
+
pin);
2585
2560
if (!reg)
2586
2561
return -EINVAL;
2587
2562
···
2599
2564
}
2600
2565
2601
2566
static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
2602
-
const struct airoha_pinctrl_conf *conf,
2603
-
int conf_size, int pin, u32 val)
2567
+
enum airoha_pinctrl_confs_type conf_type,
2568
+
int pin, u32 val)
2604
2569
{
2570
+
const struct airoha_pinctrl_confs_info *confs_info;
2605
2571
const struct airoha_pinctrl_reg *reg = NULL;
2606
2572
2607
-
reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
2573
+
confs_info = &pinctrl->confs_info[conf_type];
2574
+
2575
+
reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
2576
+
confs_info->num_confs,
2577
+
pin);
2608
2578
if (!reg)
2609
2579
return -EINVAL;
2610
2580
···
2622
2582
}
2623
2583
2624
2584
#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
2625
-
airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \
2626
-
ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
2585
+
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
2627
2586
(pin), (val))
2628
2587
#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
2629
-
airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
2630
-
ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
2588
+
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
2631
2589
(pin), (val))
2632
2590
#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
2633
-
airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
2634
-
ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
2591
+
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
2635
2592
(pin), (val))
2636
2593
#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
2637
-
airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
2638
-
ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
2594
+
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
2639
2595
(pin), (val))
2640
2596
#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
2641
-
airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
2642
-
ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
2597
+
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
2643
2598
(pin), (val))
2644
2599
#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
2645
-
airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \
2646
-
ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
2600
+
airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
2647
2601
(pin), (val))
2648
2602
#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
2649
-
airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
2650
-
ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
2603
+
airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
2651
2604
(pin), (val))
2652
2605
#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
2653
-
airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
2654
-
ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
2606
+
airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
2655
2607
(pin), (val))
2656
2608
#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
2657
-
airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
2658
-
ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
2609
+
airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
2659
2610
(pin), (val))
2660
2611
#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
2661
-
airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
2662
-
ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
2612
+
airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
2663
2613
(pin), (val))
2664
2614
2665
2615
static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
···
2826
2796
static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
2827
2797
unsigned int group, unsigned long *config)
2828
2798
{
2799
+
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2829
2800
u32 cur_config = 0;
2830
2801
int i;
2831
2802
2832
-
for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
2803
+
for (i = 0; i < pinctrl->grps[group].npins; i++) {
2833
2804
if (airoha_pinconf_get(pctrl_dev,
2834
-
airoha_pinctrl_groups[group].pins[i],
2805
+
pinctrl->grps[group].pins[i],
2835
2806
config))
2836
2807
return -ENOTSUPP;
2837
2808
···
2849
2818
unsigned int group, unsigned long *configs,
2850
2819
unsigned int num_configs)
2851
2820
{
2821
+
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2852
2822
int i;
2853
2823
2854
-
for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
2824
+
for (i = 0; i < pinctrl->grps[group].npins; i++) {
2855
2825
int err;
2856
2826
2857
2827
err = airoha_pinconf_set(pctrl_dev,
2858
-
airoha_pinctrl_groups[group].pins[i],
2828
+
pinctrl->grps[group].pins[i],
2859
2829
configs, num_configs);
2860
2830
if (err)
2861
2831
return err;
···
2882
2850
.dt_free_map = pinconf_generic_dt_free_map,
2883
2851
};
2884
2852
2885
-
static const struct pinctrl_desc airoha_pinctrl_desc = {
2886
-
.name = KBUILD_MODNAME,
2887
-
.owner = THIS_MODULE,
2888
-
.pctlops = &airoha_pctlops,
2889
-
.pmxops = &airoha_pmxops,
2890
-
.confops = &airoha_confops,
2891
-
.pins = airoha_pinctrl_pins,
2892
-
.npins = ARRAY_SIZE(airoha_pinctrl_pins),
2893
-
};
2894
-
2895
2853
static int airoha_pinctrl_probe(struct platform_device *pdev)
2896
2854
{
2855
+
const struct airoha_pinctrl_match_data *data;
2897
2856
struct device *dev = &pdev->dev;
2898
2857
struct airoha_pinctrl *pinctrl;
2899
2858
struct regmap *map;
2900
2859
int err, i;
2860
+
2861
+
data = device_get_match_data(dev);
2901
2862
2902
2863
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
2903
2864
if (!pinctrl)
···
2906
2881
2907
2882
pinctrl->chip_scu = map;
2908
2883
2909
-
err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
2884
+
/* Init pinctrl desc struct */
2885
+
pinctrl->desc.name = KBUILD_MODNAME;
2886
+
pinctrl->desc.owner = THIS_MODULE,
2887
+
pinctrl->desc.pctlops = &airoha_pctlops,
2888
+
pinctrl->desc.pmxops = &airoha_pmxops,
2889
+
pinctrl->desc.confops = &airoha_confops,
2890
+
pinctrl->desc.pins = data->pins,
2891
+
pinctrl->desc.npins = data->num_pins,
2892
+
2893
+
err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
2910
2894
pinctrl, &pinctrl->ctrl);
2911
2895
if (err)
2912
2896
return err;
2913
2897
2914
2898
/* build pin groups */
2915
-
for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
2916
-
const struct pingroup *grp = &airoha_pinctrl_groups[i];
2899
+
for (i = 0; i < data->num_grps; i++) {
2900
+
const struct pingroup *grp = &data->grps[i];
2917
2901
2918
2902
err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
2919
2903
grp->pins, grp->npins,
···
2935
2901
}
2936
2902
2937
2903
/* build functions */
2938
-
for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
2904
+
for (i = 0; i < data->num_funcs; i++) {
2939
2905
const struct airoha_pinctrl_func *func;
2940
2906
2941
-
func = &airoha_pinctrl_funcs[i];
2907
+
func = &data->funcs[i];
2942
2908
err = pinmux_generic_add_pinfunction(pinctrl->ctrl,
2943
2909
&func->desc,
2944
2910
(void *)func);
···
2949
2915
}
2950
2916
}
2951
2917
2918
+
pinctrl->grps = data->grps;
2919
+
pinctrl->funcs = data->funcs;
2920
+
pinctrl->confs_info = data->confs_info;
2921
+
2952
2922
err = pinctrl_enable(pinctrl->ctrl);
2953
2923
if (err)
2954
2924
return err;
···
2961
2923
return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
2962
2924
}
2963
2925
2926
+
static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
2927
+
.pins = en7581_pinctrl_pins,
2928
+
.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
2929
+
.grps = en7581_pinctrl_groups,
2930
+
.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
2931
+
.funcs = en7581_pinctrl_funcs,
2932
+
.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
2933
+
.confs_info = {
2934
+
[AIROHA_PINCTRL_CONFS_PULLUP] = {
2935
+
.confs = en7581_pinctrl_pullup_conf,
2936
+
.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
2937
+
},
2938
+
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
2939
+
.confs = en7581_pinctrl_pulldown_conf,
2940
+
.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
2941
+
},
2942
+
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
2943
+
.confs = en7581_pinctrl_drive_e2_conf,
2944
+
.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
2945
+
},
2946
+
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
2947
+
.confs = en7581_pinctrl_drive_e4_conf,
2948
+
.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
2949
+
},
2950
+
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
2951
+
.confs = en7581_pinctrl_pcie_rst_od_conf,
2952
+
.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
2953
+
},
2954
+
},
2955
+
};
2956
+
2964
2957
static const struct of_device_id airoha_pinctrl_of_match[] = {
2965
-
{ .compatible = "airoha,en7581-pinctrl" },
2958
+
{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
2966
2959
{ /* sentinel */ }
2967
2960
};
2968
2961
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);