Merge tag 'spi-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

+2 -2

Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml

··· 35 35 interrupts: 36 36 maxItems: 1 37 37 38 - clock-names: 38 + clocks: 39 39 maxItems: 1 40 40 41 - clocks: 41 + resets: 42 42 maxItems: 1 43 43 44 44 microchip,apb-datawidth:

+48 -4

Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml

··· 13 13 compatible: 14 14 oneOf: 15 15 - enum: 16 + - renesas,r9a08g046-rspi # RZ/G3L 16 17 - renesas,r9a09g057-rspi # RZ/V2H(P) 17 18 - renesas,r9a09g077-rspi # RZ/T2H 18 19 - items: 19 - - const: renesas,r9a09g056-rspi # RZ/V2N 20 + - enum: 21 + - renesas,r9a09g047-rspi # RZ/G3E 22 + - renesas,r9a09g056-rspi # RZ/V2N 20 23 - const: renesas,r9a09g057-rspi 21 24 - items: 22 25 - const: renesas,r9a09g087-rspi # RZ/N2H ··· 61 58 - const: tresetn 62 59 63 60 dmas: 64 - maxItems: 2 61 + minItems: 2 62 + maxItems: 10 63 + description: 64 + Must contain a list of pairs of references to DMA specifiers, one for 65 + transmission, and one for reception. 65 66 66 67 dma-names: 68 + minItems: 2 69 + maxItems: 10 67 70 items: 68 - - const: rx 69 - - const: tx 71 + enum: 72 + - rx 73 + - tx 70 74 71 75 power-domains: 72 76 maxItems: 1 ··· 91 81 92 82 allOf: 93 83 - $ref: spi-controller.yaml# 84 + - if: 85 + properties: 86 + compatible: 87 + contains: 88 + enum: 89 + - renesas,r9a08g046-rspi 90 + then: 91 + properties: 92 + clocks: 93 + maxItems: 2 94 + 95 + clock-names: 96 + items: 97 + - const: pclk 98 + - const: tclk 99 + 100 + dmas: 101 + maxItems: 2 102 + 103 + dma-names: 104 + items: 105 + - const: rx 106 + - const: tx 107 + 108 + required: 109 + - resets 110 + - reset-names 111 + 94 112 - if: 95 113 properties: 96 114 compatible: ··· 158 120 159 121 resets: false 160 122 reset-names: false 123 + 124 + dmas: 125 + maxItems: 6 126 + 127 + dma-names: 128 + maxItems: 6 161 129 162 130 unevaluatedProperties: false 163 131

+2 -2

drivers/spi/Kconfig

··· 138 138 139 139 config SPI_ATCSPI200 140 140 tristate "Andes ATCSPI200 SPI controller" 141 - depends on ARCH_ANDES 141 + depends on ARCH_ANDES || COMPILE_TEST 142 142 help 143 143 SPI driver for Andes ATCSPI200 SPI controller. 144 144 ATCSPI200 controller supports DMA and PIO modes. When DMA ··· 866 866 867 867 config SPI_PL022 868 868 tristate "ARM AMBA PL022 SSP controller" 869 - depends on ARM_AMBA 869 + depends on ARM_AMBA || COMPILE_TEST 870 870 default y if ARCH_REALVIEW 871 871 default y if INTEGRATOR_IMPD1 872 872 default y if ARCH_VERSATILE

+6 -4

drivers/spi/spi-amlogic-spisg.c

··· 647 647 int ret, i; 648 648 649 649 spisg->core = devm_clk_get_enabled(dev, "core"); 650 - if (IS_ERR_OR_NULL(spisg->core)) { 650 + if (IS_ERR(spisg->core)) { 651 651 dev_err(dev, "core clock request failed\n"); 652 652 return PTR_ERR(spisg->core); 653 653 } 654 654 655 655 spisg->pclk = devm_clk_get_enabled(dev, "pclk"); 656 - if (IS_ERR_OR_NULL(spisg->pclk)) { 656 + if (IS_ERR(spisg->pclk)) { 657 657 dev_err(dev, "pclk clock request failed\n"); 658 658 return PTR_ERR(spisg->pclk); 659 659 } ··· 703 703 } 704 704 705 705 spisg->sclk = devm_clk_hw_get_clk(dev, &div->hw, NULL); 706 - if (IS_ERR_OR_NULL(spisg->sclk)) { 706 + if (IS_ERR(spisg->sclk)) { 707 707 dev_err(dev, "get clock failed\n"); 708 708 return PTR_ERR(spisg->sclk); 709 709 } ··· 800 800 goto out_clk; 801 801 } 802 802 803 - ret = devm_spi_register_controller(dev, ctlr); 803 + ret = spi_register_controller(ctlr); 804 804 if (ret) { 805 805 dev_err(&pdev->dev, "spi controller registration failed\n"); 806 806 goto out_clk; ··· 822 822 static void aml_spisg_remove(struct platform_device *pdev) 823 823 { 824 824 struct spisg_device *spisg = platform_get_drvdata(pdev); 825 + 826 + spi_unregister_controller(spisg->controller); 825 827 826 828 if (!pm_runtime_suspended(&pdev->dev)) { 827 829 pinctrl_pm_select_sleep_state(&spisg->pdev->dev);

+6 -3

drivers/spi/spi-aspeed-smc.c

··· 972 972 return -ENOMEM; 973 973 974 974 aspi = spi_controller_get_devdata(ctlr); 975 - platform_set_drvdata(pdev, aspi); 975 + platform_set_drvdata(pdev, ctlr); 976 976 aspi->data = data; 977 977 aspi->dev = dev; 978 978 ··· 1021 1021 return ret; 1022 1022 } 1023 1023 1024 - ret = devm_spi_register_controller(dev, ctlr); 1024 + ret = spi_register_controller(ctlr); 1025 1025 if (ret) 1026 1026 dev_err(&pdev->dev, "spi_register_controller failed\n"); 1027 1027 ··· 1030 1030 1031 1031 static void aspeed_spi_remove(struct platform_device *pdev) 1032 1032 { 1033 - struct aspeed_spi *aspi = platform_get_drvdata(pdev); 1033 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 1034 + struct aspeed_spi *aspi = spi_controller_get_devdata(ctlr); 1035 + 1036 + spi_unregister_controller(ctlr); 1034 1037 1035 1038 aspeed_spi_enable(aspi, false); 1036 1039 }

+7 -1

drivers/spi/spi-at91-usart.c

··· 556 556 spin_lock_init(&aus->lock); 557 557 init_completion(&aus->xfer_completion); 558 558 559 - ret = devm_spi_register_controller(&pdev->dev, controller); 559 + ret = spi_register_controller(controller); 560 560 if (ret) 561 561 goto at91_usart_fail_register_controller; 562 562 ··· 634 634 struct spi_controller *ctlr = platform_get_drvdata(pdev); 635 635 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr); 636 636 637 + spi_controller_get(ctlr); 638 + 639 + spi_unregister_controller(ctlr); 640 + 637 641 at91_usart_spi_release_dma(ctlr); 638 642 clk_disable_unprepare(aus->clk); 643 + 644 + spi_controller_put(ctlr); 639 645 } 640 646 641 647 static const struct dev_pm_ops at91_usart_spi_pm_ops = {

+9 -20

drivers/spi/spi-atcspi200.c

··· 494 494 return dev_err_probe(spi->dev, PTR_ERR(spi->regmap), 495 495 "Failed to init regmap\n"); 496 496 497 - spi->clk = devm_clk_get(spi->dev, NULL); 498 - if (IS_ERR(spi->clk)) 499 - return dev_err_probe(spi->dev, PTR_ERR(spi->clk), 500 - "Failed to get SPI clock\n"); 501 - 502 497 spi->sclk_rate = ATCSPI_MAX_SPEED_HZ; 503 498 return 0; 504 499 } ··· 515 520 516 521 static int atcspi_enable_clk(struct atcspi_dev *spi) 517 522 { 518 - int ret; 519 - 520 - ret = clk_prepare_enable(spi->clk); 521 - if (ret) 522 - return dev_err_probe(spi->dev, ret, 523 - "Failed to enable clock\n"); 524 - 523 + spi->clk = devm_clk_get_enabled(spi->dev, NULL); 524 + if (IS_ERR(spi->clk)) 525 + return dev_err_probe(spi->dev, PTR_ERR(spi->clk), 526 + "Failed to get SPI clock\n"); 525 527 spi->clk_rate = clk_get_rate(spi->clk); 526 528 if (!spi->clk_rate) 527 529 return dev_err_probe(spi->dev, -EINVAL, ··· 559 567 spi->dev = &pdev->dev; 560 568 dev_set_drvdata(&pdev->dev, host); 561 569 570 + mutex_init(&spi->mutex_lock); 571 + 562 572 ret = atcspi_init_resources(pdev, spi, &mem_res); 563 573 if (ret) 564 574 goto free_controller; ··· 573 579 574 580 ret = atcspi_setup(spi); 575 581 if (ret) 576 - goto disable_clk; 582 + goto free_controller; 577 583 578 584 ret = devm_spi_register_controller(&pdev->dev, host); 579 585 if (ret) { 580 586 dev_err_probe(spi->dev, ret, 581 587 "Failed to register SPI controller\n"); 582 - goto disable_clk; 588 + goto free_controller; 583 589 } 584 - 585 590 spi->use_dma = false; 586 591 if (ATCSPI_DMA_SUPPORT) { 587 592 ret = atcspi_configure_dma(spi); ··· 590 597 else 591 598 spi->use_dma = true; 592 599 } 593 - mutex_init(&spi->mutex_lock); 594 600 595 601 return 0; 596 602 597 - disable_clk: 598 - clk_disable_unprepare(spi->clk); 599 - 600 603 free_controller: 604 + mutex_destroy(&spi->mutex_lock); 601 605 spi_controller_put(host); 602 606 return ret; 603 607 } ··· 651 661 .probe = atcspi_probe, 652 662 .driver = { 653 663 .name = "atcspi200", 654 - .owner = THIS_MODULE, 655 664 .of_match_table = atcspi_of_match, 656 665 .pm = pm_sleep_ptr(&atcspi_pm_ops) 657 666 }

+7 -1

drivers/spi/spi-atmel.c

··· 1654 1654 pm_runtime_set_active(&pdev->dev); 1655 1655 pm_runtime_enable(&pdev->dev); 1656 1656 1657 - ret = devm_spi_register_controller(&pdev->dev, host); 1657 + ret = spi_register_controller(host); 1658 1658 if (ret) 1659 1659 goto out_free_dma; 1660 1660 ··· 1688 1688 struct spi_controller *host = platform_get_drvdata(pdev); 1689 1689 struct atmel_spi *as = spi_controller_get_devdata(host); 1690 1690 1691 + spi_controller_get(host); 1692 + 1691 1693 pm_runtime_get_sync(&pdev->dev); 1694 + 1695 + spi_unregister_controller(host); 1692 1696 1693 1697 /* reset the hardware and block queue progress */ 1694 1698 if (as->use_dma) { ··· 1720 1716 1721 1717 pm_runtime_put_noidle(&pdev->dev); 1722 1718 pm_runtime_disable(&pdev->dev); 1719 + 1720 + spi_controller_put(host); 1723 1721 } 1724 1722 1725 1723 static int atmel_spi_runtime_suspend(struct device *dev)

-1

drivers/spi/spi-axiado.c

··· 842 842 843 843 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 844 844 845 - pm_runtime_mark_last_busy(&pdev->dev); 846 845 pm_runtime_put_autosuspend(&pdev->dev); 847 846 848 847 ctlr->mem_ops = &ax_spi_mem_ops;

+19 -35

drivers/spi/spi-bcm63xx-hsspi.c

··· 758 758 if (IS_ERR(regs)) 759 759 return PTR_ERR(regs); 760 760 761 - clk = devm_clk_get(dev, "hsspi"); 762 - 761 + clk = devm_clk_get_enabled(dev, "hsspi"); 763 762 if (IS_ERR(clk)) 764 763 return PTR_ERR(clk); 765 764 ··· 766 767 if (IS_ERR(reset)) 767 768 return PTR_ERR(reset); 768 769 769 - ret = clk_prepare_enable(clk); 770 - if (ret) 771 - return ret; 772 - 773 770 ret = reset_control_reset(reset); 774 - if (ret) { 775 - dev_err(dev, "unable to reset device: %d\n", ret); 776 - goto out_disable_clk; 777 - } 771 + if (ret) 772 + return dev_err_probe(dev, ret, "unable to reset device: %d\n", ret); 778 773 779 774 rate = clk_get_rate(clk); 780 775 if (!rate) { 781 - pll_clk = devm_clk_get(dev, "pll"); 782 - 783 - if (IS_ERR(pll_clk)) { 784 - ret = PTR_ERR(pll_clk); 785 - goto out_disable_clk; 786 - } 787 - 788 - ret = clk_prepare_enable(pll_clk); 789 - if (ret) 790 - goto out_disable_clk; 776 + pll_clk = devm_clk_get_enabled(dev, "pll"); 777 + if (IS_ERR(pll_clk)) 778 + return dev_err_probe(dev, PTR_ERR(pll_clk), 779 + "failed enable pll clk\n"); 791 780 792 781 rate = clk_get_rate(pll_clk); 793 - if (!rate) { 794 - ret = -EINVAL; 795 - goto out_disable_pll_clk; 796 - } 782 + if (!rate) 783 + return dev_err_probe(dev, -EINVAL, 784 + "failed get pll clk rate\n"); 797 785 } 798 786 799 787 host = spi_alloc_host(&pdev->dev, sizeof(*bs)); 800 - if (!host) { 801 - ret = -ENOMEM; 802 - goto out_disable_pll_clk; 803 - } 788 + if (!host) 789 + return dev_err_probe(dev, -ENOMEM, "alloc host no mem\n"); 804 790 805 791 bs = spi_controller_get_devdata(host); 806 792 bs->pdev = pdev; ··· 857 873 } 858 874 859 875 /* register and we are done */ 860 - ret = devm_spi_register_controller(dev, host); 876 + ret = spi_register_controller(host); 861 877 if (ret) 862 878 goto out_sysgroup_disable; 863 879 ··· 871 887 pm_runtime_disable(&pdev->dev); 872 888 out_put_host: 873 889 spi_controller_put(host); 874 - out_disable_pll_clk: 875 - clk_disable_unprepare(pll_clk); 876 - out_disable_clk: 877 - clk_disable_unprepare(clk); 878 890 return ret; 879 891 } 880 892 ··· 880 900 struct spi_controller *host = platform_get_drvdata(pdev); 881 901 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host); 882 902 903 + spi_controller_get(host); 904 + 905 + spi_unregister_controller(host); 906 + 883 907 /* reset the hardware and block queue progress */ 884 908 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 885 - clk_disable_unprepare(bs->pll_clk); 886 - clk_disable_unprepare(bs->clk); 887 909 sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group); 910 + 911 + spi_controller_put(host); 888 912 } 889 913 890 914 #ifdef CONFIG_PM_SLEEP

+7 -1

drivers/spi/spi-bcm63xx.c

··· 602 602 goto out_clk_disable; 603 603 604 604 /* register and we are done */ 605 - ret = devm_spi_register_controller(dev, host); 605 + ret = spi_register_controller(host); 606 606 if (ret) { 607 607 dev_err(dev, "spi register failed\n"); 608 608 goto out_clk_disable; ··· 625 625 struct spi_controller *host = platform_get_drvdata(pdev); 626 626 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 627 627 628 + spi_controller_get(host); 629 + 630 + spi_unregister_controller(host); 631 + 628 632 /* reset spi block */ 629 633 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 630 634 631 635 /* HW shutdown */ 632 636 clk_disable_unprepare(bs->clk); 637 + 638 + spi_controller_put(host); 633 639 } 634 640 635 641 static int bcm63xx_spi_suspend(struct device *dev)

+19 -34

drivers/spi/spi-bcmbca-hsspi.c

··· 452 452 if (IS_ERR(spim_ctrl)) 453 453 return PTR_ERR(spim_ctrl); 454 454 455 - clk = devm_clk_get(dev, "hsspi"); 455 + clk = devm_clk_get_enabled(dev, "hsspi"); 456 456 if (IS_ERR(clk)) 457 - return PTR_ERR(clk); 458 - 459 - ret = clk_prepare_enable(clk); 460 - if (ret) 461 - return ret; 457 + return dev_err_probe(dev, PTR_ERR(clk), 458 + "Failed to get hsspi clock\n"); 462 459 463 460 rate = clk_get_rate(clk); 464 461 if (!rate) { 465 - pll_clk = devm_clk_get(dev, "pll"); 462 + pll_clk = devm_clk_get_enabled(dev, "pll"); 466 463 467 464 if (IS_ERR(pll_clk)) { 468 - ret = PTR_ERR(pll_clk); 469 - goto out_disable_clk; 465 + return dev_err_probe(dev, PTR_ERR(pll_clk), 466 + "Failed to get pll clock\n"); 470 467 } 471 - 472 - ret = clk_prepare_enable(pll_clk); 473 - if (ret) 474 - goto out_disable_clk; 475 468 476 469 rate = clk_get_rate(pll_clk); 477 - if (!rate) { 478 - ret = -EINVAL; 479 - goto out_disable_pll_clk; 480 - } 470 + if (!rate) 471 + return dev_err_probe(dev, -EINVAL, 472 + "Failed to get pll clock rate\n"); 481 473 } 482 474 483 475 host = devm_spi_alloc_host(&pdev->dev, sizeof(*bs)); 484 - if (!host) { 485 - ret = -ENOMEM; 486 - goto out_disable_pll_clk; 487 - } 476 + if (!host) 477 + return dev_err_probe(dev, -ENOMEM, 478 + "Failed alloc spi host\n"); 488 479 489 480 bs = spi_controller_get_devdata(host); 490 481 bs->pdev = pdev; ··· 526 535 ret = devm_request_irq(dev, irq, bcmbca_hsspi_interrupt, IRQF_SHARED, 527 536 pdev->name, bs); 528 537 if (ret) 529 - goto out_disable_pll_clk; 538 + return dev_err_probe(dev, ret, "Failed request irq\n"); 530 539 } 531 540 532 541 ret = devm_pm_runtime_enable(&pdev->dev); 533 542 if (ret) 534 - goto out_disable_pll_clk; 543 + return dev_err_probe(dev, ret, "Failed pm runtime enable\n"); 535 544 536 545 ret = sysfs_create_group(&pdev->dev.kobj, &bcmbca_hsspi_group); 537 - if (ret) { 538 - dev_err(&pdev->dev, "couldn't register sysfs group\n"); 539 - goto out_disable_pll_clk; 540 - } 546 + if (ret) 547 + return dev_err_probe(dev, ret, "couldn't register sysfs group\n"); 541 548 542 549 /* register and we are done */ 543 - ret = devm_spi_register_controller(dev, host); 550 + ret = spi_register_controller(host); 544 551 if (ret) 545 552 goto out_sysgroup_disable; 546 553 ··· 548 559 549 560 out_sysgroup_disable: 550 561 sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group); 551 - out_disable_pll_clk: 552 - clk_disable_unprepare(pll_clk); 553 - out_disable_clk: 554 - clk_disable_unprepare(clk); 555 562 return ret; 556 563 } 557 564 ··· 556 571 struct spi_controller *host = platform_get_drvdata(pdev); 557 572 struct bcmbca_hsspi *bs = spi_controller_get_devdata(host); 558 573 574 + spi_unregister_controller(host); 575 + 559 576 /* reset the hardware and block queue progress */ 560 577 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 561 - clk_disable_unprepare(bs->pll_clk); 562 - clk_disable_unprepare(bs->clk); 563 578 sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group); 564 579 } 565 580

-4

drivers/spi/spi-cadence-quadspi.c

··· 1544 1544 if (op->data.nbytes && op->data.buswidth != 8) 1545 1545 return false; 1546 1546 1547 - /* A single opcode is supported, it will be repeated */ 1548 - if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF)) 1549 - return false; 1550 - 1551 1547 if (cqspi->is_rzn1) 1552 1548 return false; 1553 1549 } else if (!all_false) {

+7 -1

drivers/spi/spi-cavium-octeon.c

··· 54 54 host->bits_per_word_mask = SPI_BPW_MASK(8); 55 55 host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ; 56 56 57 - err = devm_spi_register_controller(&pdev->dev, host); 57 + err = spi_register_controller(host); 58 58 if (err) { 59 59 dev_err(&pdev->dev, "register host failed: %d\n", err); 60 60 goto fail; ··· 73 73 struct spi_controller *host = platform_get_drvdata(pdev); 74 74 struct octeon_spi *p = spi_controller_get_devdata(host); 75 75 76 + spi_controller_get(host); 77 + 78 + spi_unregister_controller(host); 79 + 76 80 /* Clear the CSENA* and put everything in a known state. */ 77 81 writeq(0, p->register_base + OCTEON_SPI_CFG(p)); 82 + 83 + spi_controller_put(host); 78 84 } 79 85 80 86 static const struct of_device_id octeon_spi_match[] = {

+7 -1

drivers/spi/spi-cavium-thunderx.c

··· 70 70 71 71 pci_set_drvdata(pdev, host); 72 72 73 - ret = devm_spi_register_controller(dev, host); 73 + ret = spi_register_controller(host); 74 74 if (ret) 75 75 goto error; 76 76 ··· 90 90 if (!p) 91 91 return; 92 92 93 + spi_controller_get(host); 94 + 95 + spi_unregister_controller(host); 96 + 93 97 /* Put everything in a known state. */ 94 98 writeq(0, p->register_base + OCTEON_SPI_CFG(p)); 99 + 100 + spi_controller_put(host); 95 101 } 96 102 97 103 static const struct pci_device_id thunderx_spi_pci_id_table[] = {

+28 -15

drivers/spi/spi-ch341.c

··· 152 152 if (ret) 153 153 return ret; 154 154 155 - ctrl = devm_spi_alloc_host(&udev->dev, sizeof(struct ch341_spi_dev)); 155 + ctrl = devm_spi_alloc_host(&intf->dev, sizeof(struct ch341_spi_dev)); 156 156 if (!ctrl) 157 157 return -ENOMEM; 158 158 ··· 163 163 ch341->read_pipe = usb_rcvbulkpipe(udev, usb_endpoint_num(in)); 164 164 165 165 ch341->rx_len = usb_endpoint_maxp(in); 166 - ch341->rx_buf = devm_kzalloc(&udev->dev, ch341->rx_len, GFP_KERNEL); 166 + ch341->rx_buf = devm_kzalloc(&intf->dev, ch341->rx_len, GFP_KERNEL); 167 167 if (!ch341->rx_buf) 168 168 return -ENOMEM; 169 169 ··· 171 171 if (!ch341->rx_urb) 172 172 return -ENOMEM; 173 173 174 - ch341->tx_buf = 175 - devm_kzalloc(&udev->dev, CH341_PACKET_LENGTH, GFP_KERNEL); 176 - if (!ch341->tx_buf) 177 - return -ENOMEM; 174 + ch341->tx_buf = devm_kzalloc(&intf->dev, CH341_PACKET_LENGTH, GFP_KERNEL); 175 + if (!ch341->tx_buf) { 176 + ret = -ENOMEM; 177 + goto err_free_urb; 178 + } 178 179 179 180 usb_fill_bulk_urb(ch341->rx_urb, udev, ch341->read_pipe, ch341->rx_buf, 180 181 ch341->rx_len, ch341_recv, ch341); 181 182 182 183 ret = usb_submit_urb(ch341->rx_urb, GFP_KERNEL); 183 - if (ret) { 184 - usb_free_urb(ch341->rx_urb); 185 - return -ENOMEM; 186 - } 184 + if (ret) 185 + goto err_free_urb; 187 186 188 187 ctrl->bus_num = -1; 189 188 ctrl->mode_bits = SPI_CPHA; ··· 194 195 195 196 ret = ch341_config_stream(ch341); 196 197 if (ret) 197 - return ret; 198 + goto err_kill_urb; 198 199 199 200 ret = ch341_enable_pins(ch341, true); 200 201 if (ret) 201 - return ret; 202 + goto err_kill_urb; 202 203 203 204 ret = spi_register_controller(ctrl); 204 205 if (ret) 205 - return ret; 206 + goto err_disable_pins; 206 207 207 208 ch341->spidev = spi_new_device(ctrl, &chip); 208 - if (!ch341->spidev) 209 - return -ENOMEM; 209 + if (!ch341->spidev) { 210 + ret = -ENOMEM; 211 + goto err_unregister; 212 + } 210 213 211 214 return 0; 215 + 216 + err_unregister: 217 + spi_unregister_controller(ctrl); 218 + err_disable_pins: 219 + ch341_enable_pins(ch341, false); 220 + err_kill_urb: 221 + usb_kill_urb(ch341->rx_urb); 222 + err_free_urb: 223 + usb_free_urb(ch341->rx_urb); 224 + 225 + return ret; 212 226 } 213 227 214 228 static void ch341_disconnect(struct usb_interface *intf) ··· 231 219 spi_unregister_device(ch341->spidev); 232 220 spi_unregister_controller(ch341->ctrl); 233 221 ch341_enable_pins(ch341, false); 222 + usb_kill_urb(ch341->rx_urb); 234 223 usb_free_urb(ch341->rx_urb); 235 224 } 236 225

+8 -2

drivers/spi/spi-coldfire-qspi.c

··· 410 410 platform_set_drvdata(pdev, host); 411 411 pm_runtime_enable(&pdev->dev); 412 412 413 - status = devm_spi_register_controller(&pdev->dev, host); 413 + status = spi_register_controller(host); 414 414 if (status) { 415 - dev_dbg(&pdev->dev, "devm_spi_register_controller failed\n"); 415 + dev_dbg(&pdev->dev, "failed to register controller\n"); 416 416 goto fail1; 417 417 } 418 418 ··· 436 436 struct spi_controller *host = platform_get_drvdata(pdev); 437 437 struct mcfqspi *mcfqspi = spi_controller_get_devdata(host); 438 438 439 + spi_controller_get(host); 440 + 441 + spi_unregister_controller(host); 442 + 439 443 pm_runtime_disable(&pdev->dev); 440 444 /* disable the hardware (set the baud rate to 0) */ 441 445 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); 442 446 443 447 mcfqspi_cs_teardown(mcfqspi); 448 + 449 + spi_controller_put(host); 444 450 } 445 451 446 452 #ifdef CONFIG_PM_SLEEP

+2 -2

drivers/spi/spi-cs42l43.c

··· 367 367 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode); 368 368 if (ret) 369 369 return ret; 370 + } else { 371 + fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars); 370 372 } 371 - 372 - fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars); 373 373 374 374 /* 375 375 * Depending on the value of nsidecars we either create a software node

+7 -1

drivers/spi/spi-dln2.c

··· 758 758 pm_runtime_set_active(&pdev->dev); 759 759 pm_runtime_enable(&pdev->dev); 760 760 761 - ret = devm_spi_register_controller(&pdev->dev, host); 761 + ret = spi_register_controller(host); 762 762 if (ret < 0) { 763 763 dev_err(&pdev->dev, "Failed to register host\n"); 764 764 goto exit_register; ··· 783 783 struct spi_controller *host = platform_get_drvdata(pdev); 784 784 struct dln2_spi *dln2 = spi_controller_get_devdata(host); 785 785 786 + spi_controller_get(host); 787 + 788 + spi_unregister_controller(host); 789 + 786 790 pm_runtime_disable(&pdev->dev); 787 791 788 792 if (dln2_spi_enable(dln2, false) < 0) 789 793 dev_err(&pdev->dev, "Failed to disable SPI module\n"); 794 + 795 + spi_controller_put(host); 790 796 } 791 797 792 798 #ifdef CONFIG_PM_SLEEP

+7 -1

drivers/spi/spi-ep93xx.c

··· 689 689 /* make sure that the hardware is disabled */ 690 690 writel(0, espi->mmio + SSPCR1); 691 691 692 - error = devm_spi_register_controller(&pdev->dev, host); 692 + error = spi_register_controller(host); 693 693 if (error) { 694 694 dev_err(&pdev->dev, "failed to register SPI host\n"); 695 695 goto fail_free_dma; ··· 713 713 struct spi_controller *host = platform_get_drvdata(pdev); 714 714 struct ep93xx_spi *espi = spi_controller_get_devdata(host); 715 715 716 + spi_controller_get(host); 717 + 718 + spi_unregister_controller(host); 719 + 716 720 ep93xx_spi_release_dma(espi); 721 + 722 + spi_controller_put(host); 717 723 } 718 724 719 725 static const struct of_device_id ep93xx_spi_of_ids[] = {

+9 -1

drivers/spi/spi-fsl-espi.c

··· 718 718 pm_runtime_enable(dev); 719 719 pm_runtime_get_sync(dev); 720 720 721 - ret = devm_spi_register_controller(dev, host); 721 + ret = spi_register_controller(host); 722 722 if (ret < 0) 723 723 goto err_pm; 724 724 ··· 782 782 783 783 static void of_fsl_espi_remove(struct platform_device *dev) 784 784 { 785 + struct spi_controller *host = platform_get_drvdata(dev); 786 + 787 + spi_controller_get(host); 788 + 789 + spi_unregister_controller(host); 790 + 785 791 pm_runtime_disable(&dev->dev); 792 + 793 + spi_controller_put(host); 786 794 } 787 795 788 796 #ifdef CONFIG_PM_SLEEP

+30 -38

drivers/spi/spi-fsl-lpspi.c

··· 75 75 #define CFGR1_PCSPOL_MASK GENMASK(11, 8) 76 76 #define CFGR1_NOSTALL BIT(3) 77 77 #define CFGR1_HOST BIT(0) 78 + #define FCR_RXWATER GENMASK(18, 16) 79 + #define FCR_TXWATER GENMASK(2, 0) 78 80 #define FSR_TXCOUNT (0xFF) 79 81 #define RSR_RXEMPTY BIT(1) 80 82 #define TCR_CPOL BIT(31) 81 83 #define TCR_CPHA BIT(30) 84 + #define TCR_MODE GENMASK(31, 30) 85 + #define TCR_PRESCALE GENMASK(29, 27) 86 + #define TCR_PCS GENMASK(25, 24) 82 87 #define TCR_CONT BIT(21) 83 88 #define TCR_CONTC BIT(20) 84 89 #define TCR_RXMSK BIT(19) 85 90 #define TCR_TXMSK BIT(18) 91 + #define TCR_FRAMESZ GENMASK(11, 0) 86 92 87 93 #define SR_CLEAR_MASK GENMASK(13, 8) 88 94 ··· 101 95 u8 bpw; 102 96 u8 chip_select; 103 97 u8 prescale; 104 - u16 mode; 98 + u32 mode; 105 99 u32 speed_hz; 106 100 u32 effective_speed_hz; 107 101 }; ··· 118 112 119 113 void *rx_buf; 120 114 const void *tx_buf; 121 - void (*tx)(struct fsl_lpspi_data *); 122 - void (*rx)(struct fsl_lpspi_data *); 115 + void (*tx)(struct fsl_lpspi_data *fsl_lpspi); 116 + void (*rx)(struct fsl_lpspi_data *fsl_lpspi); 123 117 124 118 u32 remain; 125 119 u8 watermark; ··· 262 256 263 257 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 264 258 265 - while (txfifo_cnt < fsl_lpspi->txfifosize) { 266 - if (!fsl_lpspi->remain) 267 - break; 259 + while (txfifo_cnt < fsl_lpspi->txfifosize && fsl_lpspi->remain) { 268 260 fsl_lpspi->tx(fsl_lpspi); 269 261 txfifo_cnt++; 270 262 } ··· 275 271 } 276 272 277 273 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 278 - } else 274 + } else { 279 275 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 276 + } 280 277 } 281 278 282 279 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi) ··· 286 281 fsl_lpspi->rx(fsl_lpspi); 287 282 } 288 283 289 - static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi, 290 - struct spi_device *spi) 284 + static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi) 291 285 { 292 286 u32 temp = 0; 293 287 294 - temp |= fsl_lpspi->config.bpw - 1; 295 - temp |= (fsl_lpspi->config.mode & 0x3) << 30; 296 - temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; 288 + temp |= FIELD_PREP(TCR_FRAMESZ, fsl_lpspi->config.bpw - 1); 289 + temp |= FIELD_PREP(TCR_PCS, fsl_lpspi->config.chip_select); 297 290 if (!fsl_lpspi->is_target) { 298 - temp |= fsl_lpspi->config.prescale << 27; 291 + temp |= FIELD_PREP(TCR_PRESCALE, fsl_lpspi->config.prescale); 299 292 /* 300 293 * Set TCR_CONT will keep SS asserted after current transfer. 301 294 * For the first transfer, clear TCR_CONTC to assert SS. ··· 308 305 } 309 306 } 310 307 311 - if (spi->mode & SPI_CPOL) 308 + if (fsl_lpspi->config.mode & SPI_CPOL) 312 309 temp |= TCR_CPOL; 313 310 314 - if (spi->mode & SPI_CPHA) 311 + if (fsl_lpspi->config.mode & SPI_CPHA) 315 312 temp |= TCR_CPHA; 316 313 317 314 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); ··· 321 318 322 319 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) 323 320 { 321 + u8 watermark = fsl_lpspi->watermark >> 1; 324 322 u32 temp; 325 323 326 324 if (!fsl_lpspi->usedma) 327 - temp = fsl_lpspi->watermark >> 1 | 328 - (fsl_lpspi->watermark >> 1) << 16; 325 + temp = FIELD_PREP(FCR_TXWATER, watermark) | 326 + FIELD_PREP(FCR_RXWATER, watermark); 329 327 else 330 - temp = fsl_lpspi->watermark >> 1; 328 + temp = FIELD_PREP(FCR_TXWATER, watermark); 331 329 332 330 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); 333 331 334 - dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); 332 + dev_dbg(fsl_lpspi->dev, "FCR=0x%08x\n", temp); 335 333 } 336 334 337 335 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) ··· 352 348 return -EINVAL; 353 349 } 354 350 355 - if (config.speed_hz > perclk_rate / 2) { 351 + if (config.speed_hz > perclk_rate / 2) 356 352 div = 2; 357 - } else { 353 + else 358 354 div = DIV_ROUND_UP(perclk_rate, config.speed_hz); 359 - } 360 355 361 356 for (prescale = 0; prescale <= prescale_max; prescale++) { 362 357 scldiv = div / (1 << prescale) - 2; ··· 469 466 struct fsl_lpspi_data *fsl_lpspi = 470 467 spi_controller_get_devdata(spi->controller); 471 468 472 - if (t == NULL) 473 - return -EINVAL; 474 - 475 469 fsl_lpspi->config.mode = spi->mode; 476 470 fsl_lpspi->config.bpw = t->bits_per_word; 477 471 fsl_lpspi->config.speed_hz = t->speed_hz; ··· 517 517 fsl_lpspi->usedma = false; 518 518 ret = fsl_lpspi_setup_transfer(controller, spi, t); 519 519 520 - if (fsl_lpspi_can_dma(controller, spi, t)) 521 - fsl_lpspi->usedma = true; 522 - else 523 - fsl_lpspi->usedma = false; 520 + fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t); 524 521 525 522 if (ret < 0) 526 523 return ret; 527 524 528 - fsl_lpspi_set_cmd(fsl_lpspi, spi); 525 + fsl_lpspi_set_cmd(fsl_lpspi); 529 526 530 527 /* No IRQs */ 531 528 writel(0, fsl_lpspi->base + IMX7ULP_IER); ··· 571 574 return 0; 572 575 } 573 576 574 - static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 577 + static void fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 575 578 { 576 579 u32 temp; 577 580 ··· 586 589 587 590 /* W1C for all flags in SR */ 588 591 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR); 589 - 590 - return 0; 591 592 } 592 593 593 594 static void fsl_lpspi_dma_rx_callback(void *cookie) ··· 789 794 spi_controller_get_devdata(controller); 790 795 int ret; 791 796 792 - if (fsl_lpspi_can_dma(controller, spi, t)) 793 - fsl_lpspi->usedma = true; 794 - else 795 - fsl_lpspi->usedma = false; 797 + fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t); 796 798 797 799 ret = fsl_lpspi_setup_transfer(controller, spi, t); 798 800 if (ret < 0) ··· 797 805 798 806 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz; 799 807 800 - fsl_lpspi_set_cmd(fsl_lpspi, spi); 808 + fsl_lpspi_set_cmd(fsl_lpspi); 801 809 fsl_lpspi->is_first_byte = false; 802 810 803 811 if (fsl_lpspi->usedma)

+2 -1

drivers/spi/spi-fsl-qspi.c

··· 633 633 void __iomem *base = q->iobase; 634 634 int err = 0; 635 635 636 - init_completion(&q->c); 636 + reinit_completion(&q->c); 637 637 638 638 /* 639 639 * Always start the sequence at the same index since we update ··· 965 965 if (ret < 0) 966 966 return ret; 967 967 968 + init_completion(&q->c); 968 969 ret = devm_request_irq(dev, ret, 969 970 fsl_qspi_irq_handler, 0, pdev->name, q); 970 971 if (ret) {

+13 -1

drivers/spi/spi-fsl-spi.c

··· 614 614 615 615 mpc8xxx_spi_write_reg(&reg_base->mode, regval); 616 616 617 - ret = devm_spi_register_controller(dev, host); 617 + ret = spi_register_controller(host); 618 618 if (ret < 0) 619 619 goto err_probe; 620 620 ··· 705 705 struct spi_controller *host = platform_get_drvdata(ofdev); 706 706 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host); 707 707 708 + spi_controller_get(host); 709 + 710 + spi_unregister_controller(host); 711 + 708 712 fsl_spi_cpm_free(mpc8xxx_spi); 713 + 714 + spi_controller_put(host); 709 715 } 710 716 711 717 static struct platform_driver of_fsl_spi_driver = { ··· 757 751 struct spi_controller *host = platform_get_drvdata(pdev); 758 752 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host); 759 753 754 + spi_controller_get(host); 755 + 756 + spi_unregister_controller(host); 757 + 760 758 fsl_spi_cpm_free(mpc8xxx_spi); 759 + 760 + spi_controller_put(host); 761 761 } 762 762 763 763 MODULE_ALIAS("platform:mpc8xxx_spi");

+15 -2

drivers/spi/spi-hisi-kunpeng.c

··· 196 196 unsigned long limit = loops_per_jiffy << 1; 197 197 198 198 do { 199 - while (hisi_spi_rx_not_empty(hs)) 199 + unsigned long inner_limit = loops_per_jiffy; 200 + 201 + while (hisi_spi_rx_not_empty(hs) && --inner_limit) { 200 202 readl(hs->regs + HISI_SPI_DOUT); 201 - } while (hisi_spi_busy(hs) && limit--); 203 + cpu_relax(); 204 + } 205 + 206 + if (!inner_limit) { 207 + dev_warn_ratelimited(hs->dev, "RX FIFO flush timeout\n"); 208 + break; 209 + } 210 + 211 + } while (hisi_spi_busy(hs) && --limit); 212 + 213 + if (!limit) 214 + dev_warn_ratelimited(hs->dev, "SPI busy timeout\n"); 202 215 } 203 216 204 217 /* Disable the controller and all interrupts */

+7 -1

drivers/spi/spi-img-spfi.c

··· 643 643 pm_runtime_set_active(spfi->dev); 644 644 pm_runtime_enable(spfi->dev); 645 645 646 - ret = devm_spi_register_controller(spfi->dev, host); 646 + ret = spi_register_controller(host); 647 647 if (ret) 648 648 goto disable_pm; 649 649 ··· 669 669 struct spi_controller *host = platform_get_drvdata(pdev); 670 670 struct img_spfi *spfi = spi_controller_get_devdata(host); 671 671 672 + spi_controller_get(host); 673 + 674 + spi_unregister_controller(host); 675 + 672 676 if (spfi->tx_ch) 673 677 dma_release_channel(spfi->tx_ch); 674 678 if (spfi->rx_ch) ··· 683 679 clk_disable_unprepare(spfi->spfi_clk); 684 680 clk_disable_unprepare(spfi->sys_clk); 685 681 } 682 + 683 + spi_controller_put(host); 686 684 } 687 685 688 686 #ifdef CONFIG_PM

+14 -27

drivers/spi/spi-imx.c

··· 2231 2231 target_mode = devtype_data->has_targetmode && 2232 2232 of_property_read_bool(np, "spi-slave"); 2233 2233 if (target_mode) 2234 - controller = spi_alloc_target(&pdev->dev, 2235 - sizeof(struct spi_imx_data)); 2234 + controller = devm_spi_alloc_target(&pdev->dev, sizeof(*spi_imx)); 2236 2235 else 2237 - controller = spi_alloc_host(&pdev->dev, 2238 - sizeof(struct spi_imx_data)); 2236 + controller = devm_spi_alloc_host(&pdev->dev, sizeof(*spi_imx)); 2239 2237 if (!controller) 2240 2238 return -ENOMEM; 2241 2239 ··· 2302 2304 init_completion(&spi_imx->xfer_done); 2303 2305 2304 2306 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2305 - if (IS_ERR(spi_imx->base)) { 2306 - ret = PTR_ERR(spi_imx->base); 2307 - goto out_controller_put; 2308 - } 2307 + if (IS_ERR(spi_imx->base)) 2308 + return PTR_ERR(spi_imx->base); 2309 + 2309 2310 spi_imx->base_phys = res->start; 2310 2311 2311 2312 irq = platform_get_irq(pdev, 0); 2312 - if (irq < 0) { 2313 - ret = irq; 2314 - goto out_controller_put; 2315 - } 2313 + if (irq < 0) 2314 + return irq; 2316 2315 2317 2316 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 2318 2317 dev_name(&pdev->dev), spi_imx); 2319 - if (ret) { 2320 - dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 2321 - goto out_controller_put; 2322 - } 2318 + if (ret) 2319 + return dev_err_probe(&pdev->dev, ret, "can't get irq%d\n", irq); 2323 2320 2324 2321 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2325 - if (IS_ERR(spi_imx->clk_ipg)) { 2326 - ret = PTR_ERR(spi_imx->clk_ipg); 2327 - goto out_controller_put; 2328 - } 2322 + if (IS_ERR(spi_imx->clk_ipg)) 2323 + return PTR_ERR(spi_imx->clk_ipg); 2329 2324 2330 2325 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 2331 - if (IS_ERR(spi_imx->clk_per)) { 2332 - ret = PTR_ERR(spi_imx->clk_per); 2333 - goto out_controller_put; 2334 - } 2326 + if (IS_ERR(spi_imx->clk_per)) 2327 + return PTR_ERR(spi_imx->clk_per); 2335 2328 2336 2329 ret = clk_prepare_enable(spi_imx->clk_per); 2337 2330 if (ret) 2338 - goto out_controller_put; 2331 + return ret; 2339 2332 2340 2333 ret = clk_prepare_enable(spi_imx->clk_ipg); 2341 2334 if (ret) ··· 2378 2389 clk_disable_unprepare(spi_imx->clk_ipg); 2379 2390 out_put_per: 2380 2391 clk_disable_unprepare(spi_imx->clk_per); 2381 - out_controller_put: 2382 - spi_controller_put(controller); 2383 2392 2384 2393 return ret; 2385 2394 }

+7 -1

drivers/spi/spi-lantiq-ssc.c

··· 994 994 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n", 995 995 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); 996 996 997 - err = devm_spi_register_controller(dev, host); 997 + err = spi_register_controller(host); 998 998 if (err) { 999 999 dev_err(dev, "failed to register spi host\n"); 1000 1000 goto err_wq_destroy; ··· 1016 1016 { 1017 1017 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); 1018 1018 1019 + spi_controller_get(spi->host); 1020 + 1021 + spi_unregister_controller(spi->host); 1022 + 1019 1023 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); 1020 1024 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); 1021 1025 rx_fifo_flush(spi); ··· 1028 1024 1029 1025 destroy_workqueue(spi->wq); 1030 1026 clk_put(spi->fpi_clk); 1027 + 1028 + spi_controller_put(spi->host); 1031 1029 } 1032 1030 1033 1031 static struct platform_driver lantiq_ssc_driver = {

+7 -1

drivers/spi/spi-meson-spicc.c

··· 1081 1081 } 1082 1082 } 1083 1083 1084 - ret = devm_spi_register_controller(&pdev->dev, host); 1084 + ret = spi_register_controller(host); 1085 1085 if (ret) { 1086 1086 dev_err(&pdev->dev, "spi registration failed\n"); 1087 1087 goto out_host; ··· 1099 1099 { 1100 1100 struct meson_spicc_device *spicc = platform_get_drvdata(pdev); 1101 1101 1102 + spi_controller_get(spicc->host); 1103 + 1104 + spi_unregister_controller(spicc->host); 1105 + 1102 1106 /* Disable SPI */ 1103 1107 writel(0, spicc->base + SPICC_CONREG); 1108 + 1109 + spi_controller_put(spicc->host); 1104 1110 } 1105 1111 1106 1112 static const struct meson_spicc_data meson_spicc_gx_data = {

+8 -4

drivers/spi/spi-microchip-core-qspi.c

··· 692 692 return -ENOMEM; 693 693 694 694 qspi = spi_controller_get_devdata(ctlr); 695 - platform_set_drvdata(pdev, qspi); 695 + platform_set_drvdata(pdev, ctlr); 696 696 697 697 qspi->regs = devm_platform_ioremap_resource(pdev, 0); 698 698 if (IS_ERR(qspi->regs)) ··· 732 732 ctlr->num_chipselect = 2; 733 733 ctlr->use_gpio_descriptors = true; 734 734 735 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 735 + ret = spi_register_controller(ctlr); 736 736 if (ret) 737 737 return dev_err_probe(&pdev->dev, ret, 738 738 "spi_register_controller failed\n"); ··· 742 742 743 743 static void mchp_coreqspi_remove(struct platform_device *pdev) 744 744 { 745 - struct mchp_coreqspi *qspi = platform_get_drvdata(pdev); 746 - u32 control = readl_relaxed(qspi->regs + REG_CONTROL); 745 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 746 + struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); 747 + u32 control; 747 748 749 + spi_unregister_controller(ctlr); 750 + 751 + control = readl_relaxed(qspi->regs + REG_CONTROL); 748 752 mchp_coreqspi_disable_ints(qspi); 749 753 control &= ~CONTROL_ENABLE; 750 754 writel_relaxed(control, qspi->regs + REG_CONTROL);

+3 -1

drivers/spi/spi-microchip-core-spi.c

··· 384 384 385 385 mchp_corespi_init(host, spi); 386 386 387 - ret = devm_spi_register_controller(dev, host); 387 + ret = spi_register_controller(host); 388 388 if (ret) { 389 389 mchp_corespi_disable_ints(spi); 390 390 mchp_corespi_disable(spi); ··· 398 398 { 399 399 struct spi_controller *host = platform_get_drvdata(pdev); 400 400 struct mchp_corespi *spi = spi_controller_get_devdata(host); 401 + 402 + spi_unregister_controller(host); 401 403 402 404 mchp_corespi_disable_ints(spi); 403 405 mchp_corespi_disable(spi);

+3 -1

drivers/spi/spi-mpfs.c

··· 574 574 575 575 mpfs_spi_init(host, spi); 576 576 577 - ret = devm_spi_register_controller(&pdev->dev, host); 577 + ret = spi_register_controller(host); 578 578 if (ret) { 579 579 mpfs_spi_disable_ints(spi); 580 580 mpfs_spi_disable(spi); ··· 591 591 { 592 592 struct spi_controller *host = platform_get_drvdata(pdev); 593 593 struct mpfs_spi *spi = spi_controller_get_devdata(host); 594 + 595 + spi_unregister_controller(host); 594 596 595 597 mpfs_spi_disable_ints(spi); 596 598 mpfs_spi_disable(spi);

+3 -1

drivers/spi/spi-mt65xx.c

··· 1325 1325 1326 1326 pm_runtime_enable(dev); 1327 1327 1328 - ret = devm_spi_register_controller(dev, host); 1328 + ret = spi_register_controller(host); 1329 1329 if (ret) { 1330 1330 pm_runtime_disable(dev); 1331 1331 return dev_err_probe(dev, ret, "failed to register host\n"); ··· 1339 1339 struct spi_controller *host = platform_get_drvdata(pdev); 1340 1340 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1341 1341 int ret; 1342 + 1343 + spi_unregister_controller(host); 1342 1344 1343 1345 cpu_latency_qos_remove_request(&mdata->qos_request); 1344 1346 if (mdata->use_spimem && !completion_done(&mdata->spimem_done))

+3 -1

drivers/spi/spi-mtk-nor.c

··· 913 913 pm_runtime_enable(&pdev->dev); 914 914 pm_runtime_get_noresume(&pdev->dev); 915 915 916 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 916 + ret = spi_register_controller(ctlr); 917 917 if (ret < 0) 918 918 goto err_probe; 919 919 ··· 937 937 { 938 938 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); 939 939 struct mtk_nor *sp = spi_controller_get_devdata(ctlr); 940 + 941 + spi_unregister_controller(ctlr); 940 942 941 943 pm_runtime_disable(&pdev->dev); 942 944 pm_runtime_set_suspended(&pdev->dev);

+14

drivers/spi/spi-mtk-snfi.c

··· 1303 1303 .ecc = true, 1304 1304 }; 1305 1305 1306 + static void mtk_unregister_ecc_engine(void *data) 1307 + { 1308 + struct nand_ecc_engine *eng = data; 1309 + 1310 + nand_ecc_unregister_on_host_hw_engine(eng); 1311 + } 1312 + 1306 1313 static irqreturn_t mtk_snand_irq(int irq, void *id) 1307 1314 { 1308 1315 struct mtk_snand *snf = id; ··· 1447 1440 ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); 1448 1441 if (ret) { 1449 1442 dev_err(&pdev->dev, "failed to register ecc engine.\n"); 1443 + goto release_ecc; 1444 + } 1445 + 1446 + ret = devm_add_action_or_reset(&pdev->dev, mtk_unregister_ecc_engine, 1447 + &ms->ecc_eng); 1448 + if (ret) { 1449 + dev_err_probe(&pdev->dev, ret, "failed to add ECC unregister action\n"); 1450 1450 goto release_ecc; 1451 1451 } 1452 1452

+7 -1

drivers/spi/spi-mxs.c

··· 619 619 if (ret) 620 620 goto out_pm_runtime_put; 621 621 622 - ret = devm_spi_register_controller(&pdev->dev, host); 622 + ret = spi_register_controller(host); 623 623 if (ret) { 624 624 dev_err(&pdev->dev, "Cannot register SPI host, %d\n", ret); 625 625 goto out_pm_runtime_put; ··· 650 650 spi = spi_controller_get_devdata(host); 651 651 ssp = &spi->ssp; 652 652 653 + spi_controller_get(host); 654 + 655 + spi_unregister_controller(host); 656 + 653 657 pm_runtime_disable(&pdev->dev); 654 658 if (!pm_runtime_status_suspended(&pdev->dev)) 655 659 mxs_spi_runtime_suspend(&pdev->dev); 656 660 657 661 dma_release_channel(ssp->dmach); 662 + 663 + spi_controller_put(host); 658 664 } 659 665 660 666 static struct platform_driver mxs_spi_driver = {

-8

drivers/spi/spi-npcm-fiu.c

··· 715 715 716 716 fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; 717 717 718 - platform_set_drvdata(pdev, fiu); 719 718 fiu->dev = dev; 720 719 721 720 regbase = devm_platform_ioremap_resource_byname(pdev, "control"); ··· 737 738 fiu->spix_mode = of_property_read_bool(dev->of_node, 738 739 "nuvoton,spix-mode"); 739 740 740 - platform_set_drvdata(pdev, fiu); 741 - 742 741 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD 743 742 | SPI_TX_DUAL | SPI_TX_QUAD; 744 743 ctrl->setup = npcm_fiu_setup; ··· 745 748 ctrl->num_chipselect = fiu->info->max_cs; 746 749 747 750 return devm_spi_register_controller(dev, ctrl); 748 - } 749 - 750 - static void npcm_fiu_remove(struct platform_device *pdev) 751 - { 752 751 } 753 752 754 753 MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids); ··· 756 763 .of_match_table = npcm_fiu_dt_ids, 757 764 }, 758 765 .probe = npcm_fiu_probe, 759 - .remove = npcm_fiu_remove, 760 766 }; 761 767 module_platform_driver(npcm_fiu_driver); 762 768

+7 -1

drivers/spi/spi-npcm-pspi.c

··· 413 413 /* set to default clock rate */ 414 414 npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK); 415 415 416 - ret = devm_spi_register_controller(&pdev->dev, host); 416 + ret = spi_register_controller(host); 417 417 if (ret) 418 418 goto out_disable_clk; 419 419 ··· 434 434 struct spi_controller *host = platform_get_drvdata(pdev); 435 435 struct npcm_pspi *priv = spi_controller_get_devdata(host); 436 436 437 + spi_controller_get(host); 438 + 439 + spi_unregister_controller(host); 440 + 437 441 npcm_pspi_reset_hw(priv); 438 442 clk_disable_unprepare(priv->clk); 443 + 444 + spi_controller_put(host); 439 445 } 440 446 441 447 static const struct of_device_id npcm_pspi_match[] = {

+2 -1

drivers/spi/spi-nxp-fspi.c

··· 996 996 reg = reg | FSPI_IPRXFCR_CLR; 997 997 fspi_writel(f, reg, base + FSPI_IPRXFCR); 998 998 999 - init_completion(&f->c); 999 + reinit_completion(&f->c); 1000 1000 1001 1001 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 1002 1002 /* ··· 1365 1365 if (ret < 0) 1366 1366 return dev_err_probe(dev, ret, "Failed to disable clock"); 1367 1367 1368 + init_completion(&f->c); 1368 1369 ret = devm_request_irq(dev, irq, 1369 1370 nxp_fspi_irq_handler, 0, pdev->name, f); 1370 1371 if (ret)

+2 -1

drivers/spi/spi-nxp-xspi.c

··· 958 958 writel(reg, base + XSPI_RBCT); 959 959 } 960 960 961 - init_completion(&xspi->c); 961 + reinit_completion(&xspi->c); 962 962 963 963 /* Config the data address */ 964 964 writel(op->addr.val + xspi->memmap_phy, base + XSPI_SFP_TG_SFAR); ··· 1273 1273 1274 1274 nxp_xspi_default_setup(xspi); 1275 1275 1276 + init_completion(&xspi->c); 1276 1277 ret = devm_request_irq(dev, irq, 1277 1278 nxp_xspi_irq_handler, 0, pdev->name, xspi); 1278 1279 if (ret)

+19 -6

drivers/spi/spi-omap2-mcspi.c

··· 942 942 943 943 l = mcspi_cached_chconf0(spi); 944 944 945 - /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS 946 - * REVISIT: this controller could support SPI_3WIRE mode. 947 - */ 948 - if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 945 + if (spi->mode & SPI_3WIRE) { 946 + if (t && !t->tx_buf) { 947 + l &= ~OMAP2_MCSPI_CHCONF_IS; 948 + l |= OMAP2_MCSPI_CHCONF_DPE0; 949 + } else if (t && !t->rx_buf) { 950 + l |= OMAP2_MCSPI_CHCONF_IS; 951 + l &= ~OMAP2_MCSPI_CHCONF_DPE0; 952 + } 953 + l |= OMAP2_MCSPI_CHCONF_DPE1; 954 + } else if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 949 955 l &= ~OMAP2_MCSPI_CHCONF_IS; 950 956 l &= ~OMAP2_MCSPI_CHCONF_DPE1; 951 957 l |= OMAP2_MCSPI_CHCONF_DPE0; ··· 1184 1178 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); 1185 1179 1186 1180 if (par_override || 1181 + (spi->mode & SPI_3WIRE) || 1187 1182 (t->speed_hz != spi->max_speed_hz) || 1188 1183 (t->bits_per_word != spi->bits_per_word)) { 1189 1184 par_override = 1; ··· 1491 1484 return -ENOMEM; 1492 1485 1493 1486 /* the spi->mode bits understood by this driver: */ 1494 - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1487 + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_3WIRE; 1495 1488 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1496 1489 ctlr->setup = omap2_mcspi_setup; 1497 1490 ctlr->auto_runtime_pm = true; ··· 1592 1585 if (status < 0) 1593 1586 goto disable_pm; 1594 1587 1595 - status = devm_spi_register_controller(&pdev->dev, ctlr); 1588 + status = spi_register_controller(ctlr); 1596 1589 if (status < 0) 1597 1590 goto disable_pm; 1598 1591 ··· 1613 1606 struct spi_controller *ctlr = platform_get_drvdata(pdev); 1614 1607 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); 1615 1608 1609 + spi_controller_get(ctlr); 1610 + 1611 + spi_unregister_controller(ctlr); 1612 + 1616 1613 omap2_mcspi_release_dma(ctlr); 1617 1614 1618 1615 pm_runtime_dont_use_autosuspend(mcspi->dev); 1619 1616 pm_runtime_put_sync(mcspi->dev); 1620 1617 pm_runtime_disable(&pdev->dev); 1618 + 1619 + spi_controller_put(ctlr); 1621 1620 } 1622 1621 1623 1622 /* work with hotplug and coldplug */

+7 -1

drivers/spi/spi-pic32-sqi.c

··· 642 642 host->prepare_transfer_hardware = pic32_sqi_prepare_hardware; 643 643 host->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware; 644 644 645 - ret = devm_spi_register_controller(&pdev->dev, host); 645 + ret = spi_register_controller(host); 646 646 if (ret) { 647 647 dev_err(&host->dev, "failed registering spi host\n"); 648 648 free_irq(sqi->irq, sqi); ··· 665 665 { 666 666 struct pic32_sqi *sqi = platform_get_drvdata(pdev); 667 667 668 + spi_controller_get(sqi->host); 669 + 670 + spi_unregister_controller(sqi->host); 671 + 668 672 /* release resources */ 669 673 free_irq(sqi->irq, sqi); 670 674 ring_desc_ring_free(sqi); 675 + 676 + spi_controller_put(sqi->host); 671 677 } 672 678 673 679 static const struct of_device_id pic32_sqi_of_ids[] = {

+8 -3

drivers/spi/spi-pic32.c

··· 821 821 } 822 822 823 823 /* register host */ 824 - ret = devm_spi_register_controller(&pdev->dev, host); 824 + ret = spi_register_controller(host); 825 825 if (ret) { 826 826 dev_err(&host->dev, "failed registering spi host\n"); 827 827 goto err_bailout; ··· 840 840 841 841 static void pic32_spi_remove(struct platform_device *pdev) 842 842 { 843 - struct pic32_spi *pic32s; 843 + struct pic32_spi *pic32s = platform_get_drvdata(pdev); 844 844 845 - pic32s = platform_get_drvdata(pdev); 845 + spi_controller_get(pic32s->host); 846 + 847 + spi_unregister_controller(pic32s->host); 848 + 846 849 pic32_spi_disable(pic32s); 847 850 pic32_spi_dma_unprep(pic32s); 851 + 852 + spi_controller_put(pic32s->host); 848 853 } 849 854 850 855 static const struct of_device_id pic32_spi_of_match[] = {

+12 -6

drivers/spi/spi-pl022.c

··· 1127 1127 * 1128 1128 * This function handles interrupts generated for an interrupt based transfer. 1129 1129 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1130 - * current message's state as STATE_ERROR and schedule the tasklet 1131 - * pump_transfers which will do the postprocessing of the current message by 1132 - * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1133 - * more data, and writes data in TX FIFO till it is not full. If we complete 1134 - * the transfer we move to the next transfer and schedule the tasklet. 1130 + * current transfer with SPI_TRANS_FAIL_IO and call 1131 + * spi_finalize_current_transfer() to let the core finish the message. 1132 + * Otherwise it reads data from RX FIFO till there is no more data, and writes 1133 + * data in TX FIFO till it is not full. When the transfer is complete we call 1134 + * spi_finalize_current_transfer() so the core can schedule the next one. 1135 1135 */ 1136 1136 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1137 1137 { ··· 1956 1956 1957 1957 /* Register with the SPI framework */ 1958 1958 amba_set_drvdata(adev, pl022); 1959 - status = devm_spi_register_controller(&adev->dev, host); 1959 + status = spi_register_controller(host); 1960 1960 if (status != 0) { 1961 1961 dev_err_probe(&adev->dev, status, 1962 1962 "problem registering spi host\n"); ··· 1997 1997 if (!pl022) 1998 1998 return; 1999 1999 2000 + spi_controller_get(pl022->host); 2001 + 2002 + spi_unregister_controller(pl022->host); 2003 + 2000 2004 /* 2001 2005 * undo pm_runtime_put() in probe. I assume that we're not 2002 2006 * accessing the primecell here. ··· 2012 2008 pl022_dma_remove(pl022); 2013 2009 2014 2010 amba_release_regions(adev); 2011 + 2012 + spi_controller_put(pl022->host); 2015 2013 } 2016 2014 2017 2015 #ifdef CONFIG_PM_SLEEP

+3 -3

drivers/spi/spi-pxa2xx-dma.c

··· 29 29 30 30 /* 31 31 * It is possible that one CPU is handling ROR interrupt and other 32 - * just gets DMA completion. Calling pump_transfers() twice for the 33 - * same transfer leads to problems thus we prevent concurrent calls 34 - * by using dma_running. 32 + * just gets DMA completion. Calling spi_finalize_current_transfer() 33 + * twice for the same transfer leads to problems thus we prevent 34 + * concurrent calls by using dma_running. 35 35 */ 36 36 if (atomic_dec_and_test(&drv_data->dma_running)) { 37 37 /*

+5 -6

drivers/spi/spi-pxa2xx.c

··· 796 796 * The function calculates parameters for all cases and chooses the one closest 797 797 * to the asked baud rate. 798 798 */ 799 - static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 799 + static unsigned int quark_x1000_get_clk_div(u32 rate, u32 *dds) 800 800 { 801 801 unsigned long xtal = 200000000; 802 802 unsigned long fref = xtal / 2; /* mandatory division by 2, ··· 885 885 return q - 1; 886 886 } 887 887 888 - static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 888 + static unsigned int ssp_get_clk_div(struct driver_data *drv_data, u32 rate) 889 889 { 890 - unsigned long ssp_clk = drv_data->controller->max_speed_hz; 890 + u32 ssp_clk = drv_data->controller->max_speed_hz; 891 891 const struct ssp_device *ssp = drv_data->ssp; 892 892 893 - rate = min_t(int, ssp_clk, rate); 893 + rate = min(ssp_clk, rate); 894 894 895 895 /* 896 896 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding ··· 902 902 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; 903 903 } 904 904 905 - static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 906 - int rate) 905 + static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, u32 rate) 907 906 { 908 907 struct chip_data *chip = 909 908 spi_get_ctldata(drv_data->controller->cur_msg->spi);

+7 -1

drivers/spi/spi-qup.c

··· 1193 1193 pm_runtime_set_active(dev); 1194 1194 pm_runtime_enable(dev); 1195 1195 1196 - ret = devm_spi_register_controller(dev, host); 1196 + ret = spi_register_controller(host); 1197 1197 if (ret) 1198 1198 goto disable_pm; 1199 1199 ··· 1320 1320 struct spi_qup *controller = spi_controller_get_devdata(host); 1321 1321 int ret; 1322 1322 1323 + spi_controller_get(host); 1324 + 1325 + spi_unregister_controller(host); 1326 + 1323 1327 ret = pm_runtime_get_sync(&pdev->dev); 1324 1328 1325 1329 if (ret >= 0) { ··· 1343 1339 1344 1340 pm_runtime_put_noidle(&pdev->dev); 1345 1341 pm_runtime_disable(&pdev->dev); 1342 + 1343 + spi_controller_put(host); 1346 1344 } 1347 1345 1348 1346 static const struct of_device_id spi_qup_dt_match[] = {

+16 -24

drivers/spi/spi-rockchip.c

··· 767 767 target_mode = of_property_read_bool(np, "spi-slave"); 768 768 769 769 if (target_mode) 770 - ctlr = spi_alloc_target(&pdev->dev, sizeof(struct rockchip_spi)); 770 + ctlr = devm_spi_alloc_target(&pdev->dev, sizeof(*rs)); 771 771 else 772 - ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rockchip_spi)); 772 + ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*rs)); 773 773 774 774 if (!ctlr) 775 775 return -ENOMEM; ··· 780 780 781 781 /* Get basic io resource and map it */ 782 782 rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 783 - if (IS_ERR(rs->regs)) { 784 - ret = PTR_ERR(rs->regs); 785 - goto err_put_ctlr; 786 - } 783 + if (IS_ERR(rs->regs)) 784 + return PTR_ERR(rs->regs); 787 785 788 786 rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); 789 787 if (IS_ERR(rs->apb_pclk)) { 790 - ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->apb_pclk), 791 - "Failed to get apb_pclk\n"); 792 - goto err_put_ctlr; 788 + return dev_err_probe(&pdev->dev, PTR_ERR(rs->apb_pclk), 789 + "Failed to get apb_pclk\n"); 793 790 } 794 791 795 792 rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk"); 796 793 if (IS_ERR(rs->spiclk)) { 797 - ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->spiclk), 798 - "Failed to get spi_pclk\n"); 799 - goto err_put_ctlr; 794 + return dev_err_probe(&pdev->dev, PTR_ERR(rs->spiclk), 795 + "Failed to get spi_pclk\n"); 800 796 } 801 797 802 798 spi_enable_chip(rs, false); 803 799 804 800 ret = platform_get_irq(pdev, 0); 805 801 if (ret < 0) 806 - goto err_put_ctlr; 802 + return ret; 807 803 808 804 ret = devm_request_irq(&pdev->dev, ret, rockchip_spi_isr, 0, 809 805 dev_name(&pdev->dev), ctlr); 810 806 if (ret) 811 - goto err_put_ctlr; 807 + return ret; 812 808 813 809 rs->dev = &pdev->dev; 814 810 rs->freq = clk_get_rate(rs->spiclk); ··· 826 830 } 827 831 828 832 rs->fifo_len = get_fifo_len(rs); 829 - if (!rs->fifo_len) { 830 - ret = dev_err_probe(&pdev->dev, -EINVAL, "Failed to get fifo length\n"); 831 - goto err_put_ctlr; 832 - } 833 + if (!rs->fifo_len) 834 + return dev_err_probe(&pdev->dev, -EINVAL, "Failed to get fifo length\n"); 833 835 834 836 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 835 837 pm_runtime_use_autosuspend(&pdev->dev); ··· 902 908 break; 903 909 } 904 910 905 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 911 + ret = spi_register_controller(ctlr); 906 912 if (ret < 0) { 907 913 dev_err(&pdev->dev, "Failed to register controller\n"); 908 914 goto err_free_dma_rx; ··· 918 924 dma_release_channel(ctlr->dma_tx); 919 925 err_disable_pm_runtime: 920 926 pm_runtime_disable(&pdev->dev); 921 - err_put_ctlr: 922 - spi_controller_put(ctlr); 923 927 924 928 return ret; 925 929 } 926 930 927 931 static void rockchip_spi_remove(struct platform_device *pdev) 928 932 { 929 - struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 933 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 930 934 931 935 pm_runtime_get_sync(&pdev->dev); 936 + 937 + spi_unregister_controller(ctlr); 932 938 933 939 pm_runtime_put_noidle(&pdev->dev); 934 940 pm_runtime_disable(&pdev->dev); ··· 938 944 dma_release_channel(ctlr->dma_tx); 939 945 if (ctlr->dma_rx) 940 946 dma_release_channel(ctlr->dma_rx); 941 - 942 - spi_controller_put(ctlr); 943 947 } 944 948 945 949 #ifdef CONFIG_PM_SLEEP

+8 -2

drivers/spi/spi-rspi.c

··· 1171 1171 { 1172 1172 struct rspi_data *rspi = platform_get_drvdata(pdev); 1173 1173 1174 + spi_controller_get(rspi->ctlr); 1175 + 1176 + spi_unregister_controller(rspi->ctlr); 1177 + 1174 1178 rspi_release_dma(rspi->ctlr); 1175 1179 pm_runtime_disable(&pdev->dev); 1180 + 1181 + spi_controller_put(rspi->ctlr); 1176 1182 } 1177 1183 1178 1184 static const struct spi_ops rspi_ops = { ··· 1382 1376 if (ret < 0) 1383 1377 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1384 1378 1385 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 1379 + ret = spi_register_controller(ctlr); 1386 1380 if (ret < 0) { 1387 - dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 1381 + dev_err(&pdev->dev, "failed to register controller\n"); 1388 1382 goto error3; 1389 1383 } 1390 1384

+33 -27

drivers/spi/spi-rzv2h-rspi.c

··· 50 50 51 51 /* Register SPBR */ 52 52 #define RSPI_SPBR_SPR_MIN 0 53 - #define RSPI_SPBR_SPR_PCLK_MIN 1 54 53 #define RSPI_SPBR_SPR_MAX 255 55 54 56 55 /* Register SPCMD */ ··· 76 77 77 78 #define RSPI_RESET_NUM 2 78 79 80 + #define RSPI_MAX_SPEED_HZ 50000000 81 + 79 82 struct rzv2h_rspi_best_clock { 80 83 struct clk *clk; 81 84 unsigned long clk_rate; ··· 88 87 }; 89 88 90 89 struct rzv2h_rspi_info { 91 - void (*find_tclk_rate)(struct clk *clk, u32 hz, u8 spr_min, u8 spr_max, 90 + void (*find_tclk_rate)(struct clk *clk, u32 hz, 92 91 struct rzv2h_rspi_best_clock *best_clk); 93 - void (*find_pclk_rate)(struct clk *clk, u32 hz, u8 spr_low, u8 spr_high, 92 + void (*find_pclk_rate)(struct clk *clk, u32 hz, 94 93 struct rzv2h_rspi_best_clock *best_clk); 95 94 const char *tclk_name; 96 95 unsigned int fifo_size; ··· 413 412 } 414 413 415 414 static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz, 416 - u8 spr_min, u8 spr_max, 417 415 struct rzv2h_rspi_best_clock *best) 418 416 { 419 417 long clk_rate, clk_min_rate, clk_max_rate; ··· 463 463 * minimum SPR that is in the valid range. 464 464 */ 465 465 min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1; 466 - if (min_rate_spr > spr_max) 466 + if (min_rate_spr > RSPI_SPBR_SPR_MAX) 467 467 continue; 468 468 469 469 /* ··· 473 473 * maximum SPR that is in the valid range. 474 474 */ 475 475 max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1; 476 - if (max_rate_spr < spr_min) 476 + if (max_rate_spr < RSPI_SPBR_SPR_MIN) 477 477 break; 478 478 479 - if (min_rate_spr < spr_min) 480 - min_rate_spr = spr_min; 479 + if (min_rate_spr < RSPI_SPBR_SPR_MIN) 480 + min_rate_spr = RSPI_SPBR_SPR_MIN; 481 481 482 - if (max_rate_spr > spr_max) 483 - max_rate_spr = spr_max; 482 + if (max_rate_spr > RSPI_SPBR_SPR_MAX) 483 + max_rate_spr = RSPI_SPBR_SPR_MAX; 484 484 485 485 for (spr = min_rate_spr; spr <= max_rate_spr; spr++) { 486 486 clk_rate = (spr + 1) * rate_div; ··· 511 511 } 512 512 513 513 static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz, 514 - u8 spr_min, u8 spr_max, 515 514 struct rzv2h_rspi_best_clock *best) 516 515 { 517 516 unsigned long clk_rate; ··· 532 533 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) { 533 534 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1))); 534 535 spr--; 535 - if (spr >= spr_min && spr <= spr_max) 536 + /* 537 + * Skip SPR=0 and BRDV=0 as it is not a valid combination: 538 + * - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is 539 + * fixed at 200MHz and SPR=0 and BRDV=0 results in the maximum 540 + * bit rate of 100Mbps which is prohibited. 541 + * - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as 542 + * the clock source, SPR=0 and BRDV=0 is explicitly listed 543 + * as unsupported in the hardware manual (Table 36.7). 544 + */ 545 + if (!spr && !brdv) 546 + continue; 547 + if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX) 536 548 goto clock_found; 537 549 } 538 550 ··· 573 563 }; 574 564 int ret; 575 565 576 - rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, 577 - RSPI_SPBR_SPR_MAX, &best_clock); 566 + rspi->info->find_tclk_rate(rspi->tclk, hz, &best_clock); 578 567 579 - /* 580 - * T2H and N2H can also use PCLK as a source, which is 125MHz, but not 581 - * when both SPR and BRDV are 0. 582 - */ 583 568 if (best_clock.error && rspi->info->find_pclk_rate) 584 - rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_PCLK_MIN, 585 - RSPI_SPBR_SPR_MAX, &best_clock); 569 + rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock); 586 570 587 571 if (!best_clock.clk_rate) 588 572 return -EINVAL; ··· 775 771 RSPI_SPBR_SPR_MAX, 776 772 RSPI_SPCMD_BRDV_MAX); 777 773 778 - tclk_rate = clk_round_rate(rspi->tclk, ULONG_MAX); 779 - if (tclk_rate < 0) 780 - return tclk_rate; 781 - 782 - controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate, 783 - RSPI_SPBR_SPR_MIN, 784 - RSPI_SPCMD_BRDV_MIN); 774 + controller->max_speed_hz = RSPI_MAX_SPEED_HZ; 785 775 786 776 controller->dma_tx = devm_dma_request_chan(dev, "tx"); 787 777 if (IS_ERR(controller->dma_tx)) { ··· 809 811 .num_clks = 3, 810 812 }; 811 813 814 + static const struct rzv2h_rspi_info rzg3l_info = { 815 + .find_tclk_rate = rzv2h_rspi_find_rate_fixed, 816 + .tclk_name = "tclk", 817 + .fifo_size = 16, 818 + .num_clks = 2, 819 + }; 820 + 812 821 static const struct rzv2h_rspi_info rzt2h_info = { 813 822 .find_tclk_rate = rzv2h_rspi_find_rate_variable, 814 823 .find_pclk_rate = rzv2h_rspi_find_rate_fixed, ··· 825 820 }; 826 821 827 822 static const struct of_device_id rzv2h_rspi_match[] = { 823 + { .compatible = "renesas,r9a08g046-rspi", &rzg3l_info }, 828 824 { .compatible = "renesas,r9a09g057-rspi", &rzv2h_info }, 829 825 { .compatible = "renesas,r9a09g077-rspi", &rzt2h_info }, 830 826 { /* sentinel */ }

+3 -6

drivers/spi/spi-s3c64xx.c

··· 1369 1369 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1370 1370 sdd->regs + S3C64XX_SPI_INT_EN); 1371 1371 1372 - ret = devm_spi_register_controller(&pdev->dev, host); 1372 + ret = spi_register_controller(host); 1373 1373 if (ret != 0) { 1374 1374 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret); 1375 1375 goto err_pm_put; ··· 1399 1399 1400 1400 pm_runtime_get_sync(&pdev->dev); 1401 1401 1402 - writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1402 + spi_unregister_controller(host); 1403 1403 1404 - if (!is_polling(sdd)) { 1405 - dma_release_channel(sdd->rx_dma.ch); 1406 - dma_release_channel(sdd->tx_dma.ch); 1407 - } 1404 + writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1408 1405 1409 1406 pm_runtime_put_noidle(&pdev->dev); 1410 1407 pm_runtime_disable(&pdev->dev);

+8 -2

drivers/spi/spi-sh-hspi.c

··· 257 257 ctlr->transfer_one_message = hspi_transfer_one_message; 258 258 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 259 259 260 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 260 + ret = spi_register_controller(ctlr); 261 261 if (ret < 0) { 262 - dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 262 + dev_err(&pdev->dev, "failed to register controller\n"); 263 263 goto error2; 264 264 } 265 265 ··· 279 279 { 280 280 struct hspi_priv *hspi = platform_get_drvdata(pdev); 281 281 282 + spi_controller_get(hspi->ctlr); 283 + 284 + spi_unregister_controller(hspi->ctlr); 285 + 282 286 pm_runtime_disable(&pdev->dev); 283 287 284 288 clk_put(hspi->clk); 289 + 290 + spi_controller_put(hspi->ctlr); 285 291 } 286 292 287 293 static const struct of_device_id hspi_of_match[] = {

+8 -2

drivers/spi/spi-sh-msiof.c

··· 1289 1289 if (ret < 0) 1290 1290 dev_warn(dev, "DMA not available, using PIO\n"); 1291 1291 1292 - ret = devm_spi_register_controller(dev, ctlr); 1292 + ret = spi_register_controller(ctlr); 1293 1293 if (ret < 0) { 1294 - dev_err(dev, "devm_spi_register_controller error.\n"); 1294 + dev_err(dev, "failed to register controller\n"); 1295 1295 goto err2; 1296 1296 } 1297 1297 ··· 1309 1309 { 1310 1310 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1311 1311 1312 + spi_controller_get(p->ctlr); 1313 + 1314 + spi_unregister_controller(p->ctlr); 1315 + 1312 1316 sh_msiof_release_dma(p); 1313 1317 pm_runtime_disable(&pdev->dev); 1318 + 1319 + spi_controller_put(p->ctlr); 1314 1320 } 1315 1321 1316 1322 static const struct platform_device_id spi_driver_ids[] = {

+13 -16

drivers/spi/spi-sifive.c

··· 312 312 goto put_host; 313 313 } 314 314 315 - spi->clk = devm_clk_get(&pdev->dev, NULL); 315 + /* Spin up the bus clock before hitting registers */ 316 + spi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 316 317 if (IS_ERR(spi->clk)) { 317 318 dev_err(&pdev->dev, "Unable to find bus clock\n"); 318 319 ret = PTR_ERR(spi->clk); ··· 343 342 goto put_host; 344 343 } 345 344 346 - /* Spin up the bus clock before hitting registers */ 347 - ret = clk_prepare_enable(spi->clk); 348 - if (ret) { 349 - dev_err(&pdev->dev, "Unable to enable bus clock\n"); 350 - goto put_host; 351 - } 352 - 353 345 /* probe the number of CS lines */ 354 346 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); 355 347 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU); ··· 351 357 if (!cs_bits) { 352 358 dev_err(&pdev->dev, "Could not auto probe CS lines\n"); 353 359 ret = -EINVAL; 354 - goto disable_clk; 360 + goto put_host; 355 361 } 356 362 357 363 num_cs = ilog2(cs_bits) + 1; 358 364 if (num_cs > SIFIVE_SPI_MAX_CS) { 359 365 dev_err(&pdev->dev, "Invalid number of spi targets\n"); 360 366 ret = -EINVAL; 361 - goto disable_clk; 367 + goto put_host; 362 368 } 363 369 364 370 /* Define our host */ ··· 386 392 dev_name(&pdev->dev), spi); 387 393 if (ret) { 388 394 dev_err(&pdev->dev, "Unable to bind to interrupt\n"); 389 - goto disable_clk; 395 + goto put_host; 390 396 } 391 397 392 398 dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n", 393 399 irq, host->num_chipselect); 394 400 395 - ret = devm_spi_register_controller(&pdev->dev, host); 401 + ret = spi_register_controller(host); 396 402 if (ret < 0) { 397 403 dev_err(&pdev->dev, "spi_register_host failed\n"); 398 - goto disable_clk; 404 + goto put_host; 399 405 } 400 406 401 407 return 0; 402 408 403 - disable_clk: 404 - clk_disable_unprepare(spi->clk); 405 409 put_host: 406 410 spi_controller_put(host); 407 411 ··· 411 419 struct spi_controller *host = platform_get_drvdata(pdev); 412 420 struct sifive_spi *spi = spi_controller_get_devdata(host); 413 421 422 + spi_controller_get(host); 423 + 424 + spi_unregister_controller(host); 425 + 414 426 /* Disable all the interrupts just in case */ 415 427 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0); 416 - clk_disable_unprepare(spi->clk); 428 + 429 + spi_controller_put(host); 417 430 } 418 431 419 432 static int sifive_spi_suspend(struct device *dev)

+9 -1

drivers/spi/spi-slave-mt27xx.c

··· 453 453 454 454 pm_runtime_enable(&pdev->dev); 455 455 456 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 456 + ret = spi_register_controller(ctlr); 457 457 clk_disable_unprepare(mdata->spi_clk); 458 458 if (ret) { 459 459 dev_err(&pdev->dev, ··· 473 473 474 474 static void mtk_spi_slave_remove(struct platform_device *pdev) 475 475 { 476 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 477 + 478 + spi_controller_get(ctlr); 479 + 480 + spi_unregister_controller(ctlr); 481 + 476 482 pm_runtime_disable(&pdev->dev); 483 + 484 + spi_controller_put(ctlr); 477 485 } 478 486 479 487 #ifdef CONFIG_PM_SLEEP

+1 -1

drivers/spi/spi-sn-f-ospi.c

··· 625 625 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 626 626 if (num_cs > OSPI_NUM_CS) { 627 627 dev_err(dev, "num-cs too large: %d\n", num_cs); 628 - return -ENOMEM; 628 + return -EINVAL; 629 629 } 630 630 ctlr->num_chipselect = num_cs; 631 631

+6 -2

drivers/spi/spi-sprd.c

··· 977 977 goto err_rpm_put; 978 978 } 979 979 980 - ret = devm_spi_register_controller(&pdev->dev, sctlr); 980 + ret = spi_register_controller(sctlr); 981 981 if (ret) 982 982 goto err_rpm_put; 983 983 ··· 1008 1008 if (ret < 0) 1009 1009 dev_err(ss->dev, "failed to resume SPI controller\n"); 1010 1010 1011 - spi_controller_suspend(sctlr); 1011 + spi_controller_get(sctlr); 1012 + 1013 + spi_unregister_controller(sctlr); 1012 1014 1013 1015 if (ret >= 0) { 1014 1016 if (ss->dma.enable) ··· 1019 1017 } 1020 1018 pm_runtime_put_noidle(&pdev->dev); 1021 1019 pm_runtime_disable(&pdev->dev); 1020 + 1021 + spi_controller_put(sctlr); 1022 1022 } 1023 1023 1024 1024 static int __maybe_unused sprd_spi_runtime_suspend(struct device *dev)

+7 -1

drivers/spi/spi-st-ssc4.c

··· 349 349 350 350 platform_set_drvdata(pdev, host); 351 351 352 - ret = devm_spi_register_controller(&pdev->dev, host); 352 + ret = spi_register_controller(host); 353 353 if (ret) { 354 354 dev_err(&pdev->dev, "Failed to register host\n"); 355 355 goto rpm_disable; ··· 371 371 struct spi_controller *host = platform_get_drvdata(pdev); 372 372 struct spi_st *spi_st = spi_controller_get_devdata(host); 373 373 374 + spi_controller_get(host); 375 + 376 + spi_unregister_controller(host); 377 + 374 378 pm_runtime_disable(&pdev->dev); 375 379 376 380 clk_disable_unprepare(spi_st->clk); 381 + 382 + spi_controller_put(host); 377 383 378 384 pinctrl_pm_select_sleep_state(&pdev->dev); 379 385 }

-5

drivers/spi/spi-stm32-ospi.c

··· 469 469 int timeout, err = 0, err_poll_status = 0; 470 470 u8 cs = spi->chip_select[ffs(spi->cs_index_mask) - 1]; 471 471 472 - dev_dbg(ospi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", 473 - op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 474 - op->dummy.buswidth, op->data.buswidth, 475 - op->addr.val, op->data.nbytes); 476 - 477 472 cr = readl_relaxed(ospi->regs_base + OSPI_CR); 478 473 cr &= ~CR_CSSEL; 479 474 cr |= FIELD_PREP(CR_CSSEL, cs);

+22 -50

drivers/spi/spi-stm32.c

··· 1659 1659 ret = stm32_spi_prepare_rx_dma_mdma_chaining(spi, xfer, &rx_dma_conf, 1660 1660 &rx_dma_desc, &rx_mdma_desc); 1661 1661 if (ret) { /* RX DMA MDMA chaining not possible, fallback to DMA only */ 1662 - rx_dma_conf.peripheral_config = 0; 1662 + rx_dma_conf.peripheral_config = NULL; 1663 1663 rx_dma_desc = NULL; 1664 1664 } 1665 1665 } ··· 2360 2360 int ret; 2361 2361 2362 2362 cfg = of_device_get_match_data(&pdev->dev); 2363 - if (!cfg) { 2364 - dev_err(&pdev->dev, "Failed to get match data for platform\n"); 2365 - return -ENODEV; 2366 - } 2363 + if (!cfg) 2364 + return dev_err_probe(&pdev->dev, -ENODEV, 2365 + "Failed to get match data for platform\n"); 2367 2366 2368 2367 device_mode = of_property_read_bool(np, "spi-slave"); 2369 - if (!cfg->has_device_mode && device_mode) { 2370 - dev_err(&pdev->dev, "spi-slave not supported\n"); 2371 - return -EPERM; 2372 - } 2368 + if (!cfg->has_device_mode && device_mode) 2369 + return dev_err_probe(&pdev->dev, -EPERM, "spi-slave not supported\n"); 2373 2370 2374 2371 if (device_mode) 2375 2372 ctrl = devm_spi_alloc_target(&pdev->dev, sizeof(struct stm32_spi)); 2376 2373 else 2377 2374 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(struct stm32_spi)); 2378 - if (!ctrl) { 2379 - dev_err(&pdev->dev, "spi controller allocation failed\n"); 2380 - return -ENOMEM; 2381 - } 2375 + if (!ctrl) 2376 + return dev_err_probe(&pdev->dev, -ENOMEM, "spi controller allocation failed\n"); 2382 2377 platform_set_drvdata(pdev, ctrl); 2383 2378 2384 2379 spi = spi_controller_get_devdata(ctrl); ··· 2404 2409 return ret; 2405 2410 } 2406 2411 2407 - spi->clk = devm_clk_get(&pdev->dev, NULL); 2408 - if (IS_ERR(spi->clk)) { 2409 - ret = PTR_ERR(spi->clk); 2410 - dev_err(&pdev->dev, "clk get failed: %d\n", ret); 2411 - return ret; 2412 - } 2412 + spi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 2413 + if (IS_ERR(spi->clk)) 2414 + return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), "clk enabled failed\n"); 2413 2415 2414 - ret = clk_prepare_enable(spi->clk); 2415 - if (ret) { 2416 - dev_err(&pdev->dev, "clk enable failed: %d\n", ret); 2417 - return ret; 2418 - } 2419 2416 spi->clk_rate = clk_get_rate(spi->clk); 2420 - if (!spi->clk_rate) { 2421 - dev_err(&pdev->dev, "clk rate = 0\n"); 2422 - ret = -EINVAL; 2423 - goto err_clk_disable; 2424 - } 2417 + if (!spi->clk_rate) 2418 + return dev_err_probe(&pdev->dev, -EINVAL, "clk rate = 0\n"); 2425 2419 2426 2420 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2427 2421 if (rst) { 2428 - if (IS_ERR(rst)) { 2429 - ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), 2430 - "failed to get reset\n"); 2431 - goto err_clk_disable; 2432 - } 2422 + if (IS_ERR(rst)) 2423 + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get reset\n"); 2433 2424 2434 2425 reset_control_assert(rst); 2435 2426 udelay(2); ··· 2442 2461 dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max); 2443 2462 2444 2463 ret = spi->cfg->config(spi); 2445 - if (ret) { 2446 - dev_err(&pdev->dev, "controller configuration failed: %d\n", 2447 - ret); 2448 - goto err_clk_disable; 2449 - } 2464 + if (ret) 2465 + return dev_err_probe(&pdev->dev, ret, "controller configuration failed: %d\n", ret); 2450 2466 2451 2467 ctrl->auto_runtime_pm = true; 2452 2468 ctrl->bus_num = pdev->id; ··· 2468 2490 dev_info(&pdev->dev, "tx dma disabled\n"); 2469 2491 spi->dma_tx = NULL; 2470 2492 } else { 2471 - dev_err_probe(&pdev->dev, ret, "failed to request tx dma channel\n"); 2472 - goto err_clk_disable; 2493 + return dev_err_probe(&pdev->dev, ret, "failed to request tx dma channel\n"); 2473 2494 } 2474 2495 } else { 2475 2496 ctrl->dma_tx = spi->dma_tx; ··· 2482 2505 spi->dma_rx = NULL; 2483 2506 } else { 2484 2507 dev_err_probe(&pdev->dev, ret, "failed to request rx dma channel\n"); 2485 - goto err_dma_release; 2508 + goto err_dma_tx_release; 2486 2509 } 2487 2510 } else { 2488 2511 ctrl->dma_rx = spi->dma_rx; ··· 2551 2574 if (spi->sram_pool) 2552 2575 gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf, 2553 2576 spi->sram_rx_buf_size); 2554 - err_dma_release: 2555 - if (spi->dma_tx) 2556 - dma_release_channel(spi->dma_tx); 2557 2577 if (spi->dma_rx) 2558 2578 dma_release_channel(spi->dma_rx); 2559 - err_clk_disable: 2560 - clk_disable_unprepare(spi->clk); 2579 + err_dma_tx_release: 2580 + if (spi->dma_tx) 2581 + dma_release_channel(spi->dma_tx); 2561 2582 2562 2583 return ret; 2563 2584 } ··· 2584 2609 if (spi->sram_rx_buf) 2585 2610 gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf, 2586 2611 spi->sram_rx_buf_size); 2587 - 2588 - clk_disable_unprepare(spi->clk); 2589 - 2590 2612 2591 2613 pinctrl_pm_select_sleep_state(&pdev->dev); 2592 2614 }

+9 -1

drivers/spi/spi-sun4i.c

··· 504 504 pm_runtime_enable(&pdev->dev); 505 505 pm_runtime_idle(&pdev->dev); 506 506 507 - ret = devm_spi_register_controller(&pdev->dev, host); 507 + ret = spi_register_controller(host); 508 508 if (ret) { 509 509 dev_err(&pdev->dev, "cannot register SPI host\n"); 510 510 goto err_pm_disable; ··· 522 522 523 523 static void sun4i_spi_remove(struct platform_device *pdev) 524 524 { 525 + struct spi_controller *host = platform_get_drvdata(pdev); 526 + 527 + spi_controller_get(host); 528 + 529 + spi_unregister_controller(host); 530 + 525 531 pm_runtime_force_suspend(&pdev->dev); 532 + 533 + spi_controller_put(host); 526 534 } 527 535 528 536 static const struct of_device_id sun4i_spi_match[] = {

+7 -1

drivers/spi/spi-sun6i.c

··· 742 742 pm_runtime_set_active(&pdev->dev); 743 743 pm_runtime_enable(&pdev->dev); 744 744 745 - ret = devm_spi_register_controller(&pdev->dev, host); 745 + ret = spi_register_controller(host); 746 746 if (ret) { 747 747 dev_err(&pdev->dev, "cannot register SPI host\n"); 748 748 goto err_pm_disable; ··· 768 768 { 769 769 struct spi_controller *host = platform_get_drvdata(pdev); 770 770 771 + spi_controller_get(host); 772 + 773 + spi_unregister_controller(host); 774 + 771 775 pm_runtime_force_suspend(&pdev->dev); 772 776 773 777 if (host->dma_tx) 774 778 dma_release_channel(host->dma_tx); 775 779 if (host->dma_rx) 776 780 dma_release_channel(host->dma_rx); 781 + 782 + spi_controller_put(host); 777 783 } 778 784 779 785 static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = {

+1 -14

drivers/spi/spi-sunplus-sp7021.c

··· 389 389 return ret; 390 390 } 391 391 392 - static void sp7021_spi_disable_unprepare(void *data) 393 - { 394 - clk_disable_unprepare(data); 395 - } 396 - 397 392 static void sp7021_spi_reset_control_assert(void *data) 398 393 { 399 394 reset_control_assert(data); ··· 455 460 if (pspim->s_irq < 0) 456 461 return pspim->s_irq; 457 462 458 - pspim->spi_clk = devm_clk_get(dev, NULL); 463 + pspim->spi_clk = devm_clk_get_enabled(dev, NULL); 459 464 if (IS_ERR(pspim->spi_clk)) 460 465 return dev_err_probe(dev, PTR_ERR(pspim->spi_clk), "clk get fail\n"); 461 466 462 467 pspim->rstc = devm_reset_control_get_exclusive(dev, NULL); 463 468 if (IS_ERR(pspim->rstc)) 464 469 return dev_err_probe(dev, PTR_ERR(pspim->rstc), "rst get fail\n"); 465 - 466 - ret = clk_prepare_enable(pspim->spi_clk); 467 - if (ret) 468 - return dev_err_probe(dev, ret, "failed to enable clk\n"); 469 - 470 - ret = devm_add_action_or_reset(dev, sp7021_spi_disable_unprepare, pspim->spi_clk); 471 - if (ret) 472 - return ret; 473 470 474 471 ret = reset_control_deassert(pspim->rstc); 475 472 if (ret)

+7 -1

drivers/spi/spi-synquacer.c

··· 716 716 pm_runtime_set_active(sspi->dev); 717 717 pm_runtime_enable(sspi->dev); 718 718 719 - ret = devm_spi_register_controller(sspi->dev, host); 719 + ret = spi_register_controller(host); 720 720 if (ret) 721 721 goto disable_pm; 722 722 ··· 737 737 struct spi_controller *host = platform_get_drvdata(pdev); 738 738 struct synquacer_spi *sspi = spi_controller_get_devdata(host); 739 739 740 + spi_controller_get(host); 741 + 742 + spi_unregister_controller(host); 743 + 740 744 pm_runtime_disable(sspi->dev); 741 745 742 746 clk_disable_unprepare(sspi->clk); 747 + 748 + spi_controller_put(host); 743 749 } 744 750 745 751 static int __maybe_unused synquacer_spi_suspend(struct device *dev)

+7 -1

drivers/spi/spi-tegra114.c

··· 1415 1415 goto exit_pm_disable; 1416 1416 } 1417 1417 1418 - ret = devm_spi_register_controller(&pdev->dev, host); 1418 + ret = spi_register_controller(host); 1419 1419 if (ret < 0) { 1420 1420 dev_err(&pdev->dev, "can not register to host err %d\n", ret); 1421 1421 goto exit_free_irq; ··· 1441 1441 struct spi_controller *host = platform_get_drvdata(pdev); 1442 1442 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1443 1443 1444 + spi_controller_get(host); 1445 + 1446 + spi_unregister_controller(host); 1447 + 1444 1448 free_irq(tspi->irq, tspi); 1445 1449 1446 1450 if (tspi->tx_dma_chan) ··· 1456 1452 pm_runtime_disable(&pdev->dev); 1457 1453 if (!pm_runtime_status_suspended(&pdev->dev)) 1458 1454 tegra_spi_runtime_suspend(&pdev->dev); 1455 + 1456 + spi_controller_put(host); 1459 1457 } 1460 1458 1461 1459 #ifdef CONFIG_PM_SLEEP

+7 -1

drivers/spi/spi-tegra20-sflash.c

··· 505 505 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 506 506 pm_runtime_put(&pdev->dev); 507 507 508 - ret = devm_spi_register_controller(&pdev->dev, host); 508 + ret = spi_register_controller(host); 509 509 if (ret < 0) { 510 510 dev_err(&pdev->dev, "can not register to host err %d\n", ret); 511 511 goto exit_pm_disable; ··· 528 528 struct spi_controller *host = platform_get_drvdata(pdev); 529 529 struct tegra_sflash_data *tsd = spi_controller_get_devdata(host); 530 530 531 + spi_controller_get(host); 532 + 533 + spi_unregister_controller(host); 534 + 531 535 free_irq(tsd->irq, tsd); 532 536 533 537 pm_runtime_disable(&pdev->dev); 534 538 if (!pm_runtime_status_suspended(&pdev->dev)) 535 539 tegra_sflash_runtime_suspend(&pdev->dev); 540 + 541 + spi_controller_put(host); 536 542 } 537 543 538 544 #ifdef CONFIG_PM_SLEEP

+10 -16

drivers/spi/spi-tegra20-slink.c

··· 1007 1007 1008 1008 cdata = of_device_get_match_data(&pdev->dev); 1009 1009 1010 - host = spi_alloc_host(&pdev->dev, sizeof(*tspi)); 1010 + host = devm_spi_alloc_host(&pdev->dev, sizeof(*tspi)); 1011 1011 if (!host) { 1012 1012 dev_err(&pdev->dev, "host allocation failed\n"); 1013 1013 return -ENOMEM; ··· 1034 1034 host->max_speed_hz = 25000000; /* 25MHz */ 1035 1035 1036 1036 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 1037 - if (IS_ERR(tspi->base)) { 1038 - ret = PTR_ERR(tspi->base); 1039 - goto exit_free_host; 1040 - } 1037 + if (IS_ERR(tspi->base)) 1038 + return PTR_ERR(tspi->base); 1039 + 1041 1040 tspi->phys = r->start; 1042 1041 1043 1042 /* disabled clock may cause interrupt storm upon request */ 1044 1043 tspi->clk = devm_clk_get(&pdev->dev, NULL); 1045 1044 if (IS_ERR(tspi->clk)) { 1046 1045 ret = PTR_ERR(tspi->clk); 1047 - dev_err(&pdev->dev, "Can not get clock %d\n", ret); 1048 - goto exit_free_host; 1046 + return dev_err_probe(&pdev->dev, ret, "Can not get clock\n"); 1049 1047 } 1050 1048 1051 1049 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1052 1050 if (IS_ERR(tspi->rst)) { 1053 - dev_err(&pdev->dev, "can not get reset\n"); 1054 1051 ret = PTR_ERR(tspi->rst); 1055 - goto exit_free_host; 1052 + return dev_err_probe(&pdev->dev, ret, "can not get reset\n"); 1056 1053 } 1057 1054 1058 1055 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1059 1056 if (ret) 1060 - goto exit_free_host; 1057 + return ret; 1061 1058 1062 1059 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1063 1060 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1064 1061 1065 1062 ret = tegra_slink_init_dma_param(tspi, true); 1066 1063 if (ret < 0) 1067 - goto exit_free_host; 1064 + return ret; 1068 1065 ret = tegra_slink_init_dma_param(tspi, false); 1069 1066 if (ret < 0) 1070 1067 goto exit_rx_dma_free; ··· 1122 1125 tegra_slink_deinit_dma_param(tspi, false); 1123 1126 exit_rx_dma_free: 1124 1127 tegra_slink_deinit_dma_param(tspi, true); 1125 - exit_free_host: 1126 - spi_controller_put(host); 1128 + 1127 1129 return ret; 1128 1130 } 1129 1131 1130 1132 static void tegra_slink_remove(struct platform_device *pdev) 1131 1133 { 1132 - struct spi_controller *host = spi_controller_get(platform_get_drvdata(pdev)); 1134 + struct spi_controller *host = platform_get_drvdata(pdev); 1133 1135 struct tegra_slink_data *tspi = spi_controller_get_devdata(host); 1134 1136 1135 1137 spi_unregister_controller(host); ··· 1142 1146 1143 1147 if (tspi->rx_dma_chan) 1144 1148 tegra_slink_deinit_dma_param(tspi, true); 1145 - 1146 - spi_controller_put(host); 1147 1149 } 1148 1150 1149 1151 #ifdef CONFIG_PM_SLEEP

+17 -5

drivers/spi/spi-tegra210-quad.c

··· 1000 1000 1001 1001 spin_unlock_irqrestore(&tqspi->lock, flags); 1002 1002 1003 - pm_runtime_put(tqspi->dev); 1003 + pm_runtime_put_autosuspend(tqspi->dev); 1004 1004 1005 1005 return 0; 1006 1006 } ··· 1223 1223 (&tqspi->xfer_completion, 1224 1224 QSPI_DMA_TIMEOUT); 1225 1225 1226 - if (WARN_ON_ONCE(ret == 0)) { 1226 + if (ret == 0) { 1227 1227 /* 1228 1228 * Check if hardware completed the transfer 1229 1229 * even though interrupt was lost or delayed. ··· 1232 1232 ret = tegra_qspi_handle_timeout(tqspi); 1233 1233 if (ret < 0) { 1234 1234 /* Real timeout - clean up and fail */ 1235 + WARN_ON_ONCE(1); 1235 1236 dev_err(tqspi->dev, "transfer timeout\n"); 1236 1237 1237 1238 /* Abort transfer by resetting pio/dma bit */ ··· 1341 1340 1342 1341 ret = wait_for_completion_timeout(&tqspi->xfer_completion, 1343 1342 QSPI_DMA_TIMEOUT); 1344 - if (WARN_ON(ret == 0)) { 1343 + if (ret == 0) { 1345 1344 /* 1346 1345 * Check if hardware completed the transfer even though 1347 1346 * interrupt was lost or delayed. If so, process the ··· 1350 1349 ret = tegra_qspi_handle_timeout(tqspi); 1351 1350 if (ret < 0) { 1352 1351 /* Real timeout - clean up and fail */ 1352 + WARN_ON(1); 1353 1353 dev_err(tqspi->dev, "transfer timeout\n"); 1354 1354 1355 1355 if (tqspi->is_curr_dma_xfer) ··· 1767 1765 init_completion(&tqspi->rx_dma_complete); 1768 1766 init_completion(&tqspi->xfer_completion); 1769 1767 1768 + /* 1769 + * Set autosuspend delay to 500ms. Testing shows this value eliminates 1770 + * suspend/resume overhead during burst operations while allowing quick 1771 + * suspension during idle. For longer operations, the overhead is negligible. 1772 + */ 1773 + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); 1774 + pm_runtime_use_autosuspend(&pdev->dev); 1775 + 1770 1776 pm_runtime_enable(&pdev->dev); 1771 1777 ret = pm_runtime_resume_and_get(&pdev->dev); 1772 1778 if (ret < 0) { ··· 1791 1781 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2); 1792 1782 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2); 1793 1783 1794 - pm_runtime_put(&pdev->dev); 1784 + pm_runtime_put_autosuspend(&pdev->dev); 1795 1785 1796 1786 ret = request_threaded_irq(tqspi->irq, NULL, 1797 1787 tegra_qspi_isr_thread, IRQF_ONESHOT, ··· 1812 1802 exit_free_irq: 1813 1803 free_irq(qspi_irq, tqspi); 1814 1804 exit_pm_disable: 1805 + pm_runtime_dont_use_autosuspend(&pdev->dev); 1815 1806 pm_runtime_force_suspend(&pdev->dev); 1816 1807 tegra_qspi_deinit_dma(tqspi); 1817 1808 return ret; ··· 1825 1814 1826 1815 spi_unregister_controller(host); 1827 1816 free_irq(tqspi->irq, tqspi); 1817 + pm_runtime_dont_use_autosuspend(&pdev->dev); 1828 1818 pm_runtime_force_suspend(&pdev->dev); 1829 1819 tegra_qspi_deinit_dma(tqspi); 1830 1820 } ··· 1851 1839 1852 1840 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); 1853 1841 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2); 1854 - pm_runtime_put(dev); 1842 + pm_runtime_put_autosuspend(dev); 1855 1843 1856 1844 return spi_controller_resume(host); 1857 1845 }

+6 -8

drivers/spi/spi-ti-qspi.c

··· 888 888 qspi->mmap_enabled = false; 889 889 qspi->current_cs = -1; 890 890 891 - ret = devm_spi_register_controller(&pdev->dev, host); 891 + ret = spi_register_controller(host); 892 892 if (!ret) 893 893 return 0; 894 894 ··· 903 903 static void ti_qspi_remove(struct platform_device *pdev) 904 904 { 905 905 struct ti_qspi *qspi = platform_get_drvdata(pdev); 906 - int rc; 907 906 908 - rc = spi_controller_suspend(qspi->host); 909 - if (rc) { 910 - dev_alert(&pdev->dev, "spi_controller_suspend() failed (%pe)\n", 911 - ERR_PTR(rc)); 912 - return; 913 - } 907 + spi_controller_get(qspi->host); 908 + 909 + spi_unregister_controller(qspi->host); 914 910 915 911 pm_runtime_put_sync(&pdev->dev); 916 912 pm_runtime_disable(&pdev->dev); 917 913 918 914 ti_qspi_dma_cleanup(qspi); 915 + 916 + spi_controller_put(qspi->host); 919 917 } 920 918 921 919 static const struct dev_pm_ops ti_qspi_pm_ops = {

+10 -14

drivers/spi/spi-uniphier.c

··· 666 666 } 667 667 priv->base_dma_addr = res->start; 668 668 669 - priv->clk = devm_clk_get(&pdev->dev, NULL); 669 + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); 670 670 if (IS_ERR(priv->clk)) { 671 671 dev_err(&pdev->dev, "failed to get clock\n"); 672 672 ret = PTR_ERR(priv->clk); 673 673 goto out_host_put; 674 674 } 675 675 676 - ret = clk_prepare_enable(priv->clk); 677 - if (ret) 678 - goto out_host_put; 679 - 680 676 irq = platform_get_irq(pdev, 0); 681 677 if (irq < 0) { 682 678 ret = irq; 683 - goto out_disable_clk; 679 + goto out_host_put; 684 680 } 685 681 686 682 ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler, 687 683 0, "uniphier-spi", priv); 688 684 if (ret) { 689 685 dev_err(&pdev->dev, "failed to request IRQ\n"); 690 - goto out_disable_clk; 686 + goto out_host_put; 691 687 } 692 688 693 689 init_completion(&priv->xfer_done); ··· 712 716 if (IS_ERR_OR_NULL(host->dma_tx)) { 713 717 if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER) { 714 718 ret = -EPROBE_DEFER; 715 - goto out_disable_clk; 719 + goto out_host_put; 716 720 } 717 721 host->dma_tx = NULL; 718 722 dma_tx_burst = INT_MAX; ··· 746 750 747 751 host->max_dma_len = min(dma_tx_burst, dma_rx_burst); 748 752 749 - ret = devm_spi_register_controller(&pdev->dev, host); 753 + ret = spi_register_controller(host); 750 754 if (ret) 751 755 goto out_release_dma; 752 756 ··· 762 766 host->dma_tx = NULL; 763 767 } 764 768 765 - out_disable_clk: 766 - clk_disable_unprepare(priv->clk); 767 - 768 769 out_host_put: 769 770 spi_controller_put(host); 770 771 return ret; ··· 770 777 static void uniphier_spi_remove(struct platform_device *pdev) 771 778 { 772 779 struct spi_controller *host = platform_get_drvdata(pdev); 773 - struct uniphier_spi_priv *priv = spi_controller_get_devdata(host); 780 + 781 + spi_controller_get(host); 782 + 783 + spi_unregister_controller(host); 774 784 775 785 if (host->dma_tx) 776 786 dma_release_channel(host->dma_tx); 777 787 if (host->dma_rx) 778 788 dma_release_channel(host->dma_rx); 779 789 780 - clk_disable_unprepare(priv->clk); 790 + spi_controller_put(host); 781 791 } 782 792 783 793 static const struct of_device_id uniphier_spi_match[] = {

+11 -4

drivers/spi/spi-zynq-qspi.c

··· 643 643 644 644 xqspi = spi_controller_get_devdata(ctlr); 645 645 xqspi->dev = dev; 646 - platform_set_drvdata(pdev, xqspi); 646 + platform_set_drvdata(pdev, ctlr); 647 647 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); 648 648 if (IS_ERR(xqspi->regs)) { 649 649 ret = PTR_ERR(xqspi->regs); ··· 702 702 /* QSPI controller initializations */ 703 703 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect); 704 704 705 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 705 + ret = spi_register_controller(ctlr); 706 706 if (ret) { 707 - dev_err(&pdev->dev, "devm_spi_register_controller failed\n"); 707 + dev_err(&pdev->dev, "failed to register controller\n"); 708 708 goto remove_ctlr; 709 709 } 710 710 ··· 728 728 */ 729 729 static void zynq_qspi_remove(struct platform_device *pdev) 730 730 { 731 - struct zynq_qspi *xqspi = platform_get_drvdata(pdev); 731 + struct spi_controller *ctlr = platform_get_drvdata(pdev); 732 + struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr); 733 + 734 + spi_controller_get(ctlr); 735 + 736 + spi_unregister_controller(ctlr); 732 737 733 738 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); 739 + 740 + spi_controller_put(ctlr); 734 741 } 735 742 736 743 static const struct of_device_id zynq_qspi_of_match[] = {

+3 -1

drivers/spi/spi-zynqmp-gqspi.c

··· 1324 1324 ctlr->dev.of_node = np; 1325 1325 ctlr->auto_runtime_pm = true; 1326 1326 1327 - ret = devm_spi_register_controller(&pdev->dev, ctlr); 1327 + ret = spi_register_controller(ctlr); 1328 1328 if (ret) { 1329 1329 dev_err(&pdev->dev, "spi_register_controller failed\n"); 1330 1330 goto clk_dis_all; ··· 1361 1361 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev); 1362 1362 1363 1363 pm_runtime_get_sync(&pdev->dev); 1364 + 1365 + spi_unregister_controller(xqspi->ctlr); 1364 1366 1365 1367 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 1366 1368

+82 -31

drivers/spi/spi.c

··· 89 89 } 90 90 static DEVICE_ATTR_RW(driver_override); 91 91 92 - static struct spi_statistics __percpu *spi_alloc_pcpu_stats(struct device *dev) 92 + static struct spi_statistics __percpu *spi_alloc_pcpu_stats(void) 93 93 { 94 94 struct spi_statistics __percpu *pcpu_stats; 95 + int cpu; 95 96 96 - if (dev) 97 - pcpu_stats = devm_alloc_percpu(dev, struct spi_statistics); 98 - else 99 - pcpu_stats = alloc_percpu_gfp(struct spi_statistics, GFP_KERNEL); 97 + pcpu_stats = alloc_percpu_gfp(struct spi_statistics, GFP_KERNEL); 98 + if (!pcpu_stats) 99 + return NULL; 100 100 101 - if (pcpu_stats) { 102 - int cpu; 101 + for_each_possible_cpu(cpu) { 102 + struct spi_statistics *stat; 103 103 104 - for_each_possible_cpu(cpu) { 105 - struct spi_statistics *stat; 106 - 107 - stat = per_cpu_ptr(pcpu_stats, cpu); 108 - u64_stats_init(&stat->syncp); 109 - } 104 + stat = per_cpu_ptr(pcpu_stats, cpu); 105 + u64_stats_init(&stat->syncp); 110 106 } 107 + 111 108 return pcpu_stats; 112 109 } 113 110 ··· 566 569 return NULL; 567 570 } 568 571 569 - spi->pcpu_statistics = spi_alloc_pcpu_stats(NULL); 572 + spi->pcpu_statistics = spi_alloc_pcpu_stats(); 570 573 if (!spi->pcpu_statistics) { 571 574 kfree(spi); 572 575 spi_controller_put(ctlr); ··· 633 636 return 0; 634 637 } 635 638 639 + struct spi_dev_check_info { 640 + struct spi_device *new_spi; 641 + struct spi_device *parent; /* set for ancillary devices */ 642 + }; 643 + 636 644 static int spi_dev_check(struct device *dev, void *data) 637 645 { 638 646 struct spi_device *spi = to_spi_device(dev); 639 - struct spi_device *new_spi = data; 647 + struct spi_dev_check_info *info = data; 648 + struct spi_device *new_spi = info->new_spi; 640 649 int status, idx; 650 + 651 + /* 652 + * When registering an ancillary device, skip checking against the 653 + * parent device since the ancillary is intentionally using one of 654 + * the parent's chip selects. 655 + */ 656 + if (info->parent && spi == info->parent) 657 + return 0; 641 658 642 659 if (spi->controller == new_spi->controller) { 643 660 for (idx = 0; idx < spi->num_chipselect; idx++) { ··· 669 658 spi->controller->cleanup(spi); 670 659 } 671 660 672 - static int __spi_add_device(struct spi_device *spi) 661 + static int __spi_add_device(struct spi_device *spi, struct spi_device *parent) 673 662 { 674 663 struct spi_controller *ctlr = spi->controller; 675 664 struct device *dev = ctlr->dev.parent; 665 + struct spi_dev_check_info check_info; 676 666 int status, idx; 677 667 u8 cs; 678 668 ··· 717 705 * chipselect **BEFORE** we call setup(), else we'll trash 718 706 * its configuration. 719 707 */ 720 - status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check); 708 + check_info.new_spi = spi; 709 + check_info.parent = parent; 710 + status = bus_for_each_dev(&spi_bus_type, NULL, &check_info, spi_dev_check); 721 711 if (status) 722 712 return status; 723 713 ··· 781 767 spi_dev_set_name(spi); 782 768 783 769 mutex_lock(&ctlr->add_lock); 784 - status = __spi_add_device(spi); 770 + status = __spi_add_device(spi, NULL); 785 771 mutex_unlock(&ctlr->add_lock); 786 772 return status; 787 773 } ··· 2724 2710 2725 2711 WARN_ON(!mutex_is_locked(&ctlr->add_lock)); 2726 2712 2727 - /* Register the new device */ 2728 - rc = __spi_add_device(ancillary); 2713 + /* Register the new device, passing the parent to skip CS conflict check */ 2714 + rc = __spi_add_device(ancillary, spi); 2729 2715 if (rc) { 2730 2716 dev_err(&spi->dev, "failed to register ancillary device\n"); 2731 2717 goto err_out; ··· 2738 2724 return ERR_PTR(rc); 2739 2725 } 2740 2726 EXPORT_SYMBOL_GPL(spi_new_ancillary_device); 2727 + 2728 + static void devm_spi_unregister_device(void *spi) 2729 + { 2730 + spi_unregister_device(spi); 2731 + } 2732 + 2733 + /** 2734 + * devm_spi_new_ancillary_device() - Register managed ancillary SPI device 2735 + * @spi: Pointer to the main SPI device registering the ancillary device 2736 + * @chip_select: Chip Select of the ancillary device 2737 + * 2738 + * Register an ancillary SPI device; for example some chips have a chip-select 2739 + * for normal device usage and another one for setup/firmware upload. 2740 + * 2741 + * This is the managed version of spi_new_ancillary_device(). The ancillary 2742 + * device will be unregistered automatically when the parent SPI device is 2743 + * unregistered. 2744 + * 2745 + * This may only be called from main SPI device's probe routine. 2746 + * 2747 + * Return: Pointer to new ancillary device on success; ERR_PTR on failure 2748 + */ 2749 + struct spi_device *devm_spi_new_ancillary_device(struct spi_device *spi, 2750 + u8 chip_select) 2751 + { 2752 + struct spi_device *ancillary; 2753 + int ret; 2754 + 2755 + ancillary = spi_new_ancillary_device(spi, chip_select); 2756 + if (IS_ERR(ancillary)) 2757 + return ancillary; 2758 + 2759 + ret = devm_add_action_or_reset(&spi->dev, devm_spi_unregister_device, 2760 + ancillary); 2761 + if (ret) 2762 + return ERR_PTR(ret); 2763 + 2764 + return ancillary; 2765 + } 2766 + EXPORT_SYMBOL_GPL(devm_spi_new_ancillary_device); 2741 2767 2742 2768 #ifdef CONFIG_ACPI 2743 2769 struct acpi_spi_lookup { ··· 3243 3189 if (!ctlr) 3244 3190 return NULL; 3245 3191 3246 - ctlr->pcpu_statistics = spi_alloc_pcpu_stats(NULL); 3192 + ctlr->pcpu_statistics = spi_alloc_pcpu_stats(); 3247 3193 if (!ctlr->pcpu_statistics) { 3248 3194 kfree(ctlr); 3249 3195 return NULL; ··· 3440 3386 * device identification, boards need configuration tables telling which 3441 3387 * chip is at which address. 3442 3388 * 3443 - * This must be called from context that can sleep. It returns zero on 3444 - * success, else a negative error code (dropping the controller's refcount). 3389 + * This must be called from context that can sleep. 3390 + * 3445 3391 * After a successful return, the caller is responsible for calling 3446 3392 * spi_unregister_controller(). 3447 3393 * ··· 3575 3521 * Context: can sleep 3576 3522 * 3577 3523 * Register a SPI device as with spi_register_controller() which will 3578 - * automatically be unregistered and freed. 3524 + * automatically be unregistered (and freed unless it has been allocated using 3525 + * devm_spi_alloc_host/target()). 3579 3526 * 3580 3527 * Return: zero on success, else a negative error code. 3581 3528 */ ··· 3621 3566 * 3622 3567 * This must be called from context that can sleep. 3623 3568 * 3624 - * Note that this function also drops a reference to the controller. 3569 + * Note that this function also drops a reference to the controller unless it 3570 + * has been allocated using devm_spi_alloc_host/target(). 3625 3571 */ 3626 3572 void spi_unregister_controller(struct spi_controller *ctlr) 3627 3573 { ··· 4288 4232 * SPI transfer length should be multiple of SPI word size 4289 4233 * where SPI word size should be power-of-two multiple. 4290 4234 */ 4291 - if (xfer->bits_per_word <= 8) 4292 - w_size = 1; 4293 - else if (xfer->bits_per_word <= 16) 4294 - w_size = 2; 4295 - else 4296 - w_size = 4; 4235 + w_size = spi_bpw_to_bytes(xfer->bits_per_word); 4297 4236 4298 4237 /* No partial transfers accepted */ 4299 4238 if (xfer->len % w_size)

+14 -2

include/linux/spi/spi-mem.h

··· 28 28 .dtr = true, \ 29 29 } 30 30 31 + #define SPI_MEM_DTR_OP_PACKED_CMD(__opcode, __addr, __buswidth) \ 32 + { \ 33 + .nbytes = 2, \ 34 + .opcode = __opcode << 8 | __addr, \ 35 + .buswidth = __buswidth, \ 36 + .dtr = true, \ 37 + } 38 + 31 39 #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ 32 40 { \ 33 41 .nbytes = __nbytes, \ ··· 138 130 139 131 /** 140 132 * struct spi_mem_op - describes a SPI memory operation 133 + * @cmd: the complete command 141 134 * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is 142 135 * sent MSB-first. 143 136 * @cmd.buswidth: number of IO lines used to transmit the command 144 137 * @cmd.opcode: operation opcode 145 138 * @cmd.dtr: whether the command opcode should be sent in DTR mode or not 139 + * @addr: the address attributes 146 140 * @addr.nbytes: number of address bytes to send. Can be zero if the operation 147 141 * does not need to send an address 148 142 * @addr.buswidth: number of IO lines used to transmit the address cycles ··· 153 143 * Note that only @addr.nbytes are taken into account in this 154 144 * address value, so users should make sure the value fits in the 155 145 * assigned number of bytes. 146 + * @dummy: data for dummy operation 156 147 * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can 157 148 * be zero if the operation does not require dummy bytes 158 149 * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes 159 150 * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not 151 + * @data: the data attributes 160 152 * @data.buswidth: number of IO lanes used to send/receive the data 161 153 * @data.dtr: whether the data should be sent in DTR mode or not 162 154 * @data.ecc: whether error correction is required or not ··· 285 273 }; 286 274 287 275 /** 288 - * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem 276 + * spi_mem_set_drvdata() - attach driver private data to a SPI mem 289 277 * device 290 278 * @mem: memory device 291 279 * @data: data to attach to the memory device ··· 296 284 } 297 285 298 286 /** 299 - * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem 287 + * spi_mem_get_drvdata() - get driver private data attached to a SPI mem 300 288 * device 301 289 * @mem: memory device 302 290 *

+1

include/linux/spi/spi.h

··· 382 382 } 383 383 384 384 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 385 + extern struct spi_device *devm_spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 385 386 386 387 /* Use a define to avoid include chaining to get THIS_MODULE */ 387 388 #define spi_register_driver(driver) \

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