Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mfd: rohm-bd96801: Support ROHM BD96802
The ROHM BD96802 PMIC looks from software point of view a lot like ROHM
BD96801 PMIC. Just with reduced number of voltage rails. Both PMICs
provide two physical IRQ lines referred as INTB and ERRB and contain
blocks implementing regulator controls and a weatchdog. Hence it makes
sense to use same MFD core for both PMICs.
Add support for ROHM BD96802 scalable companion PMIC to the BD96801
core driver.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/05957d194425a79a4f35f287695c3d9ca2ed1ae2.1744090658.git.mazziesaccount@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
Matti Vaittinen
and committed by
Lee Jones
4094040b
9cc95754
+311
-5
+234
-5
drivers/mfd/rohm-bd96801.c
+234
-5
drivers/mfd/rohm-bd96801.c
···
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#include <linux/types.h>
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#include <linux/mfd/rohm-bd96801.h>
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#include <linux/mfd/rohm-bd96802.h>
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#include <linux/mfd/rohm-generic.h>
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struct bd968xx {
···
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DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "ldo7-shdn-err"),
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};
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static const struct resource bd96802_reg_errb_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD96802_OTP_ERR_STAT, "otp-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_DBIST_ERR_STAT, "dbist-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_EEP_ERR_STAT, "eep-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_ABIST_ERR_STAT, "abist-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_PRSTB_ERR_STAT, "prstb-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr1"),
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DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr2"),
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DEFINE_RES_IRQ_NAMED(BD96802_SLAVE_ERR_STAT, "slave-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_VREF_ERR_STAT, "vref-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_TSD_ERR_STAT, "tsd"),
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DEFINE_RES_IRQ_NAMED(BD96802_UVLO_ERR_STAT, "uvlo-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_OVLO_ERR_STAT, "ovlo-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_OSC_ERR_STAT, "osc-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_PON_ERR_STAT, "pon-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_POFF_ERR_STAT, "poff-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_CMD_SHDN_ERR_STAT, "cmd-shdn-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_INT_SHDN_ERR_STAT, "int-shdn-err"),
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+
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"),
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+
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"),
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};
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static const struct resource bd96801_reg_intb_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "core-thermal"),
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···
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DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "ldo7-undervolt"),
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};
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static const struct resource bd96802_reg_intb_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD96802_TW_STAT, "core-thermal"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPH_STAT, "buck1-overcurr-h"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPL_STAT, "buck1-overcurr-l"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPN_STAT, "buck1-overcurr-n"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVD_STAT, "buck1-overvolt"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVD_STAT, "buck1-undervolt"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_TW_CH_STAT, "buck1-thermal"),
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+
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPH_STAT, "buck2-overcurr-h"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPL_STAT, "buck2-overcurr-l"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPN_STAT, "buck2-overcurr-n"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVD_STAT, "buck2-overvolt"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVD_STAT, "buck2-undervolt"),
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DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_TW_CH_STAT, "buck2-thermal"),
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};
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enum {
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WDG_CELL = 0,
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REGULATOR_CELL,
···
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static struct mfd_cell bd96801_cells[] = {
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[WDG_CELL] = { .name = "bd96801-wdt", },
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[REGULATOR_CELL] = { .name = "bd96801-regulator", },
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};
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static struct mfd_cell bd96802_cells[] = {
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[WDG_CELL] = { .name = "bd96801-wdt", },
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[REGULATOR_CELL] = { .name = "bd96802-regulator", },
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};
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static const struct regmap_range bd96801_volatile_ranges[] = {
···
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regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG),
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};
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static const struct regmap_access_table volatile_regs = {
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static const struct regmap_range bd96802_volatile_ranges[] = {
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/* Status regs */
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regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT),
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regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK),
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regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS),
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regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_BUCK2_ERRB),
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regmap_reg_range(BD96801_REG_INT_SYS_INTB, BD96801_REG_INT_BUCK2_INTB),
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/* Registers which do not update value unless PMIC is in STBY */
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regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB),
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regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME),
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};
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static const struct regmap_access_table bd96801_volatile_regs = {
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.yes_ranges = bd96801_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
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};
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static const struct regmap_access_table bd96802_volatile_regs = {
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.yes_ranges = bd96802_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(bd96802_volatile_ranges),
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};
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/*
···
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static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */
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static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */
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-
static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = {
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static const struct regmap_irq_sub_irq_map bd96801_errb_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
···
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REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
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};
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static const struct regmap_irq_sub_irq_map bd96802_errb_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
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};
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static const struct regmap_irq bd96801_errb_irqs[] = {
···
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REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK),
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};
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static const struct regmap_irq bd96802_errb_irqs[] = {
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/* Reg 0x52 Fatal ERRB1 */
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REGMAP_IRQ_REG(BD96802_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK),
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/* 0x53 Fatal ERRB2 */
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REGMAP_IRQ_REG(BD96802_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK),
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/* 0x54 Fatal INTB shadowed to ERRB */
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REGMAP_IRQ_REG(BD96802_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK),
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/* Reg 0x55 BUCK1 ERR IRQs */
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REGMAP_IRQ_REG(BD96802_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK),
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/* Reg 0x56 BUCK2 ERR IRQs */
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REGMAP_IRQ_REG(BD96802_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK),
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};
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static const struct regmap_irq bd96801_intb_irqs[] = {
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/* STATUS SYSTEM INTB */
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REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
···
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REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
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};
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static const struct regmap_irq bd96802_intb_irqs[] = {
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/* STATUS SYSTEM INTB */
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REGMAP_IRQ_REG(BD96802_TW_STAT, 0, BD96801_TW_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK),
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/* STATUS BUCK1 INTB */
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REGMAP_IRQ_REG(BD96802_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK),
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/* BUCK 2 INTB */
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REGMAP_IRQ_REG(BD96802_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK),
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REGMAP_IRQ_REG(BD96802_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK),
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};
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/*
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* The IRQ stuff is a bit hairy. The BD96801 / BD96802 provide two physical
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* IRQ lines called INTB and ERRB. They share the same main status register.
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*
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* For ERRB, mapping from main status to sub-status is such that the
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* 'global' faults are mapped to first 3 sub-status registers - and indicated
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* by the first bit[0] in main status reg.
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*
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* Rest of the status registers are for indicating stuff for individual
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* regulators, 1 sub register / regulator and 1 main status register bit /
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* regulator, starting from bit[1].
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*
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* Eg, regulator specific stuff has 1 to 1 mapping from main-status to sub
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* registers but 'global' ERRB IRQs require mapping from main status bit[0] to
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* 3 status registers.
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*
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* Furthermore, the BD96801 has 7 regulators where the BD96802 has only 2.
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*
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* INTB has only 1 sub status register for 'global' events and then own sub
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* status register for each of the regulators. So, for INTB we have direct
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* 1 to 1 mapping - BD96801 just having 5 register and 5 main status bits
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* more than the BD96802.
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*
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* Sharing the main status bits could be a problem if we had both INTB and
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* ERRB IRQs asserted but for different sub-status offsets. This might lead
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* IRQ controller code to go read a sub status register which indicates no
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* active IRQs. I assume this occurring repeteadly might lead the IRQ to be
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* disabled by core as a result of repeteadly returned IRQ_NONEs.
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*
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* I don't consider this as a fatal problem for now because:
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* a) Having ERRB asserted leads to PMIC fault state which will kill
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* the SoC powered by the PMIC. (So, relevant only for potential
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* case of not powering the processor with this PMIC).
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* b) Having ERRB set without having respective INTB is unlikely
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* (haven't actually verified this).
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*
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* So, let's proceed with main status enabled for both INTB and ERRB. We can
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* later disable main-status usage on systems where this ever proves to be
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* a problem.
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*/
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static const struct regmap_irq_chip bd96801_irq_chip_errb = {
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.name = "bd96801-irq-errb",
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.domain_suffix = "errb",
···
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.init_ack_masked = true,
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.num_regs = 10,
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.irq_reg_stride = 1,
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.sub_reg_offsets = &errb_sub_irq_offsets[0],
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.sub_reg_offsets = &bd96801_errb_sub_irq_offsets[0],
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};
340
+
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static const struct regmap_irq_chip bd96802_irq_chip_errb = {
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.name = "bd96802-irq-errb",
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.domain_suffix = "errb",
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.main_status = BD96801_REG_INT_MAIN,
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.num_main_regs = 1,
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.irqs = &bd96802_errb_irqs[0],
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.num_irqs = ARRAY_SIZE(bd96802_errb_irqs),
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.status_base = BD96801_REG_INT_SYS_ERRB1,
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.mask_base = BD96801_REG_MASK_SYS_ERRB,
350
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.ack_base = BD96801_REG_INT_SYS_ERRB1,
351
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.init_ack_masked = true,
352
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.num_regs = 5,
353
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.irq_reg_stride = 1,
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.sub_reg_offsets = &bd96802_errb_sub_irq_offsets[0],
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};
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static const struct regmap_irq_chip bd96801_irq_chip_intb = {
···
542
353
.irq_reg_stride = 1,
543
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};
544
355
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static const struct regmap_irq_chip bd96802_irq_chip_intb = {
357
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.name = "bd96802-irq-intb",
358
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.domain_suffix = "intb",
359
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.main_status = BD96801_REG_INT_MAIN,
360
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.num_main_regs = 1,
361
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.irqs = &bd96802_intb_irqs[0],
362
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.num_irqs = ARRAY_SIZE(bd96802_intb_irqs),
363
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.status_base = BD96801_REG_INT_SYS_INTB,
364
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.mask_base = BD96801_REG_MASK_SYS_INTB,
365
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.ack_base = BD96801_REG_INT_SYS_INTB,
366
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.init_ack_masked = true,
367
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.num_regs = 3,
368
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.irq_reg_stride = 1,
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};
370
+
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static const struct regmap_config bd96801_regmap_config = {
546
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.reg_bits = 8,
547
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.val_bits = 8,
548
-
.volatile_table = &volatile_regs,
374
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.volatile_table = &bd96801_volatile_regs,
375
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.cache_type = REGCACHE_MAPLE,
376
+
};
377
+
378
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static const struct regmap_config bd96802_regmap_config = {
379
+
.reg_bits = 8,
380
+
.val_bits = 8,
381
+
.volatile_table = &bd96802_volatile_regs,
549
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.cache_type = REGCACHE_MAPLE,
550
383
};
551
384
···
581
370
.regmap_config = &bd96801_regmap_config,
582
371
.cells = bd96801_cells,
583
372
.num_cells = ARRAY_SIZE(bd96801_cells),
373
+
.unlock_reg = BD96801_LOCK_REG,
374
+
.unlock_val = BD96801_UNLOCK,
375
+
};
376
+
377
+
static const struct bd968xx bd96802_data = {
378
+
.errb_irqs = bd96802_reg_errb_irqs,
379
+
.intb_irqs = bd96802_reg_intb_irqs,
380
+
.num_errb_irqs = ARRAY_SIZE(bd96802_reg_errb_irqs),
381
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.num_intb_irqs = ARRAY_SIZE(bd96802_reg_intb_irqs),
382
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.errb_irq_chip = &bd96802_irq_chip_errb,
383
+
.intb_irq_chip = &bd96802_irq_chip_intb,
384
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.regmap_config = &bd96802_regmap_config,
385
+
.cells = bd96802_cells,
386
+
.num_cells = ARRAY_SIZE(bd96802_cells),
584
387
.unlock_reg = BD96801_LOCK_REG,
585
388
.unlock_val = BD96801_UNLOCK,
586
389
};
···
617
392
switch (chip_type) {
618
393
case ROHM_CHIP_TYPE_BD96801:
619
394
ddata = &bd96801_data;
395
+
break;
396
+
case ROHM_CHIP_TYPE_BD96802:
397
+
ddata = &bd96802_data;
620
398
break;
621
399
default:
622
400
dev_err(&i2c->dev, "Unknown IC\n");
···
716
488
717
489
static const struct of_device_id bd96801_of_match[] = {
718
490
{ .compatible = "rohm,bd96801", .data = (void *)ROHM_CHIP_TYPE_BD96801 },
491
+
{ .compatible = "rohm,bd96802", .data = (void *)ROHM_CHIP_TYPE_BD96802 },
719
492
{ }
720
493
};
721
494
MODULE_DEVICE_TABLE(of, bd96801_of_match);
···
744
515
module_exit(bd96801_i2c_exit);
745
516
746
517
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
747
-
MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver");
518
+
MODULE_DESCRIPTION("ROHM BD9680X Power Management IC driver");
748
519
MODULE_LICENSE("GPL");
+2
include/linux/mfd/rohm-bd96801.h
+2
include/linux/mfd/rohm-bd96801.h
···
40
40
* INTB status registers are at range 0x5c ... 0x63
41
41
*/
42
42
#define BD96801_REG_INT_SYS_ERRB1 0x52
43
+
#define BD96801_REG_INT_BUCK2_ERRB 0x56
43
44
#define BD96801_REG_INT_SYS_INTB 0x5c
45
+
#define BD96801_REG_INT_BUCK2_INTB 0x5e
44
46
#define BD96801_REG_INT_LDO7_INTB 0x63
45
47
46
48
/* MASK registers */
+74
include/linux/mfd/rohm-bd96802.h
+74
include/linux/mfd/rohm-bd96802.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2025 ROHM Semiconductors
4
+
*
5
+
* The digital interface of trhe BD96802 PMIC is a reduced version of the
6
+
* BD96801. Hence the BD96801 definitions are used for registers and masks
7
+
* while this header only holds the IRQ definitions - mainly to avoid gaps in
8
+
* IRQ numbers caused by the lack of some BUCKs / LDOs and their respective
9
+
* IRQs.
10
+
*/
11
+
12
+
#ifndef __LINUX_MFD_BD96802_H__
13
+
#define __LINUX_MFD_BD96802_H__
14
+
15
+
/* ERRB IRQs */
16
+
enum {
17
+
/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
18
+
BD96802_OTP_ERR_STAT,
19
+
BD96802_DBIST_ERR_STAT,
20
+
BD96802_EEP_ERR_STAT,
21
+
BD96802_ABIST_ERR_STAT,
22
+
BD96802_PRSTB_ERR_STAT,
23
+
BD96802_DRMOS1_ERR_STAT,
24
+
BD96802_DRMOS2_ERR_STAT,
25
+
BD96802_SLAVE_ERR_STAT,
26
+
BD96802_VREF_ERR_STAT,
27
+
BD96802_TSD_ERR_STAT,
28
+
BD96802_UVLO_ERR_STAT,
29
+
BD96802_OVLO_ERR_STAT,
30
+
BD96802_OSC_ERR_STAT,
31
+
BD96802_PON_ERR_STAT,
32
+
BD96802_POFF_ERR_STAT,
33
+
BD96802_CMD_SHDN_ERR_STAT,
34
+
BD96802_INT_SHDN_ERR_STAT,
35
+
36
+
/* Reg 0x55 BUCK1 ERR IRQs */
37
+
BD96802_BUCK1_PVIN_ERR_STAT,
38
+
BD96802_BUCK1_OVP_ERR_STAT,
39
+
BD96802_BUCK1_UVP_ERR_STAT,
40
+
BD96802_BUCK1_SHDN_ERR_STAT,
41
+
42
+
/* Reg 0x56 BUCK2 ERR IRQs */
43
+
BD96802_BUCK2_PVIN_ERR_STAT,
44
+
BD96802_BUCK2_OVP_ERR_STAT,
45
+
BD96802_BUCK2_UVP_ERR_STAT,
46
+
BD96802_BUCK2_SHDN_ERR_STAT,
47
+
};
48
+
49
+
/* INTB IRQs */
50
+
enum {
51
+
/* Reg 0x5c (System INTB) */
52
+
BD96802_TW_STAT,
53
+
BD96802_WDT_ERR_STAT,
54
+
BD96802_I2C_ERR_STAT,
55
+
BD96802_CHIP_IF_ERR_STAT,
56
+
57
+
/* Reg 0x5d (BUCK1 INTB) */
58
+
BD96802_BUCK1_OCPH_STAT,
59
+
BD96802_BUCK1_OCPL_STAT,
60
+
BD96802_BUCK1_OCPN_STAT,
61
+
BD96802_BUCK1_OVD_STAT,
62
+
BD96802_BUCK1_UVD_STAT,
63
+
BD96802_BUCK1_TW_CH_STAT,
64
+
65
+
/* Reg 0x5e (BUCK2 INTB) */
66
+
BD96802_BUCK2_OCPH_STAT,
67
+
BD96802_BUCK2_OCPL_STAT,
68
+
BD96802_BUCK2_OCPN_STAT,
69
+
BD96802_BUCK2_OVD_STAT,
70
+
BD96802_BUCK2_UVD_STAT,
71
+
BD96802_BUCK2_TW_CH_STAT,
72
+
};
73
+
74
+
#endif