Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"All of these are driver fixes except a memory leak in the
pinconf_generic_parse_dt_config() helper which is the most
important fix.
- Rename and fix up the Intel Equilibrium immutable interrupt chip
- Handle the Qualcomm QCS615 dual edge GPIO IRQ by adding the right
flag
- Fix a memory leak in the widely used pinconf_generic_parse_dt_config()
and a more local leak in aml_dt_node_to_map_pinmux()
- Fix double put in the Cirrus cs42l43_pin_probe()
- Staticize amdisp_pinctrl_ops, Qualcomm SDM660 groups and functions
- Unexport CIX sky1_pinctrl_pm_ops
- Fix configuration of deferred pin in the Rockchip driver
- Implement .get_direction() in the Sunxi driver squelching a dmesg
warning message
- Fix a readout of the last bank of registers in the Cypress CY8C95x0
driver"
* tag 'pinctrl-v7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: cy8c95x0: Don't miss reading the last bank registers
pinctrl: sunxi: Implement gpiochip::get_direction()
pinctrl: rockchip: Fix configuring a deferred pin
pinctrl: cirrus: cs42l43: Fix double-put in cs42l43_pin_probe()
pinctrl: meson: amlogic-a4: Fix device node reference leak in aml_dt_node_to_map_pinmux()
pinctrl: qcom: sdm660-lpass-lpi: Make groups and functions variables static
pinctrl: cix: sky1: Unexport sky1_pinctrl_pm_ops
pinctrl: amdisp: Make amdisp_pinctrl_ops variable static
pinctrl: pinconf-generic: Fix memory leak in pinconf_generic_parse_dt_config()
pinctrl: qcom: qcs615: Add missing dual edge GPIO IRQ errata flag
pinctrl: equilibrium: fix warning trace on load
pinctrl: equilibrium: rename irq_chip function callbacks
+86
-34
+2
-3
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
+2
-3
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
+1
-2
drivers/pinctrl/cix/pinctrl-sky1.c
+1
-2
drivers/pinctrl/cix/pinctrl-sky1.c
···
522
522
return pinctrl_force_default(spctl->pctl);
523
523
}
524
524
525
-
const struct dev_pm_ops sky1_pinctrl_pm_ops = {
525
+
static const struct dev_pm_ops sky1_pinctrl_pm_ops = {
526
526
SET_LATE_SYSTEM_SLEEP_PM_OPS(sky1_pinctrl_suspend,
527
527
sky1_pinctrl_resume)
528
528
};
529
-
EXPORT_SYMBOL_GPL(sky1_pinctrl_pm_ops);
530
529
531
530
static int sky1_pinctrl_probe(struct platform_device *pdev)
532
531
{
+1
-2
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
+1
-2
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
···
679
679
unsigned int *num_maps)
680
680
{
681
681
struct device *dev = pctldev->dev;
682
-
struct device_node *pnode;
683
682
unsigned long *configs = NULL;
684
683
unsigned int num_configs = 0;
685
684
struct property *prop;
···
692
693
return -ENOENT;
693
694
}
694
695
695
-
pnode = of_get_parent(np);
696
+
struct device_node *pnode __free(device_node) = of_get_parent(np);
696
697
if (!pnode) {
697
698
dev_info(dev, "Missing function node\n");
698
699
return -EINVAL;
+2
-2
drivers/pinctrl/pinconf-generic.c
+2
-2
drivers/pinctrl/pinconf-generic.c
···
351
351
352
352
ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
353
353
if (ret)
354
-
return ret;
354
+
goto out;
355
355
if (pctldev && pctldev->desc->num_custom_params &&
356
356
pctldev->desc->custom_params) {
357
357
ret = parse_dt_cfg(np, pctldev->desc->custom_params,
358
358
pctldev->desc->num_custom_params, cfg, &ncfg);
359
359
if (ret)
360
-
return ret;
360
+
goto out;
361
361
}
362
362
363
363
/* no configs found at all */
+1
-1
drivers/pinctrl/pinctrl-amdisp.c
+1
-1
drivers/pinctrl/pinctrl-amdisp.c
+2
-2
drivers/pinctrl/pinctrl-cy8c95x0.c
+2
-2
drivers/pinctrl/pinctrl-cy8c95x0.c
···
627
627
bitmap_scatter(tmask, mask, chip->map, MAX_LINE);
628
628
bitmap_scatter(tval, val, chip->map, MAX_LINE);
629
629
630
-
for_each_set_clump8(offset, bits, tmask, chip->tpin) {
630
+
for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) {
631
631
unsigned int i = offset / 8;
632
632
633
633
write_val = bitmap_get_value8(tval, offset);
···
655
655
bitmap_scatter(tmask, mask, chip->map, MAX_LINE);
656
656
bitmap_scatter(tval, val, chip->map, MAX_LINE);
657
657
658
-
for_each_set_clump8(offset, bits, tmask, chip->tpin) {
658
+
for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) {
659
659
unsigned int i = offset / 8;
660
660
661
661
ret = cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val);
+19
-12
drivers/pinctrl/pinctrl-equilibrium.c
+19
-12
drivers/pinctrl/pinctrl-equilibrium.c
···
23
23
#define PIN_NAME_LEN 10
24
24
#define PAD_REG_OFF 0x100
25
25
26
-
static void eqbr_gpio_disable_irq(struct irq_data *d)
26
+
static void eqbr_irq_mask(struct irq_data *d)
27
27
{
28
28
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
29
29
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
···
36
36
gpiochip_disable_irq(gc, offset);
37
37
}
38
38
39
-
static void eqbr_gpio_enable_irq(struct irq_data *d)
39
+
static void eqbr_irq_unmask(struct irq_data *d)
40
40
{
41
41
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
42
42
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
···
50
50
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
51
51
}
52
52
53
-
static void eqbr_gpio_ack_irq(struct irq_data *d)
53
+
static void eqbr_irq_ack(struct irq_data *d)
54
54
{
55
55
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
56
56
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
···
62
62
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
63
63
}
64
64
65
-
static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
65
+
static void eqbr_irq_mask_ack(struct irq_data *d)
66
66
{
67
-
eqbr_gpio_disable_irq(d);
68
-
eqbr_gpio_ack_irq(d);
67
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
68
+
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
69
+
unsigned int offset = irqd_to_hwirq(d);
70
+
unsigned long flags;
71
+
72
+
raw_spin_lock_irqsave(&gctrl->lock, flags);
73
+
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
74
+
writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
75
+
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
69
76
}
70
77
71
78
static inline void eqbr_cfg_bit(void __iomem *addr,
···
99
92
return 0;
100
93
}
101
94
102
-
static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
95
+
static int eqbr_irq_set_type(struct irq_data *d, unsigned int type)
103
96
{
104
97
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105
98
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
···
173
166
174
167
static const struct irq_chip eqbr_irq_chip = {
175
168
.name = "gpio_irq",
176
-
.irq_mask = eqbr_gpio_disable_irq,
177
-
.irq_unmask = eqbr_gpio_enable_irq,
178
-
.irq_ack = eqbr_gpio_ack_irq,
179
-
.irq_mask_ack = eqbr_gpio_mask_ack_irq,
180
-
.irq_set_type = eqbr_gpio_set_irq_type,
169
+
.irq_ack = eqbr_irq_ack,
170
+
.irq_mask = eqbr_irq_mask,
171
+
.irq_mask_ack = eqbr_irq_mask_ack,
172
+
.irq_unmask = eqbr_irq_unmask,
173
+
.irq_set_type = eqbr_irq_set_type,
181
174
.flags = IRQCHIP_IMMUTABLE,
182
175
GPIOCHIP_IRQ_RESOURCE_HELPERS,
183
176
};
+4
-8
drivers/pinctrl/pinctrl-rockchip.c
+4
-8
drivers/pinctrl/pinctrl-rockchip.c
···
3640
3640
* or the gpio driver hasn't probed yet.
3641
3641
*/
3642
3642
scoped_guard(mutex, &bank->deferred_lock) {
3643
-
if (!gpio || !gpio->direction_output) {
3644
-
rc = rockchip_pinconf_defer_pin(bank,
3645
-
pin - bank->pin_base,
3646
-
param, arg);
3647
-
if (rc)
3648
-
return rc;
3649
-
break;
3650
-
}
3643
+
if (!gpio || !gpio->direction_output)
3644
+
return rockchip_pinconf_defer_pin(bank,
3645
+
pin - bank->pin_base,
3646
+
param, arg);
3651
3647
}
3652
3648
}
3653
3649
+1
drivers/pinctrl/qcom/pinctrl-qcs615.c
+1
drivers/pinctrl/qcom/pinctrl-qcs615.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
···
76
76
static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
77
77
static const char * const pdm_sync_groups[] = { "gpio19" };
78
78
79
-
const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = {
79
+
static const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = {
80
80
LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000),
81
81
LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000),
82
82
LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000),
···
113
113
LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010),
114
114
};
115
115
116
-
const struct lpi_function sdm660_lpi_pinctrl_functions[] = {
116
+
static const struct lpi_function sdm660_lpi_pinctrl_functions[] = {
117
117
LPI_FUNCTION(comp_rx),
118
118
LPI_FUNCTION(dmic1_clk),
119
119
LPI_FUNCTION(dmic1_data),
+51
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+51
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
204
204
return NULL;
205
205
}
206
206
207
+
static struct sunxi_desc_function *
208
+
sunxi_pinctrl_desc_find_function_by_pin_and_mux(struct sunxi_pinctrl *pctl,
209
+
const u16 pin_num,
210
+
const u8 muxval)
211
+
{
212
+
for (unsigned int i = 0; i < pctl->desc->npins; i++) {
213
+
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
214
+
struct sunxi_desc_function *func = pin->functions;
215
+
216
+
if (pin->pin.number != pin_num)
217
+
continue;
218
+
219
+
if (pin->variant && !(pctl->variant & pin->variant))
220
+
continue;
221
+
222
+
while (func->name) {
223
+
if (func->muxval == muxval)
224
+
return func;
225
+
226
+
func++;
227
+
}
228
+
}
229
+
230
+
return NULL;
231
+
}
232
+
207
233
static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
208
234
{
209
235
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
···
956
930
.strict = true,
957
931
};
958
932
933
+
static int sunxi_pinctrl_gpio_get_direction(struct gpio_chip *chip,
934
+
unsigned int offset)
935
+
{
936
+
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
937
+
const struct sunxi_desc_function *func;
938
+
u32 pin = offset + chip->base;
939
+
u32 reg, shift, mask;
940
+
u8 muxval;
941
+
942
+
sunxi_mux_reg(pctl, offset, ®, &shift, &mask);
943
+
944
+
muxval = (readl(pctl->membase + reg) & mask) >> shift;
945
+
946
+
func = sunxi_pinctrl_desc_find_function_by_pin_and_mux(pctl, pin, muxval);
947
+
if (!func)
948
+
return -ENODEV;
949
+
950
+
if (!strcmp(func->name, "gpio_out"))
951
+
return GPIO_LINE_DIRECTION_OUT;
952
+
if (!strcmp(func->name, "gpio_in") || !strcmp(func->name, "irq"))
953
+
return GPIO_LINE_DIRECTION_IN;
954
+
return -EINVAL;
955
+
}
956
+
959
957
static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
960
958
unsigned offset)
961
959
{
···
1649
1599
pctl->chip->request = gpiochip_generic_request;
1650
1600
pctl->chip->free = gpiochip_generic_free;
1651
1601
pctl->chip->set_config = gpiochip_generic_config;
1602
+
pctl->chip->get_direction = sunxi_pinctrl_gpio_get_direction;
1652
1603
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1653
1604
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1654
1605
pctl->chip->get = sunxi_pinctrl_gpio_get;