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clk: starfive: jh7100: Don't round divisor up twice

The problem is best illustrated by an example. Suppose a consumer wants
a 4MHz clock rate from a divider with a 10MHz parent. It would then
call

clk_round_rate(clk, 4000000)

which would call into our determine_rate() callback that correctly
rounds up and finds that a divisor of 3 gives the highest possible
frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz.

However the consumer would then call

clk_set_rate(clk, 3333333)

but since 3333333 doesn't divide 10000000 evenly our set_rate() callback
would again round the divisor up and set it to 4 which results in an
unnecessarily low rate of 2.5MHz.

Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback.

Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver")
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-2-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Emil Renner Berthing and committed by
Stephen Boyd 40dda353 e783362e

+3 -11
+3 -11
drivers/clk/starfive/clk-starfive-jh7100.c
··· 399 399 return div ? parent_rate / div : 0; 400 400 } 401 401 402 - static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk, 403 - unsigned long rate, unsigned long parent) 404 - { 405 - unsigned long max = clk->max_div; 406 - unsigned long div = DIV_ROUND_UP(parent, rate); 407 - 408 - return min(div, max); 409 - } 410 - 411 402 static int jh7100_clk_determine_rate(struct clk_hw *hw, 412 403 struct clk_rate_request *req) 413 404 { 414 405 struct jh7100_clk *clk = jh7100_clk_from(hw); 415 406 unsigned long parent = req->best_parent_rate; 416 407 unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); 417 - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent); 408 + unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); 418 409 unsigned long result = parent / div; 419 410 420 411 /* ··· 433 442 unsigned long parent_rate) 434 443 { 435 444 struct jh7100_clk *clk = jh7100_clk_from(hw); 436 - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate); 445 + unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), 446 + 1UL, (unsigned long)clk->max_div); 437 447 438 448 jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); 439 449 return 0;