Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Add new GET_PIPE_FROM_CRTC_ID ioctl.
drm/i915: Set HDMI hot plug interrupt enable for only the output in question.
drm/i915: Include 965GME pci ID in IS_I965GM(dev) to match UMS.
drm/i915: Use the GM45 VGA hotplug workaround on G45 as well.
drm/i915: ignore LVDS on intel graphics systems that lie about having it
drm/i915: sanity check IER at wait_request time
drm/i915: workaround IGD i2c bus issue in kernel side (v2)
drm/i915: Don't allow binding objects into the last page of the aperture.
drm/i915: save/restore fence registers across suspend/resume
drm/i915: x86 always has writeq. Add I915_READ64 for symmetry.
+175
-24
+11
-2
drivers/gpu/drm/i915/i915_dma.c
+11
-2
drivers/gpu/drm/i915/i915_dma.c
···
1011
1011
/* Basic memrange allocator for stolen space (aka vram) */
1012
1012
drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1013
1013
1014
-
/* Let GEM Manage from end of prealloc space to end of aperture */
1015
-
i915_gem_do_init(dev, prealloc_size, agp_size);
1014
+
/* Let GEM Manage from end of prealloc space to end of aperture.
1015
+
*
1016
+
* However, leave one page at the end still bound to the scratch page.
1017
+
* There are a number of places where the hardware apparently
1018
+
* prefetches past the end of the object, and we've seen multiple
1019
+
* hangs with the GPU head pointer stuck in a batchbuffer bound
1020
+
* at the last page of the aperture. One page should be enough to
1021
+
* keep any prefetching inside of the aperture.
1022
+
*/
1023
+
i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1016
1024
1017
1025
ret = i915_gem_init_ringbuffer(dev);
1018
1026
if (ret)
···
1358
1350
DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1359
1351
DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1360
1352
DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1353
+
DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1361
1354
};
1362
1355
1363
1356
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
+4
-7
drivers/gpu/drm/i915/i915_drv.h
+4
-7
drivers/gpu/drm/i915/i915_drv.h
···
283
283
u8 saveAR[21];
284
284
u8 saveDACMASK;
285
285
u8 saveCR[37];
286
+
uint64_t saveFENCE[16];
286
287
287
288
struct {
288
289
struct drm_mm gtt_space;
···
706
705
#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
707
706
#define I915_READ8(reg) readb(dev_priv->regs + (reg))
708
707
#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
709
-
#ifdef writeq
710
708
#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
711
-
#else
712
-
#define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
713
-
writel(upper_32_bits(val), dev_priv->regs + \
714
-
(reg) + 4))
715
-
#endif
709
+
#define I915_READ64(reg) readq(dev_priv->regs + (reg))
716
710
#define POSTING_READ(reg) (void)I915_READ(reg)
717
711
718
712
#define I915_VERBOSE 0
···
786
790
(dev)->pci_device == 0x2E22 || \
787
791
(dev)->pci_device == 0x2E32)
788
792
789
-
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
793
+
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
794
+
(dev)->pci_device == 0x2A12)
790
795
791
796
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
792
797
+9
drivers/gpu/drm/i915/i915_gem.c
+9
drivers/gpu/drm/i915/i915_gem.c
···
1691
1691
i915_wait_request(struct drm_device *dev, uint32_t seqno)
1692
1692
{
1693
1693
drm_i915_private_t *dev_priv = dev->dev_private;
1694
+
u32 ier;
1694
1695
int ret = 0;
1695
1696
1696
1697
BUG_ON(seqno == 0);
1697
1698
1698
1699
if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1700
+
ier = I915_READ(IER);
1701
+
if (!ier) {
1702
+
DRM_ERROR("something (likely vbetool) disabled "
1703
+
"interrupts, re-enabling\n");
1704
+
i915_driver_irq_preinstall(dev);
1705
+
i915_driver_irq_postinstall(dev);
1706
+
}
1707
+
1699
1708
dev_priv->mm.waiting_gem_seqno = seqno;
1700
1709
i915_user_irq_get(dev);
1701
1710
ret = wait_event_interruptible(dev_priv->irq_queue,
+1
drivers/gpu/drm/i915/i915_reg.h
+1
drivers/gpu/drm/i915/i915_reg.h
+24
drivers/gpu/drm/i915/i915_suspend.c
+24
drivers/gpu/drm/i915/i915_suspend.c
···
349
349
for (i = 0; i < 3; i++)
350
350
dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
351
351
352
+
/* Fences */
353
+
if (IS_I965G(dev)) {
354
+
for (i = 0; i < 16; i++)
355
+
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
356
+
} else {
357
+
for (i = 0; i < 8; i++)
358
+
dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
359
+
360
+
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
361
+
for (i = 0; i < 8; i++)
362
+
dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
363
+
}
352
364
i915_save_vga(dev);
353
365
354
366
return 0;
···
382
370
383
371
/* Display arbitration */
384
372
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
373
+
374
+
/* Fences */
375
+
if (IS_I965G(dev)) {
376
+
for (i = 0; i < 16; i++)
377
+
I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
378
+
} else {
379
+
for (i = 0; i < 8; i++)
380
+
I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
381
+
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
382
+
for (i = 0; i < 8; i++)
383
+
I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
384
+
}
385
385
386
386
/* Pipe & plane A info */
387
387
/* Prime the clock */
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+31
drivers/gpu/drm/i915/intel_display.c
+31
drivers/gpu/drm/i915/intel_display.c
···
1804
1804
}
1805
1805
}
1806
1806
1807
+
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1808
+
struct drm_file *file_priv)
1809
+
{
1810
+
drm_i915_private_t *dev_priv = dev->dev_private;
1811
+
struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
1812
+
struct drm_crtc *crtc = NULL;
1813
+
int pipe = -1;
1814
+
1815
+
if (!dev_priv) {
1816
+
DRM_ERROR("called with no initialization\n");
1817
+
return -EINVAL;
1818
+
}
1819
+
1820
+
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1821
+
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822
+
if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
1823
+
pipe = intel_crtc->pipe;
1824
+
break;
1825
+
}
1826
+
}
1827
+
1828
+
if (pipe == -1) {
1829
+
DRM_ERROR("no such CRTC id\n");
1830
+
return -EINVAL;
1831
+
}
1832
+
1833
+
pipe_from_crtc_id->pipe = pipe;
1834
+
1835
+
return 0;
1836
+
}
1837
+
1807
1838
struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1808
1839
{
1809
1840
struct drm_crtc *crtc = NULL;
+3
-1
drivers/gpu/drm/i915/intel_drv.h
+3
-1
drivers/gpu/drm/i915/intel_drv.h
···
109
109
void intel_i2c_destroy(struct intel_i2c_chan *chan);
110
110
int intel_ddc_get_modes(struct intel_output *intel_output);
111
111
extern bool intel_ddc_probe(struct intel_output *intel_output);
112
-
112
+
void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
113
113
extern void intel_crt_init(struct drm_device *dev);
114
114
extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
115
115
extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
···
125
125
126
126
extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
127
127
struct drm_crtc *crtc);
128
+
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
129
+
struct drm_file *file_priv);
128
130
extern void intel_wait_for_vblank(struct drm_device *dev);
129
131
extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe);
130
132
extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
+12
-5
drivers/gpu/drm/i915/intel_hdmi.c
+12
-5
drivers/gpu/drm/i915/intel_hdmi.c
···
155
155
156
156
temp = I915_READ(PORT_HOTPLUG_EN);
157
157
158
-
I915_WRITE(PORT_HOTPLUG_EN,
159
-
temp |
160
-
HDMIB_HOTPLUG_INT_EN |
161
-
HDMIC_HOTPLUG_INT_EN |
162
-
HDMID_HOTPLUG_INT_EN);
158
+
switch (hdmi_priv->sdvox_reg) {
159
+
case SDVOB:
160
+
temp |= HDMIB_HOTPLUG_INT_EN;
161
+
break;
162
+
case SDVOC:
163
+
temp |= HDMIC_HOTPLUG_INT_EN;
164
+
break;
165
+
default:
166
+
return connector_status_unknown;
167
+
}
168
+
169
+
I915_WRITE(PORT_HOTPLUG_EN, temp);
163
170
164
171
POSTING_READ(PORT_HOTPLUG_EN);
165
172
+17
drivers/gpu/drm/i915/intel_i2c.c
+17
drivers/gpu/drm/i915/intel_i2c.c
···
34
34
#include "i915_drm.h"
35
35
#include "i915_drv.h"
36
36
37
+
void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
38
+
{
39
+
struct drm_i915_private *dev_priv = dev->dev_private;
40
+
41
+
/* When using bit bashing for I2C, this bit needs to be set to 1 */
42
+
if (!IS_IGD(dev))
43
+
return;
44
+
if (enable)
45
+
I915_WRITE(CG_2D_DIS,
46
+
I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE);
47
+
else
48
+
I915_WRITE(CG_2D_DIS,
49
+
I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE));
50
+
}
51
+
37
52
/*
38
53
* Intel GPIO access functions
39
54
*/
···
168
153
goto out_free;
169
154
170
155
/* JJJ: raise SCL and SDA? */
156
+
intel_i2c_quirk_set(dev, true);
171
157
set_data(chan, 1);
172
158
set_clock(chan, 1);
159
+
intel_i2c_quirk_set(dev, false);
173
160
udelay(20);
174
161
175
162
return chan;
+46
-8
drivers/gpu/drm/i915/intel_lvds.c
+46
-8
drivers/gpu/drm/i915/intel_lvds.c
···
384
384
.destroy = intel_lvds_enc_destroy,
385
385
};
386
386
387
+
static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
388
+
{
389
+
DRM_DEBUG("Skipping LVDS initialization for %s\n", id->ident);
390
+
return 1;
391
+
}
387
392
393
+
/* These systems claim to have LVDS, but really don't */
394
+
static const struct dmi_system_id __initdata intel_no_lvds[] = {
395
+
{
396
+
.callback = intel_no_lvds_dmi_callback,
397
+
.ident = "Apple Mac Mini (Core series)",
398
+
.matches = {
399
+
DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
400
+
DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
401
+
},
402
+
},
403
+
{
404
+
.callback = intel_no_lvds_dmi_callback,
405
+
.ident = "Apple Mac Mini (Core 2 series)",
406
+
.matches = {
407
+
DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
408
+
DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
409
+
},
410
+
},
411
+
{
412
+
.callback = intel_no_lvds_dmi_callback,
413
+
.ident = "MSI IM-945GSE-A",
414
+
.matches = {
415
+
DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
416
+
DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
417
+
},
418
+
},
419
+
{
420
+
.callback = intel_no_lvds_dmi_callback,
421
+
.ident = "Dell Studio Hybrid",
422
+
.matches = {
423
+
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
424
+
DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
425
+
},
426
+
},
427
+
428
+
/* FIXME: add a check for the Aopen Mini PC */
429
+
430
+
{ } /* terminating entry */
431
+
};
388
432
389
433
/**
390
434
* intel_lvds_init - setup LVDS connectors on this device
···
448
404
u32 lvds;
449
405
int pipe;
450
406
451
-
/* Blacklist machines that we know falsely report LVDS. */
452
-
/* FIXME: add a check for the Aopen Mini PC */
453
-
454
-
/* Apple Mac Mini Core Duo and Mac Mini Core 2 Duo */
455
-
if(dmi_match(DMI_PRODUCT_NAME, "Macmini1,1") ||
456
-
dmi_match(DMI_PRODUCT_NAME, "Macmini2,1")) {
457
-
DRM_DEBUG("Skipping LVDS initialization for Apple Mac Mini\n");
407
+
/* Skip init on machines we know falsely report LVDS */
408
+
if (dmi_check_system(intel_no_lvds))
458
409
return;
459
-
}
460
410
461
411
intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
462
412
if (!intel_output) {
+6
drivers/gpu/drm/i915/intel_modes.c
+6
drivers/gpu/drm/i915/intel_modes.c
···
27
27
#include <linux/fb.h>
28
28
#include "drmP.h"
29
29
#include "intel_drv.h"
30
+
#include "i915_drv.h"
30
31
31
32
/**
32
33
* intel_ddc_probe
···
53
52
}
54
53
};
55
54
55
+
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
56
56
ret = i2c_transfer(&intel_output->ddc_bus->adapter, msgs, 2);
57
+
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
58
+
57
59
if (ret == 2)
58
60
return true;
59
61
···
74
70
struct edid *edid;
75
71
int ret = 0;
76
72
73
+
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
77
74
edid = drm_get_edid(&intel_output->base,
78
75
&intel_output->ddc_bus->adapter);
76
+
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
79
77
if (edid) {
80
78
drm_mode_connector_update_edid_property(&intel_output->base,
81
79
edid);
+10
include/drm/i915_drm.h
+10
include/drm/i915_drm.h
···
184
184
#define DRM_I915_GEM_GET_TILING 0x22
185
185
#define DRM_I915_GEM_GET_APERTURE 0x23
186
186
#define DRM_I915_GEM_MMAP_GTT 0x24
187
+
#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
187
188
188
189
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
189
190
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
···
220
219
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
221
220
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
222
221
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
222
+
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
223
223
224
224
/* Allow drivers to submit batchbuffers directly to hardware, relying
225
225
* on the security mechanisms provided by hardware.
···
657
655
* bytes
658
656
*/
659
657
__u64 aper_available_size;
658
+
};
659
+
660
+
struct drm_i915_get_pipe_from_crtc_id {
661
+
/** ID of CRTC being requested **/
662
+
__u32 crtc_id;
663
+
664
+
/** pipe of requested CRTC **/
665
+
__u32 pipe;
660
666
};
661
667
662
668
#endif /* _I915_DRM_H_ */