Merge tag 'pci-v5.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

+31 -32

2 changed files

expand all

drivers

pci

controller

dwc

pcie-designware-host.c

pcie-tegra194.c

+2 -6

drivers/pci/controller/dwc/pcie-designware-host.c

··· 397 397 pp); 398 398 399 399 ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); 400 - if (!ret) { 401 - dev_warn(pci->dev, 402 - "Failed to set DMA mask to 32-bit. " 403 - "Devices with only 32-bit MSI support" 404 - " may not work properly\n"); 405 - } 400 + if (ret) 401 + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); 406 402 407 403 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, 408 404 sizeof(pp->msi_msg),

+29 -26

drivers/pci/controller/dwc/pcie-tegra194.c

··· 853 853 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); 854 854 } 855 855 856 - static void tegra_pcie_prepare_host(struct pcie_port *pp) 856 + static int tegra_pcie_dw_host_init(struct pcie_port *pp) 857 857 { 858 858 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 859 859 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 860 860 u32 val; 861 + 862 + pp->bridge->ops = &tegra_pci_ops; 861 863 862 864 if (!pcie->pcie_cap_base) 863 865 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, ··· 909 907 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); 910 908 } 911 909 912 - dw_pcie_setup_rc(pp); 913 - 914 910 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); 915 911 912 + return 0; 913 + } 914 + 915 + static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 916 + { 917 + u32 val, offset, speed, tmp; 918 + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 919 + struct pcie_port *pp = &pci->pp; 920 + bool retry = true; 921 + 922 + if (pcie->mode == DW_PCIE_EP_TYPE) { 923 + enable_irq(pcie->pex_rst_irq); 924 + return 0; 925 + } 926 + 927 + retry_link: 916 928 /* Assert RST */ 917 929 val = appl_readl(pcie, APPL_PINMUX); 918 930 val &= ~APPL_PINMUX_PEX_RST; ··· 945 929 appl_writel(pcie, val, APPL_PINMUX); 946 930 947 931 msleep(100); 948 - } 949 - 950 - static int tegra_pcie_dw_host_init(struct pcie_port *pp) 951 - { 952 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 953 - struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 954 - u32 val, tmp, offset, speed; 955 - 956 - pp->bridge->ops = &tegra_pci_ops; 957 - 958 - tegra_pcie_prepare_host(pp); 959 932 960 933 if (dw_pcie_wait_for_link(pci)) { 934 + if (!retry) 935 + return 0; 961 936 /* 962 937 * There are some endpoints which can't get the link up if 963 938 * root port has Data Link Feature (DLF) enabled. ··· 982 975 val &= ~PCI_DLF_EXCHANGE_ENABLE; 983 976 dw_pcie_writel_dbi(pci, offset, val); 984 977 985 - tegra_pcie_prepare_host(pp); 978 + tegra_pcie_dw_host_init(pp); 979 + dw_pcie_setup_rc(pp); 986 980 987 - if (dw_pcie_wait_for_link(pci)) 988 - return 0; 981 + retry = false; 982 + goto retry_link; 989 983 } 990 984 991 985 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & ··· 1004 996 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 1005 997 1006 998 return !!(val & PCI_EXP_LNKSTA_DLLLA); 1007 - } 1008 - 1009 - static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 1010 - { 1011 - struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 1012 - 1013 - enable_irq(pcie->pex_rst_irq); 1014 - 1015 - return 0; 1016 999 } 1017 1000 1018 1001 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) ··· 2213 2214 dev_err(dev, "Failed to init host: %d\n", ret); 2214 2215 goto fail_host_init; 2215 2216 } 2217 + 2218 + ret = tegra_pcie_dw_start_link(&pcie->pci); 2219 + if (ret < 0) 2220 + goto fail_host_init; 2216 2221 2217 2222 /* Restore MSI interrupt vector */ 2218 2223 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,

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