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drm/xe/pat: define coh_mode 2way

Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.

This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260305121902.1892593-8-tejas.upadhyay@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

+12 -11
+7 -7
drivers/gpu/drm/xe/xe_pat.c
··· 92 92 }; 93 93 94 94 static const struct xe_pat_table_entry xelp_pat_table[] = { 95 - [0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 95 + [0] = { XELP_PAT_WB, XE_COH_1WAY }, 96 96 [1] = { XELP_PAT_WC, XE_COH_NONE }, 97 97 [2] = { XELP_PAT_WT, XE_COH_NONE }, 98 98 [3] = { XELP_PAT_UC, XE_COH_NONE }, ··· 102 102 [0] = { XELP_PAT_UC, XE_COH_NONE }, 103 103 [1] = { XELP_PAT_WC, XE_COH_NONE }, 104 104 [2] = { XELP_PAT_WT, XE_COH_NONE }, 105 - [3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 105 + [3] = { XELP_PAT_WB, XE_COH_1WAY }, 106 106 [4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE }, 107 - [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 107 + [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY }, 108 108 [6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE }, 109 - [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 109 + [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY }, 110 110 }; 111 111 112 112 static const struct xe_pat_table_entry xelpg_pat_table[] = { 113 113 [0] = { XELPG_PAT_0_WB, XE_COH_NONE }, 114 114 [1] = { XELPG_PAT_1_WT, XE_COH_NONE }, 115 115 [2] = { XELPG_PAT_3_UC, XE_COH_NONE }, 116 - [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY }, 117 - [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY }, 116 + [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY }, 117 + [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY }, 118 118 }; 119 119 120 120 /* ··· 147 147 REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \ 148 148 REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \ 149 149 REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \ 150 - .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \ 150 + .coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \ 151 151 .valid = 1 \ 152 152 } 153 153
+3 -2
drivers/gpu/drm/xe/xe_pat.h
··· 28 28 /** 29 29 * @coh_mode: The GPU coherency mode that @value maps to. 30 30 */ 31 - #define XE_COH_NONE 1 32 - #define XE_COH_AT_LEAST_1WAY 2 31 + #define XE_COH_NONE 1 32 + #define XE_COH_1WAY 2 33 + #define XE_COH_2WAY 3 33 34 u16 coh_mode; 34 35 35 36 /**
+1 -1
drivers/gpu/drm/xe/xe_vm.c
··· 3465 3465 goto free_bind_ops; 3466 3466 } 3467 3467 3468 - if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) { 3468 + if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) { 3469 3469 err = -EINVAL; 3470 3470 goto free_bind_ops; 3471 3471 }
+1 -1
drivers/gpu/drm/xe/xe_vm_madvise.c
··· 309 309 if (XE_IOCTL_DBG(xe, !coh_mode)) 310 310 return false; 311 311 312 - if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) 312 + if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) 313 313 return false; 314 314 315 315 if (XE_IOCTL_DBG(xe, args->pat_index.pad))