tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: gcc-sm8150: drop PLL test clock

There is no user of core_bi_pll_test_se test clock so drop it.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228140917.118861-2-krzysztof.kozlowski@linaro.org

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson 412df0f9 3db8732c

-17
-17
drivers/clk/qcom/gcc-sm8150.c
··· 26 26 enum { 27 27 P_BI_TCXO, 28 28 P_AUD_REF_CLK, 29 - P_CORE_BI_PLL_TEST_SE, 30 29 P_GPLL0_OUT_EVEN, 31 30 P_GPLL0_OUT_MAIN, 32 31 P_GPLL7_OUT_MAIN, ··· 116 117 { P_BI_TCXO, 0 }, 117 118 { P_GPLL0_OUT_MAIN, 1 }, 118 119 { P_GPLL0_OUT_EVEN, 6 }, 119 - { P_CORE_BI_PLL_TEST_SE, 7 }, 120 120 }; 121 121 122 122 static const struct clk_parent_data gcc_parents_0[] = { 123 123 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 124 124 { .hw = &gpll0.clkr.hw }, 125 125 { .hw = &gpll0_out_even.clkr.hw }, 126 - { .fw_name = "core_bi_pll_test_se" }, 127 126 }; 128 127 129 128 static const struct parent_map gcc_parent_map_1[] = { ··· 129 132 { P_GPLL0_OUT_MAIN, 1 }, 130 133 { P_SLEEP_CLK, 5 }, 131 134 { P_GPLL0_OUT_EVEN, 6 }, 132 - { P_CORE_BI_PLL_TEST_SE, 7 }, 133 135 }; 134 136 135 137 static const struct clk_parent_data gcc_parents_1[] = { ··· 136 140 { .hw = &gpll0.clkr.hw }, 137 141 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 138 142 { .hw = &gpll0_out_even.clkr.hw }, 139 - { .fw_name = "core_bi_pll_test_se" }, 140 143 }; 141 144 142 145 static const struct parent_map gcc_parent_map_2[] = { 143 146 { P_BI_TCXO, 0 }, 144 147 { P_SLEEP_CLK, 5 }, 145 - { P_CORE_BI_PLL_TEST_SE, 7 }, 146 148 }; 147 149 148 150 static const struct clk_parent_data gcc_parents_2[] = { 149 151 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 150 152 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 151 - { .fw_name = "core_bi_pll_test_se" }, 152 153 }; 153 154 154 155 static const struct parent_map gcc_parent_map_3[] = { 155 156 { P_BI_TCXO, 0 }, 156 157 { P_GPLL0_OUT_MAIN, 1 }, 157 - { P_CORE_BI_PLL_TEST_SE, 7 }, 158 158 }; 159 159 160 160 static const struct clk_parent_data gcc_parents_3[] = { 161 161 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 162 162 { .hw = &gpll0.clkr.hw }, 163 - { .fw_name = "core_bi_pll_test_se"}, 164 163 }; 165 164 166 165 static const struct parent_map gcc_parent_map_4[] = { 167 166 { P_BI_TCXO, 0 }, 168 - { P_CORE_BI_PLL_TEST_SE, 7 }, 169 167 }; 170 168 171 169 static const struct clk_parent_data gcc_parents_4[] = { 172 170 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 173 - { .fw_name = "core_bi_pll_test_se" }, 174 171 }; 175 172 176 173 static const struct parent_map gcc_parent_map_5[] = { ··· 171 182 { P_GPLL0_OUT_MAIN, 1 }, 172 183 { P_GPLL7_OUT_MAIN, 3 }, 173 184 { P_GPLL0_OUT_EVEN, 6 }, 174 - { P_CORE_BI_PLL_TEST_SE, 7 }, 175 185 }; 176 186 177 187 static const struct clk_parent_data gcc_parents_5[] = { ··· 178 190 { .hw = &gpll0.clkr.hw }, 179 191 { .hw = &gpll7.clkr.hw }, 180 192 { .hw = &gpll0_out_even.clkr.hw }, 181 - { .fw_name = "core_bi_pll_test_se" }, 182 193 }; 183 194 184 195 static const struct parent_map gcc_parent_map_6[] = { ··· 185 198 { P_GPLL0_OUT_MAIN, 1 }, 186 199 { P_GPLL9_OUT_MAIN, 2 }, 187 200 { P_GPLL0_OUT_EVEN, 6 }, 188 - { P_CORE_BI_PLL_TEST_SE, 7 }, 189 201 }; 190 202 191 203 static const struct clk_parent_data gcc_parents_6[] = { ··· 192 206 { .hw = &gpll0.clkr.hw }, 193 207 { .hw = &gpll9.clkr.hw }, 194 208 { .hw = &gpll0_out_even.clkr.hw }, 195 - { .fw_name = "core_bi_pll_test_se" }, 196 209 }; 197 210 198 211 static const struct parent_map gcc_parent_map_7[] = { ··· 199 214 { P_GPLL0_OUT_MAIN, 1 }, 200 215 { P_AUD_REF_CLK, 2 }, 201 216 { P_GPLL0_OUT_EVEN, 6 }, 202 - { P_CORE_BI_PLL_TEST_SE, 7 }, 203 217 }; 204 218 205 219 static const struct clk_parent_data gcc_parents_7[] = { ··· 206 222 { .hw = &gpll0.clkr.hw }, 207 223 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, 208 224 { .hw = &gpll0_out_even.clkr.hw }, 209 - { .fw_name = "core_bi_pll_test_se" }, 210 225 }; 211 226 212 227 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {