Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"Three fixes for the ARM GIC interrupt controller from Marc addressing
various shortcomings versus boot initialization and suspend/resume"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic: Add save/restore of the active state
irqchip/gic: Clear enable bits before restoring them
irqchip/gic: Make sure all interrupts are deactivated at boot
+45
-6
+9
-4
drivers/irqchip/irq-gic-common.c
+9
-4
drivers/irqchip/irq-gic-common.c
···
84
84
writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
85
85
86
86
/*
87
-
* Disable all interrupts. Leave the PPI and SGIs alone
88
-
* as they are enabled by redistributor registers.
87
+
* Deactivate and disable all SPIs. Leave the PPI and SGIs
88
+
* alone as they are in the redistributor registers on GICv3.
89
89
*/
90
-
for (i = 32; i < gic_irqs; i += 32)
90
+
for (i = 32; i < gic_irqs; i += 32) {
91
91
writel_relaxed(GICD_INT_EN_CLR_X32,
92
-
base + GIC_DIST_ENABLE_CLEAR + i / 8);
92
+
base + GIC_DIST_ACTIVE_CLEAR + i / 8);
93
+
writel_relaxed(GICD_INT_EN_CLR_X32,
94
+
base + GIC_DIST_ENABLE_CLEAR + i / 8);
95
+
}
93
96
94
97
if (sync_access)
95
98
sync_access();
···
105
102
/*
106
103
* Deal with the banked PPI and SGI interrupts - disable all
107
104
* PPI interrupts, ensure all SGI interrupts are enabled.
105
+
* Make sure everything is deactivated.
108
106
*/
107
+
writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
109
108
writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
110
109
writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
111
110
+36
-2
drivers/irqchip/irq-gic.c
+36
-2
drivers/irqchip/irq-gic.c
···
73
73
union gic_base cpu_base;
74
74
#ifdef CONFIG_CPU_PM
75
75
u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
76
+
u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
76
77
u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
77
78
u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
78
79
u32 __percpu *saved_ppi_enable;
80
+
u32 __percpu *saved_ppi_active;
79
81
u32 __percpu *saved_ppi_conf;
80
82
#endif
81
83
struct irq_domain *domain;
···
568
566
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
569
567
gic_data[gic_nr].saved_spi_enable[i] =
570
568
readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
569
+
570
+
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
571
+
gic_data[gic_nr].saved_spi_active[i] =
572
+
readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
571
573
}
572
574
573
575
/*
···
610
604
writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
611
605
dist_base + GIC_DIST_TARGET + i * 4);
612
606
613
-
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
607
+
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
608
+
writel_relaxed(GICD_INT_EN_CLR_X32,
609
+
dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
614
610
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
615
611
dist_base + GIC_DIST_ENABLE_SET + i * 4);
612
+
}
613
+
614
+
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
615
+
writel_relaxed(GICD_INT_EN_CLR_X32,
616
+
dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
617
+
writel_relaxed(gic_data[gic_nr].saved_spi_active[i],
618
+
dist_base + GIC_DIST_ACTIVE_SET + i * 4);
619
+
}
616
620
617
621
writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
618
622
}
···
647
631
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
648
632
ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
649
633
634
+
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
635
+
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
636
+
ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
637
+
650
638
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
651
639
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
652
640
ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
···
674
654
return;
675
655
676
656
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
677
-
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
657
+
for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
658
+
writel_relaxed(GICD_INT_EN_CLR_X32,
659
+
dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
678
660
writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
661
+
}
662
+
663
+
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
664
+
for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
665
+
writel_relaxed(GICD_INT_EN_CLR_X32,
666
+
dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
667
+
writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
668
+
}
679
669
680
670
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
681
671
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
···
739
709
gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
740
710
sizeof(u32));
741
711
BUG_ON(!gic->saved_ppi_enable);
712
+
713
+
gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
714
+
sizeof(u32));
715
+
BUG_ON(!gic->saved_ppi_active);
742
716
743
717
gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
744
718
sizeof(u32));