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clk: qcom: camcc-sm7150: Fix PLL config of PLL2

The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
parameters that are provided in the vendor driver. Instead the upstream
configuration should provide the final user_ctl value that is written to
the USER_CTL register.

Fix the config so that the PLL is configured correctly.

Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for SM7150")
Suggested-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251021-agera-pll-fixups-v1-2-8c1d8aff4afc@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Luca Weiss and committed by
Bjorn Andersson 415aad75 ab0e1314

+1 -5
+1 -5
drivers/clk/qcom/camcc-sm7150.c
··· 139 139 /* 1920MHz configuration */ 140 140 static const struct alpha_pll_config camcc_pll2_config = { 141 141 .l = 0x64, 142 - .post_div_val = 0x3 << 8, 143 - .post_div_mask = 0x3 << 8, 144 - .early_output_mask = BIT(3), 145 - .aux_output_mask = BIT(1), 146 - .main_output_mask = BIT(0), 147 142 .config_ctl_hi_val = 0x400003d6, 148 143 .config_ctl_val = 0x20000954, 144 + .user_ctl_val = 0x0000030b, 149 145 }; 150 146 151 147 static struct clk_alpha_pll camcc_pll2 = {