tjh.dev / kernel
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clk: qcom: gcc-msm8660: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909105136.3733919-3-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 41872e9f c027fa89

+41 -41
+41 -41
drivers/clk/qcom/gcc-msm8660.c
··· 123 123 .hw.init = &(struct clk_init_data){ 124 124 .name = "gsbi1_uart_src", 125 125 .parent_names = gcc_pxo_pll8, 126 - .num_parents = 2, 126 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 127 127 .ops = &clk_rcg_ops, 128 128 .flags = CLK_SET_PARENT_GATE, 129 129 }, ··· 174 174 .hw.init = &(struct clk_init_data){ 175 175 .name = "gsbi2_uart_src", 176 176 .parent_names = gcc_pxo_pll8, 177 - .num_parents = 2, 177 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 178 178 .ops = &clk_rcg_ops, 179 179 .flags = CLK_SET_PARENT_GATE, 180 180 }, ··· 225 225 .hw.init = &(struct clk_init_data){ 226 226 .name = "gsbi3_uart_src", 227 227 .parent_names = gcc_pxo_pll8, 228 - .num_parents = 2, 228 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 229 229 .ops = &clk_rcg_ops, 230 230 .flags = CLK_SET_PARENT_GATE, 231 231 }, ··· 276 276 .hw.init = &(struct clk_init_data){ 277 277 .name = "gsbi4_uart_src", 278 278 .parent_names = gcc_pxo_pll8, 279 - .num_parents = 2, 279 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 280 280 .ops = &clk_rcg_ops, 281 281 .flags = CLK_SET_PARENT_GATE, 282 282 }, ··· 327 327 .hw.init = &(struct clk_init_data){ 328 328 .name = "gsbi5_uart_src", 329 329 .parent_names = gcc_pxo_pll8, 330 - .num_parents = 2, 330 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 331 331 .ops = &clk_rcg_ops, 332 332 .flags = CLK_SET_PARENT_GATE, 333 333 }, ··· 378 378 .hw.init = &(struct clk_init_data){ 379 379 .name = "gsbi6_uart_src", 380 380 .parent_names = gcc_pxo_pll8, 381 - .num_parents = 2, 381 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 382 382 .ops = &clk_rcg_ops, 383 383 .flags = CLK_SET_PARENT_GATE, 384 384 }, ··· 429 429 .hw.init = &(struct clk_init_data){ 430 430 .name = "gsbi7_uart_src", 431 431 .parent_names = gcc_pxo_pll8, 432 - .num_parents = 2, 432 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 433 433 .ops = &clk_rcg_ops, 434 434 .flags = CLK_SET_PARENT_GATE, 435 435 }, ··· 480 480 .hw.init = &(struct clk_init_data){ 481 481 .name = "gsbi8_uart_src", 482 482 .parent_names = gcc_pxo_pll8, 483 - .num_parents = 2, 483 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 484 484 .ops = &clk_rcg_ops, 485 485 .flags = CLK_SET_PARENT_GATE, 486 486 }, ··· 529 529 .hw.init = &(struct clk_init_data){ 530 530 .name = "gsbi9_uart_src", 531 531 .parent_names = gcc_pxo_pll8, 532 - .num_parents = 2, 532 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 533 533 .ops = &clk_rcg_ops, 534 534 .flags = CLK_SET_PARENT_GATE, 535 535 }, ··· 578 578 .hw.init = &(struct clk_init_data){ 579 579 .name = "gsbi10_uart_src", 580 580 .parent_names = gcc_pxo_pll8, 581 - .num_parents = 2, 581 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 582 582 .ops = &clk_rcg_ops, 583 583 .flags = CLK_SET_PARENT_GATE, 584 584 }, ··· 627 627 .hw.init = &(struct clk_init_data){ 628 628 .name = "gsbi11_uart_src", 629 629 .parent_names = gcc_pxo_pll8, 630 - .num_parents = 2, 630 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 631 631 .ops = &clk_rcg_ops, 632 632 .flags = CLK_SET_PARENT_GATE, 633 633 }, ··· 676 676 .hw.init = &(struct clk_init_data){ 677 677 .name = "gsbi12_uart_src", 678 678 .parent_names = gcc_pxo_pll8, 679 - .num_parents = 2, 679 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 680 680 .ops = &clk_rcg_ops, 681 681 .flags = CLK_SET_PARENT_GATE, 682 682 }, ··· 738 738 .hw.init = &(struct clk_init_data){ 739 739 .name = "gsbi1_qup_src", 740 740 .parent_names = gcc_pxo_pll8, 741 - .num_parents = 2, 741 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 742 742 .ops = &clk_rcg_ops, 743 743 .flags = CLK_SET_PARENT_GATE, 744 744 }, ··· 787 787 .hw.init = &(struct clk_init_data){ 788 788 .name = "gsbi2_qup_src", 789 789 .parent_names = gcc_pxo_pll8, 790 - .num_parents = 2, 790 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 791 791 .ops = &clk_rcg_ops, 792 792 .flags = CLK_SET_PARENT_GATE, 793 793 }, ··· 836 836 .hw.init = &(struct clk_init_data){ 837 837 .name = "gsbi3_qup_src", 838 838 .parent_names = gcc_pxo_pll8, 839 - .num_parents = 2, 839 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 840 840 .ops = &clk_rcg_ops, 841 841 .flags = CLK_SET_PARENT_GATE, 842 842 }, ··· 885 885 .hw.init = &(struct clk_init_data){ 886 886 .name = "gsbi4_qup_src", 887 887 .parent_names = gcc_pxo_pll8, 888 - .num_parents = 2, 888 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 889 889 .ops = &clk_rcg_ops, 890 890 .flags = CLK_SET_PARENT_GATE, 891 891 }, ··· 934 934 .hw.init = &(struct clk_init_data){ 935 935 .name = "gsbi5_qup_src", 936 936 .parent_names = gcc_pxo_pll8, 937 - .num_parents = 2, 937 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 938 938 .ops = &clk_rcg_ops, 939 939 .flags = CLK_SET_PARENT_GATE, 940 940 }, ··· 983 983 .hw.init = &(struct clk_init_data){ 984 984 .name = "gsbi6_qup_src", 985 985 .parent_names = gcc_pxo_pll8, 986 - .num_parents = 2, 986 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 987 987 .ops = &clk_rcg_ops, 988 988 .flags = CLK_SET_PARENT_GATE, 989 989 }, ··· 1032 1032 .hw.init = &(struct clk_init_data){ 1033 1033 .name = "gsbi7_qup_src", 1034 1034 .parent_names = gcc_pxo_pll8, 1035 - .num_parents = 2, 1035 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1036 1036 .ops = &clk_rcg_ops, 1037 1037 .flags = CLK_SET_PARENT_GATE, 1038 1038 }, ··· 1081 1081 .hw.init = &(struct clk_init_data){ 1082 1082 .name = "gsbi8_qup_src", 1083 1083 .parent_names = gcc_pxo_pll8, 1084 - .num_parents = 2, 1084 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1085 1085 .ops = &clk_rcg_ops, 1086 1086 .flags = CLK_SET_PARENT_GATE, 1087 1087 }, ··· 1130 1130 .hw.init = &(struct clk_init_data){ 1131 1131 .name = "gsbi9_qup_src", 1132 1132 .parent_names = gcc_pxo_pll8, 1133 - .num_parents = 2, 1133 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1134 1134 .ops = &clk_rcg_ops, 1135 1135 .flags = CLK_SET_PARENT_GATE, 1136 1136 }, ··· 1179 1179 .hw.init = &(struct clk_init_data){ 1180 1180 .name = "gsbi10_qup_src", 1181 1181 .parent_names = gcc_pxo_pll8, 1182 - .num_parents = 2, 1182 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1183 1183 .ops = &clk_rcg_ops, 1184 1184 .flags = CLK_SET_PARENT_GATE, 1185 1185 }, ··· 1228 1228 .hw.init = &(struct clk_init_data){ 1229 1229 .name = "gsbi11_qup_src", 1230 1230 .parent_names = gcc_pxo_pll8, 1231 - .num_parents = 2, 1231 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1232 1232 .ops = &clk_rcg_ops, 1233 1233 .flags = CLK_SET_PARENT_GATE, 1234 1234 }, ··· 1277 1277 .hw.init = &(struct clk_init_data){ 1278 1278 .name = "gsbi12_qup_src", 1279 1279 .parent_names = gcc_pxo_pll8, 1280 - .num_parents = 2, 1280 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1281 1281 .ops = &clk_rcg_ops, 1282 1282 .flags = CLK_SET_PARENT_GATE, 1283 1283 }, ··· 1339 1339 .hw.init = &(struct clk_init_data){ 1340 1340 .name = "gp0_src", 1341 1341 .parent_names = gcc_pxo_pll8_cxo, 1342 - .num_parents = 3, 1342 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1343 1343 .ops = &clk_rcg_ops, 1344 1344 .flags = CLK_SET_PARENT_GATE, 1345 1345 }, ··· 1388 1388 .hw.init = &(struct clk_init_data){ 1389 1389 .name = "gp1_src", 1390 1390 .parent_names = gcc_pxo_pll8_cxo, 1391 - .num_parents = 3, 1391 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1392 1392 .ops = &clk_rcg_ops, 1393 1393 .flags = CLK_SET_RATE_GATE, 1394 1394 }, ··· 1437 1437 .hw.init = &(struct clk_init_data){ 1438 1438 .name = "gp2_src", 1439 1439 .parent_names = gcc_pxo_pll8_cxo, 1440 - .num_parents = 3, 1440 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1441 1441 .ops = &clk_rcg_ops, 1442 1442 .flags = CLK_SET_RATE_GATE, 1443 1443 }, ··· 1489 1489 .init = &(struct clk_init_data){ 1490 1490 .name = "prng_src", 1491 1491 .parent_names = gcc_pxo_pll8, 1492 - .num_parents = 2, 1492 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1493 1493 .ops = &clk_rcg_ops, 1494 1494 }, 1495 1495 }, ··· 1548 1548 .hw.init = &(struct clk_init_data){ 1549 1549 .name = "sdc1_src", 1550 1550 .parent_names = gcc_pxo_pll8, 1551 - .num_parents = 2, 1551 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1552 1552 .ops = &clk_rcg_ops, 1553 1553 }, 1554 1554 } ··· 1596 1596 .hw.init = &(struct clk_init_data){ 1597 1597 .name = "sdc2_src", 1598 1598 .parent_names = gcc_pxo_pll8, 1599 - .num_parents = 2, 1599 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1600 1600 .ops = &clk_rcg_ops, 1601 1601 }, 1602 1602 } ··· 1644 1644 .hw.init = &(struct clk_init_data){ 1645 1645 .name = "sdc3_src", 1646 1646 .parent_names = gcc_pxo_pll8, 1647 - .num_parents = 2, 1647 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1648 1648 .ops = &clk_rcg_ops, 1649 1649 }, 1650 1650 } ··· 1692 1692 .hw.init = &(struct clk_init_data){ 1693 1693 .name = "sdc4_src", 1694 1694 .parent_names = gcc_pxo_pll8, 1695 - .num_parents = 2, 1695 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1696 1696 .ops = &clk_rcg_ops, 1697 1697 }, 1698 1698 } ··· 1740 1740 .hw.init = &(struct clk_init_data){ 1741 1741 .name = "sdc5_src", 1742 1742 .parent_names = gcc_pxo_pll8, 1743 - .num_parents = 2, 1743 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1744 1744 .ops = &clk_rcg_ops, 1745 1745 }, 1746 1746 } ··· 1793 1793 .hw.init = &(struct clk_init_data){ 1794 1794 .name = "tsif_ref_src", 1795 1795 .parent_names = gcc_pxo_pll8, 1796 - .num_parents = 2, 1796 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1797 1797 .ops = &clk_rcg_ops, 1798 1798 .flags = CLK_SET_RATE_GATE, 1799 1799 }, ··· 1847 1847 .hw.init = &(struct clk_init_data){ 1848 1848 .name = "usb_hs1_xcvr_src", 1849 1849 .parent_names = gcc_pxo_pll8, 1850 - .num_parents = 2, 1850 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1851 1851 .ops = &clk_rcg_ops, 1852 1852 .flags = CLK_SET_RATE_GATE, 1853 1853 }, ··· 1896 1896 .hw.init = &(struct clk_init_data){ 1897 1897 .name = "usb_fs1_xcvr_fs_src", 1898 1898 .parent_names = gcc_pxo_pll8, 1899 - .num_parents = 2, 1899 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1900 1900 .ops = &clk_rcg_ops, 1901 1901 .flags = CLK_SET_RATE_GATE, 1902 1902 }, ··· 1914 1914 .hw.init = &(struct clk_init_data){ 1915 1915 .name = "usb_fs1_xcvr_fs_clk", 1916 1916 .parent_names = usb_fs1_xcvr_fs_src_p, 1917 - .num_parents = 1, 1917 + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 1918 1918 .ops = &clk_branch_ops, 1919 1919 .flags = CLK_SET_RATE_PARENT, 1920 1920 }, ··· 1929 1929 .enable_mask = BIT(4), 1930 1930 .hw.init = &(struct clk_init_data){ 1931 1931 .parent_names = usb_fs1_xcvr_fs_src_p, 1932 - .num_parents = 1, 1932 + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), 1933 1933 .name = "usb_fs1_system_clk", 1934 1934 .ops = &clk_branch_ops, 1935 1935 .flags = CLK_SET_RATE_PARENT, ··· 1963 1963 .hw.init = &(struct clk_init_data){ 1964 1964 .name = "usb_fs2_xcvr_fs_src", 1965 1965 .parent_names = gcc_pxo_pll8, 1966 - .num_parents = 2, 1966 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1967 1967 .ops = &clk_rcg_ops, 1968 1968 .flags = CLK_SET_RATE_GATE, 1969 1969 }, ··· 1981 1981 .hw.init = &(struct clk_init_data){ 1982 1982 .name = "usb_fs2_xcvr_fs_clk", 1983 1983 .parent_names = usb_fs2_xcvr_fs_src_p, 1984 - .num_parents = 1, 1984 + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 1985 1985 .ops = &clk_branch_ops, 1986 1986 .flags = CLK_SET_RATE_PARENT, 1987 1987 }, ··· 1997 1997 .hw.init = &(struct clk_init_data){ 1998 1998 .name = "usb_fs2_system_clk", 1999 1999 .parent_names = usb_fs2_xcvr_fs_src_p, 2000 - .num_parents = 1, 2000 + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), 2001 2001 .ops = &clk_branch_ops, 2002 2002 .flags = CLK_SET_RATE_PARENT, 2003 2003 },