Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'skfp-cleanups'
Puranjay Mohan says:
====================
net: fddi: skfp: Use PCI generic definitions instead of private duplicates
This patch series removes the private duplicates of PCI definitions in
favour of generic definitions defined in pci_regs.h.
This driver only uses some of the generic PCI definitons,
which are included from pci_regs.h and thier private versions
are removed from skfbi.h with all other private defines.
The skfbi.h defines PCI_REV_ID and other private defines with different
names, these are renamed to Generic PCI names to make them
compatible with defines in pci_regs.h.
All unused defines are removed from skfbi.h.
Changes in v5:
Removed unused PCI definitions which were left in v4
Changes in v4:
Removed unused PCI definitions which were left in v3
Changes in v3:
Renamed all local PCI definitions to Generic names.
Corrected coding style mistakes.
Changes in v2:
Converted individual patches to a series.
Made sure that individual patches build correctly
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
+3
-225
+2
-1
drivers/net/fddi/skfp/drvfbi.c
+2
-1
drivers/net/fddi/skfp/drvfbi.c
···
20
20
#include "h/supern_2.h"
21
21
#include "h/skfbiinc.h"
22
22
#include <linux/bitrev.h>
23
+
#include <linux/pci_regs.h>
23
24
24
25
#ifndef lint
25
26
static const char ID_sccs[] = "@(#)drvfbi.c 1.63 99/02/11 (C) SK " ;
···
128
127
* at very first before any other initialization functions is
129
128
* executed.
130
129
*/
131
-
rev_id = inp(PCI_C(PCI_REV_ID)) ;
130
+
rev_id = inp(PCI_C(PCI_REVISION_ID)) ;
132
131
if ((rev_id & 0xf0) == SK_ML_ID_1 || (rev_id & 0xf0) == SK_ML_ID_2) {
133
132
smc->hw.hw_is_64bit = TRUE ;
134
133
} else {
+1
-224
drivers/net/fddi/skfp/h/skfbi.h
+1
-224
drivers/net/fddi/skfp/h/skfbi.h
···
24
24
* (ML) = only defined for Monalisa
25
25
*/
26
26
27
-
/*
28
-
* Configuration Space header
29
-
*/
30
-
#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
31
-
#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
32
-
#define PCI_COMMAND 0x04 /* 16 bit Command */
33
-
#define PCI_STATUS 0x06 /* 16 bit Status */
34
-
#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
35
-
#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
36
-
#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
37
-
#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
38
-
#define PCI_HEADER_T 0x0e /* 8 bit Header Type */
39
-
#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
40
-
#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
41
-
#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
42
-
/* Byte 18..2b: Reserved */
43
-
#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
44
-
#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
45
-
#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
46
-
/* Byte 34..33: Reserved */
47
-
#define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */
48
-
/* Byte 35..3b: Reserved */
49
-
#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
50
-
#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
51
-
#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
52
-
#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
53
-
/* Device Dependent Region */
54
-
#define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */
55
-
#define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */
56
-
#define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */
57
-
/* Power Management Region */
58
-
#define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */
59
-
#define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */
60
-
#define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */
61
-
#define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */
62
-
/* Byte 0x4e: Reserved */
63
-
#define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */
64
-
/* VPD Region */
65
-
#define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */
66
-
#define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */
67
-
#define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */
68
-
#define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */
69
-
/* Byte 58..ff: Reserved */
70
27
71
28
/*
72
29
* I2C Address (PCI Config)
···
33
76
*/
34
77
#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
35
78
36
-
/*
37
-
* Define Bits and Values of the registers
38
-
*/
39
-
/* PCI_VENDOR_ID 16 bit Vendor ID */
40
-
/* PCI_DEVICE_ID 16 bit Device ID */
41
-
/* Values for Vendor ID and Device ID shall be patched into the code */
42
-
/* PCI_COMMAND 16 bit Command */
43
-
#define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */
44
-
#define PCI_SERREN 0x0100 /* Bit 8: SERR enable */
45
-
#define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */
46
-
#define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */
47
-
#define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */
48
-
#define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */
49
-
#define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */
50
-
#define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */
51
-
#define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */
52
-
#define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */
53
79
54
-
/* PCI_STATUS 16 bit Status */
55
-
#define PCI_PERR 0x8000 /* Bit 15: Parity Error */
56
-
#define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */
57
-
#define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */
58
-
#define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */
59
-
#define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */
60
-
#define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */
61
-
#define PCI_DEV_FAST (0<<9) /* fast */
62
-
#define PCI_DEV_MEDIUM (1<<9) /* medium */
63
-
#define PCI_DEV_SLOW (2<<9) /* slow */
64
-
#define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */
65
-
#define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */
66
-
#define PCI_UDF 0x0040 /* Bit 6: User Defined Features */
67
-
#define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */
68
-
#define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */
80
+
#define PCI_ERRBITS (PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY)
69
81
70
-
#define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)
71
82
72
-
/* PCI_REV_ID 8 bit Revision ID */
73
-
/* PCI_CLASS_CODE 24 bit Class Code */
74
-
/* Byte 2: Base Class (02) */
75
-
/* Byte 1: SubClass (02) */
76
-
/* Byte 0: Programming Interface (00) */
77
-
78
-
/* PCI_CACHE_LSZ 8 bit Cache Line Size */
79
-
/* Possible values: 0,2,4,8,16 */
80
-
81
-
/* PCI_LAT_TIM 8 bit Latency Timer */
82
-
83
-
/* PCI_HEADER_T 8 bit Header Type */
84
-
#define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */
85
-
#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
86
-
87
-
/* PCI_BIST 8 bit Built-in selftest */
88
-
#define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */
89
-
#define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */
90
-
#define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */
91
-
92
-
/* PCI_BASE_1ST 32 bit 1st Base address */
93
-
#define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */
94
-
#define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */
95
-
#define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */
96
-
#define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */
97
-
#define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */
98
-
#define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */
99
-
#define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */
100
-
#define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */
101
-
#define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */
102
-
103
-
/* PCI_SUB_VID 16 bit Subsystem Vendor ID */
104
-
/* PCI_SUB_ID 16 bit Subsystem ID */
105
-
106
-
/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
107
-
#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */
108
-
#define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */
109
-
#define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */
110
-
#define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */
111
-
112
-
/* PCI_CAP_PTR 8 bit New Capabilities Pointers */
113
-
/* PCI_IRQ_LINE 8 bit Interrupt Line */
114
-
/* PCI_IRQ_PIN 8 bit Interrupt Pin */
115
-
/* PCI_MIN_GNT 8 bit Min_Gnt */
116
-
/* PCI_MAX_LAT 8 bit Max_Lat */
117
-
/* Device Dependent Region */
118
-
/* PCI_OUR_REG (DV) 32 bit Our Register */
119
-
/* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */
120
-
/* Bit 31..29: reserved */
121
-
#define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */
122
-
#define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */
123
-
#define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */
124
-
/* 1 = output */
125
-
#define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */
126
-
#define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */
127
-
#define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */
128
-
#define PCI_VIO (1L<<25) /*(ML) */
129
-
#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
130
-
/* 1 = Don't boot with ROM */
131
-
/* 0 = Boot with ROM */
132
-
#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
133
-
#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
134
-
/* 1 = Map Flash to Memory */
135
-
/* 0 = Disable all addr. decoding */
136
-
#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
137
-
#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
138
-
#define PCI_PAGE_32K (1L<<20) /* 32 k pages */
139
-
#define PCI_PAGE_64K (2L<<20) /* 64 k pages */
140
-
#define PCI_PAGE_128K (3L<<20) /* 128 k pages */
141
-
/* Bit 19: reserved (ML) and (DV) */
142
-
#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
143
-
/* Bit 15: reserved */
144
-
#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
145
-
#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
146
-
#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
147
-
#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
148
-
#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
149
-
#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
150
-
#define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */
151
-
#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */
152
-
#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
153
-
154
-
/* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */
155
-
#define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */
156
-
#define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */
157
-
#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */
158
-
/* Bit 12..13 reserved */
159
-
#define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */
160
-
#define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */
161
-
#define PCI_PATCH_DIR_3 (1L<<9)
162
-
#define PCI_PATCH_DIR_4 (1L<<10)
163
-
#define PCI_PATCH_DIR_5 (1L<<11)
164
-
#define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */
165
-
#define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */
166
-
#define PCI_EXT_PATCH_3 (1L<<5)
167
-
#define PCI_EXT_PATCH_4 (1L<<6)
168
-
#define PCI_EXT_PATCH_5 (1L<<7)
169
-
#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */
170
-
#define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */
171
-
#define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */
172
-
#define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/
173
-
174
-
/* Power Management Region */
175
-
/* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */
176
-
/* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */
177
-
/* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/
178
-
#define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/
179
-
#define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */
180
-
#define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */
181
-
/* Bit 6..8 reserved */
182
-
#define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/
183
-
#define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */
184
-
#define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */
185
-
#define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */
186
-
187
-
/* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */
188
-
#define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/
189
-
#define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */
190
-
#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */
191
-
/* Bit 7.. 2 reserved */
192
-
#define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */
193
-
#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
194
-
#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
195
-
#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */
196
-
#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */
197
-
198
-
/* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */
199
-
/* VPD Region */
200
-
/* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */
201
-
/* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */
202
-
/* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */
203
-
#define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/
204
-
205
-
/* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */
206
83
207
84
/*
208
85
* Control Register File:
···
664
873
#define T3_MUX (3<<2) /* Bit 3..2: Mux position */
665
874
#define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */
666
875
667
-
/* PCI card IDs */
668
-
/*
669
-
* Note: The following 4 byte definitions shall not be used! Use OEM Concept!
670
-
*/
671
-
#define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */
672
-
#define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */
673
-
/* (High byte) */
674
-
#define PCI_DEV_ID0 0x00 /* PCI device ID */
675
-
#define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */
676
-
677
-
/*#define PCI_CLASS 0x02*/ /* PCI class code: network device */
678
-
#define PCI_NW_CLASS 0x02 /* PCI class code: network device */
679
-
#define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */
680
-
#define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */
681
876
682
877
/*
683
878
* address transmission from logical to physical offset address on board