tjh.dev / kernel
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clk: rockchip: rk3568: Add PCIe pipe clock gates

The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use. In order
not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1772799641-32164-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Shawn Lin and committed by
Heiko Stuebner 41b1a676 3e65e426

+6
+6
drivers/clk/rockchip/clk-rk3568.c
··· 827 827 RK3568_CLKGATE_CON(12), 3, GFLAGS), 828 828 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, 829 829 RK3568_CLKGATE_CON(12), 4, GFLAGS), 830 + GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED, 831 + RK3568_CLKGATE_CON(12), 5, GFLAGS), 830 832 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, 831 833 RK3568_CLKGATE_CON(12), 8, GFLAGS), 832 834 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, ··· 839 837 RK3568_CLKGATE_CON(12), 11, GFLAGS), 840 838 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, 841 839 RK3568_CLKGATE_CON(12), 12, GFLAGS), 840 + GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED, 841 + RK3568_CLKGATE_CON(12), 13, GFLAGS), 842 842 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, 843 843 RK3568_CLKGATE_CON(13), 0, GFLAGS), 844 844 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, ··· 851 847 RK3568_CLKGATE_CON(13), 3, GFLAGS), 852 848 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, 853 849 RK3568_CLKGATE_CON(13), 4, GFLAGS), 850 + GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED, 851 + RK3568_CLKGATE_CON(13), 5, GFLAGS), 854 852 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, 855 853 RK3568_CLKGATE_CON(11), 0, GFLAGS), 856 854 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,