Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
- A fix for OMAP5 and DRA7 to make the branch predictor hardening
settings take proper effect on secondary cores
- Disable USB OTG on am3517 since current driver isn't working
- Fix thermal sensor register settings on Armada 38x
- Fix suspend/resume IRQs on pxa3xx
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: am3517.dtsi: Disable reference to OMAP3 OTG controller
ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores
ARM: pxa: irq: fix handling of ICMR registers in suspend/resume
ARM: dts: armada-38x: use the new thermal binding
+49
-3
+5
arch/arm/boot/dts/am3517.dtsi
+5
arch/arm/boot/dts/am3517.dtsi
+1
-1
arch/arm/boot/dts/armada-38x.dtsi
+1
-1
arch/arm/boot/dts/armada-38x.dtsi
+41
arch/arm/mach-omap2/omap-smp.c
+41
arch/arm/mach-omap2/omap-smp.c
···
109
109
static inline void omap5_erratum_workaround_801819(void) { }
110
110
#endif
111
111
112
+
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
113
+
/*
114
+
* Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
115
+
* ICIALLU) to activate the workaround for secondary Core.
116
+
* NOTE: it is assumed that the primary core's configuration is done
117
+
* by the boot loader (kernel will detect a misconfiguration and complain
118
+
* if this is not done).
119
+
*
120
+
* In General Purpose(GP) devices, ACR bit settings can only be done
121
+
* by ROM code in "secure world" using the smc call and there is no
122
+
* option to update the "firmware" on such devices. This also works for
123
+
* High security(HS) devices, as a backup option in case the
124
+
* "update" is not done in the "security firmware".
125
+
*/
126
+
static void omap5_secondary_harden_predictor(void)
127
+
{
128
+
u32 acr, acr_mask;
129
+
130
+
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
131
+
132
+
/*
133
+
* ACTLR[0] (Enable invalidates of BTB with ICIALLU)
134
+
*/
135
+
acr_mask = BIT(0);
136
+
137
+
/* Do we already have it done.. if yes, skip expensive smc */
138
+
if ((acr & acr_mask) == acr_mask)
139
+
return;
140
+
141
+
acr |= acr_mask;
142
+
omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
143
+
144
+
pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
145
+
__func__, smp_processor_id());
146
+
}
147
+
#else
148
+
static inline void omap5_secondary_harden_predictor(void) { }
149
+
#endif
150
+
112
151
static void omap4_secondary_init(unsigned int cpu)
113
152
{
114
153
/*
···
170
131
set_cntfreq();
171
132
/* Configure ACR to disable streaming WA for 801819 */
172
133
omap5_erratum_workaround_801819();
134
+
/* Enable ACR to allow for ICUALLU workaround */
135
+
omap5_secondary_harden_predictor();
173
136
}
174
137
175
138
/*
+2
-2
arch/arm/mach-pxa/irq.c
+2
-2
arch/arm/mach-pxa/irq.c
···
185
185
{
186
186
int i;
187
187
188
-
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
188
+
for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
189
189
void __iomem *base = irq_base(i);
190
190
191
191
saved_icmr[i] = __raw_readl(base + ICMR);
···
204
204
{
205
205
int i;
206
206
207
-
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
207
+
for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
208
208
void __iomem *base = irq_base(i);
209
209
210
210
__raw_writel(saved_icmr[i], base + ICMR);