Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.18, please pull the following:
- Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi
- Ivan adds the pin controller node(s), an additional GPIO controller,
the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for
Bluetooth to the BCM2712 DTS (Raspberry Pi 5)
- Stanimir adds the Ethernet DT node and enables it for the RP1 sister
chip
- Andrea deletes a number of redundant PCIe DT node enablement, updates
a comment to describe the relationship between bcm2712 and RP1 and
finally enables the USB controllers with RP1
* tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Enable USB devicetree entries for Rpi5
arm64: dts: broadcom: rp1: Add USB nodes
arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
arm64: dts: broadcom: delete redundant pcie enablement nodes
arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5
arm64: dts: rp1: Add ethernet DT node
dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller
arm64: dts: broadcom: bcm2712: Add UARTA controller node
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
arm64: dts: broadcom: bcm2712: Add one more GPIO node
arm64: dts: broadcom: bcm2712: Add pin controller nodes
arm64: dts: broadcom: bcm2712: Add default GIC address cells
Link: https://lore.kernel.org/r/20250910171910.666401-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+271
-5
+1
-1
Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
+1
-1
Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
+133
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
+133
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
···
2
2
/dts-v1/;
3
3
4
4
#include <dt-bindings/gpio/gpio.h>
5
+
#include <dt-bindings/input/input.h>
5
6
#include "bcm2712.dtsi"
6
7
7
8
/ {
···
30
29
reg = <0 0 0 0x28000000>;
31
30
};
32
31
32
+
gpio-keys {
33
+
compatible = "gpio-keys";
34
+
pinctrl-names = "default";
35
+
pinctrl-0 = <&pwr_button_default>;
36
+
status = "okay";
37
+
38
+
power_button: power-button {
39
+
label = "pwr_button";
40
+
linux,code = <KEY_POWER>;
41
+
gpios = <&gio 20 GPIO_ACTIVE_LOW>;
42
+
debounce-interval = <50>;
43
+
};
44
+
};
45
+
33
46
sd_io_1v8_reg: sd-io-1v8-reg {
34
47
compatible = "regulator-gpio";
35
48
regulator-name = "vdd-sd-io";
···
66
51
enable-active-high;
67
52
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
68
53
};
54
+
55
+
wl_on_reg: wl-on-reg {
56
+
compatible = "regulator-fixed";
57
+
regulator-name = "wl-on-regulator";
58
+
regulator-min-microvolt = <3300000>;
59
+
regulator-max-microvolt = <3300000>;
60
+
pinctrl-0 = <&wl_on_default>;
61
+
pinctrl-names = "default";
62
+
gpio = <&gio 28 GPIO_ACTIVE_HIGH>;
63
+
startup-delay-us = <150000>;
64
+
enable-active-high;
65
+
};
66
+
};
67
+
68
+
&pinctrl {
69
+
bt_shutdown_default: bt-shutdown-default-state {
70
+
function = "gpio";
71
+
pins = "gpio29";
72
+
};
73
+
74
+
emmc_sd_default: emmc-sd-default-state {
75
+
pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
76
+
bias-pull-up;
77
+
};
78
+
79
+
pwr_button_default: pwr-button-default-state {
80
+
function = "gpio";
81
+
pins = "gpio20";
82
+
bias-pull-up;
83
+
};
84
+
85
+
sdio2_30_default: sdio2-30-default-state {
86
+
clk-pins {
87
+
function = "sd2";
88
+
pins = "gpio30";
89
+
bias-disable;
90
+
};
91
+
cmd-pins {
92
+
function = "sd2";
93
+
pins = "gpio31";
94
+
bias-pull-up;
95
+
};
96
+
dat-pins {
97
+
function = "sd2";
98
+
pins = "gpio32", "gpio33", "gpio34", "gpio35";
99
+
bias-pull-up;
100
+
};
101
+
};
102
+
103
+
uarta_24_default: uarta-24-default-state {
104
+
rts-pins {
105
+
function = "uart0";
106
+
pins = "gpio24";
107
+
bias-disable;
108
+
};
109
+
cts-pins {
110
+
function = "uart0";
111
+
pins = "gpio25";
112
+
bias-pull-up;
113
+
};
114
+
txd-pins {
115
+
function = "uart0";
116
+
pins = "gpio26";
117
+
bias-disable;
118
+
};
119
+
rxd-pins {
120
+
function = "uart0";
121
+
pins = "gpio27";
122
+
bias-pull-up;
123
+
};
124
+
};
125
+
126
+
wl_on_default: wl-on-default-state {
127
+
function = "gpio";
128
+
pins = "gpio28";
129
+
};
130
+
};
131
+
132
+
&pinctrl_aon {
133
+
emmc_aon_cd_default: emmc-aon-cd-default-state {
134
+
function = "sd_card_g";
135
+
pins = "aon_gpio5";
136
+
bias-pull-up;
137
+
};
69
138
};
70
139
71
140
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
···
161
62
162
63
/* SDIO1 is used to drive the SD card */
163
64
&sdio1 {
65
+
pinctrl-0 = <&emmc_sd_default>, <&emmc_aon_cd_default>;
66
+
pinctrl-names = "default";
164
67
vqmmc-supply = <&sd_io_1v8_reg>;
165
68
vmmc-supply = <&sd_vcc_reg>;
166
69
bus-width = <4>;
167
70
sd-uhs-sdr50;
168
71
sd-uhs-ddr50;
169
72
sd-uhs-sdr104;
73
+
cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
74
+
};
75
+
76
+
&sdio2 {
77
+
pinctrl-0 = <&sdio2_30_default>;
78
+
pinctrl-names = "default";
79
+
bus-width = <4>;
80
+
vmmc-supply = <&wl_on_reg>;
81
+
sd-uhs-ddr50;
82
+
non-removable;
83
+
status = "okay";
84
+
#address-cells = <1>;
85
+
#size-cells = <0>;
86
+
87
+
wifi: wifi@1 {
88
+
reg = <1>;
89
+
compatible = "brcm,bcm4329-fmac";
90
+
};
170
91
};
171
92
172
93
&soc {
···
213
94
compatible = "raspberrypi,bcm2835-power";
214
95
firmware = <&firmware>;
215
96
#power-domain-cells = <1>;
97
+
};
98
+
};
99
+
100
+
/* uarta communicates with the BT module */
101
+
&uarta {
102
+
uart-has-rtscts;
103
+
pinctrl-0 = <&uarta_24_default &bt_shutdown_default>;
104
+
pinctrl-names = "default";
105
+
status = "okay";
106
+
107
+
bluetooth: bluetooth {
108
+
compatible = "brcm,bcm43438-bt";
109
+
max-speed = <3000000>;
110
+
shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
216
111
};
217
112
};
218
113
+37
-4
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+37
-4
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
···
4
4
* the RP1 driver to load the RP1 dtb overlay at runtime, while
5
5
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
6
6
* already contains RP1 node, so no overlay is loaded nor needed).
7
-
* This file is not intended to be modified, nodes should be added
8
-
* to the included bcm2712-rpi-5-b-ovl-rp1.dts.
7
+
* This file is intended to host the override nodes for the RP1 peripherals,
8
+
* e.g. to declare the phy of the ethernet interface or the custom pin setup
9
+
* for several RP1 peripherals.
10
+
* This in turn is due to the fact that there's no current generic
11
+
* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
12
+
* are not yet defined in the DT since they are loaded at runtime via overlay.
13
+
* All other nodes that do not have anything to do with RP1 should be added
14
+
* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
9
15
*/
10
16
11
17
/dts-v1/;
···
22
16
#include "rp1-nexus.dtsi"
23
17
};
24
18
25
-
&pcie1 {
19
+
&rp1_eth {
20
+
status = "okay";
21
+
phy-mode = "rgmii-id";
22
+
phy-handle = <&phy1>;
23
+
24
+
mdio {
25
+
reg = <0x1>;
26
+
reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>;
27
+
reset-delay-us = <5000>;
28
+
#address-cells = <1>;
29
+
#size-cells = <0>;
30
+
31
+
phy1: ethernet-phy@1 {
32
+
reg = <0x1>;
33
+
};
34
+
};
35
+
};
36
+
37
+
&rp1_gpio {
38
+
usb_vbus_default_state: usb-vbus-default-state {
39
+
function = "vbus1";
40
+
groups = "vbus1";
41
+
};
42
+
};
43
+
44
+
&rp1_usb0 {
45
+
pinctrl-0 = <&usb_vbus_default_state>;
46
+
pinctrl-names = "default";
26
47
status = "okay";
27
48
};
28
49
29
-
&pcie2 {
50
+
&rp1_usb1 {
30
51
status = "okay";
31
52
};
+56
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+56
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
···
38
38
clock-frequency = <200000000>;
39
39
clock-output-names = "emmc2-clock";
40
40
};
41
+
42
+
clk_sw_baud: clk-sw-baud {
43
+
compatible = "fixed-clock";
44
+
#clock-cells = <0>;
45
+
clock-frequency = <96000000>;
46
+
clock-output-names = "sw-baud";
47
+
};
41
48
};
42
49
43
50
cpus: cpus {
···
250
243
status = "disabled";
251
244
};
252
245
246
+
pinctrl: pinctrl@7d504100 {
247
+
compatible = "brcm,bcm2712c0-pinctrl";
248
+
reg = <0x7d504100 0x30>;
249
+
};
250
+
251
+
gio: gpio@7d508500 {
252
+
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
253
+
reg = <0x7d508500 0x40>;
254
+
interrupt-parent = <&main_irq>;
255
+
interrupts = <0>;
256
+
gpio-controller;
257
+
#gpio-cells = <2>;
258
+
interrupt-controller;
259
+
#interrupt-cells = <2>;
260
+
brcm,gpio-bank-widths = <32 22>;
261
+
};
262
+
263
+
uarta: serial@7d50c000 {
264
+
compatible = "brcm,bcm7271-uart";
265
+
reg = <0x7d50c000 0x20>;
266
+
reg-names = "uart";
267
+
clocks = <&clk_sw_baud>;
268
+
clock-names = "sw_baud";
269
+
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
270
+
interrupt-names = "uart";
271
+
status = "disabled";
272
+
};
273
+
274
+
pinctrl_aon: pinctrl@7d510700 {
275
+
compatible = "brcm,bcm2712c0-aon-pinctrl";
276
+
reg = <0x7d510700 0x20>;
277
+
};
278
+
253
279
interrupt-controller@7d517000 {
254
280
compatible = "brcm,bcm7271-l2-intc";
255
281
reg = <0x7d517000 0x10>;
···
303
263
*/
304
264
};
305
265
266
+
sdio2: mmc@1100000 {
267
+
compatible = "brcm,bcm2712-sdhci",
268
+
"brcm,sdhci-brcmstb";
269
+
reg = <0x01100000 0x260>,
270
+
<0x01100400 0x200>;
271
+
reg-names = "host", "cfg";
272
+
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
273
+
clocks = <&clk_emmc2>;
274
+
clock-names = "sw_sdio";
275
+
sdhci-caps-mask = <0x0000C000 0x0>;
276
+
sdhci-caps = <0x0 0x0>;
277
+
mmc-ddr-3_3v;
278
+
status = "disabled";
279
+
};
280
+
306
281
gicv2: interrupt-controller@7fff9000 {
307
282
compatible = "arm,gic-400";
308
283
reg = <0x7fff9000 0x1000>,
···
325
270
<0x7fffc000 0x2000>,
326
271
<0x7fffe000 0x2000>;
327
272
interrupt-controller;
273
+
#address-cells = <0>;
328
274
#interrupt-cells = <3>;
329
275
};
330
276
+44
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+44
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
···
39
39
<1 IRQ_TYPE_LEVEL_HIGH>,
40
40
<2 IRQ_TYPE_LEVEL_HIGH>;
41
41
};
42
+
43
+
rp1_eth: ethernet@40100000 {
44
+
compatible = "raspberrypi,rp1-gem";
45
+
reg = <0x00 0x40100000 0x0 0x4000>;
46
+
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
47
+
clocks = <&rp1_clocks RP1_CLK_SYS>,
48
+
<&rp1_clocks RP1_CLK_SYS>,
49
+
<&rp1_clocks RP1_CLK_ETH>,
50
+
<&rp1_clocks RP1_CLK_ETH_TSU>;
51
+
clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
52
+
local-mac-address = [00 00 00 00 00 00];
53
+
status = "disabled";
54
+
55
+
#address-cells = <1>;
56
+
#size-cells = <0>;
57
+
};
58
+
59
+
rp1_usb0: usb@40200000 {
60
+
compatible = "snps,dwc3";
61
+
reg = <0x00 0x40200000 0x0 0x100000>;
62
+
interrupts = <31 IRQ_TYPE_EDGE_RISING>;
63
+
dr_mode = "host";
64
+
usb3-lpm-capable;
65
+
snps,dis_rxdet_inp3_quirk;
66
+
snps,parkmode-disable-hs-quirk;
67
+
snps,parkmode-disable-ss-quirk;
68
+
snps,tx-max-burst = /bits/ 8 <8>;
69
+
snps,tx-thr-num-pkt = /bits/ 8 <2>;
70
+
status = "disabled";
71
+
};
72
+
73
+
rp1_usb1: usb@40300000 {
74
+
compatible = "snps,dwc3";
75
+
reg = <0x00 0x40300000 0x0 0x100000>;
76
+
interrupts = <36 IRQ_TYPE_EDGE_RISING>;
77
+
dr_mode = "host";
78
+
usb3-lpm-capable;
79
+
snps,dis_rxdet_inp3_quirk;
80
+
snps,parkmode-disable-hs-quirk;
81
+
snps,parkmode-disable-ss-quirk;
82
+
snps,tx-max-burst = /bits/ 8 <8>;
83
+
snps,tx-thr-num-pkt = /bits/ 8 <2>;
84
+
status = "disabled";
85
+
};
42
86
};