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kernel
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linux
phy: freescale: fsl-samsung-hdmi: Refactor finding PHY settings
There are two functions, round_rate and set_rate that duplicate
a lot of the same work, so simplify the code by creating a helper
function that will identify the phy settings for a desired clock
rate and return the structure with the corresponding settings.
>From this structure, the round_rate and set_rate can both get what
they need to achieve the clock setting closest to the desired rate
as possible while minimizing the duplicated code.
Also rename phy_clk_set_rate to fsl_samsung_hdmi_phy_clk_set_rate.
Suggested-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20250504204043.418924-2-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Adam Ford
and committed by
Vinod Koul
41db4623
be79213b
+42
-66
+42
-66
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+42
-66
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
···
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int i, ret;
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u8 val;
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+
phy->cur_cfg = cfg;
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+
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/* HDMI PHY init */
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writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));
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···
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/* pll_div_regs 3-6 are fixed and pre-defined already */
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}
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-
static u32 fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate,
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u32 int_div_clk, u32 frac_div_clk)
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{
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/* Calculate the absolute value of the differences and return whichever is closest */
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if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_div_clk)))
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return int_div_clk;
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-
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return frac_div_clk;
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-
}
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-
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static long fsl_samsung_hdmi_phy_clk_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate)
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static
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const struct phy_config *fsl_samsung_hdmi_phy_find_settings(struct fsl_samsung_hdmi_phy *phy,
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unsigned long rate)
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{
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const struct phy_config *fract_div_phy;
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u32 int_div_clk;
···
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/* If the clock is out of range return error instead of searching */
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if (rate > 297000000 || rate < 22250000)
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-
return -EINVAL;
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+
return NULL;
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/* Search the fractional divider lookup table */
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fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
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if (fract_div_phy->pixclk == rate) {
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dev_dbg(phy->dev, "fractional divider match = %u\n", fract_div_phy->pixclk);
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return fract_div_phy;
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}
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-
/* If the rate is an exact match, return that value */
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if (rate == fract_div_phy->pixclk)
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return fract_div_phy->pixclk;
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-
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-
/* If the exact match isn't found, calculate the integer divider */
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+
/* Calculate the integer divider */
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int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
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fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s);
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if (int_div_clk == rate) {
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dev_dbg(phy->dev, "integer divider match = %u\n", calculated_phy_pll_cfg.pixclk);
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return &calculated_phy_pll_cfg;
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}
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/* If the int_div_clk rate is an exact match, return that value */
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if (int_div_clk == rate)
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return int_div_clk;
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+
/* Calculate the absolute value of the differences and return whichever is closest */
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if (abs((long)rate - (long)int_div_clk) <
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abs((long)rate - (long)fract_div_phy->pixclk)) {
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dev_dbg(phy->dev, "integer divider = %u\n", calculated_phy_pll_cfg.pixclk);
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return &calculated_phy_pll_cfg;
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+
}
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-
/* If neither rate is an exact match, use the value from the LUT */
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-
return fract_div_phy->pixclk;
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dev_dbg(phy->dev, "fractional divider = %u\n", phy->cur_cfg->pixclk);
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+
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return fract_div_phy;
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}
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-
static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy)
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static long fsl_samsung_hdmi_phy_clk_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate)
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{
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phy->cur_cfg = fract_div_phy;
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dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n",
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phy->cur_cfg->pixclk);
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return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
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+
struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
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const struct phy_config *target_settings = fsl_samsung_hdmi_phy_find_settings(phy, rate);
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+
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if (target_settings == NULL)
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return -EINVAL;
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+
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dev_dbg(phy->dev, "round_rate, closest rate = %u\n", target_settings->pixclk);
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return target_settings->pixclk;
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}
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-
static int phy_use_integer_div(struct fsl_samsung_hdmi_phy *phy,
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const struct phy_config *int_div_clk)
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-
{
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phy->cur_cfg = &calculated_phy_pll_cfg;
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dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n",
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phy->cur_cfg->pixclk);
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return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
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-
}
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-
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static int phy_clk_set_rate(struct clk_hw *hw,
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static int fsl_samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
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const struct phy_config *fract_div_phy;
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u32 int_div_clk;
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u16 m;
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u8 p, s;
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const struct phy_config *target_settings = fsl_samsung_hdmi_phy_find_settings(phy, rate);
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/* Search the fractional divider lookup table */
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fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
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if (target_settings == NULL)
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return -EINVAL;
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/* If the rate is an exact match, use that value */
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if (fract_div_phy->pixclk == rate)
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return phy_use_fract_div(phy, fract_div_phy);
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dev_dbg(phy->dev, "set_rate, closest rate = %u\n", target_settings->pixclk);
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/*
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* If the rate from the fractional divider is not exact, check the integer divider,
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* and use it if that value is an exact match.
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*/
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int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
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fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s);
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if (int_div_clk == rate)
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return phy_use_integer_div(phy, &calculated_phy_pll_cfg);
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-
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/*
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* Compare the difference between the integer clock and the fractional clock against
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* the desired clock and which whichever is closest.
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*/
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if (fsl_samsung_hdmi_phy_get_closest_rate(rate, int_div_clk,
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fract_div_phy->pixclk) == fract_div_phy->pixclk)
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return phy_use_fract_div(phy, fract_div_phy);
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else
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return phy_use_integer_div(phy, &calculated_phy_pll_cfg);
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return fsl_samsung_hdmi_phy_configure(phy, target_settings);
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}
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static const struct clk_ops phy_clk_ops = {
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.recalc_rate = phy_clk_recalc_rate,
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.round_rate = fsl_samsung_hdmi_phy_clk_round_rate,
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.set_rate = phy_clk_set_rate,
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.set_rate = fsl_samsung_hdmi_phy_clk_set_rate,
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};
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static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)