tjh.dev / kernel
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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

Pull ARM fixes from Russell King:
"A set of ARM fixes:

- fix an off-by-one error in the iommu DMA ops, which caused errors
with a 4GiB size.

- remove comments mentioning the non-existent CONFIG_CPU_ARM1020_CPU_IDLE
macro.

- remove useless CONFIG_CPU_ICACHE_STREAMING_DISABLE blocks, where
this symbol never appeared in any Kconfig.

- fix Feroceon code to cope with a previous change correctly (it
incorrectly left an additional word in an assembly structure
definition)

- avoid a misleading IRQ affinity warning in the ARM PMU code for
IRQs which are already affine to their CPUs.

- fix the node name printed in the IRQ affinity warning"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8352/1: perf: Fix the pmu node name in warning message
ARM: 8351/1: perf: don't warn about missing interrupt-affinity property for PPIs
ARM: 8350/1: proc-feroceon: Fix feroceon_proc_info macro
ARM: 8349/1: arch/arm/mm/proc-arm925.S: remove dead #ifdef block
ARM: 8348/1: remove comments on CPU_ARM1020_CPU_IDLE
ARM: 8347/1: dma-mapping: fix off-by-one check in arm_setup_iommu_dma_ops

Linus Torvalds 41f2a93c 8425ac7a

+13 -19
+1 -1
arch/arm/include/asm/dma-iommu.h
··· 25 25 }; 26 26 27 27 struct dma_iommu_mapping * 28 - arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size); 28 + arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size); 29 29 30 30 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping); 31 31
+7 -2
arch/arm/kernel/perf_event_cpu.c
··· 303 303 304 304 static int of_pmu_irq_cfg(struct platform_device *pdev) 305 305 { 306 - int i; 306 + int i, irq; 307 307 int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); 308 308 309 309 if (!irqs) 310 310 return -ENOMEM; 311 + 312 + /* Don't bother with PPIs; they're already affine */ 313 + irq = platform_get_irq(pdev, 0); 314 + if (irq >= 0 && irq_is_percpu(irq)) 315 + return 0; 311 316 312 317 for (i = 0; i < pdev->num_resources; ++i) { 313 318 struct device_node *dn; ··· 322 317 i); 323 318 if (!dn) { 324 319 pr_warn("Failed to parse %s/interrupt-affinity[%d]\n", 325 - of_node_full_name(dn), i); 320 + of_node_full_name(pdev->dev.of_node), i); 326 321 break; 327 322 } 328 323
+5 -8
arch/arm/mm/dma-mapping.c
··· 1878 1878 * arm_iommu_attach_device function. 1879 1879 */ 1880 1880 struct dma_iommu_mapping * 1881 - arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) 1881 + arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) 1882 1882 { 1883 1883 unsigned int bits = size >> PAGE_SHIFT; 1884 1884 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); 1885 1885 struct dma_iommu_mapping *mapping; 1886 1886 int extensions = 1; 1887 1887 int err = -ENOMEM; 1888 + 1889 + /* currently only 32-bit DMA address space is supported */ 1890 + if (size > DMA_BIT_MASK(32) + 1) 1891 + return ERR_PTR(-ERANGE); 1888 1892 1889 1893 if (!bitmap_size) 1890 1894 return ERR_PTR(-EINVAL); ··· 2059 2055 struct dma_iommu_mapping *mapping; 2060 2056 2061 2057 if (!iommu) 2062 - return false; 2063 - 2064 - /* 2065 - * currently arm_iommu_create_mapping() takes a max of size_t 2066 - * for size param. So check this limit for now. 2067 - */ 2068 - if (size > SIZE_MAX) 2069 2058 return false; 2070 2059 2071 2060 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
-2
arch/arm/mm/proc-arm1020.S
··· 22 22 * 23 23 * These are the low level assembler for performing cache and TLB 24 24 * functions on the arm1020. 25 - * 26 - * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 25 */ 28 26 #include <linux/linkage.h> 29 27 #include <linux/init.h>
-2
arch/arm/mm/proc-arm1020e.S
··· 22 22 * 23 23 * These are the low level assembler for performing cache and TLB 24 24 * functions on the arm1020e. 25 - * 26 - * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 25 */ 28 26 #include <linux/linkage.h> 29 27 #include <linux/init.h>
-3
arch/arm/mm/proc-arm925.S
··· 441 441 .type __arm925_setup, #function 442 442 __arm925_setup: 443 443 mov r0, #0 444 - #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE) 445 - orr r0,r0,#1 << 7 446 - #endif 447 444 448 445 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */ 449 446 orr r0,r0,#1 << 1 @ transparent mode on
-1
arch/arm/mm/proc-feroceon.S
··· 602 602 PMD_SECT_AP_WRITE | \ 603 603 PMD_SECT_AP_READ 604 604 initfn __feroceon_setup, __\name\()_proc_info 605 - .long __feroceon_setup 606 605 .long cpu_arch_name 607 606 .long cpu_elf_name 608 607 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP