+17 -9

drivers/char/agp/intel-agp.c

reviewed

··· 819 819 "Sandybridge", NULL, &intel_gen6_driver }, 820 820 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 821 821 "Sandybridge", NULL, &intel_gen6_driver }, 822 822 + { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG, 823 823 + "Sandybridge", NULL, &intel_gen6_driver }, 822 824 { 0, 0, NULL, NULL, NULL } 823 825 }; 824 826 825 827 static int __devinit intel_gmch_probe(struct pci_dev *pdev, 826 828 struct agp_bridge_data *bridge) 827 829 { 828 828 - int i; 830 830 + int i, mask; 831 831 + 829 832 bridge->driver = NULL; 830 833 831 834 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { ··· 848 845 849 846 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 850 847 851 851 - if (bridge->driver->mask_memory == intel_i965_mask_memory) { 852 852 - if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) 853 853 - dev_err(&intel_private.pcidev->dev, 854 854 - "set gfx device dma mask 36bit failed!\n"); 855 855 - else 856 856 - pci_set_consistent_dma_mask(intel_private.pcidev, 857 857 - DMA_BIT_MASK(36)); 858 858 - } 848 848 + if (bridge->driver->mask_memory == intel_gen6_mask_memory) 849 849 + mask = 40; 850 850 + else if (bridge->driver->mask_memory == intel_i965_mask_memory) 851 851 + mask = 36; 852 852 + else 853 853 + mask = 32; 854 854 + 855 855 + if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 856 856 + dev_err(&intel_private.pcidev->dev, 857 857 + "set gfx device dma mask %d-bit failed!\n", mask); 858 858 + else 859 859 + pci_set_consistent_dma_mask(intel_private.pcidev, 860 860 + DMA_BIT_MASK(mask)); 859 861 860 862 return 1; 861 863 }

+1

drivers/char/agp/intel-agp.h

reviewed

··· 204 204 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 205 205 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 206 206 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106 207 207 + #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG 0x0126 207 208 208 209 /* cover 915 and 945 variants */ 209 210 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \

+2

drivers/gpu/drm/i915/Makefile

reviewed

··· 8 8 i915_suspend.o \ 9 9 i915_gem.o \ 10 10 i915_gem_debug.o \ 11 11 + i915_gem_evict.o \ 11 12 i915_gem_tiling.o \ 12 13 i915_trace_points.o \ 13 14 intel_display.o \ ··· 19 18 intel_hdmi.o \ 20 19 intel_sdvo.o \ 21 20 intel_modes.o \ 21 21 + intel_panel.o \ 22 22 intel_i2c.o \ 23 23 intel_fb.o \ 24 24 intel_tv.o \

+2 -5

drivers/gpu/drm/i915/dvo.h

reviewed

··· 30 30 #include "intel_drv.h" 31 31 32 32 struct intel_dvo_device { 33 33 - char *name; 33 33 + const char *name; 34 34 int type; 35 35 /* DVOA/B/C output register */ 36 36 u32 dvo_reg; 37 37 /* GPIO register used for i2c bus to control this device */ 38 38 u32 gpio; 39 39 int slave_addr; 40 40 - struct i2c_adapter *i2c_bus; 41 40 42 41 const struct intel_dvo_dev_ops *dev_ops; 43 42 void *dev_priv; 44 44 - 45 45 - struct drm_display_mode *panel_fixed_mode; 46 46 - bool panel_wants_dither; 43 43 + struct i2c_adapter *i2c_bus; 47 44 }; 48 45 49 46 struct intel_dvo_dev_ops {

+3

drivers/gpu/drm/i915/i915_debugfs.c

reviewed

··· 467 467 } 468 468 } 469 469 470 470 + if (error->overlay) 471 471 + intel_overlay_print_error_state(m, error->overlay); 472 472 + 470 473 out: 471 474 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 472 475

+7

drivers/gpu/drm/i915/i915_dma.c

reviewed

··· 499 499 } 500 500 } 501 501 502 502 + 503 503 + if (IS_G4X(dev) || IS_IRONLAKE(dev)) { 504 504 + BEGIN_LP_RING(2); 505 505 + OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); 506 506 + OUT_RING(MI_NOOP); 507 507 + ADVANCE_LP_RING(); 508 508 + } 502 509 i915_emit_breadcrumb(dev); 503 510 504 511 return 0;

+1

drivers/gpu/drm/i915/i915_drv.c

reviewed

··· 181 181 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), 182 182 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), 183 183 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), 184 184 + INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), 184 185 {0, 0, 0} 185 186 }; 186 187

+33 -12

drivers/gpu/drm/i915/i915_drv.h

reviewed

··· 113 113 int enabled; 114 114 }; 115 115 116 116 + struct intel_overlay; 117 117 + struct intel_overlay_error_state; 118 118 + 116 119 struct drm_i915_master_private { 117 120 drm_local_map_t *sarea; 118 121 struct _drm_i915_sarea *sarea_priv; ··· 169 166 u32 purgeable:1; 170 167 } *active_bo; 171 168 u32 active_bo_count; 169 169 + struct intel_overlay_error_state *overlay; 172 170 }; 173 171 174 172 struct drm_i915_display_funcs { ··· 189 185 /* pll clock increase/decrease */ 190 186 /* clock gating init */ 191 187 }; 192 192 - 193 193 - struct intel_overlay; 194 188 195 189 struct intel_device_info { 196 190 u8 is_mobile : 1; ··· 244 242 struct pci_dev *bridge_dev; 245 243 struct intel_ring_buffer render_ring; 246 244 struct intel_ring_buffer bsd_ring; 245 245 + uint32_t next_seqno; 247 246 248 247 drm_dma_handle_t *status_page_dmah; 249 248 void *seqno_page; ··· 254 251 drm_local_map_t hws_map; 255 252 struct drm_gem_object *seqno_obj; 256 253 struct drm_gem_object *pwrctx; 254 254 + struct drm_gem_object *renderctx; 257 255 258 256 struct resource mch_res; 259 257 ··· 289 285 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 290 286 int vblank_pipe; 291 287 int num_pipe; 288 288 + u32 flush_rings; 289 289 + #define FLUSH_RENDER_RING 0x1 290 290 + #define FLUSH_BSD_RING 0x2 292 291 293 292 /* For hangcheck timer */ 294 293 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ ··· 575 568 */ 576 569 struct delayed_work retire_work; 577 570 578 578 - uint32_t next_gem_seqno; 579 579 - 580 571 /** 581 572 * Waiting sequence number, if any 582 573 */ ··· 615 610 struct sdvo_device_mapping sdvo_mappings[2]; 616 611 /* indicate whether the LVDS_BORDER should be enabled or not */ 617 612 unsigned int lvds_border_bits; 613 613 + /* Panel fitter placement and size for Ironlake+ */ 614 614 + u32 pch_pf_pos, pch_pf_size; 618 615 619 616 struct drm_crtc *plane_to_crtc_mapping[2]; 620 617 struct drm_crtc *pipe_to_crtc_mapping[2]; ··· 676 669 struct list_head list; 677 670 /** This object's place on GPU write list */ 678 671 struct list_head gpu_write_list; 672 672 + /** This object's place on eviction list */ 673 673 + struct list_head evict_list; 679 674 680 675 /** 681 676 * This is set if the object is on the active or flushing lists ··· 987 978 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 988 979 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 989 980 unsigned long end); 981 981 + int i915_gpu_idle(struct drm_device *dev); 990 982 int i915_gem_idle(struct drm_device *dev); 991 983 uint32_t i915_add_request(struct drm_device *dev, 992 984 struct drm_file *file_priv, ··· 1001 991 int write); 1002 992 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); 1003 993 int i915_gem_attach_phys_object(struct drm_device *dev, 1004 1004 - struct drm_gem_object *obj, int id); 994 994 + struct drm_gem_object *obj, 995 995 + int id, 996 996 + int align); 1005 997 void i915_gem_detach_phys_object(struct drm_device *dev, 1006 998 struct drm_gem_object *obj); 1007 999 void i915_gem_free_all_phys_object(struct drm_device *dev); ··· 1014 1002 1015 1003 void i915_gem_shrinker_init(void); 1016 1004 void i915_gem_shrinker_exit(void); 1005 1005 + 1006 1006 + /* i915_gem_evict.c */ 1007 1007 + int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); 1008 1008 + int i915_gem_evict_everything(struct drm_device *dev); 1009 1009 + int i915_gem_evict_inactive(struct drm_device *dev); 1017 1010 1018 1011 /* i915_gem_tiling.c */ 1019 1012 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); ··· 1083 1066 extern void intel_detect_pch (struct drm_device *dev); 1084 1067 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1085 1068 1069 1069 + /* overlay */ 1070 1070 + extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1071 1071 + extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1072 1072 + 1086 1073 /** 1087 1074 * Lock test for when it's just for synchronization of ring access. 1088 1075 * ··· 1113 1092 #define I915_VERBOSE 0 1114 1093 1115 1094 #define BEGIN_LP_RING(n) do { \ 1116 1116 - drm_i915_private_t *dev_priv = dev->dev_private; \ 1095 1095 + drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1117 1096 if (I915_VERBOSE) \ 1118 1097 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ 1119 1119 - intel_ring_begin(dev, &dev_priv->render_ring, (n)); \ 1098 1098 + intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ 1120 1099 } while (0) 1121 1100 1122 1101 1123 1102 #define OUT_RING(x) do { \ 1124 1124 - drm_i915_private_t *dev_priv = dev->dev_private; \ 1103 1103 + drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1125 1104 if (I915_VERBOSE) \ 1126 1105 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ 1127 1127 - intel_ring_emit(dev, &dev_priv->render_ring, x); \ 1106 1106 + intel_ring_emit(dev, &dev_priv__->render_ring, x); \ 1128 1107 } while (0) 1129 1108 1130 1109 #define ADVANCE_LP_RING() do { \ 1131 1131 - drm_i915_private_t *dev_priv = dev->dev_private; \ 1110 1110 + drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1132 1111 if (I915_VERBOSE) \ 1133 1112 DRM_DEBUG("ADVANCE_LP_RING %x\n", \ 1134 1134 - dev_priv->render_ring.tail); \ 1135 1135 - intel_ring_advance(dev, &dev_priv->render_ring); \ 1113 1113 + dev_priv__->render_ring.tail); \ 1114 1114 + intel_ring_advance(dev, &dev_priv__->render_ring); \ 1136 1115 } while(0) 1137 1116 1138 1117 /**

+93 -261

drivers/gpu/drm/i915/i915_gem.c

reviewed

··· 35 35 #include <linux/swap.h> 36 36 #include <linux/pci.h> 37 37 38 38 + static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); 38 39 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 39 40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 40 41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); ··· 49 48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, 50 49 unsigned alignment); 51 50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); 52 52 - static int i915_gem_evict_something(struct drm_device *dev, int min_size); 53 53 - static int i915_gem_evict_from_inactive_list(struct drm_device *dev); 54 51 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, 55 52 struct drm_i915_gem_pwrite *args, 56 53 struct drm_file *file_priv); ··· 56 57 57 58 static LIST_HEAD(shrink_list); 58 59 static DEFINE_SPINLOCK(shrink_list_lock); 60 60 + 61 61 + static inline bool 62 62 + i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) 63 63 + { 64 64 + return obj_priv->gtt_space && 65 65 + !obj_priv->active && 66 66 + obj_priv->pin_count == 0; 67 67 + } 59 68 60 69 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 61 70 unsigned long end) ··· 320 313 if (ret == -ENOMEM) { 321 314 struct drm_device *dev = obj->dev; 322 315 323 323 - ret = i915_gem_evict_something(dev, obj->size); 316 316 + ret = i915_gem_evict_something(dev, obj->size, 317 317 + i915_gem_get_gtt_alignment(obj)); 324 318 if (ret) 325 319 return ret; 326 320 ··· 1044 1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); 1045 1037 } 1046 1038 1039 1039 + 1040 1040 + /* Maintain LRU order of "inactive" objects */ 1041 1041 + if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) 1042 1042 + list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 1043 1043 + 1047 1044 drm_gem_object_unreference(obj); 1048 1045 mutex_unlock(&dev->struct_mutex); 1049 1046 return ret; ··· 1150 1137 { 1151 1138 struct drm_gem_object *obj = vma->vm_private_data; 1152 1139 struct drm_device *dev = obj->dev; 1153 1153 - struct drm_i915_private *dev_priv = dev->dev_private; 1140 1140 + drm_i915_private_t *dev_priv = dev->dev_private; 1154 1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 1155 1142 pgoff_t page_offset; 1156 1143 unsigned long pfn; ··· 1168 1155 if (ret) 1169 1156 goto unlock; 1170 1157 1171 1171 - list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 1172 1172 - 1173 1158 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1174 1159 if (ret) 1175 1160 goto unlock; ··· 1179 1168 if (ret) 1180 1169 goto unlock; 1181 1170 } 1171 1171 + 1172 1172 + if (i915_gem_object_is_inactive(obj_priv)) 1173 1173 + list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 1182 1174 1183 1175 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + 1184 1176 page_offset; ··· 1377 1363 struct drm_file *file_priv) 1378 1364 { 1379 1365 struct drm_i915_gem_mmap_gtt *args = data; 1380 1380 - struct drm_i915_private *dev_priv = dev->dev_private; 1381 1366 struct drm_gem_object *obj; 1382 1367 struct drm_i915_gem_object *obj_priv; 1383 1368 int ret; ··· 1422 1409 mutex_unlock(&dev->struct_mutex); 1423 1410 return ret; 1424 1411 } 1425 1425 - list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 1426 1412 } 1427 1413 1428 1414 drm_gem_object_unreference(obj); ··· 1505 1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 1506 1494 struct inode *inode; 1507 1495 1496 1496 + /* Our goal here is to return as much of the memory as 1497 1497 + * is possible back to the system as we are called from OOM. 1498 1498 + * To do this we must instruct the shmfs to drop all of its 1499 1499 + * backing pages, *now*. Here we mirror the actions taken 1500 1500 + * when by shmem_delete_inode() to release the backing store. 1501 1501 + */ 1508 1502 inode = obj->filp->f_path.dentry->d_inode; 1509 1509 - if (inode->i_op->truncate) 1510 1510 - inode->i_op->truncate (inode); 1503 1503 + truncate_inode_pages(inode->i_mapping, 0); 1504 1504 + if (inode->i_op->truncate_range) 1505 1505 + inode->i_op->truncate_range(inode, 0, (loff_t)-1); 1511 1506 1512 1507 obj_priv->madv = __I915_MADV_PURGED; 1513 1508 } ··· 1906 1887 flush_domains); 1907 1888 } 1908 1889 1909 1909 - static void 1910 1910 - i915_gem_flush_ring(struct drm_device *dev, 1911 1911 - uint32_t invalidate_domains, 1912 1912 - uint32_t flush_domains, 1913 1913 - struct intel_ring_buffer *ring) 1914 1914 - { 1915 1915 - if (flush_domains & I915_GEM_DOMAIN_CPU) 1916 1916 - drm_agp_chipset_flush(dev); 1917 1917 - ring->flush(dev, ring, 1918 1918 - invalidate_domains, 1919 1919 - flush_domains); 1920 1920 - } 1921 1921 - 1922 1890 /** 1923 1891 * Ensures that all rendering to the object has completed and the object is 1924 1892 * safe to unbind from the GTT or access from the CPU. ··· 1979 1973 * cause memory corruption through use-after-free. 1980 1974 */ 1981 1975 1982 1982 - BUG_ON(obj_priv->active); 1983 1983 - 1984 1976 /* release the fence reg _after_ flushing */ 1985 1977 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) 1986 1978 i915_gem_clear_fence_reg(obj); ··· 2014 2010 return ret; 2015 2011 } 2016 2012 2017 2017 - static struct drm_gem_object * 2018 2018 - i915_gem_find_inactive_object(struct drm_device *dev, int min_size) 2019 2019 - { 2020 2020 - drm_i915_private_t *dev_priv = dev->dev_private; 2021 2021 - struct drm_i915_gem_object *obj_priv; 2022 2022 - struct drm_gem_object *best = NULL; 2023 2023 - struct drm_gem_object *first = NULL; 2024 2024 - 2025 2025 - /* Try to find the smallest clean object */ 2026 2026 - list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { 2027 2027 - struct drm_gem_object *obj = &obj_priv->base; 2028 2028 - if (obj->size >= min_size) { 2029 2029 - if ((!obj_priv->dirty || 2030 2030 - i915_gem_object_is_purgeable(obj_priv)) && 2031 2031 - (!best || obj->size < best->size)) { 2032 2032 - best = obj; 2033 2033 - if (best->size == min_size) 2034 2034 - return best; 2035 2035 - } 2036 2036 - if (!first) 2037 2037 - first = obj; 2038 2038 - } 2039 2039 - } 2040 2040 - 2041 2041 - return best ? best : first; 2042 2042 - } 2043 2043 - 2044 2044 - static int 2013 2013 + int 2045 2014 i915_gpu_idle(struct drm_device *dev) 2046 2015 { 2047 2016 drm_i915_private_t *dev_priv = dev->dev_private; ··· 2053 2076 2054 2077 2055 2078 return ret; 2056 2056 - } 2057 2057 - 2058 2058 - static int 2059 2059 - i915_gem_evict_everything(struct drm_device *dev) 2060 2060 - { 2061 2061 - drm_i915_private_t *dev_priv = dev->dev_private; 2062 2062 - int ret; 2063 2063 - bool lists_empty; 2064 2064 - 2065 2065 - spin_lock(&dev_priv->mm.active_list_lock); 2066 2066 - lists_empty = (list_empty(&dev_priv->mm.inactive_list) && 2067 2067 - list_empty(&dev_priv->mm.flushing_list) && 2068 2068 - list_empty(&dev_priv->render_ring.active_list) && 2069 2069 - (!HAS_BSD(dev) 2070 2070 - || list_empty(&dev_priv->bsd_ring.active_list))); 2071 2071 - spin_unlock(&dev_priv->mm.active_list_lock); 2072 2072 - 2073 2073 - if (lists_empty) 2074 2074 - return -ENOSPC; 2075 2075 - 2076 2076 - /* Flush everything (on to the inactive lists) and evict */ 2077 2077 - ret = i915_gpu_idle(dev); 2078 2078 - if (ret) 2079 2079 - return ret; 2080 2080 - 2081 2081 - BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); 2082 2082 - 2083 2083 - ret = i915_gem_evict_from_inactive_list(dev); 2084 2084 - if (ret) 2085 2085 - return ret; 2086 2086 - 2087 2087 - spin_lock(&dev_priv->mm.active_list_lock); 2088 2088 - lists_empty = (list_empty(&dev_priv->mm.inactive_list) && 2089 2089 - list_empty(&dev_priv->mm.flushing_list) && 2090 2090 - list_empty(&dev_priv->render_ring.active_list) && 2091 2091 - (!HAS_BSD(dev) 2092 2092 - || list_empty(&dev_priv->bsd_ring.active_list))); 2093 2093 - spin_unlock(&dev_priv->mm.active_list_lock); 2094 2094 - BUG_ON(!lists_empty); 2095 2095 - 2096 2096 - return 0; 2097 2097 - } 2098 2098 - 2099 2099 - static int 2100 2100 - i915_gem_evict_something(struct drm_device *dev, int min_size) 2101 2101 - { 2102 2102 - drm_i915_private_t *dev_priv = dev->dev_private; 2103 2103 - struct drm_gem_object *obj; 2104 2104 - int ret; 2105 2105 - 2106 2106 - struct intel_ring_buffer *render_ring = &dev_priv->render_ring; 2107 2107 - struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring; 2108 2108 - for (;;) { 2109 2109 - i915_gem_retire_requests(dev); 2110 2110 - 2111 2111 - /* If there's an inactive buffer available now, grab it 2112 2112 - * and be done. 2113 2113 - */ 2114 2114 - obj = i915_gem_find_inactive_object(dev, min_size); 2115 2115 - if (obj) { 2116 2116 - struct drm_i915_gem_object *obj_priv; 2117 2117 - 2118 2118 - #if WATCH_LRU 2119 2119 - DRM_INFO("%s: evicting %p\n", __func__, obj); 2120 2120 - #endif 2121 2121 - obj_priv = to_intel_bo(obj); 2122 2122 - BUG_ON(obj_priv->pin_count != 0); 2123 2123 - BUG_ON(obj_priv->active); 2124 2124 - 2125 2125 - /* Wait on the rendering and unbind the buffer. */ 2126 2126 - return i915_gem_object_unbind(obj); 2127 2127 - } 2128 2128 - 2129 2129 - /* If we didn't get anything, but the ring is still processing 2130 2130 - * things, wait for the next to finish and hopefully leave us 2131 2131 - * a buffer to evict. 2132 2132 - */ 2133 2133 - if (!list_empty(&render_ring->request_list)) { 2134 2134 - struct drm_i915_gem_request *request; 2135 2135 - 2136 2136 - request = list_first_entry(&render_ring->request_list, 2137 2137 - struct drm_i915_gem_request, 2138 2138 - list); 2139 2139 - 2140 2140 - ret = i915_wait_request(dev, 2141 2141 - request->seqno, request->ring); 2142 2142 - if (ret) 2143 2143 - return ret; 2144 2144 - 2145 2145 - continue; 2146 2146 - } 2147 2147 - 2148 2148 - if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) { 2149 2149 - struct drm_i915_gem_request *request; 2150 2150 - 2151 2151 - request = list_first_entry(&bsd_ring->request_list, 2152 2152 - struct drm_i915_gem_request, 2153 2153 - list); 2154 2154 - 2155 2155 - ret = i915_wait_request(dev, 2156 2156 - request->seqno, request->ring); 2157 2157 - if (ret) 2158 2158 - return ret; 2159 2159 - 2160 2160 - continue; 2161 2161 - } 2162 2162 - 2163 2163 - /* If we didn't have anything on the request list but there 2164 2164 - * are buffers awaiting a flush, emit one and try again. 2165 2165 - * When we wait on it, those buffers waiting for that flush 2166 2166 - * will get moved to inactive. 2167 2167 - */ 2168 2168 - if (!list_empty(&dev_priv->mm.flushing_list)) { 2169 2169 - struct drm_i915_gem_object *obj_priv; 2170 2170 - 2171 2171 - /* Find an object that we can immediately reuse */ 2172 2172 - list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { 2173 2173 - obj = &obj_priv->base; 2174 2174 - if (obj->size >= min_size) 2175 2175 - break; 2176 2176 - 2177 2177 - obj = NULL; 2178 2178 - } 2179 2179 - 2180 2180 - if (obj != NULL) { 2181 2181 - uint32_t seqno; 2182 2182 - 2183 2183 - i915_gem_flush_ring(dev, 2184 2184 - obj->write_domain, 2185 2185 - obj->write_domain, 2186 2186 - obj_priv->ring); 2187 2187 - seqno = i915_add_request(dev, NULL, 2188 2188 - obj->write_domain, 2189 2189 - obj_priv->ring); 2190 2190 - if (seqno == 0) 2191 2191 - return -ENOMEM; 2192 2192 - continue; 2193 2193 - } 2194 2194 - } 2195 2195 - 2196 2196 - /* If we didn't do any of the above, there's no single buffer 2197 2197 - * large enough to swap out for the new one, so just evict 2198 2198 - * everything and start again. (This should be rare.) 2199 2199 - */ 2200 2200 - if (!list_empty (&dev_priv->mm.inactive_list)) 2201 2201 - return i915_gem_evict_from_inactive_list(dev); 2202 2202 - else 2203 2203 - return i915_gem_evict_everything(dev); 2204 2204 - } 2205 2079 } 2206 2080 2207 2081 int ··· 2494 2666 #if WATCH_LRU 2495 2667 DRM_INFO("%s: GTT full, evicting something\n", __func__); 2496 2668 #endif 2497 2497 - ret = i915_gem_evict_something(dev, obj->size); 2669 2669 + ret = i915_gem_evict_something(dev, obj->size, alignment); 2498 2670 if (ret) 2499 2671 return ret; 2500 2672 ··· 2512 2684 2513 2685 if (ret == -ENOMEM) { 2514 2686 /* first try to clear up some space from the GTT */ 2515 2515 - ret = i915_gem_evict_something(dev, obj->size); 2687 2687 + ret = i915_gem_evict_something(dev, obj->size, 2688 2688 + alignment); 2516 2689 if (ret) { 2517 2690 /* now try to shrink everyone else */ 2518 2691 if (gfpmask) { ··· 2543 2714 drm_mm_put_block(obj_priv->gtt_space); 2544 2715 obj_priv->gtt_space = NULL; 2545 2716 2546 2546 - ret = i915_gem_evict_something(dev, obj->size); 2717 2717 + ret = i915_gem_evict_something(dev, obj->size, alignment); 2547 2718 if (ret) 2548 2719 return ret; 2549 2720 ··· 2551 2722 } 2552 2723 atomic_inc(&dev->gtt_count); 2553 2724 atomic_add(obj->size, &dev->gtt_memory); 2725 2725 + 2726 2726 + /* keep track of bounds object by adding it to the inactive list */ 2727 2727 + list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 2554 2728 2555 2729 /* Assert that the object is not currently in any GPU domain. As it 2556 2730 * wasn't in the GTT, there shouldn't be any way it could have been in ··· 2949 3117 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) 2950 3118 { 2951 3119 struct drm_device *dev = obj->dev; 3120 3120 + drm_i915_private_t *dev_priv = dev->dev_private; 2952 3121 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 2953 3122 uint32_t invalidate_domains = 0; 2954 3123 uint32_t flush_domains = 0; ··· 3011 3178 if (flush_domains == 0 && obj->pending_write_domain == 0) 3012 3179 obj->pending_write_domain = obj->write_domain; 3013 3180 obj->read_domains = obj->pending_read_domains; 3181 3181 + 3182 3182 + if (flush_domains & I915_GEM_GPU_DOMAINS) { 3183 3183 + if (obj_priv->ring == &dev_priv->render_ring) 3184 3184 + dev_priv->flush_rings |= FLUSH_RENDER_RING; 3185 3185 + else if (obj_priv->ring == &dev_priv->bsd_ring) 3186 3186 + dev_priv->flush_rings |= FLUSH_BSD_RING; 3187 3187 + } 3014 3188 3015 3189 dev->invalidate_domains |= invalidate_domains; 3016 3190 dev->flush_domains |= flush_domains; ··· 3558 3718 ring = &dev_priv->render_ring; 3559 3719 } 3560 3720 3561 3561 - 3562 3721 if (args->buffer_count < 1) { 3563 3722 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 3564 3723 return -EINVAL; ··· 3731 3892 */ 3732 3893 dev->invalidate_domains = 0; 3733 3894 dev->flush_domains = 0; 3895 3895 + dev_priv->flush_rings = 0; 3734 3896 3735 3897 for (i = 0; i < args->buffer_count; i++) { 3736 3898 struct drm_gem_object *obj = object_list[i]; ··· 3752 3912 i915_gem_flush(dev, 3753 3913 dev->invalidate_domains, 3754 3914 dev->flush_domains); 3755 3755 - if (dev->flush_domains & I915_GEM_GPU_DOMAINS) { 3915 3915 + if (dev_priv->flush_rings & FLUSH_RENDER_RING) 3756 3916 (void)i915_add_request(dev, file_priv, 3757 3757 - dev->flush_domains, 3758 3758 - &dev_priv->render_ring); 3759 3759 - 3760 3760 - if (HAS_BSD(dev)) 3761 3761 - (void)i915_add_request(dev, file_priv, 3762 3762 - dev->flush_domains, 3763 3763 - &dev_priv->bsd_ring); 3764 3764 - } 3917 3917 + dev->flush_domains, 3918 3918 + &dev_priv->render_ring); 3919 3919 + if (dev_priv->flush_rings & FLUSH_BSD_RING) 3920 3920 + (void)i915_add_request(dev, file_priv, 3921 3921 + dev->flush_domains, 3922 3922 + &dev_priv->bsd_ring); 3765 3923 } 3766 3924 3767 3925 for (i = 0; i < args->buffer_count; i++) { ··· 4030 4192 if (alignment == 0) 4031 4193 alignment = i915_gem_get_gtt_alignment(obj); 4032 4194 if (obj_priv->gtt_offset & (alignment - 1)) { 4195 4195 + WARN(obj_priv->pin_count, 4196 4196 + "bo is already pinned with incorrect alignment:" 4197 4197 + " offset=%x, req.alignment=%x\n", 4198 4198 + obj_priv->gtt_offset, alignment); 4033 4199 ret = i915_gem_object_unbind(obj); 4034 4200 if (ret) 4035 4201 return ret; ··· 4055 4213 atomic_inc(&dev->pin_count); 4056 4214 atomic_add(obj->size, &dev->pin_memory); 4057 4215 if (!obj_priv->active && 4058 4058 - (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && 4059 4059 - !list_empty(&obj_priv->list)) 4216 4216 + (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) 4060 4217 list_del_init(&obj_priv->list); 4061 4218 } 4062 4219 i915_verify_inactive(dev, __FILE__, __LINE__); ··· 4200 4359 } 4201 4360 4202 4361 mutex_lock(&dev->struct_mutex); 4203 4203 - /* Update the active list for the hardware's current position. 4204 4204 - * Otherwise this only updates on a delayed timer or when irqs are 4205 4205 - * actually unmasked, and our working set ends up being larger than 4206 4206 - * required. 4207 4207 - */ 4208 4208 - i915_gem_retire_requests(dev); 4209 4362 4210 4210 - obj_priv = to_intel_bo(obj); 4211 4211 - /* Don't count being on the flushing list against the object being 4212 4212 - * done. Otherwise, a buffer left on the flushing list but not getting 4213 4213 - * flushed (because nobody's flushing that domain) won't ever return 4214 4214 - * unbusy and get reused by libdrm's bo cache. The other expected 4215 4215 - * consumer of this interface, OpenGL's occlusion queries, also specs 4216 4216 - * that the objects get unbusy "eventually" without any interference. 4363 4363 + /* Count all active objects as busy, even if they are currently not used 4364 4364 + * by the gpu. Users of this interface expect objects to eventually 4365 4365 + * become non-busy without any further actions, therefore emit any 4366 4366 + * necessary flushes here. 4217 4367 */ 4218 4218 - args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; 4368 4368 + obj_priv = to_intel_bo(obj); 4369 4369 + args->busy = obj_priv->active; 4370 4370 + if (args->busy) { 4371 4371 + /* Unconditionally flush objects, even when the gpu still uses this 4372 4372 + * object. Userspace calling this function indicates that it wants to 4373 4373 + * use this buffer rather sooner than later, so issuing the required 4374 4374 + * flush earlier is beneficial. 4375 4375 + */ 4376 4376 + if (obj->write_domain) { 4377 4377 + i915_gem_flush(dev, 0, obj->write_domain); 4378 4378 + (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring); 4379 4379 + } 4380 4380 + 4381 4381 + /* Update the active list for the hardware's current position. 4382 4382 + * Otherwise this only updates on a delayed timer or when irqs 4383 4383 + * are actually unmasked, and our working set ends up being 4384 4384 + * larger than required. 4385 4385 + */ 4386 4386 + i915_gem_retire_requests_ring(dev, obj_priv->ring); 4387 4387 + 4388 4388 + args->busy = obj_priv->active; 4389 4389 + } 4219 4390 4220 4391 drm_gem_object_unreference(obj); 4221 4392 mutex_unlock(&dev->struct_mutex); ··· 4367 4514 i915_gem_free_object_tail(obj); 4368 4515 } 4369 4516 4370 4370 - /** Unbinds all inactive objects. */ 4371 4371 - static int 4372 4372 - i915_gem_evict_from_inactive_list(struct drm_device *dev) 4373 4373 - { 4374 4374 - drm_i915_private_t *dev_priv = dev->dev_private; 4375 4375 - 4376 4376 - while (!list_empty(&dev_priv->mm.inactive_list)) { 4377 4377 - struct drm_gem_object *obj; 4378 4378 - int ret; 4379 4379 - 4380 4380 - obj = &list_first_entry(&dev_priv->mm.inactive_list, 4381 4381 - struct drm_i915_gem_object, 4382 4382 - list)->base; 4383 4383 - 4384 4384 - ret = i915_gem_object_unbind(obj); 4385 4385 - if (ret != 0) { 4386 4386 - DRM_ERROR("Error unbinding object: %d\n", ret); 4387 4387 - return ret; 4388 4388 - } 4389 4389 - } 4390 4390 - 4391 4391 - return 0; 4392 4392 - } 4393 4393 - 4394 4517 int 4395 4518 i915_gem_idle(struct drm_device *dev) 4396 4519 { ··· 4391 4562 4392 4563 /* Under UMS, be paranoid and evict. */ 4393 4564 if (!drm_core_check_feature(dev, DRIVER_MODESET)) { 4394 4394 - ret = i915_gem_evict_from_inactive_list(dev); 4565 4565 + ret = i915_gem_evict_inactive(dev); 4395 4566 if (ret) { 4396 4567 mutex_unlock(&dev->struct_mutex); 4397 4568 return ret; ··· 4508 4679 if (ret) 4509 4680 goto cleanup_render_ring; 4510 4681 } 4682 4682 + 4683 4683 + dev_priv->next_seqno = 1; 4511 4684 4512 4685 return 0; 4513 4686 ··· 4672 4841 * e.g. for cursor + overlay regs 4673 4842 */ 4674 4843 int i915_gem_init_phys_object(struct drm_device *dev, 4675 4675 - int id, int size) 4844 4844 + int id, int size, int align) 4676 4845 { 4677 4846 drm_i915_private_t *dev_priv = dev->dev_private; 4678 4847 struct drm_i915_gem_phys_object *phys_obj; ··· 4687 4856 4688 4857 phys_obj->id = id; 4689 4858 4690 4690 - phys_obj->handle = drm_pci_alloc(dev, size, 0); 4859 4859 + phys_obj->handle = drm_pci_alloc(dev, size, align); 4691 4860 if (!phys_obj->handle) { 4692 4861 ret = -ENOMEM; 4693 4862 goto kfree_obj; ··· 4769 4938 4770 4939 int 4771 4940 i915_gem_attach_phys_object(struct drm_device *dev, 4772 4772 - struct drm_gem_object *obj, int id) 4941 4941 + struct drm_gem_object *obj, 4942 4942 + int id, 4943 4943 + int align) 4773 4944 { 4774 4945 drm_i915_private_t *dev_priv = dev->dev_private; 4775 4946 struct drm_i915_gem_object *obj_priv; ··· 4790 4957 i915_gem_detach_phys_object(dev, obj); 4791 4958 } 4792 4959 4793 4793 - 4794 4960 /* create a new object */ 4795 4961 if (!dev_priv->mm.phys_objs[id - 1]) { 4796 4962 ret = i915_gem_init_phys_object(dev, id, 4797 4797 - obj->size); 4963 4963 + obj->size, align); 4798 4964 if (ret) { 4799 4965 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); 4800 4966 goto out;

+271

drivers/gpu/drm/i915/i915_gem_evict.c

reviewed

··· 1 1 + /* 2 2 + * Copyright © 2008-2010 Intel Corporation 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice (including the next 12 12 + * paragraph) shall be included in all copies or substantial portions of the 13 13 + * Software. 14 14 + * 15 15 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 16 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 17 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 18 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 19 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 20 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 21 + * IN THE SOFTWARE. 22 22 + * 23 23 + * Authors: 24 24 + * Eric Anholt <eric@anholt.net> 25 25 + * Chris Wilson <chris@chris-wilson.co.uuk> 26 26 + * 27 27 + */ 28 28 + 29 29 + #include "drmP.h" 30 30 + #include "drm.h" 31 31 + #include "i915_drv.h" 32 32 + #include "i915_drm.h" 33 33 + 34 34 + static struct drm_i915_gem_object * 35 35 + i915_gem_next_active_object(struct drm_device *dev, 36 36 + struct list_head **render_iter, 37 37 + struct list_head **bsd_iter) 38 38 + { 39 39 + drm_i915_private_t *dev_priv = dev->dev_private; 40 40 + struct drm_i915_gem_object *render_obj = NULL, *bsd_obj = NULL; 41 41 + 42 42 + if (*render_iter != &dev_priv->render_ring.active_list) 43 43 + render_obj = list_entry(*render_iter, 44 44 + struct drm_i915_gem_object, 45 45 + list); 46 46 + 47 47 + if (HAS_BSD(dev)) { 48 48 + if (*bsd_iter != &dev_priv->bsd_ring.active_list) 49 49 + bsd_obj = list_entry(*bsd_iter, 50 50 + struct drm_i915_gem_object, 51 51 + list); 52 52 + 53 53 + if (render_obj == NULL) { 54 54 + *bsd_iter = (*bsd_iter)->next; 55 55 + return bsd_obj; 56 56 + } 57 57 + 58 58 + if (bsd_obj == NULL) { 59 59 + *render_iter = (*render_iter)->next; 60 60 + return render_obj; 61 61 + } 62 62 + 63 63 + /* XXX can we handle seqno wrapping? */ 64 64 + if (render_obj->last_rendering_seqno < bsd_obj->last_rendering_seqno) { 65 65 + *render_iter = (*render_iter)->next; 66 66 + return render_obj; 67 67 + } else { 68 68 + *bsd_iter = (*bsd_iter)->next; 69 69 + return bsd_obj; 70 70 + } 71 71 + } else { 72 72 + *render_iter = (*render_iter)->next; 73 73 + return render_obj; 74 74 + } 75 75 + } 76 76 + 77 77 + static bool 78 78 + mark_free(struct drm_i915_gem_object *obj_priv, 79 79 + struct list_head *unwind) 80 80 + { 81 81 + list_add(&obj_priv->evict_list, unwind); 82 82 + return drm_mm_scan_add_block(obj_priv->gtt_space); 83 83 + } 84 84 + 85 85 + #define i915_for_each_active_object(OBJ, R, B) \ 86 86 + *(R) = dev_priv->render_ring.active_list.next; \ 87 87 + *(B) = dev_priv->bsd_ring.active_list.next; \ 88 88 + while (((OBJ) = i915_gem_next_active_object(dev, (R), (B))) != NULL) 89 89 + 90 90 + int 91 91 + i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment) 92 92 + { 93 93 + drm_i915_private_t *dev_priv = dev->dev_private; 94 94 + struct list_head eviction_list, unwind_list; 95 95 + struct drm_i915_gem_object *obj_priv, *tmp_obj_priv; 96 96 + struct list_head *render_iter, *bsd_iter; 97 97 + int ret = 0; 98 98 + 99 99 + i915_gem_retire_requests(dev); 100 100 + 101 101 + /* Re-check for free space after retiring requests */ 102 102 + if (drm_mm_search_free(&dev_priv->mm.gtt_space, 103 103 + min_size, alignment, 0)) 104 104 + return 0; 105 105 + 106 106 + /* 107 107 + * The goal is to evict objects and amalgamate space in LRU order. 108 108 + * The oldest idle objects reside on the inactive list, which is in 109 109 + * retirement order. The next objects to retire are those on the (per 110 110 + * ring) active list that do not have an outstanding flush. Once the 111 111 + * hardware reports completion (the seqno is updated after the 112 112 + * batchbuffer has been finished) the clean buffer objects would 113 113 + * be retired to the inactive list. Any dirty objects would be added 114 114 + * to the tail of the flushing list. So after processing the clean 115 115 + * active objects we need to emit a MI_FLUSH to retire the flushing 116 116 + * list, hence the retirement order of the flushing list is in 117 117 + * advance of the dirty objects on the active lists. 118 118 + * 119 119 + * The retirement sequence is thus: 120 120 + * 1. Inactive objects (already retired) 121 121 + * 2. Clean active objects 122 122 + * 3. Flushing list 123 123 + * 4. Dirty active objects. 124 124 + * 125 125 + * On each list, the oldest objects lie at the HEAD with the freshest 126 126 + * object on the TAIL. 127 127 + */ 128 128 + 129 129 + INIT_LIST_HEAD(&unwind_list); 130 130 + drm_mm_init_scan(&dev_priv->mm.gtt_space, min_size, alignment); 131 131 + 132 132 + /* First see if there is a large enough contiguous idle region... */ 133 133 + list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { 134 134 + if (mark_free(obj_priv, &unwind_list)) 135 135 + goto found; 136 136 + } 137 137 + 138 138 + /* Now merge in the soon-to-be-expired objects... */ 139 139 + i915_for_each_active_object(obj_priv, &render_iter, &bsd_iter) { 140 140 + /* Does the object require an outstanding flush? */ 141 141 + if (obj_priv->base.write_domain || obj_priv->pin_count) 142 142 + continue; 143 143 + 144 144 + if (mark_free(obj_priv, &unwind_list)) 145 145 + goto found; 146 146 + } 147 147 + 148 148 + /* Finally add anything with a pending flush (in order of retirement) */ 149 149 + list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { 150 150 + if (obj_priv->pin_count) 151 151 + continue; 152 152 + 153 153 + if (mark_free(obj_priv, &unwind_list)) 154 154 + goto found; 155 155 + } 156 156 + i915_for_each_active_object(obj_priv, &render_iter, &bsd_iter) { 157 157 + if (! obj_priv->base.write_domain || obj_priv->pin_count) 158 158 + continue; 159 159 + 160 160 + if (mark_free(obj_priv, &unwind_list)) 161 161 + goto found; 162 162 + } 163 163 + 164 164 + /* Nothing found, clean up and bail out! */ 165 165 + list_for_each_entry(obj_priv, &unwind_list, evict_list) { 166 166 + ret = drm_mm_scan_remove_block(obj_priv->gtt_space); 167 167 + BUG_ON(ret); 168 168 + } 169 169 + 170 170 + /* We expect the caller to unpin, evict all and try again, or give up. 171 171 + * So calling i915_gem_evict_everything() is unnecessary. 172 172 + */ 173 173 + return -ENOSPC; 174 174 + 175 175 + found: 176 176 + INIT_LIST_HEAD(&eviction_list); 177 177 + list_for_each_entry_safe(obj_priv, tmp_obj_priv, 178 178 + &unwind_list, evict_list) { 179 179 + if (drm_mm_scan_remove_block(obj_priv->gtt_space)) { 180 180 + /* drm_mm doesn't allow any other other operations while 181 181 + * scanning, therefore store to be evicted objects on a 182 182 + * temporary list. */ 183 183 + list_move(&obj_priv->evict_list, &eviction_list); 184 184 + } 185 185 + } 186 186 + 187 187 + /* Unbinding will emit any required flushes */ 188 188 + list_for_each_entry_safe(obj_priv, tmp_obj_priv, 189 189 + &eviction_list, evict_list) { 190 190 + #if WATCH_LRU 191 191 + DRM_INFO("%s: evicting %p\n", __func__, obj); 192 192 + #endif 193 193 + ret = i915_gem_object_unbind(&obj_priv->base); 194 194 + if (ret) 195 195 + return ret; 196 196 + } 197 197 + 198 198 + /* The just created free hole should be on the top of the free stack 199 199 + * maintained by drm_mm, so this BUG_ON actually executes in O(1). 200 200 + * Furthermore all accessed data has just recently been used, so it 201 201 + * should be really fast, too. */ 202 202 + BUG_ON(!drm_mm_search_free(&dev_priv->mm.gtt_space, min_size, 203 203 + alignment, 0)); 204 204 + 205 205 + return 0; 206 206 + } 207 207 + 208 208 + int 209 209 + i915_gem_evict_everything(struct drm_device *dev) 210 210 + { 211 211 + drm_i915_private_t *dev_priv = dev->dev_private; 212 212 + int ret; 213 213 + bool lists_empty; 214 214 + 215 215 + spin_lock(&dev_priv->mm.active_list_lock); 216 216 + lists_empty = (list_empty(&dev_priv->mm.inactive_list) && 217 217 + list_empty(&dev_priv->mm.flushing_list) && 218 218 + list_empty(&dev_priv->render_ring.active_list) && 219 219 + (!HAS_BSD(dev) 220 220 + || list_empty(&dev_priv->bsd_ring.active_list))); 221 221 + spin_unlock(&dev_priv->mm.active_list_lock); 222 222 + 223 223 + if (lists_empty) 224 224 + return -ENOSPC; 225 225 + 226 226 + /* Flush everything (on to the inactive lists) and evict */ 227 227 + ret = i915_gpu_idle(dev); 228 228 + if (ret) 229 229 + return ret; 230 230 + 231 231 + BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); 232 232 + 233 233 + ret = i915_gem_evict_inactive(dev); 234 234 + if (ret) 235 235 + return ret; 236 236 + 237 237 + spin_lock(&dev_priv->mm.active_list_lock); 238 238 + lists_empty = (list_empty(&dev_priv->mm.inactive_list) && 239 239 + list_empty(&dev_priv->mm.flushing_list) && 240 240 + list_empty(&dev_priv->render_ring.active_list) && 241 241 + (!HAS_BSD(dev) 242 242 + || list_empty(&dev_priv->bsd_ring.active_list))); 243 243 + spin_unlock(&dev_priv->mm.active_list_lock); 244 244 + BUG_ON(!lists_empty); 245 245 + 246 246 + return 0; 247 247 + } 248 248 + 249 249 + /** Unbinds all inactive objects. */ 250 250 + int 251 251 + i915_gem_evict_inactive(struct drm_device *dev) 252 252 + { 253 253 + drm_i915_private_t *dev_priv = dev->dev_private; 254 254 + 255 255 + while (!list_empty(&dev_priv->mm.inactive_list)) { 256 256 + struct drm_gem_object *obj; 257 257 + int ret; 258 258 + 259 259 + obj = &list_first_entry(&dev_priv->mm.inactive_list, 260 260 + struct drm_i915_gem_object, 261 261 + list)->base; 262 262 + 263 263 + ret = i915_gem_object_unbind(obj); 264 264 + if (ret != 0) { 265 265 + DRM_ERROR("Error unbinding object: %d\n", ret); 266 266 + return ret; 267 267 + } 268 268 + } 269 269 + 270 270 + return 0; 271 271 + }

+76 -8

drivers/gpu/drm/i915/i915_irq.c

reviewed

··· 425 425 i915_error_object_create(struct drm_device *dev, 426 426 struct drm_gem_object *src) 427 427 { 428 428 + drm_i915_private_t *dev_priv = dev->dev_private; 428 429 struct drm_i915_error_object *dst; 429 430 struct drm_i915_gem_object *src_priv; 430 431 int page, page_count; 432 432 + u32 reloc_offset; 431 433 432 434 if (src == NULL) 433 435 return NULL; ··· 444 442 if (dst == NULL) 445 443 return NULL; 446 444 445 445 + reloc_offset = src_priv->gtt_offset; 447 446 for (page = 0; page < page_count; page++) { 448 448 - void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 449 447 unsigned long flags; 448 448 + void __iomem *s; 449 449 + void *d; 450 450 451 451 + d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 451 452 if (d == NULL) 452 453 goto unwind; 454 454 + 453 455 local_irq_save(flags); 454 454 - s = kmap_atomic(src_priv->pages[page], KM_IRQ0); 455 455 - memcpy(d, s, PAGE_SIZE); 456 456 - kunmap_atomic(s, KM_IRQ0); 456 456 + s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 457 457 + reloc_offset, 458 458 + KM_IRQ0); 459 459 + memcpy_fromio(d, s, PAGE_SIZE); 460 460 + io_mapping_unmap_atomic(s, KM_IRQ0); 457 461 local_irq_restore(flags); 462 462 + 458 463 dst->pages[page] = d; 464 464 + 465 465 + reloc_offset += PAGE_SIZE; 459 466 } 460 467 dst->page_count = page_count; 461 468 dst->gtt_offset = src_priv->gtt_offset; ··· 500 489 i915_error_object_free(error->batchbuffer[1]); 501 490 i915_error_object_free(error->ringbuffer); 502 491 kfree(error->active_bo); 492 492 + kfree(error->overlay); 503 493 kfree(error); 504 494 } 505 495 ··· 624 612 625 613 if (batchbuffer[1] == NULL && 626 614 error->acthd >= obj_priv->gtt_offset && 627 627 - error->acthd < obj_priv->gtt_offset + obj->size && 628 628 - batchbuffer[0] != obj) 615 615 + error->acthd < obj_priv->gtt_offset + obj->size) 629 616 batchbuffer[1] = obj; 630 617 631 618 count++; 619 619 + } 620 620 + /* Scan the other lists for completeness for those bizarre errors. */ 621 621 + if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { 622 622 + list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { 623 623 + struct drm_gem_object *obj = &obj_priv->base; 624 624 + 625 625 + if (batchbuffer[0] == NULL && 626 626 + bbaddr >= obj_priv->gtt_offset && 627 627 + bbaddr < obj_priv->gtt_offset + obj->size) 628 628 + batchbuffer[0] = obj; 629 629 + 630 630 + if (batchbuffer[1] == NULL && 631 631 + error->acthd >= obj_priv->gtt_offset && 632 632 + error->acthd < obj_priv->gtt_offset + obj->size) 633 633 + batchbuffer[1] = obj; 634 634 + 635 635 + if (batchbuffer[0] && batchbuffer[1]) 636 636 + break; 637 637 + } 638 638 + } 639 639 + if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { 640 640 + list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { 641 641 + struct drm_gem_object *obj = &obj_priv->base; 642 642 + 643 643 + if (batchbuffer[0] == NULL && 644 644 + bbaddr >= obj_priv->gtt_offset && 645 645 + bbaddr < obj_priv->gtt_offset + obj->size) 646 646 + batchbuffer[0] = obj; 647 647 + 648 648 + if (batchbuffer[1] == NULL && 649 649 + error->acthd >= obj_priv->gtt_offset && 650 650 + error->acthd < obj_priv->gtt_offset + obj->size) 651 651 + batchbuffer[1] = obj; 652 652 + 653 653 + if (batchbuffer[0] && batchbuffer[1]) 654 654 + break; 655 655 + } 632 656 } 633 657 634 658 /* We need to copy these to an anonymous buffer as the simplest 635 659 * method to avoid being overwritten by userpace. 636 660 */ 637 661 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); 638 638 - error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); 662 662 + if (batchbuffer[1] != batchbuffer[0]) 663 663 + error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); 664 664 + else 665 665 + error->batchbuffer[1] = NULL; 639 666 640 667 /* Record the ringbuffer */ 641 668 error->ringbuffer = i915_error_object_create(dev, ··· 717 666 } 718 667 719 668 do_gettimeofday(&error->time); 669 669 + 670 670 + error->overlay = intel_overlay_capture_error_state(dev); 720 671 721 672 spin_lock_irqsave(&dev_priv->error_lock, flags); 722 673 if (dev_priv->first_error == NULL) { ··· 1304 1251 &dev_priv->render_ring), 1305 1252 i915_get_tail_request(dev)->seqno)) { 1306 1253 dev_priv->hangcheck_count = 0; 1254 1254 + 1255 1255 + /* Issue a wake-up to catch stuck h/w. */ 1256 1256 + if (dev_priv->render_ring.waiting_gem_seqno | 1257 1257 + dev_priv->bsd_ring.waiting_gem_seqno) { 1258 1258 + DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); 1259 1259 + if (dev_priv->render_ring.waiting_gem_seqno) 1260 1260 + DRM_WAKEUP(&dev_priv->render_ring.irq_queue); 1261 1261 + if (dev_priv->bsd_ring.waiting_gem_seqno) 1262 1262 + DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); 1263 1263 + } 1307 1264 return; 1308 1265 } 1309 1266 ··· 1381 1318 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); 1382 1319 (void) I915_READ(DEIER); 1383 1320 1384 1384 - /* user interrupt should be enabled, but masked initial */ 1321 1321 + /* Gen6 only needs render pipe_control now */ 1322 1322 + if (IS_GEN6(dev)) 1323 1323 + render_mask = GT_PIPE_NOTIFY; 1324 1324 + 1385 1325 dev_priv->gt_irq_mask_reg = ~render_mask; 1386 1326 dev_priv->gt_irq_enable_reg = render_mask; 1387 1327 1388 1328 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1389 1329 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); 1330 1330 + if (IS_GEN6(dev)) 1331 1331 + I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); 1390 1332 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); 1391 1333 (void) I915_READ(GTIER); 1392 1334

+3 -7

drivers/gpu/drm/i915/i915_opregion.c

reviewed

··· 114 114 #define ASLE_REQ_MSK 0xf 115 115 116 116 /* response bits of ASLE irq request */ 117 117 - #define ASLE_ALS_ILLUM_FAIL (2<<10) 118 118 - #define ASLE_BACKLIGHT_FAIL (2<<12) 119 119 - #define ASLE_PFIT_FAIL (2<<14) 120 120 - #define ASLE_PWM_FREQ_FAIL (2<<16) 121 117 #define ASLE_ALS_ILLUM_FAILED (1<<10) 122 118 #define ASLE_BACKLIGHT_FAILED (1<<12) 123 119 #define ASLE_PFIT_FAILED (1<<14) ··· 151 155 u32 max_backlight, level, shift; 152 156 153 157 if (!(bclp & ASLE_BCLP_VALID)) 154 154 - return ASLE_BACKLIGHT_FAIL; 158 158 + return ASLE_BACKLIGHT_FAILED; 155 159 156 160 bclp &= ASLE_BCLP_MSK; 157 161 if (bclp < 0 || bclp > 255) 158 158 - return ASLE_BACKLIGHT_FAIL; 162 162 + return ASLE_BACKLIGHT_FAILED; 159 163 160 164 blc_pwm_ctl = I915_READ(BLC_PWM_CTL); 161 165 blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2); ··· 207 211 /* Panel fitting is currently controlled by the X code, so this is a 208 212 noop until modesetting support works fully */ 209 213 if (!(pfit & ASLE_PFIT_VALID)) 210 210 - return ASLE_PFIT_FAIL; 214 214 + return ASLE_PFIT_FAILED; 211 215 return 0; 212 216 } 213 217

+14

drivers/gpu/drm/i915/i915_reg.h

reviewed

··· 170 170 #define MI_NO_WRITE_FLUSH (1 << 2) 171 171 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 172 172 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 173 173 + #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 173 174 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 174 175 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 175 176 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) ··· 181 180 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 182 181 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 183 182 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 183 183 + #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 184 184 + #define MI_MM_SPACE_GTT (1<<8) 185 185 + #define MI_MM_SPACE_PHYSICAL (0<<8) 186 186 + #define MI_SAVE_EXT_STATE_EN (1<<3) 187 187 + #define MI_RESTORE_EXT_STATE_EN (1<<2) 188 188 + #define MI_RESTORE_INHIBIT (1<<0) 184 189 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 185 190 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 186 191 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) ··· 1106 1099 #define DDRMPLL1 0X12c20 1107 1100 #define PEG_BAND_GAP_DATA 0x14d68 1108 1101 1102 1102 + /* 1103 1103 + * Logical Context regs 1104 1104 + */ 1105 1105 + #define CCID 0x2180 1106 1106 + #define CCID_EN (1<<0) 1109 1107 /* 1110 1108 * Overlay regs 1111 1109 */ ··· 2081 2069 #define PIPE_DITHER_TYPE_ST01 (1 << 2) 2082 2070 /* Pipe A */ 2083 2071 #define PIPEADSL 0x70000 2072 2072 + #define DSL_LINEMASK 0x00000fff 2084 2073 #define PIPEACONF 0x70008 2085 2074 #define PIPEACONF_ENABLE (1<<31) 2086 2075 #define PIPEACONF_DISABLE 0 ··· 2941 2928 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 2942 2929 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 2943 2930 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 2931 2931 + #define TRANS_DP_SYNC_MASK (3<<3) 2944 2932 2945 2933 /* SNB eDP training params */ 2946 2934 /* SNB A-stepping */

+53 -44

drivers/gpu/drm/i915/i915_suspend.c

reviewed

··· 34 34 struct drm_i915_private *dev_priv = dev->dev_private; 35 35 u32 dpll_reg; 36 36 37 37 - if (IS_IRONLAKE(dev)) { 37 37 + if (HAS_PCH_SPLIT(dev)) { 38 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 39 39 } else { 40 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; ··· 53 53 if (!i915_pipe_enabled(dev, pipe)) 54 54 return; 55 55 56 56 - if (IS_IRONLAKE(dev)) 56 56 + if (HAS_PCH_SPLIT(dev)) 57 57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 58 58 59 59 if (pipe == PIPE_A) ··· 75 75 if (!i915_pipe_enabled(dev, pipe)) 76 76 return; 77 77 78 78 - if (IS_IRONLAKE(dev)) 78 78 + if (HAS_PCH_SPLIT(dev)) 79 79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 80 80 81 81 if (pipe == PIPE_A) ··· 239 239 if (drm_core_check_feature(dev, DRIVER_MODESET)) 240 240 return; 241 241 242 242 - if (IS_IRONLAKE(dev)) { 242 242 + if (HAS_PCH_SPLIT(dev)) { 243 243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 244 244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 245 245 } ··· 247 247 /* Pipe & plane A info */ 248 248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 249 249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 250 250 - if (IS_IRONLAKE(dev)) { 250 250 + if (HAS_PCH_SPLIT(dev)) { 251 251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 252 252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 253 253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); ··· 256 256 dev_priv->saveFPA1 = I915_READ(FPA1); 257 257 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 258 258 } 259 259 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 259 259 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 260 260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 261 261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 262 262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); ··· 264 264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 265 265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 266 266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 267 267 - if (!IS_IRONLAKE(dev)) 267 267 + if (!HAS_PCH_SPLIT(dev)) 268 268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 269 269 270 270 - if (IS_IRONLAKE(dev)) { 270 270 + if (HAS_PCH_SPLIT(dev)) { 271 271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 272 272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 273 273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); ··· 304 304 /* Pipe & plane B info */ 305 305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 306 306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 307 307 - if (IS_IRONLAKE(dev)) { 307 307 + if (HAS_PCH_SPLIT(dev)) { 308 308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 309 309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 310 310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); ··· 313 313 dev_priv->saveFPB1 = I915_READ(FPB1); 314 314 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 315 315 } 316 316 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 316 316 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 317 317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 318 318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 319 319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); ··· 321 321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 322 322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 323 323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 324 324 - if (!IS_IRONLAKE(dev)) 324 324 + if (!HAS_PCH_SPLIT(dev)) 325 325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 326 326 327 327 - if (IS_IRONLAKE(dev)) { 327 327 + if (HAS_PCH_SPLIT(dev)) { 328 328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 329 329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 330 330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); ··· 369 369 if (drm_core_check_feature(dev, DRIVER_MODESET)) 370 370 return; 371 371 372 372 - if (IS_IRONLAKE(dev)) { 372 372 + if (HAS_PCH_SPLIT(dev)) { 373 373 dpll_a_reg = PCH_DPLL_A; 374 374 dpll_b_reg = PCH_DPLL_B; 375 375 fpa0_reg = PCH_FPA0; ··· 385 385 fpb1_reg = FPB1; 386 386 } 387 387 388 388 - if (IS_IRONLAKE(dev)) { 388 388 + if (HAS_PCH_SPLIT(dev)) { 389 389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); 390 390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); 391 391 } ··· 395 395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 396 396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & 397 397 ~DPLL_VCO_ENABLE); 398 398 - DRM_UDELAY(150); 398 398 + POSTING_READ(dpll_a_reg); 399 399 + udelay(150); 399 400 } 400 401 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); 401 402 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); 402 403 /* Actually enable it */ 403 404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 404 404 - DRM_UDELAY(150); 405 405 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 405 405 + POSTING_READ(dpll_a_reg); 406 406 + udelay(150); 407 407 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 406 408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 407 407 - DRM_UDELAY(150); 409 409 + POSTING_READ(DPLL_A_MD); 410 410 + } 411 411 + udelay(150); 408 412 409 413 /* Restore mode */ 410 414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); ··· 417 413 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 418 414 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 419 415 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 420 420 - if (!IS_IRONLAKE(dev)) 416 416 + if (!HAS_PCH_SPLIT(dev)) 421 417 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 422 418 423 423 - if (IS_IRONLAKE(dev)) { 419 419 + if (HAS_PCH_SPLIT(dev)) { 424 420 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 425 421 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 426 422 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); ··· 464 460 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 465 461 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & 466 462 ~DPLL_VCO_ENABLE); 467 467 - DRM_UDELAY(150); 463 463 + POSTING_READ(dpll_b_reg); 464 464 + udelay(150); 468 465 } 469 466 I915_WRITE(fpb0_reg, dev_priv->saveFPB0); 470 467 I915_WRITE(fpb1_reg, dev_priv->saveFPB1); 471 468 /* Actually enable it */ 472 469 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 473 473 - DRM_UDELAY(150); 474 474 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 470 470 + POSTING_READ(dpll_b_reg); 471 471 + udelay(150); 472 472 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 475 473 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 476 476 - DRM_UDELAY(150); 474 474 + POSTING_READ(DPLL_B_MD); 475 475 + } 476 476 + udelay(150); 477 477 478 478 /* Restore mode */ 479 479 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); ··· 486 478 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 487 479 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 488 480 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 489 489 - if (!IS_IRONLAKE(dev)) 481 481 + if (!HAS_PCH_SPLIT(dev)) 490 482 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 491 483 492 492 - if (IS_IRONLAKE(dev)) { 484 484 + if (HAS_PCH_SPLIT(dev)) { 493 485 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 494 486 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 495 487 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); ··· 554 546 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 555 547 556 548 /* CRT state */ 557 557 - if (IS_IRONLAKE(dev)) { 549 549 + if (HAS_PCH_SPLIT(dev)) { 558 550 dev_priv->saveADPA = I915_READ(PCH_ADPA); 559 551 } else { 560 552 dev_priv->saveADPA = I915_READ(ADPA); 561 553 } 562 554 563 555 /* LVDS state */ 564 564 - if (IS_IRONLAKE(dev)) { 556 556 + if (HAS_PCH_SPLIT(dev)) { 565 557 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 566 558 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 567 559 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); ··· 579 571 dev_priv->saveLVDS = I915_READ(LVDS); 580 572 } 581 573 582 582 - if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 574 574 + if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 583 575 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 584 576 585 585 - if (IS_IRONLAKE(dev)) { 577 577 + if (HAS_PCH_SPLIT(dev)) { 586 578 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 587 579 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 588 580 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); ··· 610 602 611 603 /* Only save FBC state on the platform that supports FBC */ 612 604 if (I915_HAS_FBC(dev)) { 613 613 - if (IS_IRONLAKE_M(dev)) { 605 605 + if (HAS_PCH_SPLIT(dev)) { 614 606 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); 615 607 } else if (IS_GM45(dev)) { 616 608 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); ··· 626 618 dev_priv->saveVGA0 = I915_READ(VGA0); 627 619 dev_priv->saveVGA1 = I915_READ(VGA1); 628 620 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 629 629 - if (IS_IRONLAKE(dev)) 621 621 + if (HAS_PCH_SPLIT(dev)) 630 622 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 631 623 else 632 624 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); ··· 668 660 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 669 661 670 662 /* CRT state */ 671 671 - if (IS_IRONLAKE(dev)) 663 663 + if (HAS_PCH_SPLIT(dev)) 672 664 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 673 665 else 674 666 I915_WRITE(ADPA, dev_priv->saveADPA); 675 667 676 668 /* LVDS state */ 677 677 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 669 669 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 678 670 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 679 671 680 680 - if (IS_IRONLAKE(dev)) { 672 672 + if (HAS_PCH_SPLIT(dev)) { 681 673 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 682 674 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 683 675 I915_WRITE(LVDS, dev_priv->saveLVDS); 684 676 685 685 - if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 677 677 + if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 686 678 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 687 679 688 688 - if (IS_IRONLAKE(dev)) { 680 680 + if (HAS_PCH_SPLIT(dev)) { 689 681 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 690 682 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 691 683 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); ··· 716 708 717 709 /* only restore FBC info on the platform that supports FBC*/ 718 710 if (I915_HAS_FBC(dev)) { 719 719 - if (IS_IRONLAKE_M(dev)) { 711 711 + if (HAS_PCH_SPLIT(dev)) { 720 712 ironlake_disable_fbc(dev); 721 713 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); 722 714 } else if (IS_GM45(dev)) { ··· 731 723 } 732 724 } 733 725 /* VGA state */ 734 734 - if (IS_IRONLAKE(dev)) 726 726 + if (HAS_PCH_SPLIT(dev)) 735 727 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 736 728 else 737 729 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 738 730 I915_WRITE(VGA0, dev_priv->saveVGA0); 739 731 I915_WRITE(VGA1, dev_priv->saveVGA1); 740 732 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 741 741 - DRM_UDELAY(150); 733 733 + POSTING_READ(VGA_PD); 734 734 + udelay(150); 742 735 743 736 i915_restore_vga(dev); 744 737 } ··· 757 748 i915_save_display(dev); 758 749 759 750 /* Interrupt state */ 760 760 - if (IS_IRONLAKE(dev)) { 751 751 + if (HAS_PCH_SPLIT(dev)) { 761 752 dev_priv->saveDEIER = I915_READ(DEIER); 762 753 dev_priv->saveDEIMR = I915_READ(DEIMR); 763 754 dev_priv->saveGTIER = I915_READ(GTIER); ··· 771 762 dev_priv->saveIMR = I915_READ(IMR); 772 763 } 773 764 774 774 - if (IS_IRONLAKE_M(dev)) 765 765 + if (HAS_PCH_SPLIT(dev)) 775 766 ironlake_disable_drps(dev); 776 767 777 768 /* Cache mode state */ ··· 829 820 i915_restore_display(dev); 830 821 831 822 /* Interrupt state */ 832 832 - if (IS_IRONLAKE(dev)) { 823 823 + if (HAS_PCH_SPLIT(dev)) { 833 824 I915_WRITE(DEIER, dev_priv->saveDEIER); 834 825 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 835 826 I915_WRITE(GTIER, dev_priv->saveGTIER); ··· 844 835 /* Clock gating state */ 845 836 intel_init_clock_gating(dev); 846 837 847 847 - if (IS_IRONLAKE_M(dev)) 838 838 + if (HAS_PCH_SPLIT(dev)) 848 839 ironlake_enable_drps(dev); 849 840 850 841 /* Cache mode state */

+21 -32

drivers/gpu/drm/i915/intel_crt.c

reviewed

··· 160 160 struct drm_i915_private *dev_priv = dev->dev_private; 161 161 u32 adpa, temp; 162 162 bool ret; 163 163 + bool turn_off_dac = false; 163 164 164 165 temp = adpa = I915_READ(PCH_ADPA); 165 166 166 166 - if (HAS_PCH_CPT(dev)) { 167 167 - /* Disable DAC before force detect */ 168 168 - I915_WRITE(PCH_ADPA, adpa & ~ADPA_DAC_ENABLE); 169 169 - (void)I915_READ(PCH_ADPA); 170 170 - } else { 171 171 - adpa &= ~ADPA_CRT_HOTPLUG_MASK; 172 172 - /* disable HPD first */ 173 173 - I915_WRITE(PCH_ADPA, adpa); 174 174 - (void)I915_READ(PCH_ADPA); 175 175 - } 167 167 + if (HAS_PCH_SPLIT(dev)) 168 168 + turn_off_dac = true; 169 169 + 170 170 + adpa &= ~ADPA_CRT_HOTPLUG_MASK; 171 171 + if (turn_off_dac) 172 172 + adpa &= ~ADPA_DAC_ENABLE; 173 173 + 174 174 + /* disable HPD first */ 175 175 + I915_WRITE(PCH_ADPA, adpa); 176 176 + (void)I915_READ(PCH_ADPA); 176 177 177 178 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | 178 179 ADPA_CRT_HOTPLUG_WARMUP_10MS | ··· 186 185 DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); 187 186 I915_WRITE(PCH_ADPA, adpa); 188 187 189 189 - while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) 190 190 - ; 188 188 + if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 189 189 + 1000, 1)) 190 190 + DRM_ERROR("timed out waiting for FORCE_TRIGGER"); 191 191 192 192 - if (HAS_PCH_CPT(dev)) { 192 192 + if (turn_off_dac) { 193 193 I915_WRITE(PCH_ADPA, temp); 194 194 (void)I915_READ(PCH_ADPA); 195 195 } ··· 239 237 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 240 238 241 239 for (i = 0; i < tries ; i++) { 242 242 - unsigned long timeout; 243 240 /* turn on the FORCE_DETECT */ 244 241 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 245 245 - timeout = jiffies + msecs_to_jiffies(1000); 246 242 /* wait for FORCE_DETECT to go off */ 247 247 - do { 248 248 - if (!(I915_READ(PORT_HOTPLUG_EN) & 249 249 - CRT_HOTPLUG_FORCE_DETECT)) 250 250 - break; 251 251 - msleep(1); 252 252 - } while (time_after(timeout, jiffies)); 243 243 + if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 244 244 + CRT_HOTPLUG_FORCE_DETECT) == 0, 245 245 + 1000, 1)) 246 246 + DRM_ERROR("timed out waiting for FORCE_DETECT to go off"); 253 247 } 254 248 255 249 stat = I915_READ(PORT_HOTPLUG_STAT); ··· 329 331 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 330 332 /* Wait for next Vblank to substitue 331 333 * border color for Color info */ 332 332 - intel_wait_for_vblank(dev); 334 334 + intel_wait_for_vblank(dev, pipe); 333 335 st00 = I915_READ8(VGA_MSR_WRITE); 334 336 status = ((st00 & (1 << 4)) != 0) ? 335 337 connector_status_connected : ··· 506 508 .best_encoder = intel_attached_encoder, 507 509 }; 508 510 509 509 - static void intel_crt_enc_destroy(struct drm_encoder *encoder) 510 510 - { 511 511 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 512 512 - 513 513 - intel_i2c_destroy(intel_encoder->ddc_bus); 514 514 - drm_encoder_cleanup(encoder); 515 515 - kfree(intel_encoder); 516 516 - } 517 517 - 518 511 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 519 519 - .destroy = intel_crt_enc_destroy, 512 512 + .destroy = intel_encoder_destroy, 520 513 }; 521 514 522 515 void intel_crt_init(struct drm_device *dev)

+289 -230

drivers/gpu/drm/i915/intel_display.c

reviewed

··· 29 29 #include <linux/i2c.h> 30 30 #include <linux/kernel.h> 31 31 #include <linux/slab.h> 32 32 + #include <linux/vgaarb.h> 32 33 #include "drmP.h" 33 34 #include "intel_drv.h" 34 35 #include "i915_drm.h" ··· 977 976 return true; 978 977 } 979 978 980 980 - void 981 981 - intel_wait_for_vblank(struct drm_device *dev) 979 979 + /** 980 980 + * intel_wait_for_vblank - wait for vblank on a given pipe 981 981 + * @dev: drm device 982 982 + * @pipe: pipe to wait for 983 983 + * 984 984 + * Wait for vblank to occur on a given pipe. Needed for various bits of 985 985 + * mode setting code. 986 986 + */ 987 987 + void intel_wait_for_vblank(struct drm_device *dev, int pipe) 982 988 { 983 983 - /* Wait for 20ms, i.e. one cycle at 50hz. */ 984 984 - if (in_dbg_master()) 985 985 - mdelay(20); /* The kernel debugger cannot call msleep() */ 986 986 - else 987 987 - msleep(20); 989 989 + struct drm_i915_private *dev_priv = dev->dev_private; 990 990 + int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); 991 991 + 992 992 + /* Wait for vblank interrupt bit to set */ 993 993 + if (wait_for((I915_READ(pipestat_reg) & 994 994 + PIPE_VBLANK_INTERRUPT_STATUS) == 0, 995 995 + 50, 0)) 996 996 + DRM_DEBUG_KMS("vblank wait timed out\n"); 997 997 + } 998 998 + 999 999 + /** 1000 1000 + * intel_wait_for_vblank_off - wait for vblank after disabling a pipe 1001 1001 + * @dev: drm device 1002 1002 + * @pipe: pipe to wait for 1003 1003 + * 1004 1004 + * After disabling a pipe, we can't wait for vblank in the usual way, 1005 1005 + * spinning on the vblank interrupt status bit, since we won't actually 1006 1006 + * see an interrupt when the pipe is disabled. 1007 1007 + * 1008 1008 + * So this function waits for the display line value to settle (it 1009 1009 + * usually ends up stopping at the start of the next frame). 1010 1010 + */ 1011 1011 + void intel_wait_for_vblank_off(struct drm_device *dev, int pipe) 1012 1012 + { 1013 1013 + struct drm_i915_private *dev_priv = dev->dev_private; 1014 1014 + int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL); 1015 1015 + unsigned long timeout = jiffies + msecs_to_jiffies(100); 1016 1016 + u32 last_line; 1017 1017 + 1018 1018 + /* Wait for the display line to settle */ 1019 1019 + do { 1020 1020 + last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK; 1021 1021 + mdelay(5); 1022 1022 + } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) && 1023 1023 + time_after(timeout, jiffies)); 1024 1024 + 1025 1025 + if (time_after(jiffies, timeout)) 1026 1026 + DRM_DEBUG_KMS("vblank wait timed out\n"); 988 1027 } 989 1028 990 1029 /* Parameters have changed, update FBC info */ ··· 1078 1037 void i8xx_disable_fbc(struct drm_device *dev) 1079 1038 { 1080 1039 struct drm_i915_private *dev_priv = dev->dev_private; 1081 1081 - unsigned long timeout = jiffies + msecs_to_jiffies(1); 1082 1040 u32 fbc_ctl; 1083 1041 1084 1042 if (!I915_HAS_FBC(dev)) ··· 1092 1052 I915_WRITE(FBC_CONTROL, fbc_ctl); 1093 1053 1094 1054 /* Wait for compressing bit to clear */ 1095 1095 - while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) { 1096 1096 - if (time_after(jiffies, timeout)) { 1097 1097 - DRM_DEBUG_DRIVER("FBC idle timed out\n"); 1098 1098 - break; 1099 1099 - } 1100 1100 - ; /* do nothing */ 1055 1055 + if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) { 1056 1056 + DRM_DEBUG_KMS("FBC idle timed out\n"); 1057 1057 + return; 1101 1058 } 1102 1102 - 1103 1103 - intel_wait_for_vblank(dev); 1104 1059 1105 1060 DRM_DEBUG_KMS("disabled FBC\n"); 1106 1061 } ··· 1153 1118 dpfc_ctl = I915_READ(DPFC_CONTROL); 1154 1119 dpfc_ctl &= ~DPFC_CTL_EN; 1155 1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1156 1156 - intel_wait_for_vblank(dev); 1157 1121 1158 1122 DRM_DEBUG_KMS("disabled FBC\n"); 1159 1123 } ··· 1213 1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 1214 1180 dpfc_ctl &= ~DPFC_CTL_EN; 1215 1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 1216 1216 - intel_wait_for_vblank(dev); 1217 1182 1218 1183 DRM_DEBUG_KMS("disabled FBC\n"); 1219 1184 } ··· 1511 1478 if ((IS_I965G(dev) || plane == 0)) 1512 1479 intel_update_fbc(crtc, &crtc->mode); 1513 1480 1514 1514 - intel_wait_for_vblank(dev); 1481 1481 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1515 1482 intel_increase_pllclock(crtc, true); 1516 1483 1517 1484 return 0; ··· 1618 1585 Start, Offset, x, y, crtc->fb->pitch); 1619 1586 I915_WRITE(dspstride, crtc->fb->pitch); 1620 1587 if (IS_I965G(dev)) { 1621 1621 - I915_WRITE(dspbase, Offset); 1622 1622 - I915_READ(dspbase); 1623 1588 I915_WRITE(dspsurf, Start); 1624 1624 - I915_READ(dspsurf); 1625 1589 I915_WRITE(dsptileoff, (y << 16) | x); 1590 1590 + I915_WRITE(dspbase, Offset); 1626 1591 } else { 1627 1592 I915_WRITE(dspbase, Start + Offset); 1628 1628 - I915_READ(dspbase); 1629 1593 } 1594 1594 + POSTING_READ(dspbase); 1630 1595 1631 1596 if ((IS_I965G(dev) || plane == 0)) 1632 1597 intel_update_fbc(crtc, &crtc->mode); 1633 1598 1634 1634 - intel_wait_for_vblank(dev); 1599 1599 + intel_wait_for_vblank(dev, pipe); 1635 1600 1636 1601 if (old_fb) { 1637 1602 intel_fb = to_intel_framebuffer(old_fb); ··· 1657 1626 1658 1627 return 0; 1659 1628 } 1660 1660 - 1661 1661 - /* Disable the VGA plane that we never use */ 1662 1662 - static void i915_disable_vga (struct drm_device *dev) 1663 1663 - { 1664 1664 - struct drm_i915_private *dev_priv = dev->dev_private; 1665 1665 - u8 sr1; 1666 1666 - u32 vga_reg; 1667 1667 - 1668 1668 - if (HAS_PCH_SPLIT(dev)) 1669 1669 - vga_reg = CPU_VGACNTRL; 1670 1670 - else 1671 1671 - vga_reg = VGACNTRL; 1672 1672 - 1673 1673 - if (I915_READ(vga_reg) & VGA_DISP_DISABLE) 1674 1674 - return; 1675 1675 - 1676 1676 - I915_WRITE8(VGA_SR_INDEX, 1); 1677 1677 - sr1 = I915_READ8(VGA_SR_DATA); 1678 1678 - I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5)); 1679 1679 - udelay(100); 1680 1680 - 1681 1681 - I915_WRITE(vga_reg, VGA_DISP_DISABLE); 1682 1682 - } 1683 1683 - 1684 1684 - static void ironlake_disable_pll_edp (struct drm_crtc *crtc) 1685 1685 - { 1686 1686 - struct drm_device *dev = crtc->dev; 1687 1687 - struct drm_i915_private *dev_priv = dev->dev_private; 1688 1688 - u32 dpa_ctl; 1689 1689 - 1690 1690 - DRM_DEBUG_KMS("\n"); 1691 1691 - dpa_ctl = I915_READ(DP_A); 1692 1692 - dpa_ctl &= ~DP_PLL_ENABLE; 1693 1693 - I915_WRITE(DP_A, dpa_ctl); 1694 1694 - } 1695 1695 - 1696 1696 - static void ironlake_enable_pll_edp (struct drm_crtc *crtc) 1697 1697 - { 1698 1698 - struct drm_device *dev = crtc->dev; 1699 1699 - struct drm_i915_private *dev_priv = dev->dev_private; 1700 1700 - u32 dpa_ctl; 1701 1701 - 1702 1702 - dpa_ctl = I915_READ(DP_A); 1703 1703 - dpa_ctl |= DP_PLL_ENABLE; 1704 1704 - I915_WRITE(DP_A, dpa_ctl); 1705 1705 - udelay(200); 1706 1706 - } 1707 1707 - 1708 1629 1709 1630 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) 1710 1631 { ··· 1928 1945 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1929 1946 int trans_dpll_sel = (pipe == 0) ? 0 : 1; 1930 1947 u32 temp; 1931 1931 - int n; 1932 1948 u32 pipe_bpc; 1933 1949 1934 1950 temp = I915_READ(pipeconf_reg); ··· 1940 1958 case DRM_MODE_DPMS_ON: 1941 1959 case DRM_MODE_DPMS_STANDBY: 1942 1960 case DRM_MODE_DPMS_SUSPEND: 1943 1943 - DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); 1961 1961 + DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); 1944 1962 1945 1963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1946 1964 temp = I915_READ(PCH_LVDS); ··· 1950 1968 } 1951 1969 } 1952 1970 1953 1953 - if (HAS_eDP) { 1954 1954 - /* enable eDP PLL */ 1955 1955 - ironlake_enable_pll_edp(crtc); 1956 1956 - } else { 1971 1971 + if (!HAS_eDP) { 1957 1972 1958 1973 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1959 1974 temp = I915_READ(fdi_rx_reg); ··· 1984 2005 /* Enable panel fitting for LVDS */ 1985 2006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 1986 2007 || HAS_eDP || intel_pch_has_edp(crtc)) { 1987 1987 - temp = I915_READ(pf_ctl_reg); 1988 1988 - I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 1989 1989 - 1990 1990 - /* currently full aspect */ 1991 1991 - I915_WRITE(pf_win_pos, 0); 1992 1992 - 1993 1993 - I915_WRITE(pf_win_size, 1994 1994 - (dev_priv->panel_fixed_mode->hdisplay << 16) | 1995 1995 - (dev_priv->panel_fixed_mode->vdisplay)); 2008 2008 + if (dev_priv->pch_pf_size) { 2009 2009 + temp = I915_READ(pf_ctl_reg); 2010 2010 + I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 2011 2011 + I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos); 2012 2012 + I915_WRITE(pf_win_size, dev_priv->pch_pf_size); 2013 2013 + } else 2014 2014 + I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); 1996 2015 } 1997 2016 1998 2017 /* Enable CPU pipe */ ··· 2074 2097 int reg; 2075 2098 2076 2099 reg = I915_READ(trans_dp_ctl); 2077 2077 - reg &= ~TRANS_DP_PORT_SEL_MASK; 2078 2078 - reg = TRANS_DP_OUTPUT_ENABLE | 2079 2079 - TRANS_DP_ENH_FRAMING; 2100 2100 + reg &= ~(TRANS_DP_PORT_SEL_MASK | 2101 2101 + TRANS_DP_SYNC_MASK); 2102 2102 + reg |= (TRANS_DP_OUTPUT_ENABLE | 2103 2103 + TRANS_DP_ENH_FRAMING); 2080 2104 2081 2105 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2082 2106 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; ··· 2115 2137 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 2116 2138 I915_READ(transconf_reg); 2117 2139 2118 2118 - while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 2119 2119 - ; 2120 2120 - 2140 2140 + if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0)) 2141 2141 + DRM_ERROR("failed to enable transcoder\n"); 2121 2142 } 2122 2143 2123 2144 intel_crtc_load_lut(crtc); 2124 2145 2125 2146 intel_update_fbc(crtc, &crtc->mode); 2147 2147 + break; 2126 2148 2127 2127 - break; 2128 2149 case DRM_MODE_DPMS_OFF: 2129 2129 - DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 2150 2150 + DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); 2130 2151 2131 2152 drm_vblank_off(dev, pipe); 2132 2153 /* Disable display plane */ ··· 2141 2164 dev_priv->display.disable_fbc) 2142 2165 dev_priv->display.disable_fbc(dev); 2143 2166 2144 2144 - i915_disable_vga(dev); 2145 2145 - 2146 2167 /* disable cpu pipe, disable after all planes disabled */ 2147 2168 temp = I915_READ(pipeconf_reg); 2148 2169 if ((temp & PIPEACONF_ENABLE) != 0) { 2149 2170 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 2150 2150 - I915_READ(pipeconf_reg); 2151 2151 - n = 0; 2171 2171 + 2152 2172 /* wait for cpu pipe off, pipe state */ 2153 2153 - while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { 2154 2154 - n++; 2155 2155 - if (n < 60) { 2156 2156 - udelay(500); 2157 2157 - continue; 2158 2158 - } else { 2159 2159 - DRM_DEBUG_KMS("pipe %d off delay\n", 2160 2160 - pipe); 2161 2161 - break; 2162 2162 - } 2163 2163 - } 2173 2173 + if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1)) 2174 2174 + DRM_ERROR("failed to turn off cpu pipe\n"); 2164 2175 } else 2165 2176 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 2166 2177 ··· 2209 2244 temp = I915_READ(transconf_reg); 2210 2245 if ((temp & TRANS_ENABLE) != 0) { 2211 2246 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); 2212 2212 - I915_READ(transconf_reg); 2213 2213 - n = 0; 2247 2247 + 2214 2248 /* wait for PCH transcoder off, transcoder state */ 2215 2215 - while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { 2216 2216 - n++; 2217 2217 - if (n < 60) { 2218 2218 - udelay(500); 2219 2219 - continue; 2220 2220 - } else { 2221 2221 - DRM_DEBUG_KMS("transcoder %d off " 2222 2222 - "delay\n", pipe); 2223 2223 - break; 2224 2224 - } 2225 2225 - } 2249 2249 + if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1)) 2250 2250 + DRM_ERROR("failed to disable transcoder\n"); 2226 2251 } 2227 2252 2228 2253 temp = I915_READ(transconf_reg); ··· 2248 2293 temp = I915_READ(pch_dpll_reg); 2249 2294 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2250 2295 I915_READ(pch_dpll_reg); 2251 2251 - 2252 2252 - if (HAS_eDP) { 2253 2253 - ironlake_disable_pll_edp(crtc); 2254 2254 - } 2255 2296 2256 2297 /* Switch from PCDclk to Rawclk */ 2257 2298 temp = I915_READ(fdi_rx_reg); ··· 2323 2372 case DRM_MODE_DPMS_ON: 2324 2373 case DRM_MODE_DPMS_STANDBY: 2325 2374 case DRM_MODE_DPMS_SUSPEND: 2326 2326 - intel_update_watermarks(dev); 2327 2327 - 2328 2375 /* Enable the DPLL */ 2329 2376 temp = I915_READ(dpll_reg); 2330 2377 if ((temp & DPLL_VCO_ENABLE) == 0) { ··· 2362 2413 intel_crtc_dpms_overlay(intel_crtc, true); 2363 2414 break; 2364 2415 case DRM_MODE_DPMS_OFF: 2365 2365 - intel_update_watermarks(dev); 2366 2366 - 2367 2416 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2368 2417 intel_crtc_dpms_overlay(intel_crtc, false); 2369 2418 drm_vblank_off(dev, pipe); ··· 2369 2422 if (dev_priv->cfb_plane == plane && 2370 2423 dev_priv->display.disable_fbc) 2371 2424 dev_priv->display.disable_fbc(dev); 2372 2372 - 2373 2373 - /* Disable the VGA plane that we never use */ 2374 2374 - i915_disable_vga(dev); 2375 2425 2376 2426 /* Disable display plane */ 2377 2427 temp = I915_READ(dspcntr_reg); ··· 2379 2435 I915_READ(dspbase_reg); 2380 2436 } 2381 2437 2382 2382 - if (!IS_I9XX(dev)) { 2383 2383 - /* Wait for vblank for the disable to take effect */ 2384 2384 - intel_wait_for_vblank(dev); 2385 2385 - } 2438 2438 + /* Wait for vblank for the disable to take effect */ 2439 2439 + intel_wait_for_vblank_off(dev, pipe); 2386 2440 2387 2441 /* Don't disable pipe A or pipe A PLLs if needed */ 2388 2442 if (pipeconf_reg == PIPEACONF && ··· 2395 2453 } 2396 2454 2397 2455 /* Wait for vblank for the disable to take effect. */ 2398 2398 - intel_wait_for_vblank(dev); 2456 2456 + intel_wait_for_vblank_off(dev, pipe); 2399 2457 2400 2458 temp = I915_READ(dpll_reg); 2401 2459 if ((temp & DPLL_VCO_ENABLE) != 0) { ··· 2411 2469 2412 2470 /** 2413 2471 * Sets the power management mode of the pipe and plane. 2414 2414 - * 2415 2415 - * This code should probably grow support for turning the cursor off and back 2416 2416 - * on appropriately at the same time as we're turning the pipe off/on. 2417 2472 */ 2418 2473 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2419 2474 { ··· 2421 2482 int pipe = intel_crtc->pipe; 2422 2483 bool enabled; 2423 2484 2485 2485 + intel_crtc->dpms_mode = mode; 2486 2486 + intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON; 2487 2487 + 2488 2488 + /* When switching on the display, ensure that SR is disabled 2489 2489 + * with multiple pipes prior to enabling to new pipe. 2490 2490 + * 2491 2491 + * When switching off the display, make sure the cursor is 2492 2492 + * properly hidden prior to disabling the pipe. 2493 2493 + */ 2494 2494 + if (mode == DRM_MODE_DPMS_ON) 2495 2495 + intel_update_watermarks(dev); 2496 2496 + else 2497 2497 + intel_crtc_update_cursor(crtc); 2498 2498 + 2424 2499 dev_priv->display.dpms(crtc, mode); 2425 2500 2426 2426 - intel_crtc->dpms_mode = mode; 2501 2501 + if (mode == DRM_MODE_DPMS_ON) 2502 2502 + intel_crtc_update_cursor(crtc); 2503 2503 + else 2504 2504 + intel_update_watermarks(dev); 2427 2505 2428 2506 if (!dev->primary->master) 2429 2507 return; ··· 2490 2534 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 2491 2535 /* lvds has its own version of commit see intel_lvds_commit */ 2492 2536 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 2537 2537 + } 2538 2538 + 2539 2539 + void intel_encoder_destroy(struct drm_encoder *encoder) 2540 2540 + { 2541 2541 + struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 2542 2542 + 2543 2543 + if (intel_encoder->ddc_bus) 2544 2544 + intel_i2c_destroy(intel_encoder->ddc_bus); 2545 2545 + 2546 2546 + if (intel_encoder->i2c_bus) 2547 2547 + intel_i2c_destroy(intel_encoder->i2c_bus); 2548 2548 + 2549 2549 + drm_encoder_cleanup(encoder); 2550 2550 + kfree(intel_encoder); 2493 2551 } 2494 2552 2495 2553 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, ··· 2837 2867 unsigned long cursor_hpll_disable; 2838 2868 }; 2839 2869 2840 2840 - static struct cxsr_latency cxsr_latency_table[] = { 2870 2870 + static const struct cxsr_latency cxsr_latency_table[] = { 2841 2871 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 2842 2872 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 2843 2873 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ ··· 2875 2905 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 2876 2906 }; 2877 2907 2878 2878 - static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 2879 2879 - int fsb, int mem) 2908 2908 + static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 2909 2909 + int is_ddr3, 2910 2910 + int fsb, 2911 2911 + int mem) 2880 2912 { 2913 2913 + const struct cxsr_latency *latency; 2881 2914 int i; 2882 2882 - struct cxsr_latency *latency; 2883 2915 2884 2916 if (fsb == 0 || mem == 0) 2885 2917 return NULL; ··· 2902 2930 static void pineview_disable_cxsr(struct drm_device *dev) 2903 2931 { 2904 2932 struct drm_i915_private *dev_priv = dev->dev_private; 2905 2905 - u32 reg; 2906 2933 2907 2934 /* deactivate cxsr */ 2908 2908 - reg = I915_READ(DSPFW3); 2909 2909 - reg &= ~(PINEVIEW_SELF_REFRESH_EN); 2910 2910 - I915_WRITE(DSPFW3, reg); 2911 2911 - DRM_INFO("Big FIFO is disabled\n"); 2935 2935 + I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 2912 2936 } 2913 2937 2914 2938 /* ··· 2992 3024 int pixel_size) 2993 3025 { 2994 3026 struct drm_i915_private *dev_priv = dev->dev_private; 3027 3027 + const struct cxsr_latency *latency; 2995 3028 u32 reg; 2996 3029 unsigned long wm; 2997 2997 - struct cxsr_latency *latency; 2998 3030 int sr_clock; 2999 3031 3000 3000 - latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 3032 3032 + latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 3001 3033 dev_priv->fsb_freq, dev_priv->mem_freq); 3002 3034 if (!latency) { 3003 3035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); ··· 3043 3075 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 3044 3076 3045 3077 /* activate cxsr */ 3046 3046 - reg = I915_READ(DSPFW3); 3047 3047 - reg |= PINEVIEW_SELF_REFRESH_EN; 3048 3048 - I915_WRITE(DSPFW3, reg); 3078 3078 + I915_WRITE(DSPFW3, 3079 3079 + I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 3049 3080 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 3050 3081 } else { 3051 3082 pineview_disable_cxsr(dev); ··· 3321 3354 int line_count; 3322 3355 int planea_htotal = 0, planeb_htotal = 0; 3323 3356 struct drm_crtc *crtc; 3324 3324 - struct intel_crtc *intel_crtc; 3325 3357 3326 3358 /* Need htotal for all active display plane */ 3327 3359 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3328 3328 - intel_crtc = to_intel_crtc(crtc); 3329 3329 - if (crtc->enabled) { 3360 3360 + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3361 3361 + if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) { 3330 3362 if (intel_crtc->plane == 0) 3331 3363 planea_htotal = crtc->mode.htotal; 3332 3364 else ··· 3485 3519 { 3486 3520 struct drm_i915_private *dev_priv = dev->dev_private; 3487 3521 struct drm_crtc *crtc; 3488 3488 - struct intel_crtc *intel_crtc; 3489 3522 int sr_hdisplay = 0; 3490 3523 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 3491 3524 int enabled = 0, pixel_size = 0; ··· 3495 3530 3496 3531 /* Get the clock config from both planes */ 3497 3532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3498 3498 - intel_crtc = to_intel_crtc(crtc); 3499 3499 - if (crtc->enabled) { 3533 3533 + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3534 3534 + if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) { 3500 3535 enabled++; 3501 3536 if (intel_crtc->plane == 0) { 3502 3537 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", ··· 3931 3966 dpll_reg = pch_dpll_reg; 3932 3967 } 3933 3968 3934 3934 - if (is_edp) { 3935 3935 - ironlake_disable_pll_edp(crtc); 3936 3936 - } else if ((dpll & DPLL_VCO_ENABLE)) { 3969 3969 + if (!is_edp) { 3937 3970 I915_WRITE(fp_reg, fp); 3938 3971 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3939 3972 I915_READ(dpll_reg); ··· 4130 4167 I915_WRITE(pipeconf_reg, pipeconf); 4131 4168 I915_READ(pipeconf_reg); 4132 4169 4133 4133 - intel_wait_for_vblank(dev); 4170 4170 + intel_wait_for_vblank(dev, pipe); 4134 4171 4135 4172 if (IS_IRONLAKE(dev)) { 4136 4173 /* enable address swizzle for tiling buffer */ ··· 4142 4179 4143 4180 /* Flush the plane changes */ 4144 4181 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4145 4145 - 4146 4146 - if ((IS_I965G(dev) || plane == 0)) 4147 4147 - intel_update_fbc(crtc, &crtc->mode); 4148 4182 4149 4183 intel_update_watermarks(dev); 4150 4184 ··· 4176 4216 } 4177 4217 } 4178 4218 4219 4219 + static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 4220 4220 + { 4221 4221 + struct drm_device *dev = crtc->dev; 4222 4222 + struct drm_i915_private *dev_priv = dev->dev_private; 4223 4223 + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4224 4224 + bool visible = base != 0; 4225 4225 + u32 cntl; 4226 4226 + 4227 4227 + if (intel_crtc->cursor_visible == visible) 4228 4228 + return; 4229 4229 + 4230 4230 + cntl = I915_READ(CURACNTR); 4231 4231 + if (visible) { 4232 4232 + /* On these chipsets we can only modify the base whilst 4233 4233 + * the cursor is disabled. 4234 4234 + */ 4235 4235 + I915_WRITE(CURABASE, base); 4236 4236 + 4237 4237 + cntl &= ~(CURSOR_FORMAT_MASK); 4238 4238 + /* XXX width must be 64, stride 256 => 0x00 << 28 */ 4239 4239 + cntl |= CURSOR_ENABLE | 4240 4240 + CURSOR_GAMMA_ENABLE | 4241 4241 + CURSOR_FORMAT_ARGB; 4242 4242 + } else 4243 4243 + cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 4244 4244 + I915_WRITE(CURACNTR, cntl); 4245 4245 + 4246 4246 + intel_crtc->cursor_visible = visible; 4247 4247 + } 4248 4248 + 4249 4249 + static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 4250 4250 + { 4251 4251 + struct drm_device *dev = crtc->dev; 4252 4252 + struct drm_i915_private *dev_priv = dev->dev_private; 4253 4253 + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4254 4254 + int pipe = intel_crtc->pipe; 4255 4255 + bool visible = base != 0; 4256 4256 + 4257 4257 + if (intel_crtc->cursor_visible != visible) { 4258 4258 + uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 4259 4259 + if (base) { 4260 4260 + cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 4261 4261 + cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4262 4262 + cntl |= pipe << 28; /* Connect to correct pipe */ 4263 4263 + } else { 4264 4264 + cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4265 4265 + cntl |= CURSOR_MODE_DISABLE; 4266 4266 + } 4267 4267 + I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); 4268 4268 + 4269 4269 + intel_crtc->cursor_visible = visible; 4270 4270 + } 4271 4271 + /* and commit changes on next vblank */ 4272 4272 + I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); 4273 4273 + } 4274 4274 + 4179 4275 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4180 4276 static void intel_crtc_update_cursor(struct drm_crtc *crtc) 4181 4277 { ··· 4241 4225 int pipe = intel_crtc->pipe; 4242 4226 int x = intel_crtc->cursor_x; 4243 4227 int y = intel_crtc->cursor_y; 4244 4244 - uint32_t base, pos; 4228 4228 + u32 base, pos; 4245 4229 bool visible; 4246 4230 4247 4231 pos = 0; 4248 4232 4249 4249 - if (crtc->fb) { 4233 4233 + if (intel_crtc->cursor_on && crtc->fb) { 4250 4234 base = intel_crtc->cursor_addr; 4251 4235 if (x > (int) crtc->fb->width) 4252 4236 base = 0; ··· 4275 4259 pos |= y << CURSOR_Y_SHIFT; 4276 4260 4277 4261 visible = base != 0; 4278 4278 - if (!visible && !intel_crtc->cursor_visble) 4262 4262 + if (!visible && !intel_crtc->cursor_visible) 4279 4263 return; 4280 4264 4281 4265 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 4282 4282 - if (intel_crtc->cursor_visble != visible) { 4283 4283 - uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 4284 4284 - if (base) { 4285 4285 - /* Hooray for CUR*CNTR differences */ 4286 4286 - if (IS_MOBILE(dev) || IS_I9XX(dev)) { 4287 4287 - cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 4288 4288 - cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4289 4289 - cntl |= pipe << 28; /* Connect to correct pipe */ 4290 4290 - } else { 4291 4291 - cntl &= ~(CURSOR_FORMAT_MASK); 4292 4292 - cntl |= CURSOR_ENABLE; 4293 4293 - cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; 4294 4294 - } 4295 4295 - } else { 4296 4296 - if (IS_MOBILE(dev) || IS_I9XX(dev)) { 4297 4297 - cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4298 4298 - cntl |= CURSOR_MODE_DISABLE; 4299 4299 - } else { 4300 4300 - cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 4301 4301 - } 4302 4302 - } 4303 4303 - I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); 4304 4304 - 4305 4305 - intel_crtc->cursor_visble = visible; 4306 4306 - } 4307 4307 - /* and commit changes on next vblank */ 4308 4308 - I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); 4266 4266 + if (IS_845G(dev) || IS_I865G(dev)) 4267 4267 + i845_update_cursor(crtc, base); 4268 4268 + else 4269 4269 + i9xx_update_cursor(crtc, base); 4309 4270 4310 4271 if (visible) 4311 4272 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); ··· 4347 4354 4348 4355 addr = obj_priv->gtt_offset; 4349 4356 } else { 4357 4357 + int align = IS_I830(dev) ? 16 * 1024 : 256; 4350 4358 ret = i915_gem_attach_phys_object(dev, bo, 4351 4351 - (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); 4359 4359 + (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 4360 4360 + align); 4352 4361 if (ret) { 4353 4362 DRM_ERROR("failed to attach phys object\n"); 4354 4363 goto fail_locked; ··· 4539 4544 encoder_funcs->commit(encoder); 4540 4545 } 4541 4546 /* let the connector get through one full cycle before testing */ 4542 4542 - intel_wait_for_vblank(dev); 4547 4547 + intel_wait_for_vblank(dev, intel_crtc->pipe); 4543 4548 4544 4549 return crtc; 4545 4550 } ··· 4744 4749 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 4745 4750 I915_WRITE(dpll_reg, dpll); 4746 4751 dpll = I915_READ(dpll_reg); 4747 4747 - intel_wait_for_vblank(dev); 4752 4752 + intel_wait_for_vblank(dev, pipe); 4748 4753 dpll = I915_READ(dpll_reg); 4749 4754 if (dpll & DISPLAY_RATE_SELECT_FPA1) 4750 4755 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); ··· 4788 4793 dpll |= DISPLAY_RATE_SELECT_FPA1; 4789 4794 I915_WRITE(dpll_reg, dpll); 4790 4795 dpll = I915_READ(dpll_reg); 4791 4791 - intel_wait_for_vblank(dev); 4796 4796 + intel_wait_for_vblank(dev, pipe); 4792 4797 dpll = I915_READ(dpll_reg); 4793 4798 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 4794 4799 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); ··· 5078 5083 work->pending_flip_obj = obj; 5079 5084 5080 5085 if (intel_crtc->plane) 5081 5081 - flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 5086 5086 + flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5082 5087 else 5083 5083 - flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; 5088 5088 + flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5084 5089 5085 5085 - /* Wait for any previous flip to finish */ 5086 5086 - if (IS_GEN3(dev)) 5087 5087 - while (I915_READ(ISR) & flip_mask) 5088 5088 - ; 5090 5090 + if (IS_GEN3(dev) || IS_GEN2(dev)) { 5091 5091 + BEGIN_LP_RING(2); 5092 5092 + OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5093 5093 + OUT_RING(0); 5094 5094 + ADVANCE_LP_RING(); 5095 5095 + } 5089 5096 5090 5097 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5091 5098 offset = obj_priv->gtt_offset; ··· 5101 5104 OUT_RING(offset | obj_priv->tiling_mode); 5102 5105 pipesrc = I915_READ(pipesrc_reg); 5103 5106 OUT_RING(pipesrc & 0x0fff0fff); 5104 5104 - } else { 5107 5107 + } else if (IS_GEN3(dev)) { 5105 5108 OUT_RING(MI_DISPLAY_FLIP_I915 | 5109 5109 + MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5110 5110 + OUT_RING(fb->pitch); 5111 5111 + OUT_RING(offset); 5112 5112 + OUT_RING(MI_NOOP); 5113 5113 + } else { 5114 5114 + OUT_RING(MI_DISPLAY_FLIP | 5106 5115 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5107 5116 OUT_RING(fb->pitch); 5108 5117 OUT_RING(offset); ··· 5435 5432 }; 5436 5433 5437 5434 static struct drm_gem_object * 5438 5438 - intel_alloc_power_context(struct drm_device *dev) 5435 5435 + intel_alloc_context_page(struct drm_device *dev) 5439 5436 { 5440 5440 - struct drm_gem_object *pwrctx; 5437 5437 + struct drm_gem_object *ctx; 5441 5438 int ret; 5442 5439 5443 5443 - pwrctx = i915_gem_alloc_object(dev, 4096); 5444 5444 - if (!pwrctx) { 5440 5440 + ctx = i915_gem_alloc_object(dev, 4096); 5441 5441 + if (!ctx) { 5445 5442 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 5446 5443 return NULL; 5447 5444 } 5448 5445 5449 5446 mutex_lock(&dev->struct_mutex); 5450 5450 - ret = i915_gem_object_pin(pwrctx, 4096); 5447 5447 + ret = i915_gem_object_pin(ctx, 4096); 5451 5448 if (ret) { 5452 5449 DRM_ERROR("failed to pin power context: %d\n", ret); 5453 5450 goto err_unref; 5454 5451 } 5455 5452 5456 5456 - ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1); 5453 5453 + ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 5457 5454 if (ret) { 5458 5455 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 5459 5456 goto err_unpin; 5460 5457 } 5461 5458 mutex_unlock(&dev->struct_mutex); 5462 5459 5463 5463 - return pwrctx; 5460 5460 + return ctx; 5464 5461 5465 5462 err_unpin: 5466 5466 - i915_gem_object_unpin(pwrctx); 5463 5463 + i915_gem_object_unpin(ctx); 5467 5464 err_unref: 5468 5468 - drm_gem_object_unreference(pwrctx); 5465 5465 + drm_gem_object_unreference(ctx); 5469 5466 mutex_unlock(&dev->struct_mutex); 5470 5467 return NULL; 5471 5468 } ··· 5497 5494 struct drm_i915_private *dev_priv = dev->dev_private; 5498 5495 u32 rgvmodectl = I915_READ(MEMMODECTL); 5499 5496 u8 fmax, fmin, fstart, vstart; 5500 5500 - int i = 0; 5501 5497 5502 5498 /* 100ms RC evaluation intervals */ 5503 5499 I915_WRITE(RCUPEI, 100000); ··· 5540 5538 rgvmodectl |= MEMMODE_SWMODE_EN; 5541 5539 I915_WRITE(MEMMODECTL, rgvmodectl); 5542 5540 5543 5543 - while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { 5544 5544 - if (i++ > 100) { 5545 5545 - DRM_ERROR("stuck trying to change perf mode\n"); 5546 5546 - break; 5547 5547 - } 5548 5548 - msleep(1); 5549 5549 - } 5541 5541 + if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0)) 5542 5542 + DRM_ERROR("stuck trying to change perf mode\n"); 5550 5543 msleep(1); 5551 5544 5552 5545 ironlake_set_drps(dev, fstart); ··· 5722 5725 ILK_DPFC_DIS2 | 5723 5726 ILK_CLK_FBC); 5724 5727 } 5725 5725 - return; 5728 5728 + if (IS_GEN6(dev)) 5729 5729 + return; 5726 5730 } else if (IS_G4X(dev)) { 5727 5731 uint32_t dspclk_gate; 5728 5732 I915_WRITE(RENCLK_GATE_D1, 0); ··· 5766 5768 * GPU can automatically power down the render unit if given a page 5767 5769 * to save state. 5768 5770 */ 5771 5771 + if (IS_IRONLAKE_M(dev)) { 5772 5772 + if (dev_priv->renderctx == NULL) 5773 5773 + dev_priv->renderctx = intel_alloc_context_page(dev); 5774 5774 + if (dev_priv->renderctx) { 5775 5775 + struct drm_i915_gem_object *obj_priv; 5776 5776 + obj_priv = to_intel_bo(dev_priv->renderctx); 5777 5777 + if (obj_priv) { 5778 5778 + BEGIN_LP_RING(4); 5779 5779 + OUT_RING(MI_SET_CONTEXT); 5780 5780 + OUT_RING(obj_priv->gtt_offset | 5781 5781 + MI_MM_SPACE_GTT | 5782 5782 + MI_SAVE_EXT_STATE_EN | 5783 5783 + MI_RESTORE_EXT_STATE_EN | 5784 5784 + MI_RESTORE_INHIBIT); 5785 5785 + OUT_RING(MI_NOOP); 5786 5786 + OUT_RING(MI_FLUSH); 5787 5787 + ADVANCE_LP_RING(); 5788 5788 + } 5789 5789 + } else { 5790 5790 + DRM_DEBUG_KMS("Failed to allocate render context." 5791 5791 + "Disable RC6\n"); 5792 5792 + return; 5793 5793 + } 5794 5794 + } 5795 5795 + 5769 5796 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5770 5797 struct drm_i915_gem_object *obj_priv = NULL; 5771 5798 ··· 5799 5776 } else { 5800 5777 struct drm_gem_object *pwrctx; 5801 5778 5802 5802 - pwrctx = intel_alloc_power_context(dev); 5779 5779 + pwrctx = intel_alloc_context_page(dev); 5803 5780 if (pwrctx) { 5804 5781 dev_priv->pwrctx = pwrctx; 5805 5782 obj_priv = to_intel_bo(pwrctx); ··· 5971 5948 } 5972 5949 } 5973 5950 5951 5951 + /* Disable the VGA plane that we never use */ 5952 5952 + static void i915_disable_vga(struct drm_device *dev) 5953 5953 + { 5954 5954 + struct drm_i915_private *dev_priv = dev->dev_private; 5955 5955 + u8 sr1; 5956 5956 + u32 vga_reg; 5957 5957 + 5958 5958 + if (HAS_PCH_SPLIT(dev)) 5959 5959 + vga_reg = CPU_VGACNTRL; 5960 5960 + else 5961 5961 + vga_reg = VGACNTRL; 5962 5962 + 5963 5963 + vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 5964 5964 + outb(1, VGA_SR_INDEX); 5965 5965 + sr1 = inb(VGA_SR_DATA); 5966 5966 + outb(sr1 | 1<<5, VGA_SR_DATA); 5967 5967 + vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 5968 5968 + udelay(300); 5969 5969 + 5970 5970 + I915_WRITE(vga_reg, VGA_DISP_DISABLE); 5971 5971 + POSTING_READ(vga_reg); 5972 5972 + } 5973 5973 + 5974 5974 void intel_modeset_init(struct drm_device *dev) 5975 5975 { 5976 5976 struct drm_i915_private *dev_priv = dev->dev_private; ··· 6042 5996 6043 5997 intel_init_clock_gating(dev); 6044 5998 5999 5999 + /* Just disable it once at startup */ 6000 6000 + i915_disable_vga(dev); 6001 6001 + 6045 6002 if (IS_IRONLAKE_M(dev)) { 6046 6003 ironlake_enable_drps(dev); 6047 6004 intel_init_emon(dev); ··· 6082 6033 6083 6034 if (dev_priv->display.disable_fbc) 6084 6035 dev_priv->display.disable_fbc(dev); 6036 6036 + 6037 6037 + if (dev_priv->renderctx) { 6038 6038 + struct drm_i915_gem_object *obj_priv; 6039 6039 + 6040 6040 + obj_priv = to_intel_bo(dev_priv->renderctx); 6041 6041 + I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN); 6042 6042 + I915_READ(CCID); 6043 6043 + i915_gem_object_unpin(dev_priv->renderctx); 6044 6044 + drm_gem_object_unreference(dev_priv->renderctx); 6045 6045 + } 6085 6046 6086 6047 if (dev_priv->pwrctx) { 6087 6048 struct drm_i915_gem_object *obj_priv;

+306 -288

drivers/gpu/drm/i915/intel_dp.c

reviewed

··· 42 42 43 43 #define DP_LINK_CONFIGURATION_SIZE 9 44 44 45 45 - #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP) 46 46 - #define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp) 45 45 + #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) 46 46 + #define IS_PCH_eDP(i) ((i)->is_pch_edp) 47 47 48 48 - struct intel_dp_priv { 48 48 + struct intel_dp { 49 49 + struct intel_encoder base; 49 50 uint32_t output_reg; 50 51 uint32_t DP; 51 52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; ··· 55 54 uint8_t link_bw; 56 55 uint8_t lane_count; 57 56 uint8_t dpcd[4]; 58 58 - struct intel_encoder *intel_encoder; 59 57 struct i2c_adapter adapter; 60 58 struct i2c_algo_dp_aux_data algo; 61 59 bool is_pch_edp; 62 60 }; 63 61 64 64 - static void 65 65 - intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 66 66 - uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); 62 62 + static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 63 63 + { 64 64 + return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); 65 65 + } 67 66 68 68 - static void 69 69 - intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP); 67 67 + static void intel_dp_link_train(struct intel_dp *intel_dp); 68 68 + static void intel_dp_link_down(struct intel_dp *intel_dp); 70 69 71 70 void 72 71 intel_edp_link_config (struct intel_encoder *intel_encoder, 73 73 - int *lane_num, int *link_bw) 72 72 + int *lane_num, int *link_bw) 74 73 { 75 75 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 74 74 + struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 76 75 77 77 - *lane_num = dp_priv->lane_count; 78 78 - if (dp_priv->link_bw == DP_LINK_BW_1_62) 76 76 + *lane_num = intel_dp->lane_count; 77 77 + if (intel_dp->link_bw == DP_LINK_BW_1_62) 79 78 *link_bw = 162000; 80 80 - else if (dp_priv->link_bw == DP_LINK_BW_2_7) 79 79 + else if (intel_dp->link_bw == DP_LINK_BW_2_7) 81 80 *link_bw = 270000; 82 81 } 83 82 84 83 static int 85 85 - intel_dp_max_lane_count(struct intel_encoder *intel_encoder) 84 84 + intel_dp_max_lane_count(struct intel_dp *intel_dp) 86 85 { 87 87 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 88 86 int max_lane_count = 4; 89 87 90 90 - if (dp_priv->dpcd[0] >= 0x11) { 91 91 - max_lane_count = dp_priv->dpcd[2] & 0x1f; 88 88 + if (intel_dp->dpcd[0] >= 0x11) { 89 89 + max_lane_count = intel_dp->dpcd[2] & 0x1f; 92 90 switch (max_lane_count) { 93 91 case 1: case 2: case 4: 94 92 break; ··· 99 99 } 100 100 101 101 static int 102 102 - intel_dp_max_link_bw(struct intel_encoder *intel_encoder) 102 102 + intel_dp_max_link_bw(struct intel_dp *intel_dp) 103 103 { 104 104 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 105 105 - int max_link_bw = dp_priv->dpcd[1]; 104 104 + int max_link_bw = intel_dp->dpcd[1]; 106 105 107 106 switch (max_link_bw) { 108 107 case DP_LINK_BW_1_62: ··· 125 126 126 127 /* I think this is a fiction */ 127 128 static int 128 128 - intel_dp_link_required(struct drm_device *dev, 129 129 - struct intel_encoder *intel_encoder, int pixel_clock) 129 129 + intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 130 130 { 131 131 struct drm_i915_private *dev_priv = dev->dev_private; 132 132 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 133 132 134 134 - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) 133 133 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 135 134 return (pixel_clock * dev_priv->edp_bpp) / 8; 136 135 else 137 136 return pixel_clock * 3; ··· 146 149 struct drm_display_mode *mode) 147 150 { 148 151 struct drm_encoder *encoder = intel_attached_encoder(connector); 149 149 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 150 150 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 152 152 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 151 153 struct drm_device *dev = connector->dev; 152 154 struct drm_i915_private *dev_priv = dev->dev_private; 153 153 - int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); 154 154 - int max_lanes = intel_dp_max_lane_count(intel_encoder); 155 155 + int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 156 156 + int max_lanes = intel_dp_max_lane_count(intel_dp); 155 157 156 156 - if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 158 158 + if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 157 159 dev_priv->panel_fixed_mode) { 158 160 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 159 161 return MODE_PANEL; ··· 163 167 164 168 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 165 169 which are outside spec tolerances but somehow work by magic */ 166 166 - if (!IS_eDP(intel_encoder) && 167 167 - (intel_dp_link_required(connector->dev, intel_encoder, mode->clock) 170 170 + if (!IS_eDP(intel_dp) && 171 171 + (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 168 172 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 169 173 return MODE_CLOCK_HIGH; 170 174 ··· 228 232 } 229 233 230 234 static int 231 231 - intel_dp_aux_ch(struct intel_encoder *intel_encoder, 235 235 + intel_dp_aux_ch(struct intel_dp *intel_dp, 232 236 uint8_t *send, int send_bytes, 233 237 uint8_t *recv, int recv_size) 234 238 { 235 235 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 236 236 - uint32_t output_reg = dp_priv->output_reg; 237 237 - struct drm_device *dev = intel_encoder->enc.dev; 239 239 + uint32_t output_reg = intel_dp->output_reg; 240 240 + struct drm_device *dev = intel_dp->base.enc.dev; 238 241 struct drm_i915_private *dev_priv = dev->dev_private; 239 242 uint32_t ch_ctl = output_reg + 0x10; 240 243 uint32_t ch_data = ch_ctl + 4; ··· 248 253 * and would like to run at 2MHz. So, take the 249 254 * hrawclk value and divide by 2 and use that 250 255 */ 251 251 - if (IS_eDP(intel_encoder)) { 256 256 + if (IS_eDP(intel_dp)) { 252 257 if (IS_GEN6(dev)) 253 258 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 254 259 else ··· 339 344 340 345 /* Write data to the aux channel in native mode */ 341 346 static int 342 342 - intel_dp_aux_native_write(struct intel_encoder *intel_encoder, 347 347 + intel_dp_aux_native_write(struct intel_dp *intel_dp, 343 348 uint16_t address, uint8_t *send, int send_bytes) 344 349 { 345 350 int ret; ··· 356 361 memcpy(&msg[4], send, send_bytes); 357 362 msg_bytes = send_bytes + 4; 358 363 for (;;) { 359 359 - ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1); 364 364 + ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 360 365 if (ret < 0) 361 366 return ret; 362 367 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) ··· 371 376 372 377 /* Write a single byte to the aux channel in native mode */ 373 378 static int 374 374 - intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder, 379 379 + intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 375 380 uint16_t address, uint8_t byte) 376 381 { 377 377 - return intel_dp_aux_native_write(intel_encoder, address, &byte, 1); 382 382 + return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 378 383 } 379 384 380 385 /* read bytes from a native aux channel */ 381 386 static int 382 382 - intel_dp_aux_native_read(struct intel_encoder *intel_encoder, 387 387 + intel_dp_aux_native_read(struct intel_dp *intel_dp, 383 388 uint16_t address, uint8_t *recv, int recv_bytes) 384 389 { 385 390 uint8_t msg[4]; ··· 398 403 reply_bytes = recv_bytes + 1; 399 404 400 405 for (;;) { 401 401 - ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, 406 406 + ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 402 407 reply, reply_bytes); 403 408 if (ret == 0) 404 409 return -EPROTO; ··· 421 426 uint8_t write_byte, uint8_t *read_byte) 422 427 { 423 428 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 424 424 - struct intel_dp_priv *dp_priv = container_of(adapter, 425 425 - struct intel_dp_priv, 426 426 - adapter); 427 427 - struct intel_encoder *intel_encoder = dp_priv->intel_encoder; 429 429 + struct intel_dp *intel_dp = container_of(adapter, 430 430 + struct intel_dp, 431 431 + adapter); 428 432 uint16_t address = algo_data->address; 429 433 uint8_t msg[5]; 430 434 uint8_t reply[2]; ··· 462 468 } 463 469 464 470 for (;;) { 465 465 - ret = intel_dp_aux_ch(intel_encoder, 471 471 + ret = intel_dp_aux_ch(intel_dp, 466 472 msg, msg_bytes, 467 473 reply, reply_bytes); 468 474 if (ret < 0) { ··· 490 496 } 491 497 492 498 static int 493 493 - intel_dp_i2c_init(struct intel_encoder *intel_encoder, 499 499 + intel_dp_i2c_init(struct intel_dp *intel_dp, 494 500 struct intel_connector *intel_connector, const char *name) 495 501 { 496 496 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 497 497 - 498 502 DRM_DEBUG_KMS("i2c_init %s\n", name); 499 499 - dp_priv->algo.running = false; 500 500 - dp_priv->algo.address = 0; 501 501 - dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; 503 503 + intel_dp->algo.running = false; 504 504 + intel_dp->algo.address = 0; 505 505 + intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 502 506 503 503 - memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter)); 504 504 - dp_priv->adapter.owner = THIS_MODULE; 505 505 - dp_priv->adapter.class = I2C_CLASS_DDC; 506 506 - strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); 507 507 - dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; 508 508 - dp_priv->adapter.algo_data = &dp_priv->algo; 509 509 - dp_priv->adapter.dev.parent = &intel_connector->base.kdev; 510 510 - 511 511 - return i2c_dp_aux_add_bus(&dp_priv->adapter); 507 507 + memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 508 508 + intel_dp->adapter.owner = THIS_MODULE; 509 509 + intel_dp->adapter.class = I2C_CLASS_DDC; 510 510 + strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 511 511 + intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 512 512 + intel_dp->adapter.algo_data = &intel_dp->algo; 513 513 + intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 514 514 + 515 515 + return i2c_dp_aux_add_bus(&intel_dp->adapter); 512 516 } 513 517 514 518 static bool 515 519 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 516 520 struct drm_display_mode *adjusted_mode) 517 521 { 518 518 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 519 519 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 520 522 struct drm_device *dev = encoder->dev; 521 523 struct drm_i915_private *dev_priv = dev->dev_private; 524 524 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 522 525 int lane_count, clock; 523 523 - int max_lane_count = intel_dp_max_lane_count(intel_encoder); 524 524 - int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; 526 526 + int max_lane_count = intel_dp_max_lane_count(intel_dp); 527 527 + int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 525 528 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 526 529 527 527 - if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 530 530 + if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 528 531 dev_priv->panel_fixed_mode) { 529 529 - struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; 530 530 - 531 531 - adjusted_mode->hdisplay = fixed_mode->hdisplay; 532 532 - adjusted_mode->hsync_start = fixed_mode->hsync_start; 533 533 - adjusted_mode->hsync_end = fixed_mode->hsync_end; 534 534 - adjusted_mode->htotal = fixed_mode->htotal; 535 535 - 536 536 - adjusted_mode->vdisplay = fixed_mode->vdisplay; 537 537 - adjusted_mode->vsync_start = fixed_mode->vsync_start; 538 538 - adjusted_mode->vsync_end = fixed_mode->vsync_end; 539 539 - adjusted_mode->vtotal = fixed_mode->vtotal; 540 540 - 541 541 - adjusted_mode->clock = fixed_mode->clock; 542 542 - drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 543 543 - 532 532 + intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 533 533 + intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 534 534 + mode, adjusted_mode); 544 535 /* 545 536 * the mode->clock is used to calculate the Data&Link M/N 546 537 * of the pipe. For the eDP the fixed clock should be used. ··· 537 558 for (clock = 0; clock <= max_clock; clock++) { 538 559 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 539 560 540 540 - if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock) 561 561 + if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 541 562 <= link_avail) { 542 542 - dp_priv->link_bw = bws[clock]; 543 543 - dp_priv->lane_count = lane_count; 544 544 - adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 563 563 + intel_dp->link_bw = bws[clock]; 564 564 + intel_dp->lane_count = lane_count; 565 565 + adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 545 566 DRM_DEBUG_KMS("Display port link bw %02x lane " 546 567 "count %d clock %d\n", 547 547 - dp_priv->link_bw, dp_priv->lane_count, 568 568 + intel_dp->link_bw, intel_dp->lane_count, 548 569 adjusted_mode->clock); 549 570 return true; 550 571 } 551 572 } 552 573 } 553 574 554 554 - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 575 575 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 555 576 /* okay we failed just pick the highest */ 556 556 - dp_priv->lane_count = max_lane_count; 557 557 - dp_priv->link_bw = bws[max_clock]; 558 558 - adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 577 577 + intel_dp->lane_count = max_lane_count; 578 578 + intel_dp->link_bw = bws[max_clock]; 579 579 + adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 559 580 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 560 581 "count %d clock %d\n", 561 561 - dp_priv->link_bw, dp_priv->lane_count, 582 582 + intel_dp->link_bw, intel_dp->lane_count, 562 583 adjusted_mode->clock); 584 584 + 563 585 return true; 564 586 } 587 587 + 565 588 return false; 566 589 } 567 590 ··· 607 626 struct drm_encoder *encoder; 608 627 609 628 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 610 610 - struct intel_encoder *intel_encoder; 611 611 - struct intel_dp_priv *dp_priv; 629 629 + struct intel_dp *intel_dp; 612 630 613 613 - if (!encoder || encoder->crtc != crtc) 631 631 + if (encoder->crtc != crtc) 614 632 continue; 615 633 616 616 - intel_encoder = enc_to_intel_encoder(encoder); 617 617 - dp_priv = intel_encoder->dev_priv; 618 618 - 619 619 - if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) 620 620 - return dp_priv->is_pch_edp; 634 634 + intel_dp = enc_to_intel_dp(encoder); 635 635 + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 636 636 + return intel_dp->is_pch_edp; 621 637 } 622 638 return false; 623 639 } ··· 635 657 * Find the lane count in the intel_encoder private 636 658 */ 637 659 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 638 638 - struct intel_encoder *intel_encoder; 639 639 - struct intel_dp_priv *dp_priv; 660 660 + struct intel_dp *intel_dp; 640 661 641 662 if (encoder->crtc != crtc) 642 663 continue; 643 664 644 644 - intel_encoder = enc_to_intel_encoder(encoder); 645 645 - dp_priv = intel_encoder->dev_priv; 646 646 - 647 647 - if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 648 648 - lane_count = dp_priv->lane_count; 649 649 - if (IS_PCH_eDP(dp_priv)) 665 665 + intel_dp = enc_to_intel_dp(encoder); 666 666 + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 667 667 + lane_count = intel_dp->lane_count; 668 668 + if (IS_PCH_eDP(intel_dp)) 650 669 bpp = dev_priv->edp_bpp; 651 670 break; 652 671 } ··· 699 724 struct drm_display_mode *adjusted_mode) 700 725 { 701 726 struct drm_device *dev = encoder->dev; 702 702 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 703 703 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 704 704 - struct drm_crtc *crtc = intel_encoder->enc.crtc; 727 727 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 728 728 + struct drm_crtc *crtc = intel_dp->base.enc.crtc; 705 729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 706 730 707 707 - dp_priv->DP = (DP_VOLTAGE_0_4 | 731 731 + intel_dp->DP = (DP_VOLTAGE_0_4 | 708 732 DP_PRE_EMPHASIS_0); 709 733 710 734 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 711 711 - dp_priv->DP |= DP_SYNC_HS_HIGH; 735 735 + intel_dp->DP |= DP_SYNC_HS_HIGH; 712 736 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 713 713 - dp_priv->DP |= DP_SYNC_VS_HIGH; 737 737 + intel_dp->DP |= DP_SYNC_VS_HIGH; 714 738 715 715 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 716 716 - dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT; 739 739 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 740 740 + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 717 741 else 718 718 - dp_priv->DP |= DP_LINK_TRAIN_OFF; 742 742 + intel_dp->DP |= DP_LINK_TRAIN_OFF; 719 743 720 720 - switch (dp_priv->lane_count) { 744 744 + switch (intel_dp->lane_count) { 721 745 case 1: 722 722 - dp_priv->DP |= DP_PORT_WIDTH_1; 746 746 + intel_dp->DP |= DP_PORT_WIDTH_1; 723 747 break; 724 748 case 2: 725 725 - dp_priv->DP |= DP_PORT_WIDTH_2; 749 749 + intel_dp->DP |= DP_PORT_WIDTH_2; 726 750 break; 727 751 case 4: 728 728 - dp_priv->DP |= DP_PORT_WIDTH_4; 752 752 + intel_dp->DP |= DP_PORT_WIDTH_4; 729 753 break; 730 754 } 731 731 - if (dp_priv->has_audio) 732 732 - dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE; 755 755 + if (intel_dp->has_audio) 756 756 + intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 733 757 734 734 - memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 735 735 - dp_priv->link_configuration[0] = dp_priv->link_bw; 736 736 - dp_priv->link_configuration[1] = dp_priv->lane_count; 758 758 + memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 759 759 + intel_dp->link_configuration[0] = intel_dp->link_bw; 760 760 + intel_dp->link_configuration[1] = intel_dp->lane_count; 737 761 738 762 /* 739 763 * Check for DPCD version > 1.1 and enhanced framing support 740 764 */ 741 741 - if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 742 742 - dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 743 743 - dp_priv->DP |= DP_ENHANCED_FRAMING; 765 765 + if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 766 766 + intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 767 767 + intel_dp->DP |= DP_ENHANCED_FRAMING; 744 768 } 745 769 746 770 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 747 771 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 748 748 - dp_priv->DP |= DP_PIPEB_SELECT; 772 772 + intel_dp->DP |= DP_PIPEB_SELECT; 749 773 750 750 - if (IS_eDP(intel_encoder)) { 774 774 + if (IS_eDP(intel_dp)) { 751 775 /* don't miss out required setting for eDP */ 752 752 - dp_priv->DP |= DP_PLL_ENABLE; 776 776 + intel_dp->DP |= DP_PLL_ENABLE; 753 777 if (adjusted_mode->clock < 200000) 754 754 - dp_priv->DP |= DP_PLL_FREQ_160MHZ; 778 778 + intel_dp->DP |= DP_PLL_FREQ_160MHZ; 755 779 else 756 756 - dp_priv->DP |= DP_PLL_FREQ_270MHZ; 780 780 + intel_dp->DP |= DP_PLL_FREQ_270MHZ; 757 781 } 758 782 } 759 783 760 784 static void ironlake_edp_panel_on (struct drm_device *dev) 761 785 { 762 786 struct drm_i915_private *dev_priv = dev->dev_private; 763 763 - unsigned long timeout = jiffies + msecs_to_jiffies(5000); 764 764 - u32 pp, pp_status; 787 787 + u32 pp; 765 788 766 766 - pp_status = I915_READ(PCH_PP_STATUS); 767 767 - if (pp_status & PP_ON) 789 789 + if (I915_READ(PCH_PP_STATUS) & PP_ON) 768 790 return; 769 791 770 792 pp = I915_READ(PCH_PP_CONTROL); 793 793 + 794 794 + /* ILK workaround: disable reset around power sequence */ 795 795 + pp &= ~PANEL_POWER_RESET; 796 796 + I915_WRITE(PCH_PP_CONTROL, pp); 797 797 + POSTING_READ(PCH_PP_CONTROL); 798 798 + 771 799 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 772 800 I915_WRITE(PCH_PP_CONTROL, pp); 773 773 - do { 774 774 - pp_status = I915_READ(PCH_PP_STATUS); 775 775 - } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout)); 776 801 777 777 - if (time_after(jiffies, timeout)) 778 778 - DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status); 802 802 + if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) 803 803 + DRM_ERROR("panel on wait timed out: 0x%08x\n", 804 804 + I915_READ(PCH_PP_STATUS)); 779 805 780 806 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); 807 807 + pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 781 808 I915_WRITE(PCH_PP_CONTROL, pp); 809 809 + POSTING_READ(PCH_PP_CONTROL); 782 810 } 783 811 784 812 static void ironlake_edp_panel_off (struct drm_device *dev) 785 813 { 786 814 struct drm_i915_private *dev_priv = dev->dev_private; 787 787 - unsigned long timeout = jiffies + msecs_to_jiffies(5000); 788 788 - u32 pp, pp_status; 815 815 + u32 pp; 789 816 790 817 pp = I915_READ(PCH_PP_CONTROL); 818 818 + 819 819 + /* ILK workaround: disable reset around power sequence */ 820 820 + pp &= ~PANEL_POWER_RESET; 821 821 + I915_WRITE(PCH_PP_CONTROL, pp); 822 822 + POSTING_READ(PCH_PP_CONTROL); 823 823 + 791 824 pp &= ~POWER_TARGET_ON; 792 825 I915_WRITE(PCH_PP_CONTROL, pp); 793 793 - do { 794 794 - pp_status = I915_READ(PCH_PP_STATUS); 795 795 - } while ((pp_status & PP_ON) && !time_after(jiffies, timeout)); 796 826 797 797 - if (time_after(jiffies, timeout)) 798 798 - DRM_DEBUG_KMS("panel off wait timed out\n"); 827 827 + if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) 828 828 + DRM_ERROR("panel off wait timed out: 0x%08x\n", 829 829 + I915_READ(PCH_PP_STATUS)); 799 830 800 831 /* Make sure VDD is enabled so DP AUX will work */ 801 801 - pp |= EDP_FORCE_VDD; 832 832 + pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ 802 833 I915_WRITE(PCH_PP_CONTROL, pp); 834 834 + POSTING_READ(PCH_PP_CONTROL); 803 835 } 804 836 805 837 static void ironlake_edp_backlight_on (struct drm_device *dev) ··· 831 849 I915_WRITE(PCH_PP_CONTROL, pp); 832 850 } 833 851 852 852 + static void ironlake_edp_pll_on(struct drm_encoder *encoder) 853 853 + { 854 854 + struct drm_device *dev = encoder->dev; 855 855 + struct drm_i915_private *dev_priv = dev->dev_private; 856 856 + u32 dpa_ctl; 857 857 + 858 858 + DRM_DEBUG_KMS("\n"); 859 859 + dpa_ctl = I915_READ(DP_A); 860 860 + dpa_ctl &= ~DP_PLL_ENABLE; 861 861 + I915_WRITE(DP_A, dpa_ctl); 862 862 + } 863 863 + 864 864 + static void ironlake_edp_pll_off(struct drm_encoder *encoder) 865 865 + { 866 866 + struct drm_device *dev = encoder->dev; 867 867 + struct drm_i915_private *dev_priv = dev->dev_private; 868 868 + u32 dpa_ctl; 869 869 + 870 870 + dpa_ctl = I915_READ(DP_A); 871 871 + dpa_ctl |= DP_PLL_ENABLE; 872 872 + I915_WRITE(DP_A, dpa_ctl); 873 873 + udelay(200); 874 874 + } 875 875 + 876 876 + static void intel_dp_prepare(struct drm_encoder *encoder) 877 877 + { 878 878 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 879 879 + struct drm_device *dev = encoder->dev; 880 880 + struct drm_i915_private *dev_priv = dev->dev_private; 881 881 + uint32_t dp_reg = I915_READ(intel_dp->output_reg); 882 882 + 883 883 + if (IS_eDP(intel_dp)) { 884 884 + ironlake_edp_backlight_off(dev); 885 885 + ironlake_edp_panel_on(dev); 886 886 + ironlake_edp_pll_on(encoder); 887 887 + } 888 888 + if (dp_reg & DP_PORT_EN) 889 889 + intel_dp_link_down(intel_dp); 890 890 + } 891 891 + 892 892 + static void intel_dp_commit(struct drm_encoder *encoder) 893 893 + { 894 894 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 895 895 + struct drm_device *dev = encoder->dev; 896 896 + struct drm_i915_private *dev_priv = dev->dev_private; 897 897 + uint32_t dp_reg = I915_READ(intel_dp->output_reg); 898 898 + 899 899 + if (!(dp_reg & DP_PORT_EN)) { 900 900 + intel_dp_link_train(intel_dp); 901 901 + } 902 902 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 903 903 + ironlake_edp_backlight_on(dev); 904 904 + } 905 905 + 834 906 static void 835 907 intel_dp_dpms(struct drm_encoder *encoder, int mode) 836 908 { 837 837 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 838 838 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 909 909 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 839 910 struct drm_device *dev = encoder->dev; 840 911 struct drm_i915_private *dev_priv = dev->dev_private; 841 841 - uint32_t dp_reg = I915_READ(dp_priv->output_reg); 912 912 + uint32_t dp_reg = I915_READ(intel_dp->output_reg); 842 913 843 914 if (mode != DRM_MODE_DPMS_ON) { 844 844 - if (dp_reg & DP_PORT_EN) { 845 845 - intel_dp_link_down(intel_encoder, dp_priv->DP); 846 846 - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 847 847 - ironlake_edp_backlight_off(dev); 848 848 - ironlake_edp_panel_off(dev); 849 849 - } 915 915 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 916 916 + ironlake_edp_backlight_off(dev); 917 917 + ironlake_edp_panel_off(dev); 850 918 } 919 919 + if (dp_reg & DP_PORT_EN) 920 920 + intel_dp_link_down(intel_dp); 921 921 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 922 922 + ironlake_edp_pll_off(encoder); 851 923 } else { 852 924 if (!(dp_reg & DP_PORT_EN)) { 853 853 - intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 854 854 - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 925 925 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 855 926 ironlake_edp_panel_on(dev); 927 927 + intel_dp_link_train(intel_dp); 928 928 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 856 929 ironlake_edp_backlight_on(dev); 857 857 - } 858 930 } 859 931 } 860 860 - dp_priv->dpms_mode = mode; 932 932 + intel_dp->dpms_mode = mode; 861 933 } 862 934 863 935 /* ··· 919 883 * link status information 920 884 */ 921 885 static bool 922 922 - intel_dp_get_link_status(struct intel_encoder *intel_encoder, 886 886 + intel_dp_get_link_status(struct intel_dp *intel_dp, 923 887 uint8_t link_status[DP_LINK_STATUS_SIZE]) 924 888 { 925 889 int ret; 926 890 927 927 - ret = intel_dp_aux_native_read(intel_encoder, 891 891 + ret = intel_dp_aux_native_read(intel_dp, 928 892 DP_LANE0_1_STATUS, 929 893 link_status, DP_LINK_STATUS_SIZE); 930 894 if (ret != DP_LINK_STATUS_SIZE) ··· 1001 965 } 1002 966 1003 967 static void 1004 1004 - intel_get_adjust_train(struct intel_encoder *intel_encoder, 968 968 + intel_get_adjust_train(struct intel_dp *intel_dp, 1005 969 uint8_t link_status[DP_LINK_STATUS_SIZE], 1006 970 int lane_count, 1007 971 uint8_t train_set[4]) ··· 1137 1101 } 1138 1102 1139 1103 static bool 1140 1140 - intel_dp_set_link_train(struct intel_encoder *intel_encoder, 1104 1104 + intel_dp_set_link_train(struct intel_dp *intel_dp, 1141 1105 uint32_t dp_reg_value, 1142 1106 uint8_t dp_train_pat, 1143 1107 uint8_t train_set[4], 1144 1108 bool first) 1145 1109 { 1146 1146 - struct drm_device *dev = intel_encoder->enc.dev; 1110 1110 + struct drm_device *dev = intel_dp->base.enc.dev; 1147 1111 struct drm_i915_private *dev_priv = dev->dev_private; 1148 1148 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1112 1112 + struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); 1149 1113 int ret; 1150 1114 1151 1151 - I915_WRITE(dp_priv->output_reg, dp_reg_value); 1152 1152 - POSTING_READ(dp_priv->output_reg); 1115 1115 + I915_WRITE(intel_dp->output_reg, dp_reg_value); 1116 1116 + POSTING_READ(intel_dp->output_reg); 1153 1117 if (first) 1154 1154 - intel_wait_for_vblank(dev); 1118 1118 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1155 1119 1156 1156 - intel_dp_aux_native_write_1(intel_encoder, 1120 1120 + intel_dp_aux_native_write_1(intel_dp, 1157 1121 DP_TRAINING_PATTERN_SET, 1158 1122 dp_train_pat); 1159 1123 1160 1160 - ret = intel_dp_aux_native_write(intel_encoder, 1124 1124 + ret = intel_dp_aux_native_write(intel_dp, 1161 1125 DP_TRAINING_LANE0_SET, train_set, 4); 1162 1126 if (ret != 4) 1163 1127 return false; ··· 1166 1130 } 1167 1131 1168 1132 static void 1169 1169 - intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 1170 1170 - uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) 1133 1133 + intel_dp_link_train(struct intel_dp *intel_dp) 1171 1134 { 1172 1172 - struct drm_device *dev = intel_encoder->enc.dev; 1135 1135 + struct drm_device *dev = intel_dp->base.enc.dev; 1173 1136 struct drm_i915_private *dev_priv = dev->dev_private; 1174 1174 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1175 1137 uint8_t train_set[4]; 1176 1138 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1177 1139 int i; ··· 1179 1145 bool first = true; 1180 1146 int tries; 1181 1147 u32 reg; 1148 1148 + uint32_t DP = intel_dp->DP; 1182 1149 1183 1150 /* Write the link configuration data */ 1184 1184 - intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET, 1185 1185 - link_configuration, DP_LINK_CONFIGURATION_SIZE); 1151 1151 + intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1152 1152 + intel_dp->link_configuration, 1153 1153 + DP_LINK_CONFIGURATION_SIZE); 1186 1154 1187 1155 DP |= DP_PORT_EN; 1188 1188 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1156 1156 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1189 1157 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1190 1158 else 1191 1159 DP &= ~DP_LINK_TRAIN_MASK; ··· 1198 1162 for (;;) { 1199 1163 /* Use train_set[0] to set the voltage and pre emphasis values */ 1200 1164 uint32_t signal_levels; 1201 1201 - if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1165 1165 + if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1202 1166 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1203 1167 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1204 1168 } else { 1205 1205 - signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1169 1169 + signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1206 1170 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1207 1171 } 1208 1172 1209 1209 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1173 1173 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1210 1174 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1211 1175 else 1212 1176 reg = DP | DP_LINK_TRAIN_PAT_1; 1213 1177 1214 1214 - if (!intel_dp_set_link_train(intel_encoder, reg, 1178 1178 + if (!intel_dp_set_link_train(intel_dp, reg, 1215 1179 DP_TRAINING_PATTERN_1, train_set, first)) 1216 1180 break; 1217 1181 first = false; 1218 1182 /* Set training pattern 1 */ 1219 1183 1220 1184 udelay(100); 1221 1221 - if (!intel_dp_get_link_status(intel_encoder, link_status)) 1185 1185 + if (!intel_dp_get_link_status(intel_dp, link_status)) 1222 1186 break; 1223 1187 1224 1224 - if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { 1188 1188 + if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1225 1189 clock_recovery = true; 1226 1190 break; 1227 1191 } 1228 1192 1229 1193 /* Check to see if we've tried the max voltage */ 1230 1230 - for (i = 0; i < dp_priv->lane_count; i++) 1194 1194 + for (i = 0; i < intel_dp->lane_count; i++) 1231 1195 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1232 1196 break; 1233 1233 - if (i == dp_priv->lane_count) 1197 1197 + if (i == intel_dp->lane_count) 1234 1198 break; 1235 1199 1236 1200 /* Check to see if we've tried the same voltage 5 times */ ··· 1243 1207 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1244 1208 1245 1209 /* Compute new train_set as requested by target */ 1246 1246 - intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1210 1210 + intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1247 1211 } 1248 1212 1249 1213 /* channel equalization */ ··· 1253 1217 /* Use train_set[0] to set the voltage and pre emphasis values */ 1254 1218 uint32_t signal_levels; 1255 1219 1256 1256 - if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1220 1220 + if (IS_GEN6(dev) && IS_eDP(intel_dp)) { 1257 1221 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1258 1222 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1259 1223 } else { 1260 1260 - signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1224 1224 + signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); 1261 1225 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1262 1226 } 1263 1227 1264 1264 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1228 1228 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1265 1229 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1266 1230 else 1267 1231 reg = DP | DP_LINK_TRAIN_PAT_2; 1268 1232 1269 1233 /* channel eq pattern */ 1270 1270 - if (!intel_dp_set_link_train(intel_encoder, reg, 1234 1234 + if (!intel_dp_set_link_train(intel_dp, reg, 1271 1235 DP_TRAINING_PATTERN_2, train_set, 1272 1236 false)) 1273 1237 break; 1274 1238 1275 1239 udelay(400); 1276 1276 - if (!intel_dp_get_link_status(intel_encoder, link_status)) 1240 1240 + if (!intel_dp_get_link_status(intel_dp, link_status)) 1277 1241 break; 1278 1242 1279 1279 - if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { 1243 1243 + if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { 1280 1244 channel_eq = true; 1281 1245 break; 1282 1246 } ··· 1286 1250 break; 1287 1251 1288 1252 /* Compute new train_set as requested by target */ 1289 1289 - intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1253 1253 + intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); 1290 1254 ++tries; 1291 1255 } 1292 1256 1293 1293 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1257 1257 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) 1294 1258 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1295 1259 else 1296 1260 reg = DP | DP_LINK_TRAIN_OFF; 1297 1261 1298 1298 - I915_WRITE(dp_priv->output_reg, reg); 1299 1299 - POSTING_READ(dp_priv->output_reg); 1300 1300 - intel_dp_aux_native_write_1(intel_encoder, 1262 1262 + I915_WRITE(intel_dp->output_reg, reg); 1263 1263 + POSTING_READ(intel_dp->output_reg); 1264 1264 + intel_dp_aux_native_write_1(intel_dp, 1301 1265 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1302 1266 } 1303 1267 1304 1268 static void 1305 1305 - intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) 1269 1269 + intel_dp_link_down(struct intel_dp *intel_dp) 1306 1270 { 1307 1307 - struct drm_device *dev = intel_encoder->enc.dev; 1271 1271 + struct drm_device *dev = intel_dp->base.enc.dev; 1308 1272 struct drm_i915_private *dev_priv = dev->dev_private; 1309 1309 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1273 1273 + uint32_t DP = intel_dp->DP; 1310 1274 1311 1275 DRM_DEBUG_KMS("\n"); 1312 1276 1313 1313 - if (IS_eDP(intel_encoder)) { 1277 1277 + if (IS_eDP(intel_dp)) { 1314 1278 DP &= ~DP_PLL_ENABLE; 1315 1315 - I915_WRITE(dp_priv->output_reg, DP); 1316 1316 - POSTING_READ(dp_priv->output_reg); 1279 1279 + I915_WRITE(intel_dp->output_reg, DP); 1280 1280 + POSTING_READ(intel_dp->output_reg); 1317 1281 udelay(100); 1318 1282 } 1319 1283 1320 1320 - if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) { 1284 1284 + if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { 1321 1285 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1322 1322 - I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1323 1323 - POSTING_READ(dp_priv->output_reg); 1286 1286 + I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1287 1287 + POSTING_READ(intel_dp->output_reg); 1324 1288 } else { 1325 1289 DP &= ~DP_LINK_TRAIN_MASK; 1326 1326 - I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1327 1327 - POSTING_READ(dp_priv->output_reg); 1290 1290 + I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1291 1291 + POSTING_READ(intel_dp->output_reg); 1328 1292 } 1329 1293 1330 1294 udelay(17000); 1331 1295 1332 1332 - if (IS_eDP(intel_encoder)) 1296 1296 + if (IS_eDP(intel_dp)) 1333 1297 DP |= DP_LINK_TRAIN_OFF; 1334 1334 - I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1335 1335 - POSTING_READ(dp_priv->output_reg); 1298 1298 + I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1299 1299 + POSTING_READ(intel_dp->output_reg); 1336 1300 } 1337 1301 1338 1302 /* ··· 1345 1309 */ 1346 1310 1347 1311 static void 1348 1348 - intel_dp_check_link_status(struct intel_encoder *intel_encoder) 1312 1312 + intel_dp_check_link_status(struct intel_dp *intel_dp) 1349 1313 { 1350 1350 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1351 1314 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1352 1315 1353 1353 - if (!intel_encoder->enc.crtc) 1316 1316 + if (!intel_dp->base.enc.crtc) 1354 1317 return; 1355 1318 1356 1356 - if (!intel_dp_get_link_status(intel_encoder, link_status)) { 1357 1357 - intel_dp_link_down(intel_encoder, dp_priv->DP); 1319 1319 + if (!intel_dp_get_link_status(intel_dp, link_status)) { 1320 1320 + intel_dp_link_down(intel_dp); 1358 1321 return; 1359 1322 } 1360 1323 1361 1361 - if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) 1362 1362 - intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 1324 1324 + if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) 1325 1325 + intel_dp_link_train(intel_dp); 1363 1326 } 1364 1327 1365 1328 static enum drm_connector_status 1366 1329 ironlake_dp_detect(struct drm_connector *connector) 1367 1330 { 1368 1331 struct drm_encoder *encoder = intel_attached_encoder(connector); 1369 1369 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1370 1370 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1332 1332 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1371 1333 enum drm_connector_status status; 1372 1334 1373 1335 status = connector_status_disconnected; 1374 1374 - if (intel_dp_aux_native_read(intel_encoder, 1375 1375 - 0x000, dp_priv->dpcd, 1376 1376 - sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1336 1336 + if (intel_dp_aux_native_read(intel_dp, 1337 1337 + 0x000, intel_dp->dpcd, 1338 1338 + sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1377 1339 { 1378 1378 - if (dp_priv->dpcd[0] != 0) 1340 1340 + if (intel_dp->dpcd[0] != 0) 1379 1341 status = connector_status_connected; 1380 1342 } 1381 1381 - DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0], 1382 1382 - dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]); 1343 1343 + DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1344 1344 + intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1383 1345 return status; 1384 1346 } 1385 1347 ··· 1391 1357 intel_dp_detect(struct drm_connector *connector) 1392 1358 { 1393 1359 struct drm_encoder *encoder = intel_attached_encoder(connector); 1394 1394 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1395 1395 - struct drm_device *dev = intel_encoder->enc.dev; 1360 1360 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1361 1361 + struct drm_device *dev = intel_dp->base.enc.dev; 1396 1362 struct drm_i915_private *dev_priv = dev->dev_private; 1397 1397 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1398 1363 uint32_t temp, bit; 1399 1364 enum drm_connector_status status; 1400 1365 1401 1401 - dp_priv->has_audio = false; 1366 1366 + intel_dp->has_audio = false; 1402 1367 1403 1368 if (HAS_PCH_SPLIT(dev)) 1404 1369 return ironlake_dp_detect(connector); 1405 1370 1406 1406 - switch (dp_priv->output_reg) { 1371 1371 + switch (intel_dp->output_reg) { 1407 1372 case DP_B: 1408 1373 bit = DPB_HOTPLUG_INT_STATUS; 1409 1374 break; ··· 1422 1389 return connector_status_disconnected; 1423 1390 1424 1391 status = connector_status_disconnected; 1425 1425 - if (intel_dp_aux_native_read(intel_encoder, 1426 1426 - 0x000, dp_priv->dpcd, 1427 1427 - sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1392 1392 + if (intel_dp_aux_native_read(intel_dp, 1393 1393 + 0x000, intel_dp->dpcd, 1394 1394 + sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1428 1395 { 1429 1429 - if (dp_priv->dpcd[0] != 0) 1396 1396 + if (intel_dp->dpcd[0] != 0) 1430 1397 status = connector_status_connected; 1431 1398 } 1432 1399 return status; ··· 1435 1402 static int intel_dp_get_modes(struct drm_connector *connector) 1436 1403 { 1437 1404 struct drm_encoder *encoder = intel_attached_encoder(connector); 1438 1438 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1439 1439 - struct drm_device *dev = intel_encoder->enc.dev; 1405 1405 + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1406 1406 + struct drm_device *dev = intel_dp->base.enc.dev; 1440 1407 struct drm_i915_private *dev_priv = dev->dev_private; 1441 1441 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1442 1408 int ret; 1443 1409 1444 1410 /* We should parse the EDID data and find out if it has an audio sink 1445 1411 */ 1446 1412 1447 1447 - ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1413 1413 + ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); 1448 1414 if (ret) { 1449 1449 - if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 1415 1415 + if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && 1450 1416 !dev_priv->panel_fixed_mode) { 1451 1417 struct drm_display_mode *newmode; 1452 1418 list_for_each_entry(newmode, &connector->probed_modes, ··· 1462 1430 } 1463 1431 1464 1432 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1465 1465 - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 1433 1433 + if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { 1466 1434 if (dev_priv->panel_fixed_mode != NULL) { 1467 1435 struct drm_display_mode *mode; 1468 1436 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); ··· 1484 1452 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1485 1453 .dpms = intel_dp_dpms, 1486 1454 .mode_fixup = intel_dp_mode_fixup, 1487 1487 - .prepare = intel_encoder_prepare, 1455 1455 + .prepare = intel_dp_prepare, 1488 1456 .mode_set = intel_dp_mode_set, 1489 1489 - .commit = intel_encoder_commit, 1457 1457 + .commit = intel_dp_commit, 1490 1458 }; 1491 1459 1492 1460 static const struct drm_connector_funcs intel_dp_connector_funcs = { ··· 1502 1470 .best_encoder = intel_attached_encoder, 1503 1471 }; 1504 1472 1505 1505 - static void intel_dp_enc_destroy(struct drm_encoder *encoder) 1506 1506 - { 1507 1507 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1508 1508 - 1509 1509 - if (intel_encoder->i2c_bus) 1510 1510 - intel_i2c_destroy(intel_encoder->i2c_bus); 1511 1511 - drm_encoder_cleanup(encoder); 1512 1512 - kfree(intel_encoder); 1513 1513 - } 1514 1514 - 1515 1473 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1516 1516 - .destroy = intel_dp_enc_destroy, 1474 1474 + .destroy = intel_encoder_destroy, 1517 1475 }; 1518 1476 1519 1477 void 1520 1478 intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1521 1479 { 1522 1522 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1480 1480 + struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1523 1481 1524 1524 - if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1525 1525 - intel_dp_check_link_status(intel_encoder); 1482 1482 + if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1483 1483 + intel_dp_check_link_status(intel_dp); 1526 1484 } 1527 1485 1528 1486 /* Return which DP Port should be selected for Transcoder DP control */ ··· 1522 1500 struct drm_device *dev = crtc->dev; 1523 1501 struct drm_mode_config *mode_config = &dev->mode_config; 1524 1502 struct drm_encoder *encoder; 1525 1525 - struct intel_encoder *intel_encoder = NULL; 1526 1503 1527 1504 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1505 1505 + struct intel_dp *intel_dp; 1506 1506 + 1528 1507 if (encoder->crtc != crtc) 1529 1508 continue; 1530 1509 1531 1531 - intel_encoder = enc_to_intel_encoder(encoder); 1532 1532 - if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1533 1533 - struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1534 1534 - return dp_priv->output_reg; 1535 1535 - } 1510 1510 + intel_dp = enc_to_intel_dp(encoder); 1511 1511 + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1512 1512 + return intel_dp->output_reg; 1536 1513 } 1514 1514 + 1537 1515 return -1; 1538 1516 } 1539 1517 ··· 1562 1540 { 1563 1541 struct drm_i915_private *dev_priv = dev->dev_private; 1564 1542 struct drm_connector *connector; 1543 1543 + struct intel_dp *intel_dp; 1565 1544 struct intel_encoder *intel_encoder; 1566 1545 struct intel_connector *intel_connector; 1567 1567 - struct intel_dp_priv *dp_priv; 1568 1546 const char *name = NULL; 1569 1547 int type; 1570 1548 1571 1571 - intel_encoder = kcalloc(sizeof(struct intel_encoder) + 1572 1572 - sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1573 1573 - if (!intel_encoder) 1549 1549 + intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1550 1550 + if (!intel_dp) 1574 1551 return; 1575 1552 1576 1553 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1577 1554 if (!intel_connector) { 1578 1578 - kfree(intel_encoder); 1555 1555 + kfree(intel_dp); 1579 1556 return; 1580 1557 } 1558 1558 + intel_encoder = &intel_dp->base; 1581 1559 1582 1582 - dp_priv = (struct intel_dp_priv *)(intel_encoder + 1); 1583 1583 - 1584 1584 - if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D)) 1560 1560 + if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1585 1561 if (intel_dpd_is_edp(dev)) 1586 1586 - dp_priv->is_pch_edp = true; 1562 1562 + intel_dp->is_pch_edp = true; 1587 1563 1588 1588 - if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1564 1564 + if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 1589 1565 type = DRM_MODE_CONNECTOR_eDP; 1590 1566 intel_encoder->type = INTEL_OUTPUT_EDP; 1591 1567 } else { ··· 1604 1584 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1605 1585 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1606 1586 1607 1607 - if (IS_eDP(intel_encoder)) 1587 1587 + if (IS_eDP(intel_dp)) 1608 1588 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1609 1589 1610 1590 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1611 1591 connector->interlace_allowed = true; 1612 1592 connector->doublescan_allowed = 0; 1613 1593 1614 1614 - dp_priv->intel_encoder = intel_encoder; 1615 1615 - dp_priv->output_reg = output_reg; 1616 1616 - dp_priv->has_audio = false; 1617 1617 - dp_priv->dpms_mode = DRM_MODE_DPMS_ON; 1618 1618 - intel_encoder->dev_priv = dp_priv; 1594 1594 + intel_dp->output_reg = output_reg; 1595 1595 + intel_dp->has_audio = false; 1596 1596 + intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1619 1597 1620 1598 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, 1621 1599 DRM_MODE_ENCODER_TMDS); ··· 1648 1630 break; 1649 1631 } 1650 1632 1651 1651 - intel_dp_i2c_init(intel_encoder, intel_connector, name); 1633 1633 + intel_dp_i2c_init(intel_dp, intel_connector, name); 1652 1634 1653 1653 - intel_encoder->ddc_bus = &dp_priv->adapter; 1635 1635 + intel_encoder->ddc_bus = &intel_dp->adapter; 1654 1636 intel_encoder->hot_plug = intel_dp_hot_plug; 1655 1637 1656 1656 - if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1638 1638 + if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { 1657 1639 /* initialize panel mode from VBT if available for eDP */ 1658 1640 if (dev_priv->lfp_lvds_vbt_mode) { 1659 1641 dev_priv->panel_fixed_mode =

+25 -4

drivers/gpu/drm/i915/intel_drv.h

reviewed

··· 32 32 #include "drm_crtc.h" 33 33 34 34 #include "drm_crtc_helper.h" 35 35 + 36 36 + #define wait_for(COND, MS, W) ({ \ 37 37 + unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 38 38 + int ret__ = 0; \ 39 39 + while (! (COND)) { \ 40 40 + if (time_after(jiffies, timeout__)) { \ 41 41 + ret__ = -ETIMEDOUT; \ 42 42 + break; \ 43 43 + } \ 44 44 + if (W) msleep(W); \ 45 45 + } \ 46 46 + ret__; \ 47 47 + }) 48 48 + 35 49 /* 36 50 * Display related stuff 37 51 */ ··· 116 102 struct i2c_adapter *ddc_bus; 117 103 bool load_detect_temp; 118 104 bool needs_tv_clock; 119 119 - void *dev_priv; 120 105 void (*hot_plug)(struct intel_encoder *); 121 106 int crtc_mask; 122 107 int clone_mask; ··· 123 110 124 111 struct intel_connector { 125 112 struct drm_connector base; 126 126 - void *dev_priv; 127 113 }; 128 114 129 115 struct intel_crtc; ··· 168 156 uint32_t cursor_addr; 169 157 int16_t cursor_x, cursor_y; 170 158 int16_t cursor_width, cursor_height; 171 171 - bool cursor_visble; 159 159 + bool cursor_visible, cursor_on; 172 160 }; 173 161 174 162 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) ··· 200 188 extern void intel_edp_link_config (struct intel_encoder *, int *, int *); 201 189 202 190 191 191 + extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 192 192 + struct drm_display_mode *adjusted_mode); 193 193 + extern void intel_pch_panel_fitting(struct drm_device *dev, 194 194 + int fitting_mode, 195 195 + struct drm_display_mode *mode, 196 196 + struct drm_display_mode *adjusted_mode); 197 197 + 203 198 extern int intel_panel_fitter_pipe (struct drm_device *dev); 204 199 extern void intel_crtc_load_lut(struct drm_crtc *crtc); 205 200 extern void intel_encoder_prepare (struct drm_encoder *encoder); 206 201 extern void intel_encoder_commit (struct drm_encoder *encoder); 202 202 + extern void intel_encoder_destroy(struct drm_encoder *encoder); 207 203 208 204 extern struct drm_encoder *intel_attached_encoder(struct drm_connector *connector); 209 205 ··· 219 199 struct drm_crtc *crtc); 220 200 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 221 201 struct drm_file *file_priv); 222 222 - extern void intel_wait_for_vblank(struct drm_device *dev); 202 202 + extern void intel_wait_for_vblank_off(struct drm_device *dev, int pipe); 203 203 + extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 223 204 extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe); 224 205 extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 225 206 struct drm_connector *connector,

+64 -70

drivers/gpu/drm/i915/intel_dvo.c

reviewed

··· 38 38 #define CH7xxx_ADDR 0x76 39 39 #define TFP410_ADDR 0x38 40 40 41 41 - static struct intel_dvo_device intel_dvo_devices[] = { 41 41 + static const struct intel_dvo_device intel_dvo_devices[] = { 42 42 { 43 43 .type = INTEL_DVO_CHIP_TMDS, 44 44 .name = "sil164", ··· 77 77 } 78 78 }; 79 79 80 80 + struct intel_dvo { 81 81 + struct intel_encoder base; 82 82 + 83 83 + struct intel_dvo_device dev; 84 84 + 85 85 + struct drm_display_mode *panel_fixed_mode; 86 86 + bool panel_wants_dither; 87 87 + }; 88 88 + 89 89 + static struct intel_dvo *enc_to_intel_dvo(struct drm_encoder *encoder) 90 90 + { 91 91 + return container_of(enc_to_intel_encoder(encoder), struct intel_dvo, base); 92 92 + } 93 93 + 80 94 static void intel_dvo_dpms(struct drm_encoder *encoder, int mode) 81 95 { 82 96 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 83 83 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 84 84 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 85 85 - u32 dvo_reg = dvo->dvo_reg; 97 97 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 98 98 + u32 dvo_reg = intel_dvo->dev.dvo_reg; 86 99 u32 temp = I915_READ(dvo_reg); 87 100 88 101 if (mode == DRM_MODE_DPMS_ON) { 89 102 I915_WRITE(dvo_reg, temp | DVO_ENABLE); 90 103 I915_READ(dvo_reg); 91 91 - dvo->dev_ops->dpms(dvo, mode); 104 104 + intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode); 92 105 } else { 93 93 - dvo->dev_ops->dpms(dvo, mode); 106 106 + intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode); 94 107 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); 95 108 I915_READ(dvo_reg); 96 109 } ··· 113 100 struct drm_display_mode *mode) 114 101 { 115 102 struct drm_encoder *encoder = intel_attached_encoder(connector); 116 116 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 117 117 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 103 103 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 118 104 119 105 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 120 106 return MODE_NO_DBLESCAN; 121 107 122 108 /* XXX: Validate clock range */ 123 109 124 124 - if (dvo->panel_fixed_mode) { 125 125 - if (mode->hdisplay > dvo->panel_fixed_mode->hdisplay) 110 110 + if (intel_dvo->panel_fixed_mode) { 111 111 + if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) 126 112 return MODE_PANEL; 127 127 - if (mode->vdisplay > dvo->panel_fixed_mode->vdisplay) 113 113 + if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) 128 114 return MODE_PANEL; 129 115 } 130 116 131 131 - return dvo->dev_ops->mode_valid(dvo, mode); 117 117 + return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 132 118 } 133 119 134 120 static bool intel_dvo_mode_fixup(struct drm_encoder *encoder, 135 121 struct drm_display_mode *mode, 136 122 struct drm_display_mode *adjusted_mode) 137 123 { 138 138 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 139 139 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 124 124 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 140 125 141 126 /* If we have timings from the BIOS for the panel, put them in 142 127 * to the adjusted mode. The CRTC will be set up for this mode, 143 128 * with the panel scaling set up to source from the H/VDisplay 144 129 * of the original mode. 145 130 */ 146 146 - if (dvo->panel_fixed_mode != NULL) { 147 147 - #define C(x) adjusted_mode->x = dvo->panel_fixed_mode->x 131 131 + if (intel_dvo->panel_fixed_mode != NULL) { 132 132 + #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x 148 133 C(hdisplay); 149 134 C(hsync_start); 150 135 C(hsync_end); ··· 156 145 #undef C 157 146 } 158 147 159 159 - if (dvo->dev_ops->mode_fixup) 160 160 - return dvo->dev_ops->mode_fixup(dvo, mode, adjusted_mode); 148 148 + if (intel_dvo->dev.dev_ops->mode_fixup) 149 149 + return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, mode, adjusted_mode); 161 150 162 151 return true; 163 152 } ··· 169 158 struct drm_device *dev = encoder->dev; 170 159 struct drm_i915_private *dev_priv = dev->dev_private; 171 160 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 172 172 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 173 173 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 161 161 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 174 162 int pipe = intel_crtc->pipe; 175 163 u32 dvo_val; 176 176 - u32 dvo_reg = dvo->dvo_reg, dvo_srcdim_reg; 164 164 + u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; 177 165 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 178 166 179 167 switch (dvo_reg) { ··· 188 178 break; 189 179 } 190 180 191 191 - dvo->dev_ops->mode_set(dvo, mode, adjusted_mode); 181 181 + intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, mode, adjusted_mode); 192 182 193 183 /* Save the data order, since I don't know what it should be set to. */ 194 184 dvo_val = I915_READ(dvo_reg) & ··· 224 214 static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector) 225 215 { 226 216 struct drm_encoder *encoder = intel_attached_encoder(connector); 227 227 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 228 228 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 217 217 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 229 218 230 230 - return dvo->dev_ops->detect(dvo); 219 219 + return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 231 220 } 232 221 233 222 static int intel_dvo_get_modes(struct drm_connector *connector) 234 223 { 235 224 struct drm_encoder *encoder = intel_attached_encoder(connector); 236 236 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 237 237 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 225 225 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 238 226 239 227 /* We should probably have an i2c driver get_modes function for those 240 228 * devices which will have a fixed set of modes determined by the chip 241 229 * (TV-out, for example), but for now with just TMDS and LVDS, 242 230 * that's not the case. 243 231 */ 244 244 - intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 232 232 + intel_ddc_get_modes(connector, intel_dvo->base.ddc_bus); 245 233 if (!list_empty(&connector->probed_modes)) 246 234 return 1; 247 235 248 248 - 249 249 - if (dvo->panel_fixed_mode != NULL) { 236 236 + if (intel_dvo->panel_fixed_mode != NULL) { 250 237 struct drm_display_mode *mode; 251 251 - mode = drm_mode_duplicate(connector->dev, dvo->panel_fixed_mode); 238 238 + mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); 252 239 if (mode) { 253 240 drm_mode_probed_add(connector, mode); 254 241 return 1; 255 242 } 256 243 } 244 244 + 257 245 return 0; 258 246 } 259 247 260 260 - static void intel_dvo_destroy (struct drm_connector *connector) 248 248 + static void intel_dvo_destroy(struct drm_connector *connector) 261 249 { 262 250 drm_sysfs_connector_remove(connector); 263 251 drm_connector_cleanup(connector); ··· 285 277 286 278 static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 287 279 { 288 288 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 289 289 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 280 280 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 290 281 291 291 - if (dvo) { 292 292 - if (dvo->dev_ops->destroy) 293 293 - dvo->dev_ops->destroy(dvo); 294 294 - if (dvo->panel_fixed_mode) 295 295 - kfree(dvo->panel_fixed_mode); 296 296 - } 297 297 - if (intel_encoder->i2c_bus) 298 298 - intel_i2c_destroy(intel_encoder->i2c_bus); 299 299 - if (intel_encoder->ddc_bus) 300 300 - intel_i2c_destroy(intel_encoder->ddc_bus); 301 301 - drm_encoder_cleanup(encoder); 302 302 - kfree(intel_encoder); 282 282 + if (intel_dvo->dev.dev_ops->destroy) 283 283 + intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 284 284 + 285 285 + kfree(intel_dvo->panel_fixed_mode); 286 286 + 287 287 + intel_encoder_destroy(encoder); 303 288 } 304 289 305 290 static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 306 291 .destroy = intel_dvo_enc_destroy, 307 292 }; 308 308 - 309 293 310 294 /** 311 295 * Attempts to get a fixed panel timing for LVDS (currently only the i830). ··· 306 306 * chip being on DVOB/C and having multiple pipes. 307 307 */ 308 308 static struct drm_display_mode * 309 309 - intel_dvo_get_current_mode (struct drm_connector *connector) 309 309 + intel_dvo_get_current_mode(struct drm_connector *connector) 310 310 { 311 311 struct drm_device *dev = connector->dev; 312 312 struct drm_i915_private *dev_priv = dev->dev_private; 313 313 struct drm_encoder *encoder = intel_attached_encoder(connector); 314 314 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 315 315 - struct intel_dvo_device *dvo = intel_encoder->dev_priv; 316 316 - uint32_t dvo_reg = dvo->dvo_reg; 317 317 - uint32_t dvo_val = I915_READ(dvo_reg); 314 314 + struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); 315 315 + uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); 318 316 struct drm_display_mode *mode = NULL; 319 317 320 318 /* If the DVO port is active, that'll be the LVDS, so we can pull out ··· 325 327 crtc = intel_get_crtc_from_pipe(dev, pipe); 326 328 if (crtc) { 327 329 mode = intel_crtc_mode_get(dev, crtc); 328 328 - 329 330 if (mode) { 330 331 mode->type |= DRM_MODE_TYPE_PREFERRED; 331 332 if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) ··· 334 337 } 335 338 } 336 339 } 340 340 + 337 341 return mode; 338 342 } 339 343 340 344 void intel_dvo_init(struct drm_device *dev) 341 345 { 342 346 struct intel_encoder *intel_encoder; 347 347 + struct intel_dvo *intel_dvo; 343 348 struct intel_connector *intel_connector; 344 344 - struct intel_dvo_device *dvo; 345 349 struct i2c_adapter *i2cbus = NULL; 346 350 int ret = 0; 347 351 int i; 348 352 int encoder_type = DRM_MODE_ENCODER_NONE; 349 349 - intel_encoder = kzalloc (sizeof(struct intel_encoder), GFP_KERNEL); 350 350 - if (!intel_encoder) 353 353 + 354 354 + intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL); 355 355 + if (!intel_dvo) 351 356 return; 352 357 353 358 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 354 359 if (!intel_connector) { 355 355 - kfree(intel_encoder); 360 360 + kfree(intel_dvo); 356 361 return; 357 362 } 363 363 + 364 364 + intel_encoder = &intel_dvo->base; 358 365 359 366 /* Set up the DDC bus */ 360 367 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "DVODDC_D"); ··· 368 367 /* Now, try to find a controller */ 369 368 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 370 369 struct drm_connector *connector = &intel_connector->base; 370 370 + const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; 371 371 int gpio; 372 372 - 373 373 - dvo = &intel_dvo_devices[i]; 374 372 375 373 /* Allow the I2C driver info to specify the GPIO to be used in 376 374 * special cases, but otherwise default to what's defined ··· 393 393 continue; 394 394 } 395 395 396 396 - if (dvo->dev_ops!= NULL) 397 397 - ret = dvo->dev_ops->init(dvo, i2cbus); 398 398 - else 399 399 - ret = false; 400 400 - 396 396 + intel_dvo->dev = *dvo; 397 397 + ret = dvo->dev_ops->init(&intel_dvo->dev, i2cbus); 401 398 if (!ret) 402 399 continue; 403 400 ··· 426 429 connector->interlace_allowed = false; 427 430 connector->doublescan_allowed = false; 428 431 429 429 - intel_encoder->dev_priv = dvo; 430 430 - intel_encoder->i2c_bus = i2cbus; 431 431 - 432 432 drm_encoder_init(dev, &intel_encoder->enc, 433 433 &intel_dvo_enc_funcs, encoder_type); 434 434 drm_encoder_helper_add(&intel_encoder->enc, ··· 441 447 * headers, likely), so for now, just get the current 442 448 * mode being output through DVO. 443 449 */ 444 444 - dvo->panel_fixed_mode = 450 450 + intel_dvo->panel_fixed_mode = 445 451 intel_dvo_get_current_mode(connector); 446 446 - dvo->panel_wants_dither = true; 452 452 + intel_dvo->panel_wants_dither = true; 447 453 } 448 454 449 455 drm_sysfs_connector_add(connector); ··· 455 461 if (i2cbus != NULL) 456 462 intel_i2c_destroy(i2cbus); 457 463 free_intel: 458 458 - kfree(intel_encoder); 464 464 + kfree(intel_dvo); 459 465 kfree(intel_connector); 460 466 }

+33 -44

drivers/gpu/drm/i915/intel_hdmi.c

reviewed

··· 37 37 #include "i915_drm.h" 38 38 #include "i915_drv.h" 39 39 40 40 - struct intel_hdmi_priv { 40 40 + struct intel_hdmi { 41 41 + struct intel_encoder base; 41 42 u32 sdvox_reg; 42 43 bool has_hdmi_sink; 43 44 }; 45 45 + 46 46 + static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 47 47 + { 48 48 + return container_of(enc_to_intel_encoder(encoder), struct intel_hdmi, base); 49 49 + } 44 50 45 51 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 46 52 struct drm_display_mode *mode, ··· 56 50 struct drm_i915_private *dev_priv = dev->dev_private; 57 51 struct drm_crtc *crtc = encoder->crtc; 58 52 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 59 59 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 60 60 - struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; 53 53 + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 61 54 u32 sdvox; 62 55 63 56 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; ··· 65 60 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 66 61 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 67 62 68 68 - if (hdmi_priv->has_hdmi_sink) { 63 63 + if (intel_hdmi->has_hdmi_sink) { 69 64 sdvox |= SDVO_AUDIO_ENABLE; 70 65 if (HAS_PCH_CPT(dev)) 71 66 sdvox |= HDMI_MODE_SELECT; ··· 78 73 sdvox |= SDVO_PIPE_B_SELECT; 79 74 } 80 75 81 81 - I915_WRITE(hdmi_priv->sdvox_reg, sdvox); 82 82 - POSTING_READ(hdmi_priv->sdvox_reg); 76 76 + I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 77 77 + POSTING_READ(intel_hdmi->sdvox_reg); 83 78 } 84 79 85 80 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 86 81 { 87 82 struct drm_device *dev = encoder->dev; 88 83 struct drm_i915_private *dev_priv = dev->dev_private; 89 89 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 90 90 - struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; 84 84 + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 91 85 u32 temp; 92 86 93 93 - temp = I915_READ(hdmi_priv->sdvox_reg); 87 87 + temp = I915_READ(intel_hdmi->sdvox_reg); 94 88 95 89 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 96 90 * we do this anyway which shows more stable in testing. 97 91 */ 98 92 if (HAS_PCH_SPLIT(dev)) { 99 99 - I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); 100 100 - POSTING_READ(hdmi_priv->sdvox_reg); 93 93 + I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 94 94 + POSTING_READ(intel_hdmi->sdvox_reg); 101 95 } 102 96 103 97 if (mode != DRM_MODE_DPMS_ON) { ··· 105 101 temp |= SDVO_ENABLE; 106 102 } 107 103 108 108 - I915_WRITE(hdmi_priv->sdvox_reg, temp); 109 109 - POSTING_READ(hdmi_priv->sdvox_reg); 104 104 + I915_WRITE(intel_hdmi->sdvox_reg, temp); 105 105 + POSTING_READ(intel_hdmi->sdvox_reg); 110 106 111 107 /* HW workaround, need to write this twice for issue that may result 112 108 * in first write getting masked. 113 109 */ 114 110 if (HAS_PCH_SPLIT(dev)) { 115 115 - I915_WRITE(hdmi_priv->sdvox_reg, temp); 116 116 - POSTING_READ(hdmi_priv->sdvox_reg); 111 111 + I915_WRITE(intel_hdmi->sdvox_reg, temp); 112 112 + POSTING_READ(intel_hdmi->sdvox_reg); 117 113 } 118 114 } 119 115 ··· 142 138 intel_hdmi_detect(struct drm_connector *connector) 143 139 { 144 140 struct drm_encoder *encoder = intel_attached_encoder(connector); 145 145 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 146 146 - struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; 141 141 + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 147 142 struct edid *edid = NULL; 148 143 enum drm_connector_status status = connector_status_disconnected; 149 144 150 150 - hdmi_priv->has_hdmi_sink = false; 151 151 - edid = drm_get_edid(connector, 152 152 - intel_encoder->ddc_bus); 145 145 + intel_hdmi->has_hdmi_sink = false; 146 146 + edid = drm_get_edid(connector, intel_hdmi->base.ddc_bus); 153 147 154 148 if (edid) { 155 149 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 156 150 status = connector_status_connected; 157 157 - hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 151 151 + intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 158 152 } 159 153 connector->display_info.raw_edid = NULL; 160 154 kfree(edid); ··· 164 162 static int intel_hdmi_get_modes(struct drm_connector *connector) 165 163 { 166 164 struct drm_encoder *encoder = intel_attached_encoder(connector); 167 167 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 165 165 + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 168 166 169 167 /* We should parse the EDID data and find out if it's an HDMI sink so 170 168 * we can send audio to it. 171 169 */ 172 170 173 173 - return intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 171 171 + return intel_ddc_get_modes(connector, intel_hdmi->base.ddc_bus); 174 172 } 175 173 176 174 static void intel_hdmi_destroy(struct drm_connector *connector) ··· 201 199 .best_encoder = intel_attached_encoder, 202 200 }; 203 201 204 204 - static void intel_hdmi_enc_destroy(struct drm_encoder *encoder) 205 205 - { 206 206 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 207 207 - 208 208 - if (intel_encoder->i2c_bus) 209 209 - intel_i2c_destroy(intel_encoder->i2c_bus); 210 210 - drm_encoder_cleanup(encoder); 211 211 - kfree(intel_encoder); 212 212 - } 213 213 - 214 202 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 215 215 - .destroy = intel_hdmi_enc_destroy, 203 203 + .destroy = intel_encoder_destroy, 216 204 }; 217 205 218 206 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) ··· 211 219 struct drm_connector *connector; 212 220 struct intel_encoder *intel_encoder; 213 221 struct intel_connector *intel_connector; 214 214 - struct intel_hdmi_priv *hdmi_priv; 222 222 + struct intel_hdmi *intel_hdmi; 215 223 216 216 - intel_encoder = kcalloc(sizeof(struct intel_encoder) + 217 217 - sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); 218 218 - if (!intel_encoder) 224 224 + intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); 225 225 + if (!intel_hdmi) 219 226 return; 220 227 221 228 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 222 229 if (!intel_connector) { 223 223 - kfree(intel_encoder); 230 230 + kfree(intel_hdmi); 224 231 return; 225 232 } 226 233 227 227 - hdmi_priv = (struct intel_hdmi_priv *)(intel_encoder + 1); 228 228 - 234 234 + intel_encoder = &intel_hdmi->base; 229 235 connector = &intel_connector->base; 230 236 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 231 237 DRM_MODE_CONNECTOR_HDMIA); ··· 264 274 if (!intel_encoder->ddc_bus) 265 275 goto err_connector; 266 276 267 267 - hdmi_priv->sdvox_reg = sdvox_reg; 268 268 - intel_encoder->dev_priv = hdmi_priv; 277 277 + intel_hdmi->sdvox_reg = sdvox_reg; 269 278 270 279 drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs, 271 280 DRM_MODE_ENCODER_TMDS); ··· 287 298 288 299 err_connector: 289 300 drm_connector_cleanup(connector); 290 290 - kfree(intel_encoder); 301 301 + kfree(intel_hdmi); 291 302 kfree(intel_connector); 292 303 293 304 return;

+41 -65

drivers/gpu/drm/i915/intel_lvds.c

reviewed

··· 41 41 #include <linux/acpi.h> 42 42 43 43 /* Private structure for the integrated LVDS support */ 44 44 - struct intel_lvds_priv { 44 44 + struct intel_lvds { 45 45 + struct intel_encoder base; 45 46 int fitting_mode; 46 47 u32 pfit_control; 47 48 u32 pfit_pgm_ratios; 48 49 }; 50 50 + 51 51 + static struct intel_lvds *enc_to_intel_lvds(struct drm_encoder *encoder) 52 52 + { 53 53 + return container_of(enc_to_intel_encoder(encoder), struct intel_lvds, base); 54 54 + } 49 55 50 56 /** 51 57 * Sets the backlight level. ··· 96 90 static void intel_lvds_set_power(struct drm_device *dev, bool on) 97 91 { 98 92 struct drm_i915_private *dev_priv = dev->dev_private; 99 99 - u32 pp_status, ctl_reg, status_reg, lvds_reg; 93 93 + u32 ctl_reg, status_reg, lvds_reg; 100 94 101 95 if (HAS_PCH_SPLIT(dev)) { 102 96 ctl_reg = PCH_PP_CONTROL; ··· 114 108 115 109 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | 116 110 POWER_TARGET_ON); 117 117 - do { 118 118 - pp_status = I915_READ(status_reg); 119 119 - } while ((pp_status & PP_ON) == 0); 111 111 + if (wait_for(I915_READ(status_reg) & PP_ON, 1000, 0)) 112 112 + DRM_ERROR("timed out waiting to enable LVDS pipe"); 120 113 121 114 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); 122 115 } else { ··· 123 118 124 119 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & 125 120 ~POWER_TARGET_ON); 126 126 - do { 127 127 - pp_status = I915_READ(status_reg); 128 128 - } while (pp_status & PP_ON); 121 121 + if (wait_for((I915_READ(status_reg) & PP_ON) == 0, 1000, 0)) 122 122 + DRM_ERROR("timed out waiting for LVDS pipe to turn off"); 129 123 130 124 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); 131 125 POSTING_READ(lvds_reg); ··· 223 219 struct drm_device *dev = encoder->dev; 224 220 struct drm_i915_private *dev_priv = dev->dev_private; 225 221 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 222 222 + struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); 226 223 struct drm_encoder *tmp_encoder; 227 227 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 228 228 - struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; 229 224 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 230 225 231 226 /* Should never happen!! */ ··· 244 241 /* If we don't have a panel mode, there is nothing we can do */ 245 242 if (dev_priv->panel_fixed_mode == NULL) 246 243 return true; 244 244 + 247 245 /* 248 246 * We have timings from the BIOS for the panel, put them in 249 247 * to the adjusted mode. The CRTC will be set up for this mode, 250 248 * with the panel scaling set up to source from the H/VDisplay 251 249 * of the original mode. 252 250 */ 253 253 - adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; 254 254 - adjusted_mode->hsync_start = 255 255 - dev_priv->panel_fixed_mode->hsync_start; 256 256 - adjusted_mode->hsync_end = 257 257 - dev_priv->panel_fixed_mode->hsync_end; 258 258 - adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; 259 259 - adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; 260 260 - adjusted_mode->vsync_start = 261 261 - dev_priv->panel_fixed_mode->vsync_start; 262 262 - adjusted_mode->vsync_end = 263 263 - dev_priv->panel_fixed_mode->vsync_end; 264 264 - adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; 265 265 - adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; 266 266 - drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 251 251 + intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 252 252 + 253 253 + if (HAS_PCH_SPLIT(dev)) { 254 254 + intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, 255 255 + mode, adjusted_mode); 256 256 + return true; 257 257 + } 267 258 268 259 /* Make sure pre-965s set dither correctly */ 269 260 if (!IS_I965G(dev)) { ··· 268 271 /* Native modes don't need fitting */ 269 272 if (adjusted_mode->hdisplay == mode->hdisplay && 270 273 adjusted_mode->vdisplay == mode->vdisplay) 271 271 - goto out; 272 272 - 273 273 - /* full screen scale for now */ 274 274 - if (HAS_PCH_SPLIT(dev)) 275 274 goto out; 276 275 277 276 /* 965+ wants fuzzy fitting */ ··· 281 288 * to register description and PRM. 282 289 * Change the value here to see the borders for debugging 283 290 */ 284 284 - if (!HAS_PCH_SPLIT(dev)) { 285 285 - I915_WRITE(BCLRPAT_A, 0); 286 286 - I915_WRITE(BCLRPAT_B, 0); 287 287 - } 291 291 + I915_WRITE(BCLRPAT_A, 0); 292 292 + I915_WRITE(BCLRPAT_B, 0); 288 293 289 289 - switch (lvds_priv->fitting_mode) { 294 294 + switch (intel_lvds->fitting_mode) { 290 295 case DRM_MODE_SCALE_CENTER: 291 296 /* 292 297 * For centered modes, we have to calculate border widths & ··· 369 378 } 370 379 371 380 out: 372 372 - lvds_priv->pfit_control = pfit_control; 373 373 - lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; 381 381 + intel_lvds->pfit_control = pfit_control; 382 382 + intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; 374 383 dev_priv->lvds_border_bits = border; 375 384 376 385 /* ··· 418 427 { 419 428 struct drm_device *dev = encoder->dev; 420 429 struct drm_i915_private *dev_priv = dev->dev_private; 421 421 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 422 422 - struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; 430 430 + struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); 423 431 424 432 /* 425 433 * The LVDS pin pair will already have been turned on in the ··· 434 444 * screen. Should be enabled before the pipe is enabled, according to 435 445 * register description and PRM. 436 446 */ 437 437 - I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios); 438 438 - I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); 447 447 + I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); 448 448 + I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); 439 449 } 440 450 441 451 /** ··· 590 600 connector->encoder) { 591 601 struct drm_crtc *crtc = connector->encoder->crtc; 592 602 struct drm_encoder *encoder = connector->encoder; 593 593 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 594 594 - struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; 603 603 + struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); 595 604 596 605 if (value == DRM_MODE_SCALE_NONE) { 597 606 DRM_DEBUG_KMS("no scaling not supported\n"); 598 607 return 0; 599 608 } 600 600 - if (lvds_priv->fitting_mode == value) { 609 609 + if (intel_lvds->fitting_mode == value) { 601 610 /* the LVDS scaling property is not changed */ 602 611 return 0; 603 612 } 604 604 - lvds_priv->fitting_mode = value; 613 613 + intel_lvds->fitting_mode = value; 605 614 if (crtc && crtc->enabled) { 606 615 /* 607 616 * If the CRTC is enabled, the display will be changed ··· 636 647 .destroy = intel_lvds_destroy, 637 648 }; 638 649 639 639 - 640 640 - static void intel_lvds_enc_destroy(struct drm_encoder *encoder) 641 641 - { 642 642 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 643 643 - 644 644 - if (intel_encoder->ddc_bus) 645 645 - intel_i2c_destroy(intel_encoder->ddc_bus); 646 646 - drm_encoder_cleanup(encoder); 647 647 - kfree(intel_encoder); 648 648 - } 649 649 - 650 650 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 651 651 - .destroy = intel_lvds_enc_destroy, 651 651 + .destroy = intel_encoder_destroy, 652 652 }; 653 653 654 654 static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) ··· 821 843 void intel_lvds_init(struct drm_device *dev) 822 844 { 823 845 struct drm_i915_private *dev_priv = dev->dev_private; 846 846 + struct intel_lvds *intel_lvds; 824 847 struct intel_encoder *intel_encoder; 825 848 struct intel_connector *intel_connector; 826 849 struct drm_connector *connector; 827 850 struct drm_encoder *encoder; 828 851 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 829 852 struct drm_crtc *crtc; 830 830 - struct intel_lvds_priv *lvds_priv; 831 853 u32 lvds; 832 854 int pipe, gpio = GPIOC; 833 855 ··· 850 872 gpio = PCH_GPIOC; 851 873 } 852 874 853 853 - intel_encoder = kzalloc(sizeof(struct intel_encoder) + 854 854 - sizeof(struct intel_lvds_priv), GFP_KERNEL); 855 855 - if (!intel_encoder) { 875 875 + intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); 876 876 + if (!intel_lvds) { 856 877 return; 857 878 } 858 879 859 880 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 860 881 if (!intel_connector) { 861 861 - kfree(intel_encoder); 882 882 + kfree(intel_lvds); 862 883 return; 863 884 } 864 885 865 865 - connector = &intel_connector->base; 886 886 + intel_encoder = &intel_lvds->base; 866 887 encoder = &intel_encoder->enc; 888 888 + connector = &intel_connector->base; 867 889 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 868 890 DRM_MODE_CONNECTOR_LVDS); 869 891 ··· 883 905 connector->interlace_allowed = false; 884 906 connector->doublescan_allowed = false; 885 907 886 886 - lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1); 887 887 - intel_encoder->dev_priv = lvds_priv; 888 908 /* create the scaling mode property */ 889 909 drm_mode_create_scaling_mode_property(dev); 890 910 /* ··· 892 916 drm_connector_attach_property(&intel_connector->base, 893 917 dev->mode_config.scaling_mode_property, 894 918 DRM_MODE_SCALE_ASPECT); 895 895 - lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT; 919 919 + intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; 896 920 /* 897 921 * LVDS discovery: 898 922 * 1) check for EDID on DDC ··· 1000 1024 intel_i2c_destroy(intel_encoder->ddc_bus); 1001 1025 drm_connector_cleanup(connector); 1002 1026 drm_encoder_cleanup(encoder); 1003 1003 - kfree(intel_encoder); 1027 1027 + kfree(intel_lvds); 1004 1028 kfree(intel_connector); 1005 1029 }

+98 -1

drivers/gpu/drm/i915/intel_overlay.c

reviewed

··· 1367 1367 overlay->flip_addr = overlay->reg_bo->gtt_offset; 1368 1368 } else { 1369 1369 ret = i915_gem_attach_phys_object(dev, reg_bo, 1370 1370 - I915_GEM_PHYS_OVERLAY_REGS); 1370 1370 + I915_GEM_PHYS_OVERLAY_REGS, 1371 1371 + 0); 1371 1372 if (ret) { 1372 1373 DRM_ERROR("failed to attach phys overlay regs\n"); 1373 1374 goto out_free_bo; ··· 1416 1415 1417 1416 kfree(dev_priv->overlay); 1418 1417 } 1418 1418 + } 1419 1419 + 1420 1420 + struct intel_overlay_error_state { 1421 1421 + struct overlay_registers regs; 1422 1422 + unsigned long base; 1423 1423 + u32 dovsta; 1424 1424 + u32 isr; 1425 1425 + }; 1426 1426 + 1427 1427 + struct intel_overlay_error_state * 1428 1428 + intel_overlay_capture_error_state(struct drm_device *dev) 1429 1429 + { 1430 1430 + drm_i915_private_t *dev_priv = dev->dev_private; 1431 1431 + struct intel_overlay *overlay = dev_priv->overlay; 1432 1432 + struct intel_overlay_error_state *error; 1433 1433 + struct overlay_registers __iomem *regs; 1434 1434 + 1435 1435 + if (!overlay || !overlay->active) 1436 1436 + return NULL; 1437 1437 + 1438 1438 + error = kmalloc(sizeof(*error), GFP_ATOMIC); 1439 1439 + if (error == NULL) 1440 1440 + return NULL; 1441 1441 + 1442 1442 + error->dovsta = I915_READ(DOVSTA); 1443 1443 + error->isr = I915_READ(ISR); 1444 1444 + if (OVERLAY_NONPHYSICAL(overlay->dev)) 1445 1445 + error->base = (long) overlay->reg_bo->gtt_offset; 1446 1446 + else 1447 1447 + error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr; 1448 1448 + 1449 1449 + regs = intel_overlay_map_regs_atomic(overlay); 1450 1450 + if (!regs) 1451 1451 + goto err; 1452 1452 + 1453 1453 + memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); 1454 1454 + intel_overlay_unmap_regs_atomic(overlay); 1455 1455 + 1456 1456 + return error; 1457 1457 + 1458 1458 + err: 1459 1459 + kfree(error); 1460 1460 + return NULL; 1461 1461 + } 1462 1462 + 1463 1463 + void 1464 1464 + intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error) 1465 1465 + { 1466 1466 + seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1467 1467 + error->dovsta, error->isr); 1468 1468 + seq_printf(m, " Register file at 0x%08lx:\n", 1469 1469 + error->base); 1470 1470 + 1471 1471 + #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1472 1472 + P(OBUF_0Y); 1473 1473 + P(OBUF_1Y); 1474 1474 + P(OBUF_0U); 1475 1475 + P(OBUF_0V); 1476 1476 + P(OBUF_1U); 1477 1477 + P(OBUF_1V); 1478 1478 + P(OSTRIDE); 1479 1479 + P(YRGB_VPH); 1480 1480 + P(UV_VPH); 1481 1481 + P(HORZ_PH); 1482 1482 + P(INIT_PHS); 1483 1483 + P(DWINPOS); 1484 1484 + P(DWINSZ); 1485 1485 + P(SWIDTH); 1486 1486 + P(SWIDTHSW); 1487 1487 + P(SHEIGHT); 1488 1488 + P(YRGBSCALE); 1489 1489 + P(UVSCALE); 1490 1490 + P(OCLRC0); 1491 1491 + P(OCLRC1); 1492 1492 + P(DCLRKV); 1493 1493 + P(DCLRKM); 1494 1494 + P(SCLRKVH); 1495 1495 + P(SCLRKVL); 1496 1496 + P(SCLRKEN); 1497 1497 + P(OCONFIG); 1498 1498 + P(OCMD); 1499 1499 + P(OSTART_0Y); 1500 1500 + P(OSTART_1Y); 1501 1501 + P(OSTART_0U); 1502 1502 + P(OSTART_0V); 1503 1503 + P(OSTART_1U); 1504 1504 + P(OSTART_1V); 1505 1505 + P(OTILEOFF_0Y); 1506 1506 + P(OTILEOFF_1Y); 1507 1507 + P(OTILEOFF_0U); 1508 1508 + P(OTILEOFF_0V); 1509 1509 + P(OTILEOFF_1U); 1510 1510 + P(OTILEOFF_1V); 1511 1511 + P(FASTHSCALE); 1512 1512 + P(UVSCALEV); 1513 1513 + #undef P 1419 1514 }

+111

drivers/gpu/drm/i915/intel_panel.c

reviewed

··· 1 1 + /* 2 2 + * Copyright © 2006-2010 Intel Corporation 3 3 + * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 4 + * 5 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 6 + * copy of this software and associated documentation files (the "Software"), 7 7 + * to deal in the Software without restriction, including without limitation 8 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 10 + * Software is furnished to do so, subject to the following conditions: 11 11 + * 12 12 + * The above copyright notice and this permission notice (including the next 13 13 + * paragraph) shall be included in all copies or substantial portions of the 14 14 + * Software. 15 15 + * 16 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 21 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 22 + * DEALINGS IN THE SOFTWARE. 23 23 + * 24 24 + * Authors: 25 25 + * Eric Anholt <eric@anholt.net> 26 26 + * Dave Airlie <airlied@linux.ie> 27 27 + * Jesse Barnes <jesse.barnes@intel.com> 28 28 + * Chris Wilson <chris@chris-wilson.co.uk> 29 29 + */ 30 30 + 31 31 + #include "intel_drv.h" 32 32 + 33 33 + void 34 34 + intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 35 35 + struct drm_display_mode *adjusted_mode) 36 36 + { 37 37 + adjusted_mode->hdisplay = fixed_mode->hdisplay; 38 38 + adjusted_mode->hsync_start = fixed_mode->hsync_start; 39 39 + adjusted_mode->hsync_end = fixed_mode->hsync_end; 40 40 + adjusted_mode->htotal = fixed_mode->htotal; 41 41 + 42 42 + adjusted_mode->vdisplay = fixed_mode->vdisplay; 43 43 + adjusted_mode->vsync_start = fixed_mode->vsync_start; 44 44 + adjusted_mode->vsync_end = fixed_mode->vsync_end; 45 45 + adjusted_mode->vtotal = fixed_mode->vtotal; 46 46 + 47 47 + adjusted_mode->clock = fixed_mode->clock; 48 48 + 49 49 + drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 50 50 + } 51 51 + 52 52 + /* adjusted_mode has been preset to be the panel's fixed mode */ 53 53 + void 54 54 + intel_pch_panel_fitting(struct drm_device *dev, 55 55 + int fitting_mode, 56 56 + struct drm_display_mode *mode, 57 57 + struct drm_display_mode *adjusted_mode) 58 58 + { 59 59 + struct drm_i915_private *dev_priv = dev->dev_private; 60 60 + int x, y, width, height; 61 61 + 62 62 + x = y = width = height = 0; 63 63 + 64 64 + /* Native modes don't need fitting */ 65 65 + if (adjusted_mode->hdisplay == mode->hdisplay && 66 66 + adjusted_mode->vdisplay == mode->vdisplay) 67 67 + goto done; 68 68 + 69 69 + switch (fitting_mode) { 70 70 + case DRM_MODE_SCALE_CENTER: 71 71 + width = mode->hdisplay; 72 72 + height = mode->vdisplay; 73 73 + x = (adjusted_mode->hdisplay - width + 1)/2; 74 74 + y = (adjusted_mode->vdisplay - height + 1)/2; 75 75 + break; 76 76 + 77 77 + case DRM_MODE_SCALE_ASPECT: 78 78 + /* Scale but preserve the aspect ratio */ 79 79 + { 80 80 + u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; 81 81 + u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; 82 82 + if (scaled_width > scaled_height) { /* pillar */ 83 83 + width = scaled_height / mode->vdisplay; 84 84 + x = (adjusted_mode->hdisplay - width + 1) / 2; 85 85 + y = 0; 86 86 + height = adjusted_mode->vdisplay; 87 87 + } else if (scaled_width < scaled_height) { /* letter */ 88 88 + height = scaled_width / mode->hdisplay; 89 89 + y = (adjusted_mode->vdisplay - height + 1) / 2; 90 90 + x = 0; 91 91 + width = adjusted_mode->hdisplay; 92 92 + } else { 93 93 + x = y = 0; 94 94 + width = adjusted_mode->hdisplay; 95 95 + height = adjusted_mode->vdisplay; 96 96 + } 97 97 + } 98 98 + break; 99 99 + 100 100 + default: 101 101 + case DRM_MODE_SCALE_FULLSCREEN: 102 102 + x = y = 0; 103 103 + width = adjusted_mode->hdisplay; 104 104 + height = adjusted_mode->vdisplay; 105 105 + break; 106 106 + } 107 107 + 108 108 + done: 109 109 + dev_priv->pch_pf_pos = (x << 16) | y; 110 110 + dev_priv->pch_pf_size = (width << 16) | height; 111 111 + }

+58 -45

drivers/gpu/drm/i915/intel_ringbuffer.c

reviewed

··· 33 33 #include "i915_drm.h" 34 34 #include "i915_trace.h" 35 35 36 36 + static u32 i915_gem_get_seqno(struct drm_device *dev) 37 37 + { 38 38 + drm_i915_private_t *dev_priv = dev->dev_private; 39 39 + u32 seqno; 40 40 + 41 41 + seqno = dev_priv->next_seqno; 42 42 + 43 43 + /* reserve 0 for non-seqno */ 44 44 + if (++dev_priv->next_seqno == 0) 45 45 + dev_priv->next_seqno = 1; 46 46 + 47 47 + return seqno; 48 48 + } 49 49 + 36 50 static void 37 51 render_ring_flush(struct drm_device *dev, 38 52 struct intel_ring_buffer *ring, 39 53 u32 invalidate_domains, 40 54 u32 flush_domains) 41 55 { 56 56 + drm_i915_private_t *dev_priv = dev->dev_private; 57 57 + u32 cmd; 58 58 + 42 59 #if WATCH_EXEC 43 60 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, 44 61 invalidate_domains, flush_domains); 45 62 #endif 46 46 - u32 cmd; 47 47 - trace_i915_gem_request_flush(dev, ring->next_seqno, 63 63 + 64 64 + trace_i915_gem_request_flush(dev, dev_priv->next_seqno, 48 65 invalidate_domains, flush_domains); 49 66 50 67 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { ··· 250 233 struct drm_file *file_priv, 251 234 u32 flush_domains) 252 235 { 253 253 - u32 seqno; 254 236 drm_i915_private_t *dev_priv = dev->dev_private; 255 255 - seqno = intel_ring_get_seqno(dev, ring); 237 237 + u32 seqno; 238 238 + 239 239 + seqno = i915_gem_get_seqno(dev); 256 240 257 241 if (IS_GEN6(dev)) { 258 242 BEGIN_LP_RING(6); ··· 423 405 u32 flush_domains) 424 406 { 425 407 u32 seqno; 426 426 - seqno = intel_ring_get_seqno(dev, ring); 408 408 + 409 409 + seqno = i915_gem_get_seqno(dev); 410 410 + 427 411 intel_ring_begin(dev, ring, 4); 428 412 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); 429 413 intel_ring_emit(dev, ring, ··· 499 479 exec_start = (uint32_t) exec_offset + exec->batch_start_offset; 500 480 exec_len = (uint32_t) exec->batch_len; 501 481 502 502 - trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1); 482 482 + trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); 503 483 504 484 count = nbox ? nbox : 1; 505 485 ··· 535 515 intel_ring_advance(dev, ring); 536 516 } 537 517 518 518 + if (IS_G4X(dev) || IS_IRONLAKE(dev)) { 519 519 + intel_ring_begin(dev, ring, 2); 520 520 + intel_ring_emit(dev, ring, MI_FLUSH | 521 521 + MI_NO_WRITE_FLUSH | 522 522 + MI_INVALIDATE_ISP ); 523 523 + intel_ring_emit(dev, ring, MI_NOOP); 524 524 + intel_ring_advance(dev, ring); 525 525 + } 538 526 /* XXX breadcrumb */ 527 527 + 539 528 return 0; 540 529 } 541 530 ··· 617 588 int intel_init_ring_buffer(struct drm_device *dev, 618 589 struct intel_ring_buffer *ring) 619 590 { 620 620 - int ret; 621 591 struct drm_i915_gem_object *obj_priv; 622 592 struct drm_gem_object *obj; 593 593 + int ret; 594 594 + 623 595 ring->dev = dev; 624 596 625 597 if (I915_NEED_GFX_HWS(dev)) { ··· 633 603 if (obj == NULL) { 634 604 DRM_ERROR("Failed to allocate ringbuffer\n"); 635 605 ret = -ENOMEM; 636 636 - goto cleanup; 606 606 + goto err_hws; 637 607 } 638 608 639 609 ring->gem_object = obj; 640 610 641 611 ret = i915_gem_object_pin(obj, ring->alignment); 642 642 - if (ret != 0) { 643 643 - drm_gem_object_unreference(obj); 644 644 - goto cleanup; 645 645 - } 612 612 + if (ret) 613 613 + goto err_unref; 646 614 647 615 obj_priv = to_intel_bo(obj); 648 616 ring->map.size = ring->size; ··· 652 624 drm_core_ioremap_wc(&ring->map, dev); 653 625 if (ring->map.handle == NULL) { 654 626 DRM_ERROR("Failed to map ringbuffer.\n"); 655 655 - i915_gem_object_unpin(obj); 656 656 - drm_gem_object_unreference(obj); 657 627 ret = -EINVAL; 658 658 - goto cleanup; 628 628 + goto err_unpin; 659 629 } 660 630 661 631 ring->virtual_start = ring->map.handle; 662 632 ret = ring->init(dev, ring); 663 663 - if (ret != 0) { 664 664 - intel_cleanup_ring_buffer(dev, ring); 665 665 - return ret; 666 666 - } 633 633 + if (ret) 634 634 + goto err_unmap; 667 635 668 636 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 669 637 i915_kernel_lost_context(dev); ··· 673 649 INIT_LIST_HEAD(&ring->active_list); 674 650 INIT_LIST_HEAD(&ring->request_list); 675 651 return ret; 676 676 - cleanup: 652 652 + 653 653 + err_unmap: 654 654 + drm_core_ioremapfree(&ring->map, dev); 655 655 + err_unpin: 656 656 + i915_gem_object_unpin(obj); 657 657 + err_unref: 658 658 + drm_gem_object_unreference(obj); 659 659 + ring->gem_object = NULL; 660 660 + err_hws: 677 661 cleanup_status_page(dev, ring); 678 662 return ret; 679 663 } ··· 714 682 } 715 683 716 684 virt = (unsigned int *)(ring->virtual_start + ring->tail); 717 717 - rem /= 4; 718 718 - while (rem--) 685 685 + rem /= 8; 686 686 + while (rem--) { 719 687 *virt++ = MI_NOOP; 688 688 + *virt++ = MI_NOOP; 689 689 + } 720 690 721 691 ring->tail = 0; 722 692 ring->space = ring->head - 8; ··· 763 729 intel_wrap_ring_buffer(dev, ring); 764 730 if (unlikely(ring->space < n)) 765 731 intel_wait_ring_buffer(dev, ring, n); 766 766 - } 767 732 768 768 - void intel_ring_emit(struct drm_device *dev, 769 769 - struct intel_ring_buffer *ring, unsigned int data) 770 770 - { 771 771 - unsigned int *virt = ring->virtual_start + ring->tail; 772 772 - *virt = data; 773 773 - ring->tail += 4; 774 774 - ring->tail &= ring->size - 1; 775 775 - ring->space -= 4; 733 733 + ring->space -= n; 776 734 } 777 735 778 736 void intel_ring_advance(struct drm_device *dev, 779 737 struct intel_ring_buffer *ring) 780 738 { 739 739 + ring->tail &= ring->size - 1; 781 740 ring->advance_ring(dev, ring); 782 741 } 783 742 ··· 787 760 ring->tail &= ring->size - 1; 788 761 ring->space -= len; 789 762 intel_ring_advance(dev, ring); 790 790 - } 791 791 - 792 792 - u32 intel_ring_get_seqno(struct drm_device *dev, 793 793 - struct intel_ring_buffer *ring) 794 794 - { 795 795 - u32 seqno; 796 796 - seqno = ring->next_seqno; 797 797 - 798 798 - /* reserve 0 for non-seqno */ 799 799 - if (++ring->next_seqno == 0) 800 800 - ring->next_seqno = 1; 801 801 - return seqno; 802 763 } 803 764 804 765 struct intel_ring_buffer render_ring = { ··· 806 791 .head = 0, 807 792 .tail = 0, 808 793 .space = 0, 809 809 - .next_seqno = 1, 810 794 .user_irq_refcount = 0, 811 795 .irq_gem_seqno = 0, 812 796 .waiting_gem_seqno = 0, ··· 844 830 .head = 0, 845 831 .tail = 0, 846 832 .space = 0, 847 847 - .next_seqno = 1, 848 833 .user_irq_refcount = 0, 849 834 .irq_gem_seqno = 0, 850 835 .waiting_gem_seqno = 0,

+10 -3

drivers/gpu/drm/i915/intel_ringbuffer.h

reviewed

··· 26 26 unsigned int head; 27 27 unsigned int tail; 28 28 unsigned int space; 29 29 - u32 next_seqno; 30 29 struct intel_hw_status_page status_page; 31 30 32 31 u32 irq_gem_seqno; /* last seq seem at irq time */ ··· 105 106 struct intel_ring_buffer *ring); 106 107 void intel_ring_begin(struct drm_device *dev, 107 108 struct intel_ring_buffer *ring, int n); 108 108 - void intel_ring_emit(struct drm_device *dev, 109 109 - struct intel_ring_buffer *ring, u32 data); 109 109 + 110 110 + static inline void intel_ring_emit(struct drm_device *dev, 111 111 + struct intel_ring_buffer *ring, 112 112 + unsigned int data) 113 113 + { 114 114 + unsigned int *virt = ring->virtual_start + ring->tail; 115 115 + *virt = data; 116 116 + ring->tail += 4; 117 117 + } 118 118 + 110 119 void intel_fill_struct(struct drm_device *dev, 111 120 struct intel_ring_buffer *ring, 112 121 void *data,

+936 -1187

drivers/gpu/drm/i915/intel_sdvo.c

reviewed

··· 31 31 #include "drmP.h" 32 32 #include "drm.h" 33 33 #include "drm_crtc.h" 34 34 - #include "intel_drv.h" 35 34 #include "drm_edid.h" 35 35 + #include "intel_drv.h" 36 36 #include "i915_drm.h" 37 37 #include "i915_drv.h" 38 38 #include "intel_sdvo_regs.h" ··· 47 47 48 48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49 49 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 50 50 + #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 50 51 51 52 52 52 - static char *tv_format_names[] = { 53 53 + static const char *tv_format_names[] = { 53 54 "NTSC_M" , "NTSC_J" , "NTSC_443", 54 55 "PAL_B" , "PAL_D" , "PAL_G" , 55 56 "PAL_H" , "PAL_I" , "PAL_M" , ··· 62 61 63 62 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 64 63 65 65 - struct intel_sdvo_priv { 64 64 + struct intel_sdvo { 65 65 + struct intel_encoder base; 66 66 + 66 67 u8 slave_addr; 67 68 68 69 /* Register for the SDVO device: SDVOB or SDVOC */ ··· 98 95 bool is_tv; 99 96 100 97 /* This is for current tv format name */ 101 101 - char *tv_format_name; 98 98 + int tv_format_index; 102 99 103 100 /** 104 101 * This is set if we treat the device as HDMI, instead of DVI. ··· 135 132 }; 136 133 137 134 struct intel_sdvo_connector { 135 135 + struct intel_connector base; 136 136 + 138 137 /* Mark the type of connector */ 139 138 uint16_t output_flag; 140 139 141 140 /* This contains all current supported TV format */ 142 142 - char *tv_format_supported[TV_FORMAT_NUM]; 141 141 + u8 tv_format_supported[TV_FORMAT_NUM]; 143 142 int format_supported_num; 144 144 - struct drm_property *tv_format_property; 145 145 - struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; 146 146 - 147 147 - /** 148 148 - * Returned SDTV resolutions allowed for the current format, if the 149 149 - * device reported it. 150 150 - */ 151 151 - struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; 143 143 + struct drm_property *tv_format; 152 144 153 145 /* add the property for the SDVO-TV */ 154 154 - struct drm_property *left_property; 155 155 - struct drm_property *right_property; 156 156 - struct drm_property *top_property; 157 157 - struct drm_property *bottom_property; 158 158 - struct drm_property *hpos_property; 159 159 - struct drm_property *vpos_property; 146 146 + struct drm_property *left; 147 147 + struct drm_property *right; 148 148 + struct drm_property *top; 149 149 + struct drm_property *bottom; 150 150 + struct drm_property *hpos; 151 151 + struct drm_property *vpos; 152 152 + struct drm_property *contrast; 153 153 + struct drm_property *saturation; 154 154 + struct drm_property *hue; 155 155 + struct drm_property *sharpness; 156 156 + struct drm_property *flicker_filter; 157 157 + struct drm_property *flicker_filter_adaptive; 158 158 + struct drm_property *flicker_filter_2d; 159 159 + struct drm_property *tv_chroma_filter; 160 160 + struct drm_property *tv_luma_filter; 161 161 + struct drm_property *dot_crawl; 160 162 161 163 /* add the property for the SDVO-TV/LVDS */ 162 162 - struct drm_property *brightness_property; 163 163 - struct drm_property *contrast_property; 164 164 - struct drm_property *saturation_property; 165 165 - struct drm_property *hue_property; 164 164 + struct drm_property *brightness; 166 165 167 166 /* Add variable to record current setting for the above property */ 168 167 u32 left_margin, right_margin, top_margin, bottom_margin; 168 168 + 169 169 /* this is to get the range of margin.*/ 170 170 u32 max_hscan, max_vscan; 171 171 u32 max_hpos, cur_hpos; ··· 177 171 u32 cur_contrast, max_contrast; 178 172 u32 cur_saturation, max_saturation; 179 173 u32 cur_hue, max_hue; 174 174 + u32 cur_sharpness, max_sharpness; 175 175 + u32 cur_flicker_filter, max_flicker_filter; 176 176 + u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 177 177 + u32 cur_flicker_filter_2d, max_flicker_filter_2d; 178 178 + u32 cur_tv_chroma_filter, max_tv_chroma_filter; 179 179 + u32 cur_tv_luma_filter, max_tv_luma_filter; 180 180 + u32 cur_dot_crawl, max_dot_crawl; 180 181 }; 181 182 183 183 + static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder) 184 184 + { 185 185 + return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base); 186 186 + } 187 187 + 188 188 + static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 189 189 + { 190 190 + return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 191 191 + } 192 192 + 182 193 static bool 183 183 - intel_sdvo_output_setup(struct intel_encoder *intel_encoder, 184 184 - uint16_t flags); 185 185 - static void 186 186 - intel_sdvo_tv_create_property(struct drm_connector *connector, int type); 187 187 - static void 188 188 - intel_sdvo_create_enhance_property(struct drm_connector *connector); 194 194 + intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 195 195 + static bool 196 196 + intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 197 197 + struct intel_sdvo_connector *intel_sdvo_connector, 198 198 + int type); 199 199 + static bool 200 200 + intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 201 201 + struct intel_sdvo_connector *intel_sdvo_connector); 189 202 190 203 /** 191 204 * Writes the SDVOB or SDVOC with the given value, but always writes both 192 205 * SDVOB and SDVOC to work around apparent hardware issues (according to 193 206 * comments in the BIOS). 194 207 */ 195 195 - static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val) 208 208 + static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 196 209 { 197 197 - struct drm_device *dev = intel_encoder->enc.dev; 210 210 + struct drm_device *dev = intel_sdvo->base.enc.dev; 198 211 struct drm_i915_private *dev_priv = dev->dev_private; 199 199 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 200 212 u32 bval = val, cval = val; 201 213 int i; 202 214 203 203 - if (sdvo_priv->sdvo_reg == PCH_SDVOB) { 204 204 - I915_WRITE(sdvo_priv->sdvo_reg, val); 205 205 - I915_READ(sdvo_priv->sdvo_reg); 215 215 + if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 216 216 + I915_WRITE(intel_sdvo->sdvo_reg, val); 217 217 + I915_READ(intel_sdvo->sdvo_reg); 206 218 return; 207 219 } 208 220 209 209 - if (sdvo_priv->sdvo_reg == SDVOB) { 221 221 + if (intel_sdvo->sdvo_reg == SDVOB) { 210 222 cval = I915_READ(SDVOC); 211 223 } else { 212 224 bval = I915_READ(SDVOB); ··· 243 219 } 244 220 } 245 221 246 246 - static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr, 247 247 - u8 *ch) 222 222 + static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 248 223 { 249 249 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 250 250 - u8 out_buf[2]; 224 224 + u8 out_buf[2] = { addr, 0 }; 251 225 u8 buf[2]; 252 252 - int ret; 253 253 - 254 226 struct i2c_msg msgs[] = { 255 227 { 256 256 - .addr = sdvo_priv->slave_addr >> 1, 228 228 + .addr = intel_sdvo->slave_addr >> 1, 257 229 .flags = 0, 258 230 .len = 1, 259 231 .buf = out_buf, 260 232 }, 261 233 { 262 262 - .addr = sdvo_priv->slave_addr >> 1, 234 234 + .addr = intel_sdvo->slave_addr >> 1, 263 235 .flags = I2C_M_RD, 264 236 .len = 1, 265 237 .buf = buf, 266 238 } 267 239 }; 240 240 + int ret; 268 241 269 269 - out_buf[0] = addr; 270 270 - out_buf[1] = 0; 271 271 - 272 272 - if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2) 242 242 + if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2) 273 243 { 274 244 *ch = buf[0]; 275 245 return true; ··· 273 255 return false; 274 256 } 275 257 276 276 - static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr, 277 277 - u8 ch) 258 258 + static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch) 278 259 { 279 279 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 280 280 - u8 out_buf[2]; 260 260 + u8 out_buf[2] = { addr, ch }; 281 261 struct i2c_msg msgs[] = { 282 262 { 283 283 - .addr = sdvo_priv->slave_addr >> 1, 263 263 + .addr = intel_sdvo->slave_addr >> 1, 284 264 .flags = 0, 285 265 .len = 2, 286 266 .buf = out_buf, 287 267 } 288 268 }; 289 269 290 290 - out_buf[0] = addr; 291 291 - out_buf[1] = ch; 292 292 - 293 293 - if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1) 294 294 - { 295 295 - return true; 296 296 - } 297 297 - return false; 270 270 + return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1; 298 271 } 299 272 300 273 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 301 274 /** Mapping of command numbers to names, for debug output */ 302 275 static const struct _sdvo_cmd_name { 303 276 u8 cmd; 304 304 - char *name; 277 277 + const char *name; 305 278 } sdvo_cmd_names[] = { 306 279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 307 280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), ··· 337 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 338 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 339 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 331 331 + 340 332 /* Add the op code for SDVO enhancements */ 341 341 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H), 342 342 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H), 343 343 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H), 344 344 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V), 345 345 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V), 346 346 - SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V), 333 333 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 334 334 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 335 335 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 336 336 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 337 337 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 338 338 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 347 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 348 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 349 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), ··· 363 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 364 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 365 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 356 356 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 357 357 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 358 358 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 359 359 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 360 360 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 361 361 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 362 362 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 363 363 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 364 364 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 365 365 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 366 366 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 367 367 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 368 368 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 369 369 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 370 370 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 371 371 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 372 372 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 373 373 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 374 374 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 375 375 + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 376 376 + 366 377 /* HDMI op code */ 367 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 368 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), ··· 408 377 }; 409 378 410 379 #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) 411 411 - #define SDVO_NAME(dev_priv) (IS_SDVOB((dev_priv)->sdvo_reg) ? "SDVOB" : "SDVOC") 412 412 - #define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv) 380 380 + #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") 413 381 414 414 - static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd, 415 415 - void *args, int args_len) 382 382 + static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 383 383 + const void *args, int args_len) 416 384 { 417 417 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 418 385 int i; 419 386 420 387 DRM_DEBUG_KMS("%s: W: %02X ", 421 421 - SDVO_NAME(sdvo_priv), cmd); 388 388 + SDVO_NAME(intel_sdvo), cmd); 422 389 for (i = 0; i < args_len; i++) 423 390 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); 424 391 for (; i < 8; i++) ··· 432 403 DRM_LOG_KMS("\n"); 433 404 } 434 405 435 435 - static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd, 436 436 - void *args, int args_len) 406 406 + static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 407 407 + const void *args, int args_len) 437 408 { 438 409 int i; 439 410 440 440 - intel_sdvo_debug_write(intel_encoder, cmd, args, args_len); 411 411 + intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 441 412 442 413 for (i = 0; i < args_len; i++) { 443 443 - intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i, 444 444 - ((u8*)args)[i]); 414 414 + if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i, 415 415 + ((u8*)args)[i])) 416 416 + return false; 445 417 } 446 418 447 447 - intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd); 419 419 + return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd); 448 420 } 449 421 450 422 static const char *cmd_status_names[] = { ··· 458 428 "Scaling not supported" 459 429 }; 460 430 461 461 - static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder, 431 431 + static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo, 462 432 void *response, int response_len, 463 433 u8 status) 464 434 { 465 465 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 466 435 int i; 467 436 468 468 - DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); 437 437 + DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); 469 438 for (i = 0; i < response_len; i++) 470 439 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); 471 440 for (; i < 8; i++) ··· 476 447 DRM_LOG_KMS("\n"); 477 448 } 478 449 479 479 - static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder, 480 480 - void *response, int response_len) 450 450 + static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 451 451 + void *response, int response_len) 481 452 { 482 453 int i; 483 454 u8 status; ··· 486 457 while (retry--) { 487 458 /* Read the command response */ 488 459 for (i = 0; i < response_len; i++) { 489 489 - intel_sdvo_read_byte(intel_encoder, 490 490 - SDVO_I2C_RETURN_0 + i, 491 491 - &((u8 *)response)[i]); 460 460 + if (!intel_sdvo_read_byte(intel_sdvo, 461 461 + SDVO_I2C_RETURN_0 + i, 462 462 + &((u8 *)response)[i])) 463 463 + return false; 492 464 } 493 465 494 466 /* read the return status */ 495 495 - intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS, 496 496 - &status); 467 467 + if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS, 468 468 + &status)) 469 469 + return false; 497 470 498 498 - intel_sdvo_debug_response(intel_encoder, response, response_len, 471 471 + intel_sdvo_debug_response(intel_sdvo, response, response_len, 499 472 status); 500 473 if (status != SDVO_CMD_STATUS_PENDING) 501 501 - return status; 474 474 + break; 502 475 503 476 mdelay(50); 504 477 } 505 478 506 506 - return status; 479 479 + return status == SDVO_CMD_STATUS_SUCCESS; 507 480 } 508 481 509 482 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) ··· 525 494 * another I2C transaction after issuing the DDC bus switch, it will be 526 495 * switched to the internal SDVO register. 527 496 */ 528 528 - static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder, 497 497 + static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 529 498 u8 target) 530 499 { 531 531 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 532 500 u8 out_buf[2], cmd_buf[2], ret_value[2], ret; 533 501 struct i2c_msg msgs[] = { 534 502 { 535 535 - .addr = sdvo_priv->slave_addr >> 1, 503 503 + .addr = intel_sdvo->slave_addr >> 1, 536 504 .flags = 0, 537 505 .len = 2, 538 506 .buf = out_buf, 539 507 }, 540 508 /* the following two are to read the response */ 541 509 { 542 542 - .addr = sdvo_priv->slave_addr >> 1, 510 510 + .addr = intel_sdvo->slave_addr >> 1, 543 511 .flags = 0, 544 512 .len = 1, 545 513 .buf = cmd_buf, 546 514 }, 547 515 { 548 548 - .addr = sdvo_priv->slave_addr >> 1, 516 516 + .addr = intel_sdvo->slave_addr >> 1, 549 517 .flags = I2C_M_RD, 550 518 .len = 1, 551 519 .buf = ret_value, 552 520 }, 553 521 }; 554 522 555 555 - intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH, 523 523 + intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH, 556 524 &target, 1); 557 525 /* write the DDC switch command argument */ 558 558 - intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target); 526 526 + intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target); 559 527 560 528 out_buf[0] = SDVO_I2C_OPCODE; 561 529 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; ··· 563 533 ret_value[0] = 0; 564 534 ret_value[1] = 0; 565 535 566 566 - ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3); 536 536 + ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3); 567 537 if (ret != 3) { 568 538 /* failure in I2C transfer */ 569 539 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); ··· 577 547 return; 578 548 } 579 549 580 580 - static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1) 550 550 + static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 551 551 + { 552 552 + if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 553 553 + return false; 554 554 + 555 555 + return intel_sdvo_read_response(intel_sdvo, NULL, 0); 556 556 + } 557 557 + 558 558 + static bool 559 559 + intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 560 560 + { 561 561 + if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 562 562 + return false; 563 563 + 564 564 + return intel_sdvo_read_response(intel_sdvo, value, len); 565 565 + } 566 566 + 567 567 + static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 581 568 { 582 569 struct intel_sdvo_set_target_input_args targets = {0}; 583 583 - u8 status; 584 584 - 585 585 - if (target_0 && target_1) 586 586 - return SDVO_CMD_STATUS_NOTSUPP; 587 587 - 588 588 - if (target_1) 589 589 - targets.target_1 = 1; 590 590 - 591 591 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets, 592 592 - sizeof(targets)); 593 593 - 594 594 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 595 595 - 596 596 - return (status == SDVO_CMD_STATUS_SUCCESS); 570 570 + return intel_sdvo_set_value(intel_sdvo, 571 571 + SDVO_CMD_SET_TARGET_INPUT, 572 572 + &targets, sizeof(targets)); 597 573 } 598 574 599 575 /** ··· 608 572 * This function is making an assumption about the layout of the response, 609 573 * which should be checked against the docs. 610 574 */ 611 611 - static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2) 575 575 + static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 612 576 { 613 577 struct intel_sdvo_get_trained_inputs_response response; 614 614 - u8 status; 615 578 616 616 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); 617 617 - status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response)); 618 618 - if (status != SDVO_CMD_STATUS_SUCCESS) 579 579 + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 580 580 + &response, sizeof(response))) 619 581 return false; 620 582 621 583 *input_1 = response.input0_trained; ··· 621 587 return true; 622 588 } 623 589 624 624 - static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder, 590 590 + static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 625 591 u16 outputs) 626 592 { 627 627 - u8 status; 628 628 - 629 629 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, 630 630 - sizeof(outputs)); 631 631 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 632 632 - return (status == SDVO_CMD_STATUS_SUCCESS); 593 593 + return intel_sdvo_set_value(intel_sdvo, 594 594 + SDVO_CMD_SET_ACTIVE_OUTPUTS, 595 595 + &outputs, sizeof(outputs)); 633 596 } 634 597 635 635 - static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder, 598 598 + static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 636 599 int mode) 637 600 { 638 638 - u8 status, state = SDVO_ENCODER_STATE_ON; 601 601 + u8 state = SDVO_ENCODER_STATE_ON; 639 602 640 603 switch (mode) { 641 604 case DRM_MODE_DPMS_ON: ··· 649 618 break; 650 619 } 651 620 652 652 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, 653 653 - sizeof(state)); 654 654 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 655 655 - 656 656 - return (status == SDVO_CMD_STATUS_SUCCESS); 621 621 + return intel_sdvo_set_value(intel_sdvo, 622 622 + SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 657 623 } 658 624 659 659 - static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder, 625 625 + static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 660 626 int *clock_min, 661 627 int *clock_max) 662 628 { 663 629 struct intel_sdvo_pixel_clock_range clocks; 664 664 - u8 status; 665 630 666 666 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 667 667 - NULL, 0); 668 668 - 669 669 - status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks)); 670 670 - 671 671 - if (status != SDVO_CMD_STATUS_SUCCESS) 631 631 + if (!intel_sdvo_get_value(intel_sdvo, 632 632 + SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 633 633 + &clocks, sizeof(clocks))) 672 634 return false; 673 635 674 636 /* Convert the values from units of 10 kHz to kHz. */ 675 637 *clock_min = clocks.min * 10; 676 638 *clock_max = clocks.max * 10; 677 677 - 678 639 return true; 679 640 } 680 641 681 681 - static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder, 642 642 + static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 682 643 u16 outputs) 683 644 { 684 684 - u8 status; 685 685 - 686 686 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, 687 687 - sizeof(outputs)); 688 688 - 689 689 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 690 690 - return (status == SDVO_CMD_STATUS_SUCCESS); 645 645 + return intel_sdvo_set_value(intel_sdvo, 646 646 + SDVO_CMD_SET_TARGET_OUTPUT, 647 647 + &outputs, sizeof(outputs)); 691 648 } 692 649 693 693 - static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd, 650 650 + static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 694 651 struct intel_sdvo_dtd *dtd) 695 652 { 696 696 - u8 status; 697 697 - 698 698 - intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1)); 699 699 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 700 700 - if (status != SDVO_CMD_STATUS_SUCCESS) 701 701 - return false; 702 702 - 703 703 - intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 704 704 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 705 705 - if (status != SDVO_CMD_STATUS_SUCCESS) 706 706 - return false; 707 707 - 708 708 - return true; 653 653 + return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 654 654 + intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 709 655 } 710 656 711 711 - static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder, 657 657 + static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 712 658 struct intel_sdvo_dtd *dtd) 713 659 { 714 714 - return intel_sdvo_set_timing(intel_encoder, 660 660 + return intel_sdvo_set_timing(intel_sdvo, 715 661 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 716 662 } 717 663 718 718 - static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder, 664 664 + static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 719 665 struct intel_sdvo_dtd *dtd) 720 666 { 721 721 - return intel_sdvo_set_timing(intel_encoder, 667 667 + return intel_sdvo_set_timing(intel_sdvo, 722 668 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 723 669 } 724 670 725 671 static bool 726 726 - intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder, 672 672 + intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 727 673 uint16_t clock, 728 674 uint16_t width, 729 675 uint16_t height) 730 676 { 731 677 struct intel_sdvo_preferred_input_timing_args args; 732 732 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 733 733 - uint8_t status; 734 678 735 679 memset(&args, 0, sizeof(args)); 736 680 args.clock = clock; ··· 713 707 args.height = height; 714 708 args.interlace = 0; 715 709 716 716 - if (sdvo_priv->is_lvds && 717 717 - (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width || 718 718 - sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) 710 710 + if (intel_sdvo->is_lvds && 711 711 + (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 712 712 + intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 719 713 args.scaled = 1; 720 714 721 721 - intel_sdvo_write_cmd(intel_encoder, 722 722 - SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 723 723 - &args, sizeof(args)); 724 724 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 725 725 - if (status != SDVO_CMD_STATUS_SUCCESS) 726 726 - return false; 727 727 - 728 728 - return true; 715 715 + return intel_sdvo_set_value(intel_sdvo, 716 716 + SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 717 717 + &args, sizeof(args)); 729 718 } 730 719 731 731 - static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder, 720 720 + static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 732 721 struct intel_sdvo_dtd *dtd) 733 722 { 734 734 - bool status; 735 735 - 736 736 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 737 737 - NULL, 0); 738 738 - 739 739 - status = intel_sdvo_read_response(intel_encoder, &dtd->part1, 740 740 - sizeof(dtd->part1)); 741 741 - if (status != SDVO_CMD_STATUS_SUCCESS) 742 742 - return false; 743 743 - 744 744 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 745 745 - NULL, 0); 746 746 - 747 747 - status = intel_sdvo_read_response(intel_encoder, &dtd->part2, 748 748 - sizeof(dtd->part2)); 749 749 - if (status != SDVO_CMD_STATUS_SUCCESS) 750 750 - return false; 751 751 - 752 752 - return false; 723 723 + return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 724 724 + &dtd->part1, sizeof(dtd->part1)) && 725 725 + intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 726 726 + &dtd->part2, sizeof(dtd->part2)); 753 727 } 754 728 755 755 - static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val) 729 729 + static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 756 730 { 757 757 - u8 status; 758 758 - 759 759 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 760 760 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 761 761 - if (status != SDVO_CMD_STATUS_SUCCESS) 762 762 - return false; 763 763 - 764 764 - return true; 731 731 + return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 765 732 } 766 733 767 734 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 768 768 - struct drm_display_mode *mode) 735 735 + const struct drm_display_mode *mode) 769 736 { 770 737 uint16_t width, height; 771 738 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; ··· 787 808 } 788 809 789 810 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 790 790 - struct intel_sdvo_dtd *dtd) 811 811 + const struct intel_sdvo_dtd *dtd) 791 812 { 792 813 mode->hdisplay = dtd->part1.h_active; 793 814 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; ··· 819 840 mode->flags |= DRM_MODE_FLAG_PVSYNC; 820 841 } 821 842 822 822 - static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder, 843 843 + static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, 823 844 struct intel_sdvo_encode *encode) 824 845 { 825 825 - uint8_t status; 846 846 + if (intel_sdvo_get_value(intel_sdvo, 847 847 + SDVO_CMD_GET_SUPP_ENCODE, 848 848 + encode, sizeof(*encode))) 849 849 + return true; 826 850 827 827 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); 828 828 - status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode)); 829 829 - if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ 830 830 - memset(encode, 0, sizeof(*encode)); 831 831 - return false; 832 832 - } 833 833 - 834 834 - return true; 851 851 + /* non-support means DVI */ 852 852 + memset(encode, 0, sizeof(*encode)); 853 853 + return false; 835 854 } 836 855 837 837 - static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder, 856 856 + static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 838 857 uint8_t mode) 839 858 { 840 840 - uint8_t status; 841 841 - 842 842 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1); 843 843 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 844 844 - 845 845 - return (status == SDVO_CMD_STATUS_SUCCESS); 859 859 + return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 846 860 } 847 861 848 848 - static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder, 862 862 + static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 849 863 uint8_t mode) 850 864 { 851 851 - uint8_t status; 852 852 - 853 853 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 854 854 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 855 855 - 856 856 - return (status == SDVO_CMD_STATUS_SUCCESS); 865 865 + return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 857 866 } 858 867 859 868 #if 0 860 860 - static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder) 869 869 + static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 861 870 { 862 871 int i, j; 863 872 uint8_t set_buf_index[2]; ··· 854 887 uint8_t buf[48]; 855 888 uint8_t *pos; 856 889 857 857 - intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); 858 858 - intel_sdvo_read_response(encoder, &av_split, 1); 890 890 + intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 859 891 860 892 for (i = 0; i <= av_split; i++) { 861 893 set_buf_index[0] = i; set_buf_index[1] = 0; ··· 874 908 } 875 909 #endif 876 910 877 877 - static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder, 911 911 + static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, 878 912 int index, 879 913 uint8_t *data, int8_t size, uint8_t tx_rate) 880 914 { ··· 883 917 set_buf_index[0] = index; 884 918 set_buf_index[1] = 0; 885 919 886 886 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX, 887 887 - set_buf_index, 2); 920 920 + if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, 921 921 + set_buf_index, 2)) 922 922 + return false; 888 923 889 924 for (; size > 0; size -= 8) { 890 890 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8); 925 925 + if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8)) 926 926 + return false; 927 927 + 891 928 data += 8; 892 929 } 893 930 894 894 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 931 931 + return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 895 932 } 896 933 897 934 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) ··· 969 1000 } __attribute__ ((packed)) u; 970 1001 } __attribute__((packed)); 971 1002 972 972 - static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder, 1003 1003 + static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 973 1004 struct drm_display_mode * mode) 974 1005 { 975 1006 struct dip_infoframe avi_if = { ··· 980 1011 981 1012 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 982 1013 4 + avi_if.len); 983 983 - intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if, 984 984 - 4 + avi_if.len, 985 985 - SDVO_HBUF_TX_VSYNC); 1014 1014 + return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, 1015 1015 + 4 + avi_if.len, 1016 1016 + SDVO_HBUF_TX_VSYNC); 986 1017 } 987 1018 988 988 - static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder) 1019 1019 + static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 989 1020 { 990 990 - 991 1021 struct intel_sdvo_tv_format format; 992 992 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 993 993 - uint32_t format_map, i; 994 994 - uint8_t status; 1022 1022 + uint32_t format_map; 995 1023 996 996 - for (i = 0; i < TV_FORMAT_NUM; i++) 997 997 - if (tv_format_names[i] == sdvo_priv->tv_format_name) 998 998 - break; 999 999 - 1000 1000 - format_map = 1 << i; 1024 1024 + format_map = 1 << intel_sdvo->tv_format_index; 1001 1025 memset(&format, 0, sizeof(format)); 1002 1002 - memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? 1003 1003 - sizeof(format) : sizeof(format_map)); 1026 1026 + memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1004 1027 1005 1005 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format, 1006 1006 - sizeof(format)); 1028 1028 + BUILD_BUG_ON(sizeof(format) != 6); 1029 1029 + return intel_sdvo_set_value(intel_sdvo, 1030 1030 + SDVO_CMD_SET_TV_FORMAT, 1031 1031 + &format, sizeof(format)); 1032 1032 + } 1007 1033 1008 1008 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 1009 1009 - if (status != SDVO_CMD_STATUS_SUCCESS) 1010 1010 - DRM_DEBUG_KMS("%s: Failed to set TV format\n", 1011 1011 - SDVO_NAME(sdvo_priv)); 1034 1034 + static bool 1035 1035 + intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1036 1036 + struct drm_display_mode *mode) 1037 1037 + { 1038 1038 + struct intel_sdvo_dtd output_dtd; 1039 1039 + 1040 1040 + if (!intel_sdvo_set_target_output(intel_sdvo, 1041 1041 + intel_sdvo->attached_output)) 1042 1042 + return false; 1043 1043 + 1044 1044 + intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1045 1045 + if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1046 1046 + return false; 1047 1047 + 1048 1048 + return true; 1049 1049 + } 1050 1050 + 1051 1051 + static bool 1052 1052 + intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, 1053 1053 + struct drm_display_mode *mode, 1054 1054 + struct drm_display_mode *adjusted_mode) 1055 1055 + { 1056 1056 + struct intel_sdvo_dtd input_dtd; 1057 1057 + 1058 1058 + /* Reset the input timing to the screen. Assume always input 0. */ 1059 1059 + if (!intel_sdvo_set_target_input(intel_sdvo)) 1060 1060 + return false; 1061 1061 + 1062 1062 + if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1063 1063 + mode->clock / 10, 1064 1064 + mode->hdisplay, 1065 1065 + mode->vdisplay)) 1066 1066 + return false; 1067 1067 + 1068 1068 + if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1069 1069 + &input_dtd)) 1070 1070 + return false; 1071 1071 + 1072 1072 + intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1073 1073 + intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags; 1074 1074 + 1075 1075 + drm_mode_set_crtcinfo(adjusted_mode, 0); 1076 1076 + mode->clock = adjusted_mode->clock; 1077 1077 + return true; 1012 1078 } 1013 1079 1014 1080 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 1015 1081 struct drm_display_mode *mode, 1016 1082 struct drm_display_mode *adjusted_mode) 1017 1083 { 1018 1018 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1019 1019 - struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv; 1084 1084 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1020 1085 1021 1021 - if (dev_priv->is_tv) { 1022 1022 - struct intel_sdvo_dtd output_dtd; 1023 1023 - bool success; 1024 1024 - 1025 1025 - /* We need to construct preferred input timings based on our 1026 1026 - * output timings. To do that, we have to set the output 1027 1027 - * timings, even though this isn't really the right place in 1028 1028 - * the sequence to do it. Oh well. 1029 1029 - */ 1030 1030 - 1031 1031 - 1032 1032 - /* Set output timings */ 1033 1033 - intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1034 1034 - intel_sdvo_set_target_output(intel_encoder, 1035 1035 - dev_priv->attached_output); 1036 1036 - intel_sdvo_set_output_timing(intel_encoder, &output_dtd); 1037 1037 - 1038 1038 - /* Set the input timing to the screen. Assume always input 0. */ 1039 1039 - intel_sdvo_set_target_input(intel_encoder, true, false); 1040 1040 - 1041 1041 - 1042 1042 - success = intel_sdvo_create_preferred_input_timing(intel_encoder, 1043 1043 - mode->clock / 10, 1044 1044 - mode->hdisplay, 1045 1045 - mode->vdisplay); 1046 1046 - if (success) { 1047 1047 - struct intel_sdvo_dtd input_dtd; 1048 1048 - 1049 1049 - intel_sdvo_get_preferred_input_timing(intel_encoder, 1050 1050 - &input_dtd); 1051 1051 - intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1052 1052 - dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; 1053 1053 - 1054 1054 - drm_mode_set_crtcinfo(adjusted_mode, 0); 1055 1055 - 1056 1056 - mode->clock = adjusted_mode->clock; 1057 1057 - 1058 1058 - adjusted_mode->clock *= 1059 1059 - intel_sdvo_get_pixel_multiplier(mode); 1060 1060 - } else { 1086 1086 + /* We need to construct preferred input timings based on our 1087 1087 + * output timings. To do that, we have to set the output 1088 1088 + * timings, even though this isn't really the right place in 1089 1089 + * the sequence to do it. Oh well. 1090 1090 + */ 1091 1091 + if (intel_sdvo->is_tv) { 1092 1092 + if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1061 1093 return false; 1062 1062 - } 1063 1063 - } else if (dev_priv->is_lvds) { 1064 1064 - struct intel_sdvo_dtd output_dtd; 1065 1065 - bool success; 1066 1094 1067 1067 - drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0); 1068 1068 - /* Set output timings */ 1069 1069 - intel_sdvo_get_dtd_from_mode(&output_dtd, 1070 1070 - dev_priv->sdvo_lvds_fixed_mode); 1071 1071 - 1072 1072 - intel_sdvo_set_target_output(intel_encoder, 1073 1073 - dev_priv->attached_output); 1074 1074 - intel_sdvo_set_output_timing(intel_encoder, &output_dtd); 1075 1075 - 1076 1076 - /* Set the input timing to the screen. Assume always input 0. */ 1077 1077 - intel_sdvo_set_target_input(intel_encoder, true, false); 1078 1078 - 1079 1079 - 1080 1080 - success = intel_sdvo_create_preferred_input_timing( 1081 1081 - intel_encoder, 1082 1082 - mode->clock / 10, 1083 1083 - mode->hdisplay, 1084 1084 - mode->vdisplay); 1085 1085 - 1086 1086 - if (success) { 1087 1087 - struct intel_sdvo_dtd input_dtd; 1088 1088 - 1089 1089 - intel_sdvo_get_preferred_input_timing(intel_encoder, 1090 1090 - &input_dtd); 1091 1091 - intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1092 1092 - dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; 1093 1093 - 1094 1094 - drm_mode_set_crtcinfo(adjusted_mode, 0); 1095 1095 - 1096 1096 - mode->clock = adjusted_mode->clock; 1097 1097 - 1098 1098 - adjusted_mode->clock *= 1099 1099 - intel_sdvo_get_pixel_multiplier(mode); 1100 1100 - } else { 1095 1095 + if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode)) 1101 1096 return false; 1102 1102 - } 1097 1097 + } else if (intel_sdvo->is_lvds) { 1098 1098 + drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0); 1103 1099 1104 1104 - } else { 1105 1105 - /* Make the CRTC code factor in the SDVO pixel multiplier. The 1106 1106 - * SDVO device will be told of the multiplier during mode_set. 1107 1107 - */ 1108 1108 - adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); 1100 1100 + if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1101 1101 + intel_sdvo->sdvo_lvds_fixed_mode)) 1102 1102 + return false; 1103 1103 + 1104 1104 + if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode)) 1105 1105 + return false; 1109 1106 } 1107 1107 + 1108 1108 + /* Make the CRTC code factor in the SDVO pixel multiplier. The 1109 1109 + * SDVO device will be told of the multiplier during mode_set. 1110 1110 + */ 1111 1111 + adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); 1112 1112 + 1110 1113 return true; 1111 1114 } 1112 1115 ··· 1090 1149 struct drm_i915_private *dev_priv = dev->dev_private; 1091 1150 struct drm_crtc *crtc = encoder->crtc; 1092 1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1093 1093 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1094 1094 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1152 1152 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1095 1153 u32 sdvox = 0; 1096 1096 - int sdvo_pixel_multiply; 1154 1154 + int sdvo_pixel_multiply, rate; 1097 1155 struct intel_sdvo_in_out_map in_out; 1098 1156 struct intel_sdvo_dtd input_dtd; 1099 1099 - u8 status; 1100 1157 1101 1158 if (!mode) 1102 1159 return; ··· 1105 1166 * channel on the motherboard. In a two-input device, the first input 1106 1167 * will be SDVOB and the second SDVOC. 1107 1168 */ 1108 1108 - in_out.in0 = sdvo_priv->attached_output; 1169 1169 + in_out.in0 = intel_sdvo->attached_output; 1109 1170 in_out.in1 = 0; 1110 1171 1111 1111 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP, 1112 1112 - &in_out, sizeof(in_out)); 1113 1113 - status = intel_sdvo_read_response(intel_encoder, NULL, 0); 1172 1172 + if (!intel_sdvo_set_value(intel_sdvo, 1173 1173 + SDVO_CMD_SET_IN_OUT_MAP, 1174 1174 + &in_out, sizeof(in_out))) 1175 1175 + return; 1114 1176 1115 1115 - if (sdvo_priv->is_hdmi) { 1116 1116 - intel_sdvo_set_avi_infoframe(intel_encoder, mode); 1177 1177 + if (intel_sdvo->is_hdmi) { 1178 1178 + if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) 1179 1179 + return; 1180 1180 + 1117 1181 sdvox |= SDVO_AUDIO_ENABLE; 1118 1182 } 1119 1183 1120 1184 /* We have tried to get input timing in mode_fixup, and filled into 1121 1185 adjusted_mode */ 1122 1122 - if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { 1186 1186 + if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { 1123 1187 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1124 1124 - input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags; 1188 1188 + input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags; 1125 1189 } else 1126 1190 intel_sdvo_get_dtd_from_mode(&input_dtd, mode); 1127 1191 1128 1192 /* If it's a TV, we already set the output timing in mode_fixup. 1129 1193 * Otherwise, the output timing is equal to the input timing. 1130 1194 */ 1131 1131 - if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { 1195 1195 + if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) { 1132 1196 /* Set the output timing to the screen */ 1133 1133 - intel_sdvo_set_target_output(intel_encoder, 1134 1134 - sdvo_priv->attached_output); 1135 1135 - intel_sdvo_set_output_timing(intel_encoder, &input_dtd); 1197 1197 + if (!intel_sdvo_set_target_output(intel_sdvo, 1198 1198 + intel_sdvo->attached_output)) 1199 1199 + return; 1200 1200 + 1201 1201 + if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd)) 1202 1202 + return; 1136 1203 } 1137 1204 1138 1205 /* Set the input timing to the screen. Assume always input 0. */ 1139 1139 - intel_sdvo_set_target_input(intel_encoder, true, false); 1206 1206 + if (!intel_sdvo_set_target_input(intel_sdvo)) 1207 1207 + return; 1140 1208 1141 1141 - if (sdvo_priv->is_tv) 1142 1142 - intel_sdvo_set_tv_format(intel_encoder); 1209 1209 + if (intel_sdvo->is_tv) { 1210 1210 + if (!intel_sdvo_set_tv_format(intel_sdvo)) 1211 1211 + return; 1212 1212 + } 1143 1213 1144 1214 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1145 1215 * provide the device with a timing it can support, if it supports that ··· 1165 1217 intel_sdvo_set_input_timing(encoder, &input_dtd); 1166 1218 } 1167 1219 #else 1168 1168 - intel_sdvo_set_input_timing(intel_encoder, &input_dtd); 1220 1220 + if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1221 1221 + return; 1169 1222 #endif 1170 1223 1171 1171 - switch (intel_sdvo_get_pixel_multiplier(mode)) { 1172 1172 - case 1: 1173 1173 - intel_sdvo_set_clock_rate_mult(intel_encoder, 1174 1174 - SDVO_CLOCK_RATE_MULT_1X); 1175 1175 - break; 1176 1176 - case 2: 1177 1177 - intel_sdvo_set_clock_rate_mult(intel_encoder, 1178 1178 - SDVO_CLOCK_RATE_MULT_2X); 1179 1179 - break; 1180 1180 - case 4: 1181 1181 - intel_sdvo_set_clock_rate_mult(intel_encoder, 1182 1182 - SDVO_CLOCK_RATE_MULT_4X); 1183 1183 - break; 1224 1224 + sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); 1225 1225 + switch (sdvo_pixel_multiply) { 1226 1226 + case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1227 1227 + case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1228 1228 + case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1184 1229 } 1230 1230 + if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1231 1231 + return; 1185 1232 1186 1233 /* Set the SDVO control regs. */ 1187 1234 if (IS_I965G(dev)) { ··· 1186 1243 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1187 1244 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 1188 1245 } else { 1189 1189 - sdvox |= I915_READ(sdvo_priv->sdvo_reg); 1190 1190 - switch (sdvo_priv->sdvo_reg) { 1246 1246 + sdvox |= I915_READ(intel_sdvo->sdvo_reg); 1247 1247 + switch (intel_sdvo->sdvo_reg) { 1191 1248 case SDVOB: 1192 1249 sdvox &= SDVOB_PRESERVE_MASK; 1193 1250 break; ··· 1200 1257 if (intel_crtc->pipe == 1) 1201 1258 sdvox |= SDVO_PIPE_B_SELECT; 1202 1259 1203 1203 - sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); 1204 1260 if (IS_I965G(dev)) { 1205 1261 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1206 1262 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { ··· 1208 1266 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1209 1267 } 1210 1268 1211 1211 - if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) 1269 1269 + if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL) 1212 1270 sdvox |= SDVO_STALL_SELECT; 1213 1213 - intel_sdvo_write_sdvox(intel_encoder, sdvox); 1271 1271 + intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1214 1272 } 1215 1273 1216 1274 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1217 1275 { 1218 1276 struct drm_device *dev = encoder->dev; 1219 1277 struct drm_i915_private *dev_priv = dev->dev_private; 1220 1220 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1221 1221 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1278 1278 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1279 1279 + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 1222 1280 u32 temp; 1223 1281 1224 1282 if (mode != DRM_MODE_DPMS_ON) { 1225 1225 - intel_sdvo_set_active_outputs(intel_encoder, 0); 1283 1283 + intel_sdvo_set_active_outputs(intel_sdvo, 0); 1226 1284 if (0) 1227 1227 - intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1285 1285 + intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1228 1286 1229 1287 if (mode == DRM_MODE_DPMS_OFF) { 1230 1230 - temp = I915_READ(sdvo_priv->sdvo_reg); 1288 1288 + temp = I915_READ(intel_sdvo->sdvo_reg); 1231 1289 if ((temp & SDVO_ENABLE) != 0) { 1232 1232 - intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE); 1290 1290 + intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1233 1291 } 1234 1292 } 1235 1293 } else { ··· 1237 1295 int i; 1238 1296 u8 status; 1239 1297 1240 1240 - temp = I915_READ(sdvo_priv->sdvo_reg); 1298 1298 + temp = I915_READ(intel_sdvo->sdvo_reg); 1241 1299 if ((temp & SDVO_ENABLE) == 0) 1242 1242 - intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE); 1300 1300 + intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1243 1301 for (i = 0; i < 2; i++) 1244 1244 - intel_wait_for_vblank(dev); 1302 1302 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1245 1303 1246 1246 - status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, 1247 1247 - &input2); 1248 1248 - 1249 1249 - 1304 1304 + status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1250 1305 /* Warn if the device reported failure to sync. 1251 1306 * A lot of SDVO devices fail to notify of sync, but it's 1252 1307 * a given it the status is a success, we succeeded. 1253 1308 */ 1254 1309 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1255 1310 DRM_DEBUG_KMS("First %s output reported failure to " 1256 1256 - "sync\n", SDVO_NAME(sdvo_priv)); 1311 1311 + "sync\n", SDVO_NAME(intel_sdvo)); 1257 1312 } 1258 1313 1259 1314 if (0) 1260 1260 - intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1261 1261 - intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output); 1315 1315 + intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1316 1316 + intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1262 1317 } 1263 1318 return; 1264 1319 } ··· 1264 1325 struct drm_display_mode *mode) 1265 1326 { 1266 1327 struct drm_encoder *encoder = intel_attached_encoder(connector); 1267 1267 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1268 1268 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1328 1328 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1269 1329 1270 1330 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1271 1331 return MODE_NO_DBLESCAN; 1272 1332 1273 1273 - if (sdvo_priv->pixel_clock_min > mode->clock) 1333 1333 + if (intel_sdvo->pixel_clock_min > mode->clock) 1274 1334 return MODE_CLOCK_LOW; 1275 1335 1276 1276 - if (sdvo_priv->pixel_clock_max < mode->clock) 1336 1336 + if (intel_sdvo->pixel_clock_max < mode->clock) 1277 1337 return MODE_CLOCK_HIGH; 1278 1338 1279 1279 - if (sdvo_priv->is_lvds == true) { 1280 1280 - if (sdvo_priv->sdvo_lvds_fixed_mode == NULL) 1339 1339 + if (intel_sdvo->is_lvds) { 1340 1340 + if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1281 1341 return MODE_PANEL; 1282 1342 1283 1283 - if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay) 1284 1284 - return MODE_PANEL; 1285 1285 - 1286 1286 - if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay) 1343 1343 + if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1287 1344 return MODE_PANEL; 1288 1345 } 1289 1346 1290 1347 return MODE_OK; 1291 1348 } 1292 1349 1293 1293 - static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps) 1350 1350 + static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1294 1351 { 1295 1295 - u8 status; 1296 1296 - 1297 1297 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); 1298 1298 - status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps)); 1299 1299 - if (status != SDVO_CMD_STATUS_SUCCESS) 1300 1300 - return false; 1301 1301 - 1302 1302 - return true; 1352 1352 + return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps)); 1303 1353 } 1304 1354 1305 1355 /* No use! */ ··· 1296 1368 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) 1297 1369 { 1298 1370 struct drm_connector *connector = NULL; 1299 1299 - struct intel_encoder *iout = NULL; 1300 1300 - struct intel_sdvo_priv *sdvo; 1371 1371 + struct intel_sdvo *iout = NULL; 1372 1372 + struct intel_sdvo *sdvo; 1301 1373 1302 1374 /* find the sdvo connector */ 1303 1375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1304 1304 - iout = to_intel_encoder(connector); 1376 1376 + iout = to_intel_sdvo(connector); 1305 1377 1306 1378 if (iout->type != INTEL_OUTPUT_SDVO) 1307 1379 continue; ··· 1323 1395 { 1324 1396 u8 response[2]; 1325 1397 u8 status; 1326 1326 - struct intel_encoder *intel_encoder; 1398 1398 + struct intel_sdvo *intel_sdvo; 1327 1399 DRM_DEBUG_KMS("\n"); 1328 1400 1329 1401 if (!connector) 1330 1402 return 0; 1331 1403 1332 1332 - intel_encoder = to_intel_encoder(connector); 1404 1404 + intel_sdvo = to_intel_sdvo(connector); 1333 1405 1334 1334 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1335 1335 - status = intel_sdvo_read_response(intel_encoder, &response, 2); 1336 1336 - 1337 1337 - if (response[0] !=0) 1338 1338 - return 1; 1339 1339 - 1340 1340 - return 0; 1406 1406 + return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1407 1407 + &response, 2) && response[0]; 1341 1408 } 1342 1409 1343 1410 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) 1344 1411 { 1345 1412 u8 response[2]; 1346 1413 u8 status; 1347 1347 - struct intel_encoder *intel_encoder = to_intel_encoder(connector); 1414 1414 + struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); 1348 1415 1349 1349 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1350 1350 - intel_sdvo_read_response(intel_encoder, &response, 2); 1416 1416 + intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1417 1417 + intel_sdvo_read_response(intel_sdvo, &response, 2); 1351 1418 1352 1419 if (on) { 1353 1353 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1354 1354 - status = intel_sdvo_read_response(intel_encoder, &response, 2); 1420 1420 + intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1421 1421 + status = intel_sdvo_read_response(intel_sdvo, &response, 2); 1355 1422 1356 1356 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1423 1423 + intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1357 1424 } else { 1358 1425 response[0] = 0; 1359 1426 response[1] = 0; 1360 1360 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1427 1427 + intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1361 1428 } 1362 1429 1363 1363 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1364 1364 - intel_sdvo_read_response(intel_encoder, &response, 2); 1430 1430 + intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1431 1431 + intel_sdvo_read_response(intel_sdvo, &response, 2); 1365 1432 } 1366 1433 #endif 1367 1434 1368 1435 static bool 1369 1369 - intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder) 1436 1436 + intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1370 1437 { 1371 1371 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1372 1438 int caps = 0; 1373 1439 1374 1374 - if (sdvo_priv->caps.output_flags & 1440 1440 + if (intel_sdvo->caps.output_flags & 1375 1441 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) 1376 1442 caps++; 1377 1377 - if (sdvo_priv->caps.output_flags & 1443 1443 + if (intel_sdvo->caps.output_flags & 1378 1444 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) 1379 1445 caps++; 1380 1380 - if (sdvo_priv->caps.output_flags & 1446 1446 + if (intel_sdvo->caps.output_flags & 1381 1447 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) 1382 1448 caps++; 1383 1383 - if (sdvo_priv->caps.output_flags & 1449 1449 + if (intel_sdvo->caps.output_flags & 1384 1450 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) 1385 1451 caps++; 1386 1386 - if (sdvo_priv->caps.output_flags & 1452 1452 + if (intel_sdvo->caps.output_flags & 1387 1453 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) 1388 1454 caps++; 1389 1455 1390 1390 - if (sdvo_priv->caps.output_flags & 1456 1456 + if (intel_sdvo->caps.output_flags & 1391 1457 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) 1392 1458 caps++; 1393 1459 1394 1394 - if (sdvo_priv->caps.output_flags & 1460 1460 + if (intel_sdvo->caps.output_flags & 1395 1461 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) 1396 1462 caps++; 1397 1463 ··· 1397 1475 { 1398 1476 struct drm_connector *connector; 1399 1477 struct drm_encoder *encoder; 1400 1400 - struct intel_encoder *intel_encoder; 1478 1478 + struct intel_sdvo *intel_sdvo; 1401 1479 1402 1480 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1403 1403 - intel_encoder = enc_to_intel_encoder(encoder); 1404 1404 - if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { 1481 1481 + intel_sdvo = enc_to_intel_sdvo(encoder); 1482 1482 + if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) { 1405 1483 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1406 1484 if (encoder == intel_attached_encoder(connector)) 1407 1485 return connector; ··· 1415 1493 intel_analog_is_connected(struct drm_device *dev) 1416 1494 { 1417 1495 struct drm_connector *analog_connector; 1418 1418 - analog_connector = intel_find_analog_connector(dev); 1419 1496 1497 1497 + analog_connector = intel_find_analog_connector(dev); 1420 1498 if (!analog_connector) 1421 1499 return false; 1422 1500 ··· 1431 1509 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1432 1510 { 1433 1511 struct drm_encoder *encoder = intel_attached_encoder(connector); 1434 1434 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1435 1435 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1436 1436 - struct intel_connector *intel_connector = to_intel_connector(connector); 1437 1437 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 1512 1512 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1513 1513 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1438 1514 enum drm_connector_status status = connector_status_connected; 1439 1515 struct edid *edid = NULL; 1440 1516 1441 1441 - edid = drm_get_edid(connector, intel_encoder->ddc_bus); 1517 1517 + edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); 1442 1518 1443 1519 /* This is only applied to SDVO cards with multiple outputs */ 1444 1444 - if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) { 1520 1520 + if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1445 1521 uint8_t saved_ddc, temp_ddc; 1446 1446 - saved_ddc = sdvo_priv->ddc_bus; 1447 1447 - temp_ddc = sdvo_priv->ddc_bus >> 1; 1522 1522 + saved_ddc = intel_sdvo->ddc_bus; 1523 1523 + temp_ddc = intel_sdvo->ddc_bus >> 1; 1448 1524 /* 1449 1525 * Don't use the 1 as the argument of DDC bus switch to get 1450 1526 * the EDID. It is used for SDVO SPD ROM. 1451 1527 */ 1452 1528 while(temp_ddc > 1) { 1453 1453 - sdvo_priv->ddc_bus = temp_ddc; 1454 1454 - edid = drm_get_edid(connector, intel_encoder->ddc_bus); 1529 1529 + intel_sdvo->ddc_bus = temp_ddc; 1530 1530 + edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); 1455 1531 if (edid) { 1456 1532 /* 1457 1533 * When we can get the EDID, maybe it is the 1458 1534 * correct DDC bus. Update it. 1459 1535 */ 1460 1460 - sdvo_priv->ddc_bus = temp_ddc; 1536 1536 + intel_sdvo->ddc_bus = temp_ddc; 1461 1537 break; 1462 1538 } 1463 1539 temp_ddc >>= 1; 1464 1540 } 1465 1541 if (edid == NULL) 1466 1466 - sdvo_priv->ddc_bus = saved_ddc; 1542 1542 + intel_sdvo->ddc_bus = saved_ddc; 1467 1543 } 1468 1544 /* when there is no edid and no monitor is connected with VGA 1469 1545 * port, try to use the CRT ddc to read the EDID for DVI-connector 1470 1546 */ 1471 1471 - if (edid == NULL && sdvo_priv->analog_ddc_bus && 1547 1547 + if (edid == NULL && intel_sdvo->analog_ddc_bus && 1472 1548 !intel_analog_is_connected(connector->dev)) 1473 1473 - edid = drm_get_edid(connector, sdvo_priv->analog_ddc_bus); 1549 1549 + edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus); 1474 1550 1475 1551 if (edid != NULL) { 1476 1552 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1477 1477 - bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK); 1553 1553 + bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK); 1478 1554 1479 1555 /* DDC bus is shared, match EDID to connector type */ 1480 1556 if (is_digital && need_digital) 1481 1481 - sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid); 1557 1557 + intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); 1482 1558 else if (is_digital != need_digital) 1483 1559 status = connector_status_disconnected; 1484 1560 ··· 1492 1572 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) 1493 1573 { 1494 1574 uint16_t response; 1495 1495 - u8 status; 1496 1575 struct drm_encoder *encoder = intel_attached_encoder(connector); 1497 1497 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1498 1498 - struct intel_connector *intel_connector = to_intel_connector(connector); 1499 1499 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1500 1500 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 1576 1576 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1577 1577 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1501 1578 enum drm_connector_status ret; 1502 1579 1503 1503 - intel_sdvo_write_cmd(intel_encoder, 1504 1504 - SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); 1505 1505 - if (sdvo_priv->is_tv) { 1580 1580 + if (!intel_sdvo_write_cmd(intel_sdvo, 1581 1581 + SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1582 1582 + return connector_status_unknown; 1583 1583 + if (intel_sdvo->is_tv) { 1506 1584 /* add 30ms delay when the output type is SDVO-TV */ 1507 1585 mdelay(30); 1508 1586 } 1509 1509 - status = intel_sdvo_read_response(intel_encoder, &response, 2); 1587 1587 + if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) 1588 1588 + return connector_status_unknown; 1510 1589 1511 1590 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); 1512 1512 - 1513 1513 - if (status != SDVO_CMD_STATUS_SUCCESS) 1514 1514 - return connector_status_unknown; 1515 1591 1516 1592 if (response == 0) 1517 1593 return connector_status_disconnected; 1518 1594 1519 1519 - sdvo_priv->attached_output = response; 1595 1595 + intel_sdvo->attached_output = response; 1520 1596 1521 1521 - if ((sdvo_connector->output_flag & response) == 0) 1597 1597 + if ((intel_sdvo_connector->output_flag & response) == 0) 1522 1598 ret = connector_status_disconnected; 1523 1599 else if (response & SDVO_TMDS_MASK) 1524 1600 ret = intel_sdvo_hdmi_sink_detect(connector); ··· 1523 1607 1524 1608 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1525 1609 if (ret == connector_status_connected) { 1526 1526 - sdvo_priv->is_tv = false; 1527 1527 - sdvo_priv->is_lvds = false; 1528 1528 - intel_encoder->needs_tv_clock = false; 1610 1610 + intel_sdvo->is_tv = false; 1611 1611 + intel_sdvo->is_lvds = false; 1612 1612 + intel_sdvo->base.needs_tv_clock = false; 1529 1613 1530 1614 if (response & SDVO_TV_MASK) { 1531 1531 - sdvo_priv->is_tv = true; 1532 1532 - intel_encoder->needs_tv_clock = true; 1615 1615 + intel_sdvo->is_tv = true; 1616 1616 + intel_sdvo->base.needs_tv_clock = true; 1533 1617 } 1534 1618 if (response & SDVO_LVDS_MASK) 1535 1535 - sdvo_priv->is_lvds = true; 1619 1619 + intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1536 1620 } 1537 1621 1538 1622 return ret; ··· 1541 1625 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1542 1626 { 1543 1627 struct drm_encoder *encoder = intel_attached_encoder(connector); 1544 1544 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1545 1545 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1628 1628 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1546 1629 int num_modes; 1547 1630 1548 1631 /* set the bus switch and get the modes */ 1549 1549 - num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1632 1632 + num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); 1550 1633 1551 1634 /* 1552 1635 * Mac mini hack. On this device, the DVI-I connector shares one DDC ··· 1554 1639 * which case we'll look there for the digital DDC data. 1555 1640 */ 1556 1641 if (num_modes == 0 && 1557 1557 - sdvo_priv->analog_ddc_bus && 1642 1642 + intel_sdvo->analog_ddc_bus && 1558 1643 !intel_analog_is_connected(connector->dev)) { 1559 1644 /* Switch to the analog ddc bus and try that 1560 1645 */ 1561 1561 - (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus); 1646 1646 + (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus); 1562 1647 } 1563 1648 } 1564 1649 ··· 1630 1715 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1631 1716 { 1632 1717 struct drm_encoder *encoder = intel_attached_encoder(connector); 1633 1633 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1634 1634 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1718 1718 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1635 1719 struct intel_sdvo_sdtv_resolution_request tv_res; 1636 1720 uint32_t reply = 0, format_map = 0; 1637 1721 int i; 1638 1638 - uint8_t status; 1639 1639 - 1640 1722 1641 1723 /* Read the list of supported input resolutions for the selected TV 1642 1724 * format. 1643 1725 */ 1644 1644 - for (i = 0; i < TV_FORMAT_NUM; i++) 1645 1645 - if (tv_format_names[i] == sdvo_priv->tv_format_name) 1646 1646 - break; 1647 1647 - 1648 1648 - format_map = (1 << i); 1726 1726 + format_map = 1 << intel_sdvo->tv_format_index; 1649 1727 memcpy(&tv_res, &format_map, 1650 1650 - sizeof(struct intel_sdvo_sdtv_resolution_request) > 1651 1651 - sizeof(format_map) ? sizeof(format_map) : 1652 1652 - sizeof(struct intel_sdvo_sdtv_resolution_request)); 1728 1728 + min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1653 1729 1654 1654 - intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output); 1730 1730 + if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1731 1731 + return; 1655 1732 1656 1656 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1657 1657 - &tv_res, sizeof(tv_res)); 1658 1658 - status = intel_sdvo_read_response(intel_encoder, &reply, 3); 1659 1659 - if (status != SDVO_CMD_STATUS_SUCCESS) 1733 1733 + BUILD_BUG_ON(sizeof(tv_res) != 3); 1734 1734 + if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1735 1735 + &tv_res, sizeof(tv_res))) 1736 1736 + return; 1737 1737 + if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1660 1738 return; 1661 1739 1662 1740 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1663 1741 if (reply & (1 << i)) { 1664 1742 struct drm_display_mode *nmode; 1665 1743 nmode = drm_mode_duplicate(connector->dev, 1666 1666 - &sdvo_tv_modes[i]); 1744 1744 + &sdvo_tv_modes[i]); 1667 1745 if (nmode) 1668 1746 drm_mode_probed_add(connector, nmode); 1669 1747 } 1670 1670 - 1671 1748 } 1672 1749 1673 1750 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1674 1751 { 1675 1752 struct drm_encoder *encoder = intel_attached_encoder(connector); 1676 1676 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1753 1753 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1677 1754 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1678 1678 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1679 1755 struct drm_display_mode *newmode; 1680 1756 1681 1757 /* ··· 1674 1768 * Assume that the preferred modes are 1675 1769 * arranged in priority order. 1676 1770 */ 1677 1677 - intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1771 1771 + intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); 1678 1772 if (list_empty(&connector->probed_modes) == false) 1679 1773 goto end; 1680 1774 ··· 1693 1787 end: 1694 1788 list_for_each_entry(newmode, &connector->probed_modes, head) { 1695 1789 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1696 1696 - sdvo_priv->sdvo_lvds_fixed_mode = 1790 1790 + intel_sdvo->sdvo_lvds_fixed_mode = 1697 1791 drm_mode_duplicate(connector->dev, newmode); 1792 1792 + intel_sdvo->is_lvds = true; 1698 1793 break; 1699 1794 } 1700 1795 } ··· 1704 1797 1705 1798 static int intel_sdvo_get_modes(struct drm_connector *connector) 1706 1799 { 1707 1707 - struct intel_connector *intel_connector = to_intel_connector(connector); 1708 1708 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 1800 1800 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1709 1801 1710 1710 - if (IS_TV(sdvo_connector)) 1802 1802 + if (IS_TV(intel_sdvo_connector)) 1711 1803 intel_sdvo_get_tv_modes(connector); 1712 1712 - else if (IS_LVDS(sdvo_connector)) 1804 1804 + else if (IS_LVDS(intel_sdvo_connector)) 1713 1805 intel_sdvo_get_lvds_modes(connector); 1714 1806 else 1715 1807 intel_sdvo_get_ddc_modes(connector); 1716 1808 1717 1717 - if (list_empty(&connector->probed_modes)) 1718 1718 - return 0; 1719 1719 - return 1; 1809 1809 + return !list_empty(&connector->probed_modes); 1720 1810 } 1721 1811 1722 1722 - static 1723 1723 - void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1812 1812 + static void 1813 1813 + intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1724 1814 { 1725 1725 - struct intel_connector *intel_connector = to_intel_connector(connector); 1726 1726 - struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv; 1815 1815 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1727 1816 struct drm_device *dev = connector->dev; 1728 1817 1729 1729 - if (IS_TV(sdvo_priv)) { 1730 1730 - if (sdvo_priv->left_property) 1731 1731 - drm_property_destroy(dev, sdvo_priv->left_property); 1732 1732 - if (sdvo_priv->right_property) 1733 1733 - drm_property_destroy(dev, sdvo_priv->right_property); 1734 1734 - if (sdvo_priv->top_property) 1735 1735 - drm_property_destroy(dev, sdvo_priv->top_property); 1736 1736 - if (sdvo_priv->bottom_property) 1737 1737 - drm_property_destroy(dev, sdvo_priv->bottom_property); 1738 1738 - if (sdvo_priv->hpos_property) 1739 1739 - drm_property_destroy(dev, sdvo_priv->hpos_property); 1740 1740 - if (sdvo_priv->vpos_property) 1741 1741 - drm_property_destroy(dev, sdvo_priv->vpos_property); 1742 1742 - if (sdvo_priv->saturation_property) 1743 1743 - drm_property_destroy(dev, 1744 1744 - sdvo_priv->saturation_property); 1745 1745 - if (sdvo_priv->contrast_property) 1746 1746 - drm_property_destroy(dev, 1747 1747 - sdvo_priv->contrast_property); 1748 1748 - if (sdvo_priv->hue_property) 1749 1749 - drm_property_destroy(dev, sdvo_priv->hue_property); 1750 1750 - } 1751 1751 - if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { 1752 1752 - if (sdvo_priv->brightness_property) 1753 1753 - drm_property_destroy(dev, 1754 1754 - sdvo_priv->brightness_property); 1755 1755 - } 1756 1756 - return; 1818 1818 + if (intel_sdvo_connector->left) 1819 1819 + drm_property_destroy(dev, intel_sdvo_connector->left); 1820 1820 + if (intel_sdvo_connector->right) 1821 1821 + drm_property_destroy(dev, intel_sdvo_connector->right); 1822 1822 + if (intel_sdvo_connector->top) 1823 1823 + drm_property_destroy(dev, intel_sdvo_connector->top); 1824 1824 + if (intel_sdvo_connector->bottom) 1825 1825 + drm_property_destroy(dev, intel_sdvo_connector->bottom); 1826 1826 + if (intel_sdvo_connector->hpos) 1827 1827 + drm_property_destroy(dev, intel_sdvo_connector->hpos); 1828 1828 + if (intel_sdvo_connector->vpos) 1829 1829 + drm_property_destroy(dev, intel_sdvo_connector->vpos); 1830 1830 + if (intel_sdvo_connector->saturation) 1831 1831 + drm_property_destroy(dev, intel_sdvo_connector->saturation); 1832 1832 + if (intel_sdvo_connector->contrast) 1833 1833 + drm_property_destroy(dev, intel_sdvo_connector->contrast); 1834 1834 + if (intel_sdvo_connector->hue) 1835 1835 + drm_property_destroy(dev, intel_sdvo_connector->hue); 1836 1836 + if (intel_sdvo_connector->sharpness) 1837 1837 + drm_property_destroy(dev, intel_sdvo_connector->sharpness); 1838 1838 + if (intel_sdvo_connector->flicker_filter) 1839 1839 + drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); 1840 1840 + if (intel_sdvo_connector->flicker_filter_2d) 1841 1841 + drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); 1842 1842 + if (intel_sdvo_connector->flicker_filter_adaptive) 1843 1843 + drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); 1844 1844 + if (intel_sdvo_connector->tv_luma_filter) 1845 1845 + drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); 1846 1846 + if (intel_sdvo_connector->tv_chroma_filter) 1847 1847 + drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); 1848 1848 + if (intel_sdvo_connector->dot_crawl) 1849 1849 + drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); 1850 1850 + if (intel_sdvo_connector->brightness) 1851 1851 + drm_property_destroy(dev, intel_sdvo_connector->brightness); 1757 1852 } 1758 1853 1759 1854 static void intel_sdvo_destroy(struct drm_connector *connector) 1760 1855 { 1761 1761 - struct intel_connector *intel_connector = to_intel_connector(connector); 1762 1762 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 1856 1856 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1763 1857 1764 1764 - if (sdvo_connector->tv_format_property) 1858 1858 + if (intel_sdvo_connector->tv_format) 1765 1859 drm_property_destroy(connector->dev, 1766 1766 - sdvo_connector->tv_format_property); 1860 1860 + intel_sdvo_connector->tv_format); 1767 1861 1768 1862 intel_sdvo_destroy_enhance_property(connector); 1769 1863 drm_sysfs_connector_remove(connector); ··· 1778 1870 uint64_t val) 1779 1871 { 1780 1872 struct drm_encoder *encoder = intel_attached_encoder(connector); 1781 1781 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1782 1782 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1783 1783 - struct intel_connector *intel_connector = to_intel_connector(connector); 1784 1784 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 1785 1785 - struct drm_crtc *crtc = encoder->crtc; 1786 1786 - int ret = 0; 1787 1787 - bool changed = false; 1788 1788 - uint8_t cmd, status; 1873 1873 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1874 1874 + struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1789 1875 uint16_t temp_value; 1876 1876 + uint8_t cmd; 1877 1877 + int ret; 1790 1878 1791 1879 ret = drm_connector_property_set_value(connector, property, val); 1792 1792 - if (ret < 0) 1793 1793 - goto out; 1880 1880 + if (ret) 1881 1881 + return ret; 1794 1882 1795 1795 - if (property == sdvo_connector->tv_format_property) { 1796 1796 - if (val >= TV_FORMAT_NUM) { 1797 1797 - ret = -EINVAL; 1798 1798 - goto out; 1799 1799 - } 1800 1800 - if (sdvo_priv->tv_format_name == 1801 1801 - sdvo_connector->tv_format_supported[val]) 1802 1802 - goto out; 1803 1803 - 1804 1804 - sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val]; 1805 1805 - changed = true; 1883 1883 + #define CHECK_PROPERTY(name, NAME) \ 1884 1884 + if (intel_sdvo_connector->name == property) { \ 1885 1885 + if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 1886 1886 + if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 1887 1887 + cmd = SDVO_CMD_SET_##NAME; \ 1888 1888 + intel_sdvo_connector->cur_##name = temp_value; \ 1889 1889 + goto set_value; \ 1806 1890 } 1807 1891 1808 1808 - if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) { 1809 1809 - cmd = 0; 1892 1892 + if (property == intel_sdvo_connector->tv_format) { 1893 1893 + if (val >= TV_FORMAT_NUM) 1894 1894 + return -EINVAL; 1895 1895 + 1896 1896 + if (intel_sdvo->tv_format_index == 1897 1897 + intel_sdvo_connector->tv_format_supported[val]) 1898 1898 + return 0; 1899 1899 + 1900 1900 + intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 1901 1901 + goto done; 1902 1902 + } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 1810 1903 temp_value = val; 1811 1811 - if (sdvo_connector->left_property == property) { 1904 1904 + if (intel_sdvo_connector->left == property) { 1812 1905 drm_connector_property_set_value(connector, 1813 1813 - sdvo_connector->right_property, val); 1814 1814 - if (sdvo_connector->left_margin == temp_value) 1815 1815 - goto out; 1906 1906 + intel_sdvo_connector->right, val); 1907 1907 + if (intel_sdvo_connector->left_margin == temp_value) 1908 1908 + return 0; 1816 1909 1817 1817 - sdvo_connector->left_margin = temp_value; 1818 1818 - sdvo_connector->right_margin = temp_value; 1819 1819 - temp_value = sdvo_connector->max_hscan - 1820 1820 - sdvo_connector->left_margin; 1910 1910 + intel_sdvo_connector->left_margin = temp_value; 1911 1911 + intel_sdvo_connector->right_margin = temp_value; 1912 1912 + temp_value = intel_sdvo_connector->max_hscan - 1913 1913 + intel_sdvo_connector->left_margin; 1821 1914 cmd = SDVO_CMD_SET_OVERSCAN_H; 1822 1822 - } else if (sdvo_connector->right_property == property) { 1915 1915 + goto set_value; 1916 1916 + } else if (intel_sdvo_connector->right == property) { 1823 1917 drm_connector_property_set_value(connector, 1824 1824 - sdvo_connector->left_property, val); 1825 1825 - if (sdvo_connector->right_margin == temp_value) 1826 1826 - goto out; 1918 1918 + intel_sdvo_connector->left, val); 1919 1919 + if (intel_sdvo_connector->right_margin == temp_value) 1920 1920 + return 0; 1827 1921 1828 1828 - sdvo_connector->left_margin = temp_value; 1829 1829 - sdvo_connector->right_margin = temp_value; 1830 1830 - temp_value = sdvo_connector->max_hscan - 1831 1831 - sdvo_connector->left_margin; 1922 1922 + intel_sdvo_connector->left_margin = temp_value; 1923 1923 + intel_sdvo_connector->right_margin = temp_value; 1924 1924 + temp_value = intel_sdvo_connector->max_hscan - 1925 1925 + intel_sdvo_connector->left_margin; 1832 1926 cmd = SDVO_CMD_SET_OVERSCAN_H; 1833 1833 - } else if (sdvo_connector->top_property == property) { 1927 1927 + goto set_value; 1928 1928 + } else if (intel_sdvo_connector->top == property) { 1834 1929 drm_connector_property_set_value(connector, 1835 1835 - sdvo_connector->bottom_property, val); 1836 1836 - if (sdvo_connector->top_margin == temp_value) 1837 1837 - goto out; 1930 1930 + intel_sdvo_connector->bottom, val); 1931 1931 + if (intel_sdvo_connector->top_margin == temp_value) 1932 1932 + return 0; 1838 1933 1839 1839 - sdvo_connector->top_margin = temp_value; 1840 1840 - sdvo_connector->bottom_margin = temp_value; 1841 1841 - temp_value = sdvo_connector->max_vscan - 1842 1842 - sdvo_connector->top_margin; 1934 1934 + intel_sdvo_connector->top_margin = temp_value; 1935 1935 + intel_sdvo_connector->bottom_margin = temp_value; 1936 1936 + temp_value = intel_sdvo_connector->max_vscan - 1937 1937 + intel_sdvo_connector->top_margin; 1843 1938 cmd = SDVO_CMD_SET_OVERSCAN_V; 1844 1844 - } else if (sdvo_connector->bottom_property == property) { 1939 1939 + goto set_value; 1940 1940 + } else if (intel_sdvo_connector->bottom == property) { 1845 1941 drm_connector_property_set_value(connector, 1846 1846 - sdvo_connector->top_property, val); 1847 1847 - if (sdvo_connector->bottom_margin == temp_value) 1848 1848 - goto out; 1849 1849 - sdvo_connector->top_margin = temp_value; 1850 1850 - sdvo_connector->bottom_margin = temp_value; 1851 1851 - temp_value = sdvo_connector->max_vscan - 1852 1852 - sdvo_connector->top_margin; 1942 1942 + intel_sdvo_connector->top, val); 1943 1943 + if (intel_sdvo_connector->bottom_margin == temp_value) 1944 1944 + return 0; 1945 1945 + 1946 1946 + intel_sdvo_connector->top_margin = temp_value; 1947 1947 + intel_sdvo_connector->bottom_margin = temp_value; 1948 1948 + temp_value = intel_sdvo_connector->max_vscan - 1949 1949 + intel_sdvo_connector->top_margin; 1853 1950 cmd = SDVO_CMD_SET_OVERSCAN_V; 1854 1854 - } else if (sdvo_connector->hpos_property == property) { 1855 1855 - if (sdvo_connector->cur_hpos == temp_value) 1856 1856 - goto out; 1857 1857 - 1858 1858 - cmd = SDVO_CMD_SET_POSITION_H; 1859 1859 - sdvo_connector->cur_hpos = temp_value; 1860 1860 - } else if (sdvo_connector->vpos_property == property) { 1861 1861 - if (sdvo_connector->cur_vpos == temp_value) 1862 1862 - goto out; 1863 1863 - 1864 1864 - cmd = SDVO_CMD_SET_POSITION_V; 1865 1865 - sdvo_connector->cur_vpos = temp_value; 1866 1866 - } else if (sdvo_connector->saturation_property == property) { 1867 1867 - if (sdvo_connector->cur_saturation == temp_value) 1868 1868 - goto out; 1869 1869 - 1870 1870 - cmd = SDVO_CMD_SET_SATURATION; 1871 1871 - sdvo_connector->cur_saturation = temp_value; 1872 1872 - } else if (sdvo_connector->contrast_property == property) { 1873 1873 - if (sdvo_connector->cur_contrast == temp_value) 1874 1874 - goto out; 1875 1875 - 1876 1876 - cmd = SDVO_CMD_SET_CONTRAST; 1877 1877 - sdvo_connector->cur_contrast = temp_value; 1878 1878 - } else if (sdvo_connector->hue_property == property) { 1879 1879 - if (sdvo_connector->cur_hue == temp_value) 1880 1880 - goto out; 1881 1881 - 1882 1882 - cmd = SDVO_CMD_SET_HUE; 1883 1883 - sdvo_connector->cur_hue = temp_value; 1884 1884 - } else if (sdvo_connector->brightness_property == property) { 1885 1885 - if (sdvo_connector->cur_brightness == temp_value) 1886 1886 - goto out; 1887 1887 - 1888 1888 - cmd = SDVO_CMD_SET_BRIGHTNESS; 1889 1889 - sdvo_connector->cur_brightness = temp_value; 1951 1951 + goto set_value; 1890 1952 } 1891 1891 - if (cmd) { 1892 1892 - intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2); 1893 1893 - status = intel_sdvo_read_response(intel_encoder, 1894 1894 - NULL, 0); 1895 1895 - if (status != SDVO_CMD_STATUS_SUCCESS) { 1896 1896 - DRM_DEBUG_KMS("Incorrect SDVO command \n"); 1897 1897 - return -EINVAL; 1898 1898 - } 1899 1899 - changed = true; 1900 1900 - } 1953 1953 + CHECK_PROPERTY(hpos, HPOS) 1954 1954 + CHECK_PROPERTY(vpos, VPOS) 1955 1955 + CHECK_PROPERTY(saturation, SATURATION) 1956 1956 + CHECK_PROPERTY(contrast, CONTRAST) 1957 1957 + CHECK_PROPERTY(hue, HUE) 1958 1958 + CHECK_PROPERTY(brightness, BRIGHTNESS) 1959 1959 + CHECK_PROPERTY(sharpness, SHARPNESS) 1960 1960 + CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 1961 1961 + CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 1962 1962 + CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 1963 1963 + CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 1964 1964 + CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 1965 1965 + CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 1901 1966 } 1902 1902 - if (changed && crtc) 1967 1967 + 1968 1968 + return -EINVAL; /* unknown property */ 1969 1969 + 1970 1970 + set_value: 1971 1971 + if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 1972 1972 + return -EIO; 1973 1973 + 1974 1974 + 1975 1975 + done: 1976 1976 + if (encoder->crtc) { 1977 1977 + struct drm_crtc *crtc = encoder->crtc; 1978 1978 + 1903 1979 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, 1904 1904 - crtc->y, crtc->fb); 1905 1905 - out: 1906 1906 - return ret; 1980 1980 + crtc->y, crtc->fb); 1981 1981 + } 1982 1982 + 1983 1983 + return 0; 1984 1984 + #undef CHECK_PROPERTY 1907 1985 } 1908 1986 1909 1987 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { ··· 1916 2022 1917 2023 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1918 2024 { 1919 1919 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1920 1920 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2025 2025 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1921 2026 1922 1922 - if (intel_encoder->i2c_bus) 1923 1923 - intel_i2c_destroy(intel_encoder->i2c_bus); 1924 1924 - if (intel_encoder->ddc_bus) 1925 1925 - intel_i2c_destroy(intel_encoder->ddc_bus); 1926 1926 - if (sdvo_priv->analog_ddc_bus) 1927 1927 - intel_i2c_destroy(sdvo_priv->analog_ddc_bus); 2027 2027 + if (intel_sdvo->analog_ddc_bus) 2028 2028 + intel_i2c_destroy(intel_sdvo->analog_ddc_bus); 1928 2029 1929 1929 - if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) 2030 2030 + if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 1930 2031 drm_mode_destroy(encoder->dev, 1931 1931 - sdvo_priv->sdvo_lvds_fixed_mode); 2032 2032 + intel_sdvo->sdvo_lvds_fixed_mode); 1932 2033 1933 1933 - drm_encoder_cleanup(encoder); 1934 1934 - kfree(intel_encoder); 2034 2034 + intel_encoder_destroy(encoder); 1935 2035 } 1936 2036 1937 2037 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { ··· 1942 2054 */ 1943 2055 static void 1944 2056 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 1945 1945 - struct intel_sdvo_priv *sdvo, u32 reg) 2057 2057 + struct intel_sdvo *sdvo, u32 reg) 1946 2058 { 1947 2059 struct sdvo_device_mapping *mapping; 1948 2060 ··· 1955 2067 } 1956 2068 1957 2069 static bool 1958 1958 - intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device) 2070 2070 + intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) 1959 2071 { 1960 1960 - struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1961 1961 - uint8_t status; 1962 1962 - 1963 1963 - if (device == 0) 1964 1964 - intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0); 1965 1965 - else 1966 1966 - intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1); 1967 1967 - 1968 1968 - intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0); 1969 1969 - status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1); 1970 1970 - if (status != SDVO_CMD_STATUS_SUCCESS) 1971 1971 - return false; 1972 1972 - return true; 2072 2072 + return intel_sdvo_set_target_output(intel_sdvo, 2073 2073 + device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) && 2074 2074 + intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 2075 2075 + &intel_sdvo->is_hdmi, 1); 1973 2076 } 1974 2077 1975 1975 - static struct intel_encoder * 1976 1976 - intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan) 2078 2078 + static struct intel_sdvo * 2079 2079 + intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan) 1977 2080 { 1978 2081 struct drm_device *dev = chan->drm_dev; 1979 2082 struct drm_encoder *encoder; 1980 1980 - struct intel_encoder *intel_encoder = NULL; 1981 2083 1982 2084 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1983 1983 - intel_encoder = enc_to_intel_encoder(encoder); 1984 1984 - if (intel_encoder->ddc_bus == &chan->adapter) 1985 1985 - break; 2085 2085 + struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 2086 2086 + if (intel_sdvo->base.ddc_bus == &chan->adapter) 2087 2087 + return intel_sdvo; 1986 2088 } 1987 1987 - return intel_encoder; 2089 2089 + 2090 2090 + return NULL; 1988 2091 } 1989 2092 1990 2093 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, 1991 2094 struct i2c_msg msgs[], int num) 1992 2095 { 1993 1993 - struct intel_encoder *intel_encoder; 1994 1994 - struct intel_sdvo_priv *sdvo_priv; 2096 2096 + struct intel_sdvo *intel_sdvo; 1995 2097 struct i2c_algo_bit_data *algo_data; 1996 2098 const struct i2c_algorithm *algo; 1997 2099 1998 2100 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; 1999 1999 - intel_encoder = 2000 2000 - intel_sdvo_chan_to_intel_encoder( 2001 2001 - (struct intel_i2c_chan *)(algo_data->data)); 2002 2002 - if (intel_encoder == NULL) 2101 2101 + intel_sdvo = 2102 2102 + intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *) 2103 2103 + (algo_data->data)); 2104 2104 + if (intel_sdvo == NULL) 2003 2105 return -EINVAL; 2004 2106 2005 2005 - sdvo_priv = intel_encoder->dev_priv; 2006 2006 - algo = intel_encoder->i2c_bus->algo; 2107 2107 + algo = intel_sdvo->base.i2c_bus->algo; 2007 2108 2008 2008 - intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus); 2109 2109 + intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus); 2009 2110 return algo->master_xfer(i2c_adap, msgs, num); 2010 2111 } 2011 2112 ··· 2039 2162 return 0x72; 2040 2163 } 2041 2164 2042 2042 - static bool 2043 2043 - intel_sdvo_connector_alloc (struct intel_connector **ret) 2044 2044 - { 2045 2045 - struct intel_connector *intel_connector; 2046 2046 - struct intel_sdvo_connector *sdvo_connector; 2047 2047 - 2048 2048 - *ret = kzalloc(sizeof(*intel_connector) + 2049 2049 - sizeof(*sdvo_connector), GFP_KERNEL); 2050 2050 - if (!*ret) 2051 2051 - return false; 2052 2052 - 2053 2053 - intel_connector = *ret; 2054 2054 - sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1); 2055 2055 - intel_connector->dev_priv = sdvo_connector; 2056 2056 - 2057 2057 - return true; 2058 2058 - } 2059 2059 - 2060 2165 static void 2061 2061 - intel_sdvo_connector_create (struct drm_encoder *encoder, 2062 2062 - struct drm_connector *connector) 2166 2166 + intel_sdvo_connector_init(struct drm_encoder *encoder, 2167 2167 + struct drm_connector *connector) 2063 2168 { 2064 2169 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, 2065 2170 connector->connector_type); ··· 2057 2198 } 2058 2199 2059 2200 static bool 2060 2060 - intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device) 2201 2201 + intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2061 2202 { 2062 2062 - struct drm_encoder *encoder = &intel_encoder->enc; 2063 2063 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2203 2203 + struct drm_encoder *encoder = &intel_sdvo->base.enc; 2064 2204 struct drm_connector *connector; 2065 2205 struct intel_connector *intel_connector; 2066 2066 - struct intel_sdvo_connector *sdvo_connector; 2206 2206 + struct intel_sdvo_connector *intel_sdvo_connector; 2067 2207 2068 2068 - if (!intel_sdvo_connector_alloc(&intel_connector)) 2208 2208 + intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2209 2209 + if (!intel_sdvo_connector) 2069 2210 return false; 2070 2211 2071 2071 - sdvo_connector = intel_connector->dev_priv; 2072 2072 - 2073 2212 if (device == 0) { 2074 2074 - sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0; 2075 2075 - sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2213 2213 + intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2214 2214 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2076 2215 } else if (device == 1) { 2077 2077 - sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1; 2078 2078 - sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2216 2216 + intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2217 2217 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2079 2218 } 2080 2219 2220 2220 + intel_connector = &intel_sdvo_connector->base; 2081 2221 connector = &intel_connector->base; 2082 2222 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2083 2223 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2084 2224 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2085 2225 2086 2086 - if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode) 2087 2087 - && intel_sdvo_get_digital_encoding_mode(intel_encoder, device) 2088 2088 - && sdvo_priv->is_hdmi) { 2226 2226 + if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) 2227 2227 + && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) 2228 2228 + && intel_sdvo->is_hdmi) { 2089 2229 /* enable hdmi encoding mode if supported */ 2090 2090 - intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI); 2091 2091 - intel_sdvo_set_colorimetry(intel_encoder, 2230 2230 + intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 2231 2231 + intel_sdvo_set_colorimetry(intel_sdvo, 2092 2232 SDVO_COLORIMETRY_RGB256); 2093 2233 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2094 2234 } 2095 2095 - intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2096 2096 - (1 << INTEL_ANALOG_CLONE_BIT); 2235 2235 + intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2236 2236 + (1 << INTEL_ANALOG_CLONE_BIT)); 2097 2237 2098 2098 - intel_sdvo_connector_create(encoder, connector); 2238 2238 + intel_sdvo_connector_init(encoder, connector); 2099 2239 2100 2240 return true; 2101 2241 } 2102 2242 2103 2243 static bool 2104 2104 - intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type) 2244 2244 + intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2105 2245 { 2106 2106 - struct drm_encoder *encoder = &intel_encoder->enc; 2107 2107 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2246 2246 + struct drm_encoder *encoder = &intel_sdvo->base.enc; 2108 2247 struct drm_connector *connector; 2109 2248 struct intel_connector *intel_connector; 2110 2110 - struct intel_sdvo_connector *sdvo_connector; 2249 2249 + struct intel_sdvo_connector *intel_sdvo_connector; 2111 2250 2112 2112 - if (!intel_sdvo_connector_alloc(&intel_connector)) 2113 2113 - return false; 2251 2251 + intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2252 2252 + if (!intel_sdvo_connector) 2253 2253 + return false; 2114 2254 2255 2255 + intel_connector = &intel_sdvo_connector->base; 2115 2256 connector = &intel_connector->base; 2116 2257 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2117 2258 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2118 2118 - sdvo_connector = intel_connector->dev_priv; 2119 2259 2120 2120 - sdvo_priv->controlled_output |= type; 2121 2121 - sdvo_connector->output_flag = type; 2260 2260 + intel_sdvo->controlled_output |= type; 2261 2261 + intel_sdvo_connector->output_flag = type; 2122 2262 2123 2123 - sdvo_priv->is_tv = true; 2124 2124 - intel_encoder->needs_tv_clock = true; 2125 2125 - intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2263 2263 + intel_sdvo->is_tv = true; 2264 2264 + intel_sdvo->base.needs_tv_clock = true; 2265 2265 + intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2126 2266 2127 2127 - intel_sdvo_connector_create(encoder, connector); 2267 2267 + intel_sdvo_connector_init(encoder, connector); 2128 2268 2129 2129 - intel_sdvo_tv_create_property(connector, type); 2269 2269 + if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2270 2270 + goto err; 2130 2271 2131 2131 - intel_sdvo_create_enhance_property(connector); 2272 2272 + if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2273 2273 + goto err; 2132 2274 2133 2275 return true; 2276 2276 + 2277 2277 + err: 2278 2278 + intel_sdvo_destroy_enhance_property(connector); 2279 2279 + kfree(intel_sdvo_connector); 2280 2280 + return false; 2134 2281 } 2135 2282 2136 2283 static bool 2137 2137 - intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device) 2284 2284 + intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2138 2285 { 2139 2139 - struct drm_encoder *encoder = &intel_encoder->enc; 2140 2140 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2286 2286 + struct drm_encoder *encoder = &intel_sdvo->base.enc; 2141 2287 struct drm_connector *connector; 2142 2288 struct intel_connector *intel_connector; 2143 2143 - struct intel_sdvo_connector *sdvo_connector; 2289 2289 + struct intel_sdvo_connector *intel_sdvo_connector; 2144 2290 2145 2145 - if (!intel_sdvo_connector_alloc(&intel_connector)) 2146 2146 - return false; 2291 2291 + intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2292 2292 + if (!intel_sdvo_connector) 2293 2293 + return false; 2147 2294 2295 2295 + intel_connector = &intel_sdvo_connector->base; 2148 2296 connector = &intel_connector->base; 2149 2297 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2150 2298 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2151 2299 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2152 2152 - sdvo_connector = intel_connector->dev_priv; 2153 2300 2154 2301 if (device == 0) { 2155 2155 - sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0; 2156 2156 - sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2302 2302 + intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2303 2303 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2157 2304 } else if (device == 1) { 2158 2158 - sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1; 2159 2159 - sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2305 2305 + intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2306 2306 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2160 2307 } 2161 2308 2162 2162 - intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2163 2163 - (1 << INTEL_ANALOG_CLONE_BIT); 2309 2309 + intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2310 2310 + (1 << INTEL_ANALOG_CLONE_BIT)); 2164 2311 2165 2165 - intel_sdvo_connector_create(encoder, connector); 2312 2312 + intel_sdvo_connector_init(encoder, connector); 2166 2313 return true; 2167 2314 } 2168 2315 2169 2316 static bool 2170 2170 - intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device) 2317 2317 + intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2171 2318 { 2172 2172 - struct drm_encoder *encoder = &intel_encoder->enc; 2173 2173 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2319 2319 + struct drm_encoder *encoder = &intel_sdvo->base.enc; 2174 2320 struct drm_connector *connector; 2175 2321 struct intel_connector *intel_connector; 2176 2176 - struct intel_sdvo_connector *sdvo_connector; 2322 2322 + struct intel_sdvo_connector *intel_sdvo_connector; 2177 2323 2178 2178 - if (!intel_sdvo_connector_alloc(&intel_connector)) 2179 2179 - return false; 2324 2324 + intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2325 2325 + if (!intel_sdvo_connector) 2326 2326 + return false; 2180 2327 2181 2181 - connector = &intel_connector->base; 2328 2328 + intel_connector = &intel_sdvo_connector->base; 2329 2329 + connector = &intel_connector->base; 2182 2330 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2183 2331 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2184 2184 - sdvo_connector = intel_connector->dev_priv; 2185 2185 - 2186 2186 - sdvo_priv->is_lvds = true; 2187 2332 2188 2333 if (device == 0) { 2189 2189 - sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0; 2190 2190 - sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2334 2334 + intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2335 2335 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2191 2336 } else if (device == 1) { 2192 2192 - sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1; 2193 2193 - sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2337 2337 + intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2338 2338 + intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2194 2339 } 2195 2340 2196 2196 - intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | 2197 2197 - (1 << INTEL_SDVO_LVDS_CLONE_BIT); 2341 2341 + intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | 2342 2342 + (1 << INTEL_SDVO_LVDS_CLONE_BIT)); 2198 2343 2199 2199 - intel_sdvo_connector_create(encoder, connector); 2200 2200 - intel_sdvo_create_enhance_property(connector); 2201 2201 - return true; 2344 2344 + intel_sdvo_connector_init(encoder, connector); 2345 2345 + if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2346 2346 + goto err; 2347 2347 + 2348 2348 + return true; 2349 2349 + 2350 2350 + err: 2351 2351 + intel_sdvo_destroy_enhance_property(connector); 2352 2352 + kfree(intel_sdvo_connector); 2353 2353 + return false; 2202 2354 } 2203 2355 2204 2356 static bool 2205 2205 - intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags) 2357 2357 + intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2206 2358 { 2207 2207 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2208 2208 - 2209 2209 - sdvo_priv->is_tv = false; 2210 2210 - intel_encoder->needs_tv_clock = false; 2211 2211 - sdvo_priv->is_lvds = false; 2359 2359 + intel_sdvo->is_tv = false; 2360 2360 + intel_sdvo->base.needs_tv_clock = false; 2361 2361 + intel_sdvo->is_lvds = false; 2212 2362 2213 2363 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2214 2364 2215 2365 if (flags & SDVO_OUTPUT_TMDS0) 2216 2216 - if (!intel_sdvo_dvi_init(intel_encoder, 0)) 2366 2366 + if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2217 2367 return false; 2218 2368 2219 2369 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2220 2220 - if (!intel_sdvo_dvi_init(intel_encoder, 1)) 2370 2370 + if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2221 2371 return false; 2222 2372 2223 2373 /* TV has no XXX1 function block */ 2224 2374 if (flags & SDVO_OUTPUT_SVID0) 2225 2225 - if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0)) 2375 2375 + if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2226 2376 return false; 2227 2377 2228 2378 if (flags & SDVO_OUTPUT_CVBS0) 2229 2229 - if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0)) 2379 2379 + if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2230 2380 return false; 2231 2381 2232 2382 if (flags & SDVO_OUTPUT_RGB0) 2233 2233 - if (!intel_sdvo_analog_init(intel_encoder, 0)) 2383 2383 + if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2234 2384 return false; 2235 2385 2236 2386 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2237 2237 - if (!intel_sdvo_analog_init(intel_encoder, 1)) 2387 2387 + if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2238 2388 return false; 2239 2389 2240 2390 if (flags & SDVO_OUTPUT_LVDS0) 2241 2241 - if (!intel_sdvo_lvds_init(intel_encoder, 0)) 2391 2391 + if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2242 2392 return false; 2243 2393 2244 2394 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2245 2245 - if (!intel_sdvo_lvds_init(intel_encoder, 1)) 2395 2395 + if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2246 2396 return false; 2247 2397 2248 2398 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2249 2399 unsigned char bytes[2]; 2250 2400 2251 2251 - sdvo_priv->controlled_output = 0; 2252 2252 - memcpy(bytes, &sdvo_priv->caps.output_flags, 2); 2401 2401 + intel_sdvo->controlled_output = 0; 2402 2402 + memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2253 2403 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2254 2254 - SDVO_NAME(sdvo_priv), 2404 2404 + SDVO_NAME(intel_sdvo), 2255 2405 bytes[0], bytes[1]); 2256 2406 return false; 2257 2407 } 2258 2258 - intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2408 2408 + intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); 2259 2409 2260 2410 return true; 2261 2411 } 2262 2412 2263 2263 - static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type) 2413 2413 + static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2414 2414 + struct intel_sdvo_connector *intel_sdvo_connector, 2415 2415 + int type) 2264 2416 { 2265 2265 - struct drm_encoder *encoder = intel_attached_encoder(connector); 2266 2266 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 2267 2267 - struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2268 2268 - struct intel_connector *intel_connector = to_intel_connector(connector); 2269 2269 - struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; 2417 2417 + struct drm_device *dev = intel_sdvo->base.enc.dev; 2270 2418 struct intel_sdvo_tv_format format; 2271 2419 uint32_t format_map, i; 2272 2272 - uint8_t status; 2273 2420 2274 2274 - intel_sdvo_set_target_output(intel_encoder, type); 2421 2421 + if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2422 2422 + return false; 2275 2423 2276 2276 - intel_sdvo_write_cmd(intel_encoder, 2277 2277 - SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); 2278 2278 - status = intel_sdvo_read_response(intel_encoder, 2279 2279 - &format, sizeof(format)); 2280 2280 - if (status != SDVO_CMD_STATUS_SUCCESS) 2281 2281 - return; 2424 2424 + if (!intel_sdvo_get_value(intel_sdvo, 2425 2425 + SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2426 2426 + &format, sizeof(format))) 2427 2427 + return false; 2282 2428 2283 2283 - memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? 2284 2284 - sizeof(format_map) : sizeof(format)); 2429 2429 + memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2285 2430 2286 2431 if (format_map == 0) 2287 2287 - return; 2432 2432 + return false; 2288 2433 2289 2289 - sdvo_connector->format_supported_num = 0; 2434 2434 + intel_sdvo_connector->format_supported_num = 0; 2290 2435 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2291 2291 - if (format_map & (1 << i)) { 2292 2292 - sdvo_connector->tv_format_supported 2293 2293 - [sdvo_connector->format_supported_num++] = 2294 2294 - tv_format_names[i]; 2295 2295 - } 2436 2436 + if (format_map & (1 << i)) 2437 2437 + intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2296 2438 2297 2439 2298 2298 - sdvo_connector->tv_format_property = 2299 2299 - drm_property_create( 2300 2300 - connector->dev, DRM_MODE_PROP_ENUM, 2301 2301 - "mode", sdvo_connector->format_supported_num); 2440 2440 + intel_sdvo_connector->tv_format = 2441 2441 + drm_property_create(dev, DRM_MODE_PROP_ENUM, 2442 2442 + "mode", intel_sdvo_connector->format_supported_num); 2443 2443 + if (!intel_sdvo_connector->tv_format) 2444 2444 + return false; 2302 2445 2303 2303 - for (i = 0; i < sdvo_connector->format_supported_num; i++) 2446 2446 + for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2304 2447 drm_property_add_enum( 2305 2305 - sdvo_connector->tv_format_property, i, 2306 2306 - i, sdvo_connector->tv_format_supported[i]); 2448 2448 + intel_sdvo_connector->tv_format, i, 2449 2449 + i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2307 2450 2308 2308 - sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0]; 2309 2309 - drm_connector_attach_property( 2310 2310 - connector, sdvo_connector->tv_format_property, 0); 2451 2451 + intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2452 2452 + drm_connector_attach_property(&intel_sdvo_connector->base.base, 2453 2453 + intel_sdvo_connector->tv_format, 0); 2454 2454 + return true; 2311 2455 2312 2456 } 2313 2457 2314 2314 - static void intel_sdvo_create_enhance_property(struct drm_connector *connector) 2458 2458 + #define ENHANCEMENT(name, NAME) do { \ 2459 2459 + if (enhancements.name) { \ 2460 2460 + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2461 2461 + !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2462 2462 + return false; \ 2463 2463 + intel_sdvo_connector->max_##name = data_value[0]; \ 2464 2464 + intel_sdvo_connector->cur_##name = response; \ 2465 2465 + intel_sdvo_connector->name = \ 2466 2466 + drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ 2467 2467 + if (!intel_sdvo_connector->name) return false; \ 2468 2468 + intel_sdvo_connector->name->values[0] = 0; \ 2469 2469 + intel_sdvo_connector->name->values[1] = data_value[0]; \ 2470 2470 + drm_connector_attach_property(connector, \ 2471 2471 + intel_sdvo_connector->name, \ 2472 2472 + intel_sdvo_connector->cur_##name); \ 2473 2473 + DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2474 2474 + data_value[0], data_value[1], response); \ 2475 2475 + } \ 2476 2476 + } while(0) 2477 2477 + 2478 2478 + static bool 2479 2479 + intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2480 2480 + struct intel_sdvo_connector *intel_sdvo_connector, 2481 2481 + struct intel_sdvo_enhancements_reply enhancements) 2315 2482 { 2316 2316 - struct drm_encoder *encoder = intel_attached_encoder(connector); 2317 2317 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 2318 2318 - struct intel_connector *intel_connector = to_intel_connector(connector); 2319 2319 - struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv; 2320 2320 - struct intel_sdvo_enhancements_reply sdvo_data; 2321 2321 - struct drm_device *dev = connector->dev; 2322 2322 - uint8_t status; 2483 2483 + struct drm_device *dev = intel_sdvo->base.enc.dev; 2484 2484 + struct drm_connector *connector = &intel_sdvo_connector->base.base; 2323 2485 uint16_t response, data_value[2]; 2324 2486 2325 2325 - intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2326 2326 - NULL, 0); 2327 2327 - status = intel_sdvo_read_response(intel_encoder, &sdvo_data, 2328 2328 - sizeof(sdvo_data)); 2329 2329 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2330 2330 - DRM_DEBUG_KMS(" incorrect response is returned\n"); 2331 2331 - return; 2487 2487 + /* when horizontal overscan is supported, Add the left/right property */ 2488 2488 + if (enhancements.overscan_h) { 2489 2489 + if (!intel_sdvo_get_value(intel_sdvo, 2490 2490 + SDVO_CMD_GET_MAX_OVERSCAN_H, 2491 2491 + &data_value, 4)) 2492 2492 + return false; 2493 2493 + 2494 2494 + if (!intel_sdvo_get_value(intel_sdvo, 2495 2495 + SDVO_CMD_GET_OVERSCAN_H, 2496 2496 + &response, 2)) 2497 2497 + return false; 2498 2498 + 2499 2499 + intel_sdvo_connector->max_hscan = data_value[0]; 2500 2500 + intel_sdvo_connector->left_margin = data_value[0] - response; 2501 2501 + intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2502 2502 + intel_sdvo_connector->left = 2503 2503 + drm_property_create(dev, DRM_MODE_PROP_RANGE, 2504 2504 + "left_margin", 2); 2505 2505 + if (!intel_sdvo_connector->left) 2506 2506 + return false; 2507 2507 + 2508 2508 + intel_sdvo_connector->left->values[0] = 0; 2509 2509 + intel_sdvo_connector->left->values[1] = data_value[0]; 2510 2510 + drm_connector_attach_property(connector, 2511 2511 + intel_sdvo_connector->left, 2512 2512 + intel_sdvo_connector->left_margin); 2513 2513 + 2514 2514 + intel_sdvo_connector->right = 2515 2515 + drm_property_create(dev, DRM_MODE_PROP_RANGE, 2516 2516 + "right_margin", 2); 2517 2517 + if (!intel_sdvo_connector->right) 2518 2518 + return false; 2519 2519 + 2520 2520 + intel_sdvo_connector->right->values[0] = 0; 2521 2521 + intel_sdvo_connector->right->values[1] = data_value[0]; 2522 2522 + drm_connector_attach_property(connector, 2523 2523 + intel_sdvo_connector->right, 2524 2524 + intel_sdvo_connector->right_margin); 2525 2525 + DRM_DEBUG_KMS("h_overscan: max %d, " 2526 2526 + "default %d, current %d\n", 2527 2527 + data_value[0], data_value[1], response); 2332 2528 } 2333 2333 - response = *((uint16_t *)&sdvo_data); 2334 2334 - if (!response) { 2529 2529 + 2530 2530 + if (enhancements.overscan_v) { 2531 2531 + if (!intel_sdvo_get_value(intel_sdvo, 2532 2532 + SDVO_CMD_GET_MAX_OVERSCAN_V, 2533 2533 + &data_value, 4)) 2534 2534 + return false; 2535 2535 + 2536 2536 + if (!intel_sdvo_get_value(intel_sdvo, 2537 2537 + SDVO_CMD_GET_OVERSCAN_V, 2538 2538 + &response, 2)) 2539 2539 + return false; 2540 2540 + 2541 2541 + intel_sdvo_connector->max_vscan = data_value[0]; 2542 2542 + intel_sdvo_connector->top_margin = data_value[0] - response; 2543 2543 + intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2544 2544 + intel_sdvo_connector->top = 2545 2545 + drm_property_create(dev, DRM_MODE_PROP_RANGE, 2546 2546 + "top_margin", 2); 2547 2547 + if (!intel_sdvo_connector->top) 2548 2548 + return false; 2549 2549 + 2550 2550 + intel_sdvo_connector->top->values[0] = 0; 2551 2551 + intel_sdvo_connector->top->values[1] = data_value[0]; 2552 2552 + drm_connector_attach_property(connector, 2553 2553 + intel_sdvo_connector->top, 2554 2554 + intel_sdvo_connector->top_margin); 2555 2555 + 2556 2556 + intel_sdvo_connector->bottom = 2557 2557 + drm_property_create(dev, DRM_MODE_PROP_RANGE, 2558 2558 + "bottom_margin", 2); 2559 2559 + if (!intel_sdvo_connector->bottom) 2560 2560 + return false; 2561 2561 + 2562 2562 + intel_sdvo_connector->bottom->values[0] = 0; 2563 2563 + intel_sdvo_connector->bottom->values[1] = data_value[0]; 2564 2564 + drm_connector_attach_property(connector, 2565 2565 + intel_sdvo_connector->bottom, 2566 2566 + intel_sdvo_connector->bottom_margin); 2567 2567 + DRM_DEBUG_KMS("v_overscan: max %d, " 2568 2568 + "default %d, current %d\n", 2569 2569 + data_value[0], data_value[1], response); 2570 2570 + } 2571 2571 + 2572 2572 + ENHANCEMENT(hpos, HPOS); 2573 2573 + ENHANCEMENT(vpos, VPOS); 2574 2574 + ENHANCEMENT(saturation, SATURATION); 2575 2575 + ENHANCEMENT(contrast, CONTRAST); 2576 2576 + ENHANCEMENT(hue, HUE); 2577 2577 + ENHANCEMENT(sharpness, SHARPNESS); 2578 2578 + ENHANCEMENT(brightness, BRIGHTNESS); 2579 2579 + ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2580 2580 + ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2581 2581 + ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2582 2582 + ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2583 2583 + ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2584 2584 + 2585 2585 + if (enhancements.dot_crawl) { 2586 2586 + if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2587 2587 + return false; 2588 2588 + 2589 2589 + intel_sdvo_connector->max_dot_crawl = 1; 2590 2590 + intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2591 2591 + intel_sdvo_connector->dot_crawl = 2592 2592 + drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); 2593 2593 + if (!intel_sdvo_connector->dot_crawl) 2594 2594 + return false; 2595 2595 + 2596 2596 + intel_sdvo_connector->dot_crawl->values[0] = 0; 2597 2597 + intel_sdvo_connector->dot_crawl->values[1] = 1; 2598 2598 + drm_connector_attach_property(connector, 2599 2599 + intel_sdvo_connector->dot_crawl, 2600 2600 + intel_sdvo_connector->cur_dot_crawl); 2601 2601 + DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2602 2602 + } 2603 2603 + 2604 2604 + return true; 2605 2605 + } 2606 2606 + 2607 2607 + static bool 2608 2608 + intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2609 2609 + struct intel_sdvo_connector *intel_sdvo_connector, 2610 2610 + struct intel_sdvo_enhancements_reply enhancements) 2611 2611 + { 2612 2612 + struct drm_device *dev = intel_sdvo->base.enc.dev; 2613 2613 + struct drm_connector *connector = &intel_sdvo_connector->base.base; 2614 2614 + uint16_t response, data_value[2]; 2615 2615 + 2616 2616 + ENHANCEMENT(brightness, BRIGHTNESS); 2617 2617 + 2618 2618 + return true; 2619 2619 + } 2620 2620 + #undef ENHANCEMENT 2621 2621 + 2622 2622 + static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2623 2623 + struct intel_sdvo_connector *intel_sdvo_connector) 2624 2624 + { 2625 2625 + union { 2626 2626 + struct intel_sdvo_enhancements_reply reply; 2627 2627 + uint16_t response; 2628 2628 + } enhancements; 2629 2629 + 2630 2630 + if (!intel_sdvo_get_value(intel_sdvo, 2631 2631 + SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2632 2632 + &enhancements, sizeof(enhancements))) 2633 2633 + return false; 2634 2634 + 2635 2635 + if (enhancements.response == 0) { 2335 2636 DRM_DEBUG_KMS("No enhancement is supported\n"); 2336 2336 - return; 2637 2637 + return true; 2337 2638 } 2338 2338 - if (IS_TV(sdvo_priv)) { 2339 2339 - /* when horizontal overscan is supported, Add the left/right 2340 2340 - * property 2341 2341 - */ 2342 2342 - if (sdvo_data.overscan_h) { 2343 2343 - intel_sdvo_write_cmd(intel_encoder, 2344 2344 - SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); 2345 2345 - status = intel_sdvo_read_response(intel_encoder, 2346 2346 - &data_value, 4); 2347 2347 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2348 2348 - DRM_DEBUG_KMS("Incorrect SDVO max " 2349 2349 - "h_overscan\n"); 2350 2350 - return; 2351 2351 - } 2352 2352 - intel_sdvo_write_cmd(intel_encoder, 2353 2353 - SDVO_CMD_GET_OVERSCAN_H, NULL, 0); 2354 2354 - status = intel_sdvo_read_response(intel_encoder, 2355 2355 - &response, 2); 2356 2356 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2357 2357 - DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); 2358 2358 - return; 2359 2359 - } 2360 2360 - sdvo_priv->max_hscan = data_value[0]; 2361 2361 - sdvo_priv->left_margin = data_value[0] - response; 2362 2362 - sdvo_priv->right_margin = sdvo_priv->left_margin; 2363 2363 - sdvo_priv->left_property = 2364 2364 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2365 2365 - "left_margin", 2); 2366 2366 - sdvo_priv->left_property->values[0] = 0; 2367 2367 - sdvo_priv->left_property->values[1] = data_value[0]; 2368 2368 - drm_connector_attach_property(connector, 2369 2369 - sdvo_priv->left_property, 2370 2370 - sdvo_priv->left_margin); 2371 2371 - sdvo_priv->right_property = 2372 2372 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2373 2373 - "right_margin", 2); 2374 2374 - sdvo_priv->right_property->values[0] = 0; 2375 2375 - sdvo_priv->right_property->values[1] = data_value[0]; 2376 2376 - drm_connector_attach_property(connector, 2377 2377 - sdvo_priv->right_property, 2378 2378 - sdvo_priv->right_margin); 2379 2379 - DRM_DEBUG_KMS("h_overscan: max %d, " 2380 2380 - "default %d, current %d\n", 2381 2381 - data_value[0], data_value[1], response); 2382 2382 - } 2383 2383 - if (sdvo_data.overscan_v) { 2384 2384 - intel_sdvo_write_cmd(intel_encoder, 2385 2385 - SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0); 2386 2386 - status = intel_sdvo_read_response(intel_encoder, 2387 2387 - &data_value, 4); 2388 2388 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2389 2389 - DRM_DEBUG_KMS("Incorrect SDVO max " 2390 2390 - "v_overscan\n"); 2391 2391 - return; 2392 2392 - } 2393 2393 - intel_sdvo_write_cmd(intel_encoder, 2394 2394 - SDVO_CMD_GET_OVERSCAN_V, NULL, 0); 2395 2395 - status = intel_sdvo_read_response(intel_encoder, 2396 2396 - &response, 2); 2397 2397 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2398 2398 - DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n"); 2399 2399 - return; 2400 2400 - } 2401 2401 - sdvo_priv->max_vscan = data_value[0]; 2402 2402 - sdvo_priv->top_margin = data_value[0] - response; 2403 2403 - sdvo_priv->bottom_margin = sdvo_priv->top_margin; 2404 2404 - sdvo_priv->top_property = 2405 2405 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2406 2406 - "top_margin", 2); 2407 2407 - sdvo_priv->top_property->values[0] = 0; 2408 2408 - sdvo_priv->top_property->values[1] = data_value[0]; 2409 2409 - drm_connector_attach_property(connector, 2410 2410 - sdvo_priv->top_property, 2411 2411 - sdvo_priv->top_margin); 2412 2412 - sdvo_priv->bottom_property = 2413 2413 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2414 2414 - "bottom_margin", 2); 2415 2415 - sdvo_priv->bottom_property->values[0] = 0; 2416 2416 - sdvo_priv->bottom_property->values[1] = data_value[0]; 2417 2417 - drm_connector_attach_property(connector, 2418 2418 - sdvo_priv->bottom_property, 2419 2419 - sdvo_priv->bottom_margin); 2420 2420 - DRM_DEBUG_KMS("v_overscan: max %d, " 2421 2421 - "default %d, current %d\n", 2422 2422 - data_value[0], data_value[1], response); 2423 2423 - } 2424 2424 - if (sdvo_data.position_h) { 2425 2425 - intel_sdvo_write_cmd(intel_encoder, 2426 2426 - SDVO_CMD_GET_MAX_POSITION_H, NULL, 0); 2427 2427 - status = intel_sdvo_read_response(intel_encoder, 2428 2428 - &data_value, 4); 2429 2429 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2430 2430 - DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n"); 2431 2431 - return; 2432 2432 - } 2433 2433 - intel_sdvo_write_cmd(intel_encoder, 2434 2434 - SDVO_CMD_GET_POSITION_H, NULL, 0); 2435 2435 - status = intel_sdvo_read_response(intel_encoder, 2436 2436 - &response, 2); 2437 2437 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2438 2438 - DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n"); 2439 2439 - return; 2440 2440 - } 2441 2441 - sdvo_priv->max_hpos = data_value[0]; 2442 2442 - sdvo_priv->cur_hpos = response; 2443 2443 - sdvo_priv->hpos_property = 2444 2444 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2445 2445 - "hpos", 2); 2446 2446 - sdvo_priv->hpos_property->values[0] = 0; 2447 2447 - sdvo_priv->hpos_property->values[1] = data_value[0]; 2448 2448 - drm_connector_attach_property(connector, 2449 2449 - sdvo_priv->hpos_property, 2450 2450 - sdvo_priv->cur_hpos); 2451 2451 - DRM_DEBUG_KMS("h_position: max %d, " 2452 2452 - "default %d, current %d\n", 2453 2453 - data_value[0], data_value[1], response); 2454 2454 - } 2455 2455 - if (sdvo_data.position_v) { 2456 2456 - intel_sdvo_write_cmd(intel_encoder, 2457 2457 - SDVO_CMD_GET_MAX_POSITION_V, NULL, 0); 2458 2458 - status = intel_sdvo_read_response(intel_encoder, 2459 2459 - &data_value, 4); 2460 2460 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2461 2461 - DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n"); 2462 2462 - return; 2463 2463 - } 2464 2464 - intel_sdvo_write_cmd(intel_encoder, 2465 2465 - SDVO_CMD_GET_POSITION_V, NULL, 0); 2466 2466 - status = intel_sdvo_read_response(intel_encoder, 2467 2467 - &response, 2); 2468 2468 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2469 2469 - DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n"); 2470 2470 - return; 2471 2471 - } 2472 2472 - sdvo_priv->max_vpos = data_value[0]; 2473 2473 - sdvo_priv->cur_vpos = response; 2474 2474 - sdvo_priv->vpos_property = 2475 2475 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2476 2476 - "vpos", 2); 2477 2477 - sdvo_priv->vpos_property->values[0] = 0; 2478 2478 - sdvo_priv->vpos_property->values[1] = data_value[0]; 2479 2479 - drm_connector_attach_property(connector, 2480 2480 - sdvo_priv->vpos_property, 2481 2481 - sdvo_priv->cur_vpos); 2482 2482 - DRM_DEBUG_KMS("v_position: max %d, " 2483 2483 - "default %d, current %d\n", 2484 2484 - data_value[0], data_value[1], response); 2485 2485 - } 2486 2486 - if (sdvo_data.saturation) { 2487 2487 - intel_sdvo_write_cmd(intel_encoder, 2488 2488 - SDVO_CMD_GET_MAX_SATURATION, NULL, 0); 2489 2489 - status = intel_sdvo_read_response(intel_encoder, 2490 2490 - &data_value, 4); 2491 2491 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2492 2492 - DRM_DEBUG_KMS("Incorrect SDVO Max sat\n"); 2493 2493 - return; 2494 2494 - } 2495 2495 - intel_sdvo_write_cmd(intel_encoder, 2496 2496 - SDVO_CMD_GET_SATURATION, NULL, 0); 2497 2497 - status = intel_sdvo_read_response(intel_encoder, 2498 2498 - &response, 2); 2499 2499 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2500 2500 - DRM_DEBUG_KMS("Incorrect SDVO get sat\n"); 2501 2501 - return; 2502 2502 - } 2503 2503 - sdvo_priv->max_saturation = data_value[0]; 2504 2504 - sdvo_priv->cur_saturation = response; 2505 2505 - sdvo_priv->saturation_property = 2506 2506 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2507 2507 - "saturation", 2); 2508 2508 - sdvo_priv->saturation_property->values[0] = 0; 2509 2509 - sdvo_priv->saturation_property->values[1] = 2510 2510 - data_value[0]; 2511 2511 - drm_connector_attach_property(connector, 2512 2512 - sdvo_priv->saturation_property, 2513 2513 - sdvo_priv->cur_saturation); 2514 2514 - DRM_DEBUG_KMS("saturation: max %d, " 2515 2515 - "default %d, current %d\n", 2516 2516 - data_value[0], data_value[1], response); 2517 2517 - } 2518 2518 - if (sdvo_data.contrast) { 2519 2519 - intel_sdvo_write_cmd(intel_encoder, 2520 2520 - SDVO_CMD_GET_MAX_CONTRAST, NULL, 0); 2521 2521 - status = intel_sdvo_read_response(intel_encoder, 2522 2522 - &data_value, 4); 2523 2523 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2524 2524 - DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n"); 2525 2525 - return; 2526 2526 - } 2527 2527 - intel_sdvo_write_cmd(intel_encoder, 2528 2528 - SDVO_CMD_GET_CONTRAST, NULL, 0); 2529 2529 - status = intel_sdvo_read_response(intel_encoder, 2530 2530 - &response, 2); 2531 2531 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2532 2532 - DRM_DEBUG_KMS("Incorrect SDVO get contrast\n"); 2533 2533 - return; 2534 2534 - } 2535 2535 - sdvo_priv->max_contrast = data_value[0]; 2536 2536 - sdvo_priv->cur_contrast = response; 2537 2537 - sdvo_priv->contrast_property = 2538 2538 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2539 2539 - "contrast", 2); 2540 2540 - sdvo_priv->contrast_property->values[0] = 0; 2541 2541 - sdvo_priv->contrast_property->values[1] = data_value[0]; 2542 2542 - drm_connector_attach_property(connector, 2543 2543 - sdvo_priv->contrast_property, 2544 2544 - sdvo_priv->cur_contrast); 2545 2545 - DRM_DEBUG_KMS("contrast: max %d, " 2546 2546 - "default %d, current %d\n", 2547 2547 - data_value[0], data_value[1], response); 2548 2548 - } 2549 2549 - if (sdvo_data.hue) { 2550 2550 - intel_sdvo_write_cmd(intel_encoder, 2551 2551 - SDVO_CMD_GET_MAX_HUE, NULL, 0); 2552 2552 - status = intel_sdvo_read_response(intel_encoder, 2553 2553 - &data_value, 4); 2554 2554 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2555 2555 - DRM_DEBUG_KMS("Incorrect SDVO Max hue\n"); 2556 2556 - return; 2557 2557 - } 2558 2558 - intel_sdvo_write_cmd(intel_encoder, 2559 2559 - SDVO_CMD_GET_HUE, NULL, 0); 2560 2560 - status = intel_sdvo_read_response(intel_encoder, 2561 2561 - &response, 2); 2562 2562 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2563 2563 - DRM_DEBUG_KMS("Incorrect SDVO get hue\n"); 2564 2564 - return; 2565 2565 - } 2566 2566 - sdvo_priv->max_hue = data_value[0]; 2567 2567 - sdvo_priv->cur_hue = response; 2568 2568 - sdvo_priv->hue_property = 2569 2569 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2570 2570 - "hue", 2); 2571 2571 - sdvo_priv->hue_property->values[0] = 0; 2572 2572 - sdvo_priv->hue_property->values[1] = 2573 2573 - data_value[0]; 2574 2574 - drm_connector_attach_property(connector, 2575 2575 - sdvo_priv->hue_property, 2576 2576 - sdvo_priv->cur_hue); 2577 2577 - DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n", 2578 2578 - data_value[0], data_value[1], response); 2579 2579 - } 2580 2580 - } 2581 2581 - if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { 2582 2582 - if (sdvo_data.brightness) { 2583 2583 - intel_sdvo_write_cmd(intel_encoder, 2584 2584 - SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); 2585 2585 - status = intel_sdvo_read_response(intel_encoder, 2586 2586 - &data_value, 4); 2587 2587 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2588 2588 - DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); 2589 2589 - return; 2590 2590 - } 2591 2591 - intel_sdvo_write_cmd(intel_encoder, 2592 2592 - SDVO_CMD_GET_BRIGHTNESS, NULL, 0); 2593 2593 - status = intel_sdvo_read_response(intel_encoder, 2594 2594 - &response, 2); 2595 2595 - if (status != SDVO_CMD_STATUS_SUCCESS) { 2596 2596 - DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); 2597 2597 - return; 2598 2598 - } 2599 2599 - sdvo_priv->max_brightness = data_value[0]; 2600 2600 - sdvo_priv->cur_brightness = response; 2601 2601 - sdvo_priv->brightness_property = 2602 2602 - drm_property_create(dev, DRM_MODE_PROP_RANGE, 2603 2603 - "brightness", 2); 2604 2604 - sdvo_priv->brightness_property->values[0] = 0; 2605 2605 - sdvo_priv->brightness_property->values[1] = 2606 2606 - data_value[0]; 2607 2607 - drm_connector_attach_property(connector, 2608 2608 - sdvo_priv->brightness_property, 2609 2609 - sdvo_priv->cur_brightness); 2610 2610 - DRM_DEBUG_KMS("brightness: max %d, " 2611 2611 - "default %d, current %d\n", 2612 2612 - data_value[0], data_value[1], response); 2613 2613 - } 2614 2614 - } 2615 2615 - return; 2639 2639 + 2640 2640 + if (IS_TV(intel_sdvo_connector)) 2641 2641 + return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2642 2642 + else if(IS_LVDS(intel_sdvo_connector)) 2643 2643 + return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2644 2644 + else 2645 2645 + return true; 2646 2646 + 2616 2647 } 2617 2648 2618 2649 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2619 2650 { 2620 2651 struct drm_i915_private *dev_priv = dev->dev_private; 2621 2652 struct intel_encoder *intel_encoder; 2622 2622 - struct intel_sdvo_priv *sdvo_priv; 2653 2653 + struct intel_sdvo *intel_sdvo; 2623 2654 u8 ch[0x40]; 2624 2655 int i; 2625 2656 u32 i2c_reg, ddc_reg, analog_ddc_reg; 2626 2657 2627 2627 - intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); 2628 2628 - if (!intel_encoder) { 2658 2658 + intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); 2659 2659 + if (!intel_sdvo) 2629 2660 return false; 2630 2630 - } 2631 2661 2632 2632 - sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1); 2633 2633 - sdvo_priv->sdvo_reg = sdvo_reg; 2662 2662 + intel_sdvo->sdvo_reg = sdvo_reg; 2634 2663 2635 2635 - intel_encoder->dev_priv = sdvo_priv; 2664 2664 + intel_encoder = &intel_sdvo->base; 2636 2665 intel_encoder->type = INTEL_OUTPUT_SDVO; 2637 2666 2638 2667 if (HAS_PCH_SPLIT(dev)) { ··· 2542 2795 if (!intel_encoder->i2c_bus) 2543 2796 goto err_inteloutput; 2544 2797 2545 2545 - sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); 2798 2798 + intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); 2546 2799 2547 2800 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2548 2801 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; 2549 2802 2550 2803 /* Read the regs to test if we can talk to the device */ 2551 2804 for (i = 0; i < 0x40; i++) { 2552 2552 - if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) { 2805 2805 + if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) { 2553 2806 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2554 2807 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2555 2808 goto err_i2c; ··· 2559 2812 /* setup the DDC bus. */ 2560 2813 if (IS_SDVOB(sdvo_reg)) { 2561 2814 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS"); 2562 2562 - sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2815 2815 + intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2563 2816 "SDVOB/VGA DDC BUS"); 2564 2817 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2565 2818 } else { 2566 2819 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS"); 2567 2567 - sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2820 2820 + intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2568 2821 "SDVOC/VGA DDC BUS"); 2569 2822 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2570 2823 } 2571 2571 - 2572 2572 - if (intel_encoder->ddc_bus == NULL) 2824 2824 + if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL) 2573 2825 goto err_i2c; 2574 2826 2575 2827 /* Wrap with our custom algo which switches to DDC mode */ ··· 2579 2833 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); 2580 2834 2581 2835 /* In default case sdvo lvds is false */ 2582 2582 - intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps); 2836 2836 + if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2837 2837 + goto err_enc; 2583 2838 2584 2584 - if (intel_sdvo_output_setup(intel_encoder, 2585 2585 - sdvo_priv->caps.output_flags) != true) { 2839 2839 + if (intel_sdvo_output_setup(intel_sdvo, 2840 2840 + intel_sdvo->caps.output_flags) != true) { 2586 2841 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2587 2842 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2588 2588 - goto err_i2c; 2843 2843 + goto err_enc; 2589 2844 } 2590 2845 2591 2591 - intel_sdvo_select_ddc_bus(dev_priv, sdvo_priv, sdvo_reg); 2846 2846 + intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 2592 2847 2593 2848 /* Set the input timing to the screen. Assume always input 0. */ 2594 2594 - intel_sdvo_set_target_input(intel_encoder, true, false); 2849 2849 + if (!intel_sdvo_set_target_input(intel_sdvo)) 2850 2850 + goto err_enc; 2595 2851 2596 2596 - intel_sdvo_get_input_pixel_clock_range(intel_encoder, 2597 2597 - &sdvo_priv->pixel_clock_min, 2598 2598 - &sdvo_priv->pixel_clock_max); 2599 2599 - 2852 2852 + if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 2853 2853 + &intel_sdvo->pixel_clock_min, 2854 2854 + &intel_sdvo->pixel_clock_max)) 2855 2855 + goto err_enc; 2600 2856 2601 2857 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2602 2858 "clock range %dMHz - %dMHz, " 2603 2859 "input 1: %c, input 2: %c, " 2604 2860 "output 1: %c, output 2: %c\n", 2605 2605 - SDVO_NAME(sdvo_priv), 2606 2606 - sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, 2607 2607 - sdvo_priv->caps.device_rev_id, 2608 2608 - sdvo_priv->pixel_clock_min / 1000, 2609 2609 - sdvo_priv->pixel_clock_max / 1000, 2610 2610 - (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2611 2611 - (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2861 2861 + SDVO_NAME(intel_sdvo), 2862 2862 + intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 2863 2863 + intel_sdvo->caps.device_rev_id, 2864 2864 + intel_sdvo->pixel_clock_min / 1000, 2865 2865 + intel_sdvo->pixel_clock_max / 1000, 2866 2866 + (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2867 2867 + (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2612 2868 /* check currently supported outputs */ 2613 2613 - sdvo_priv->caps.output_flags & 2869 2869 + intel_sdvo->caps.output_flags & 2614 2870 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 2615 2615 - sdvo_priv->caps.output_flags & 2871 2871 + intel_sdvo->caps.output_flags & 2616 2872 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2617 2617 - 2618 2873 return true; 2619 2874 2875 2875 + err_enc: 2876 2876 + drm_encoder_cleanup(&intel_encoder->enc); 2620 2877 err_i2c: 2621 2621 - if (sdvo_priv->analog_ddc_bus != NULL) 2622 2622 - intel_i2c_destroy(sdvo_priv->analog_ddc_bus); 2878 2878 + if (intel_sdvo->analog_ddc_bus != NULL) 2879 2879 + intel_i2c_destroy(intel_sdvo->analog_ddc_bus); 2623 2880 if (intel_encoder->ddc_bus != NULL) 2624 2881 intel_i2c_destroy(intel_encoder->ddc_bus); 2625 2882 if (intel_encoder->i2c_bus != NULL) 2626 2883 intel_i2c_destroy(intel_encoder->i2c_bus); 2627 2884 err_inteloutput: 2628 2628 - kfree(intel_encoder); 2885 2885 + kfree(intel_sdvo); 2629 2886 2630 2887 return false; 2631 2888 }

+25 -25

drivers/gpu/drm/i915/intel_sdvo_regs.h

reviewed

··· 312 312 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 313 313 314 314 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 315 315 - /** 5 bytes of bit flags for TV formats shared by all TV format functions */ 315 315 + /** 6 bytes of bit flags for TV formats shared by all TV format functions */ 316 316 struct intel_sdvo_tv_format { 317 317 unsigned int ntsc_m:1; 318 318 unsigned int ntsc_j:1; ··· 596 596 unsigned int overscan_h:1; 597 597 598 598 unsigned int overscan_v:1; 599 599 - unsigned int position_h:1; 600 600 - unsigned int position_v:1; 599 599 + unsigned int hpos:1; 600 600 + unsigned int vpos:1; 601 601 unsigned int sharpness:1; 602 602 unsigned int dot_crawl:1; 603 603 unsigned int dither:1; 604 604 - unsigned int max_tv_chroma_filter:1; 605 605 - unsigned int max_tv_luma_filter:1; 604 604 + unsigned int tv_chroma_filter:1; 605 605 + unsigned int tv_luma_filter:1; 606 606 } __attribute__((packed)); 607 607 608 608 /* Picture enhancement limits below are dependent on the current TV format, 609 609 * and thus need to be queried and set after it. 610 610 */ 611 611 - #define SDVO_CMD_GET_MAX_FLICKER_FITER 0x4d 612 612 - #define SDVO_CMD_GET_MAX_ADAPTIVE_FLICKER_FITER 0x7b 613 613 - #define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52 611 611 + #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d 612 612 + #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b 613 613 + #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52 614 614 #define SDVO_CMD_GET_MAX_SATURATION 0x55 615 615 #define SDVO_CMD_GET_MAX_HUE 0x58 616 616 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 617 617 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e 618 618 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 619 619 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 620 620 - #define SDVO_CMD_GET_MAX_POSITION_H 0x67 621 621 - #define SDVO_CMD_GET_MAX_POSITION_V 0x6a 622 622 - #define SDVO_CMD_GET_MAX_SHARPNESS_V 0x6d 623 623 - #define SDVO_CMD_GET_MAX_TV_CHROMA 0x74 624 624 - #define SDVO_CMD_GET_MAX_TV_LUMA 0x77 620 620 + #define SDVO_CMD_GET_MAX_HPOS 0x67 621 621 + #define SDVO_CMD_GET_MAX_VPOS 0x6a 622 622 + #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d 623 623 + #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 624 624 + #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 625 625 struct intel_sdvo_enhancement_limits_reply { 626 626 u16 max_value; 627 627 u16 default_value; ··· 638 638 639 639 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e 640 640 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f 641 641 - #define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50 642 642 - #define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51 643 643 - #define SDVO_CMD_GET_2D_FLICKER_FITER 0x53 644 644 - #define SDVO_CMD_SET_2D_FLICKER_FITER 0x54 641 641 + #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50 642 642 + #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51 643 643 + #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53 644 644 + #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54 645 645 #define SDVO_CMD_GET_SATURATION 0x56 646 646 #define SDVO_CMD_SET_SATURATION 0x57 647 647 #define SDVO_CMD_GET_HUE 0x59 ··· 654 654 #define SDVO_CMD_SET_OVERSCAN_H 0x63 655 655 #define SDVO_CMD_GET_OVERSCAN_V 0x65 656 656 #define SDVO_CMD_SET_OVERSCAN_V 0x66 657 657 - #define SDVO_CMD_GET_POSITION_H 0x68 658 658 - #define SDVO_CMD_SET_POSITION_H 0x69 659 659 - #define SDVO_CMD_GET_POSITION_V 0x6b 660 660 - #define SDVO_CMD_SET_POSITION_V 0x6c 657 657 + #define SDVO_CMD_GET_HPOS 0x68 658 658 + #define SDVO_CMD_SET_HPOS 0x69 659 659 + #define SDVO_CMD_GET_VPOS 0x6b 660 660 + #define SDVO_CMD_SET_VPOS 0x6c 661 661 #define SDVO_CMD_GET_SHARPNESS 0x6e 662 662 #define SDVO_CMD_SET_SHARPNESS 0x6f 663 663 - #define SDVO_CMD_GET_TV_CHROMA 0x75 664 664 - #define SDVO_CMD_SET_TV_CHROMA 0x76 665 665 - #define SDVO_CMD_GET_TV_LUMA 0x78 666 666 - #define SDVO_CMD_SET_TV_LUMA 0x79 663 663 + #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75 664 664 + #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76 665 665 + #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 666 666 + #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 667 667 struct intel_sdvo_enhancements_arg { 668 668 u16 value; 669 669 }__attribute__((packed));

+76 -83

drivers/gpu/drm/i915/intel_tv.c

reviewed

··· 44 44 }; 45 45 46 46 /** Private structure for the integrated TV support */ 47 47 - struct intel_tv_priv { 47 47 + struct intel_tv { 48 48 + struct intel_encoder base; 49 49 + 48 50 int type; 49 51 char *tv_format; 50 52 int margin[4]; ··· 898 896 }, 899 897 }; 900 898 899 899 + static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder) 900 900 + { 901 901 + return container_of(enc_to_intel_encoder(encoder), struct intel_tv, base); 902 902 + } 903 903 + 901 904 static void 902 905 intel_tv_dpms(struct drm_encoder *encoder, int mode) 903 906 { ··· 936 929 } 937 930 938 931 static const struct tv_mode * 939 939 - intel_tv_mode_find (struct intel_encoder *intel_encoder) 932 932 + intel_tv_mode_find (struct intel_tv *intel_tv) 940 933 { 941 941 - struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 942 942 - 943 943 - return intel_tv_mode_lookup(tv_priv->tv_format); 934 934 + return intel_tv_mode_lookup(intel_tv->tv_format); 944 935 } 945 936 946 937 static enum drm_mode_status 947 938 intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) 948 939 { 949 940 struct drm_encoder *encoder = intel_attached_encoder(connector); 950 950 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 951 951 - const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 941 941 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 942 942 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 952 943 953 944 /* Ensure TV refresh is close to desired refresh */ 954 945 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) ··· 962 957 { 963 958 struct drm_device *dev = encoder->dev; 964 959 struct drm_mode_config *drm_config = &dev->mode_config; 965 965 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 966 966 - const struct tv_mode *tv_mode = intel_tv_mode_find (intel_encoder); 960 960 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 961 961 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 967 962 struct drm_encoder *other_encoder; 968 963 969 964 if (!tv_mode) ··· 988 983 struct drm_i915_private *dev_priv = dev->dev_private; 989 984 struct drm_crtc *crtc = encoder->crtc; 990 985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 991 991 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 992 992 - struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 993 993 - const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 986 986 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 987 987 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 994 988 u32 tv_ctl; 995 989 u32 hctl1, hctl2, hctl3; 996 990 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; ··· 1005 1001 tv_ctl = I915_READ(TV_CTL); 1006 1002 tv_ctl &= TV_CTL_SAVE; 1007 1003 1008 1008 - switch (tv_priv->type) { 1004 1004 + switch (intel_tv->type) { 1009 1005 default: 1010 1006 case DRM_MODE_CONNECTOR_Unknown: 1011 1007 case DRM_MODE_CONNECTOR_Composite: ··· 1158 1154 1159 1155 /* Wait for vblank for the disable to take effect */ 1160 1156 if (!IS_I9XX(dev)) 1161 1161 - intel_wait_for_vblank(dev); 1157 1157 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1162 1158 1163 1159 I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE); 1164 1160 /* Wait for vblank for the disable to take effect. */ 1165 1165 - intel_wait_for_vblank(dev); 1161 1161 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1166 1162 1167 1163 /* Filter ctl must be set before TV_WIN_SIZE */ 1168 1164 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE); ··· 1172 1168 else 1173 1169 ysize = 2*tv_mode->nbr_end + 1; 1174 1170 1175 1175 - xpos += tv_priv->margin[TV_MARGIN_LEFT]; 1176 1176 - ypos += tv_priv->margin[TV_MARGIN_TOP]; 1177 1177 - xsize -= (tv_priv->margin[TV_MARGIN_LEFT] + 1178 1178 - tv_priv->margin[TV_MARGIN_RIGHT]); 1179 1179 - ysize -= (tv_priv->margin[TV_MARGIN_TOP] + 1180 1180 - tv_priv->margin[TV_MARGIN_BOTTOM]); 1171 1171 + xpos += intel_tv->margin[TV_MARGIN_LEFT]; 1172 1172 + ypos += intel_tv->margin[TV_MARGIN_TOP]; 1173 1173 + xsize -= (intel_tv->margin[TV_MARGIN_LEFT] + 1174 1174 + intel_tv->margin[TV_MARGIN_RIGHT]); 1175 1175 + ysize -= (intel_tv->margin[TV_MARGIN_TOP] + 1176 1176 + intel_tv->margin[TV_MARGIN_BOTTOM]); 1181 1177 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos); 1182 1178 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize); 1183 1179 ··· 1226 1222 * \return false if TV is disconnected. 1227 1223 */ 1228 1224 static int 1229 1229 - intel_tv_detect_type (struct drm_crtc *crtc, struct intel_encoder *intel_encoder) 1225 1225 + intel_tv_detect_type (struct intel_tv *intel_tv) 1230 1226 { 1231 1231 - struct drm_encoder *encoder = &intel_encoder->enc; 1227 1227 + struct drm_encoder *encoder = &intel_tv->base.enc; 1232 1228 struct drm_device *dev = encoder->dev; 1233 1229 struct drm_i915_private *dev_priv = dev->dev_private; 1230 1230 + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 1234 1231 unsigned long irqflags; 1235 1232 u32 tv_ctl, save_tv_ctl; 1236 1233 u32 tv_dac, save_tv_dac; ··· 1268 1263 DAC_C_0_7_V); 1269 1264 I915_WRITE(TV_CTL, tv_ctl); 1270 1265 I915_WRITE(TV_DAC, tv_dac); 1271 1271 - intel_wait_for_vblank(dev); 1266 1266 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1272 1267 tv_dac = I915_READ(TV_DAC); 1273 1268 I915_WRITE(TV_DAC, save_tv_dac); 1274 1269 I915_WRITE(TV_CTL, save_tv_ctl); 1275 1275 - intel_wait_for_vblank(dev); 1270 1270 + intel_wait_for_vblank(dev, intel_crtc->pipe); 1276 1271 /* 1277 1272 * A B C 1278 1273 * 0 1 1 Composite ··· 1309 1304 static void intel_tv_find_better_format(struct drm_connector *connector) 1310 1305 { 1311 1306 struct drm_encoder *encoder = intel_attached_encoder(connector); 1312 1312 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1313 1313 - struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 1314 1314 - const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 1307 1307 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 1308 1308 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 1315 1309 int i; 1316 1310 1317 1317 - if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == 1311 1311 + if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) == 1318 1312 tv_mode->component_only) 1319 1313 return; 1320 1314 ··· 1321 1317 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { 1322 1318 tv_mode = tv_modes + i; 1323 1319 1324 1324 - if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == 1320 1320 + if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) == 1325 1321 tv_mode->component_only) 1326 1322 break; 1327 1323 } 1328 1324 1329 1329 - tv_priv->tv_format = tv_mode->name; 1325 1325 + intel_tv->tv_format = tv_mode->name; 1330 1326 drm_connector_property_set_value(connector, 1331 1327 connector->dev->mode_config.tv_mode_property, i); 1332 1328 } ··· 1340 1336 static enum drm_connector_status 1341 1337 intel_tv_detect(struct drm_connector *connector) 1342 1338 { 1343 1343 - struct drm_crtc *crtc; 1344 1339 struct drm_display_mode mode; 1345 1340 struct drm_encoder *encoder = intel_attached_encoder(connector); 1346 1346 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1347 1347 - struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 1348 1348 - int dpms_mode; 1349 1349 - int type = tv_priv->type; 1341 1341 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 1342 1342 + int type; 1350 1343 1351 1344 mode = reported_modes[0]; 1352 1345 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); 1353 1346 1354 1347 if (encoder->crtc && encoder->crtc->enabled) { 1355 1355 - type = intel_tv_detect_type(encoder->crtc, intel_encoder); 1348 1348 + type = intel_tv_detect_type(intel_tv); 1356 1349 } else { 1357 1357 - crtc = intel_get_load_detect_pipe(intel_encoder, connector, 1350 1350 + struct drm_crtc *crtc; 1351 1351 + int dpms_mode; 1352 1352 + 1353 1353 + crtc = intel_get_load_detect_pipe(&intel_tv->base, connector, 1358 1354 &mode, &dpms_mode); 1359 1355 if (crtc) { 1360 1360 - type = intel_tv_detect_type(crtc, intel_encoder); 1361 1361 - intel_release_load_detect_pipe(intel_encoder, connector, 1356 1356 + type = intel_tv_detect_type(intel_tv); 1357 1357 + intel_release_load_detect_pipe(&intel_tv->base, connector, 1362 1358 dpms_mode); 1363 1359 } else 1364 1360 type = -1; 1365 1361 } 1366 1362 1367 1367 - tv_priv->type = type; 1363 1363 + intel_tv->type = type; 1368 1364 1369 1365 if (type < 0) 1370 1366 return connector_status_disconnected; ··· 1395 1391 struct drm_display_mode *mode_ptr) 1396 1392 { 1397 1393 struct drm_encoder *encoder = intel_attached_encoder(connector); 1398 1398 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1399 1399 - const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 1394 1394 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 1395 1395 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 1400 1396 1401 1397 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480) 1402 1398 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; ··· 1421 1417 { 1422 1418 struct drm_display_mode *mode_ptr; 1423 1419 struct drm_encoder *encoder = intel_attached_encoder(connector); 1424 1424 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1425 1425 - const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 1420 1420 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 1421 1421 + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 1426 1422 int j, count = 0; 1427 1423 u64 tmp; 1428 1424 ··· 1487 1483 { 1488 1484 struct drm_device *dev = connector->dev; 1489 1485 struct drm_encoder *encoder = intel_attached_encoder(connector); 1490 1490 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1491 1491 - struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 1486 1486 + struct intel_tv *intel_tv = enc_to_intel_tv(encoder); 1492 1487 struct drm_crtc *crtc = encoder->crtc; 1493 1488 int ret = 0; 1494 1489 bool changed = false; ··· 1497 1494 goto out; 1498 1495 1499 1496 if (property == dev->mode_config.tv_left_margin_property && 1500 1500 - tv_priv->margin[TV_MARGIN_LEFT] != val) { 1501 1501 - tv_priv->margin[TV_MARGIN_LEFT] = val; 1497 1497 + intel_tv->margin[TV_MARGIN_LEFT] != val) { 1498 1498 + intel_tv->margin[TV_MARGIN_LEFT] = val; 1502 1499 changed = true; 1503 1500 } else if (property == dev->mode_config.tv_right_margin_property && 1504 1504 - tv_priv->margin[TV_MARGIN_RIGHT] != val) { 1505 1505 - tv_priv->margin[TV_MARGIN_RIGHT] = val; 1501 1501 + intel_tv->margin[TV_MARGIN_RIGHT] != val) { 1502 1502 + intel_tv->margin[TV_MARGIN_RIGHT] = val; 1506 1503 changed = true; 1507 1504 } else if (property == dev->mode_config.tv_top_margin_property && 1508 1508 - tv_priv->margin[TV_MARGIN_TOP] != val) { 1509 1509 - tv_priv->margin[TV_MARGIN_TOP] = val; 1505 1505 + intel_tv->margin[TV_MARGIN_TOP] != val) { 1506 1506 + intel_tv->margin[TV_MARGIN_TOP] = val; 1510 1507 changed = true; 1511 1508 } else if (property == dev->mode_config.tv_bottom_margin_property && 1512 1512 - tv_priv->margin[TV_MARGIN_BOTTOM] != val) { 1513 1513 - tv_priv->margin[TV_MARGIN_BOTTOM] = val; 1509 1509 + intel_tv->margin[TV_MARGIN_BOTTOM] != val) { 1510 1510 + intel_tv->margin[TV_MARGIN_BOTTOM] = val; 1514 1511 changed = true; 1515 1512 } else if (property == dev->mode_config.tv_mode_property) { 1516 1513 if (val >= ARRAY_SIZE(tv_modes)) { 1517 1514 ret = -EINVAL; 1518 1515 goto out; 1519 1516 } 1520 1520 - if (!strcmp(tv_priv->tv_format, tv_modes[val].name)) 1517 1517 + if (!strcmp(intel_tv->tv_format, tv_modes[val].name)) 1521 1518 goto out; 1522 1519 1523 1523 - tv_priv->tv_format = tv_modes[val].name; 1520 1520 + intel_tv->tv_format = tv_modes[val].name; 1524 1521 changed = true; 1525 1522 } else { 1526 1523 ret = -EINVAL; ··· 1556 1553 .best_encoder = intel_attached_encoder, 1557 1554 }; 1558 1555 1559 1559 - static void intel_tv_enc_destroy(struct drm_encoder *encoder) 1560 1560 - { 1561 1561 - struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1562 1562 - 1563 1563 - drm_encoder_cleanup(encoder); 1564 1564 - kfree(intel_encoder); 1565 1565 - } 1566 1566 - 1567 1556 static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1568 1568 - .destroy = intel_tv_enc_destroy, 1557 1557 + .destroy = intel_encoder_destroy, 1569 1558 }; 1570 1559 1571 1560 /* ··· 1601 1606 { 1602 1607 struct drm_i915_private *dev_priv = dev->dev_private; 1603 1608 struct drm_connector *connector; 1609 1609 + struct intel_tv *intel_tv; 1604 1610 struct intel_encoder *intel_encoder; 1605 1611 struct intel_connector *intel_connector; 1606 1606 - struct intel_tv_priv *tv_priv; 1607 1612 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1608 1613 char **tv_format_names; 1609 1614 int i, initial_mode = 0; ··· 1642 1647 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1643 1648 return; 1644 1649 1645 1645 - intel_encoder = kzalloc(sizeof(struct intel_encoder) + 1646 1646 - sizeof(struct intel_tv_priv), GFP_KERNEL); 1647 1647 - if (!intel_encoder) { 1650 1650 + intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL); 1651 1651 + if (!intel_tv) { 1648 1652 return; 1649 1653 } 1650 1654 1651 1655 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1652 1656 if (!intel_connector) { 1653 1653 - kfree(intel_encoder); 1657 1657 + kfree(intel_tv); 1654 1658 return; 1655 1659 } 1656 1660 1661 1661 + intel_encoder = &intel_tv->base; 1657 1662 connector = &intel_connector->base; 1658 1663 1659 1664 drm_connector_init(dev, connector, &intel_tv_connector_funcs, ··· 1663 1668 DRM_MODE_ENCODER_TVDAC); 1664 1669 1665 1670 drm_mode_connector_attach_encoder(&intel_connector->base, &intel_encoder->enc); 1666 1666 - tv_priv = (struct intel_tv_priv *)(intel_encoder + 1); 1667 1671 intel_encoder->type = INTEL_OUTPUT_TVOUT; 1668 1672 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1669 1673 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT); 1670 1674 intel_encoder->enc.possible_crtcs = ((1 << 0) | (1 << 1)); 1671 1675 intel_encoder->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT); 1672 1672 - intel_encoder->dev_priv = tv_priv; 1673 1673 - tv_priv->type = DRM_MODE_CONNECTOR_Unknown; 1676 1676 + intel_tv->type = DRM_MODE_CONNECTOR_Unknown; 1674 1677 1675 1678 /* BIOS margin values */ 1676 1676 - tv_priv->margin[TV_MARGIN_LEFT] = 54; 1677 1677 - tv_priv->margin[TV_MARGIN_TOP] = 36; 1678 1678 - tv_priv->margin[TV_MARGIN_RIGHT] = 46; 1679 1679 - tv_priv->margin[TV_MARGIN_BOTTOM] = 37; 1679 1679 + intel_tv->margin[TV_MARGIN_LEFT] = 54; 1680 1680 + intel_tv->margin[TV_MARGIN_TOP] = 36; 1681 1681 + intel_tv->margin[TV_MARGIN_RIGHT] = 46; 1682 1682 + intel_tv->margin[TV_MARGIN_BOTTOM] = 37; 1680 1683 1681 1681 - tv_priv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL); 1684 1684 + intel_tv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL); 1682 1685 1683 1686 drm_encoder_helper_add(&intel_encoder->enc, &intel_tv_helper_funcs); 1684 1687 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); ··· 1696 1703 initial_mode); 1697 1704 drm_connector_attach_property(connector, 1698 1705 dev->mode_config.tv_left_margin_property, 1699 1699 - tv_priv->margin[TV_MARGIN_LEFT]); 1706 1706 + intel_tv->margin[TV_MARGIN_LEFT]); 1700 1707 drm_connector_attach_property(connector, 1701 1708 dev->mode_config.tv_top_margin_property, 1702 1702 - tv_priv->margin[TV_MARGIN_TOP]); 1709 1709 + intel_tv->margin[TV_MARGIN_TOP]); 1703 1710 drm_connector_attach_property(connector, 1704 1711 dev->mode_config.tv_right_margin_property, 1705 1705 - tv_priv->margin[TV_MARGIN_RIGHT]); 1712 1712 + intel_tv->margin[TV_MARGIN_RIGHT]); 1706 1713 drm_connector_attach_property(connector, 1707 1714 dev->mode_config.tv_bottom_margin_property, 1708 1708 - tv_priv->margin[TV_MARGIN_BOTTOM]); 1715 1715 + intel_tv->margin[TV_MARGIN_BOTTOM]); 1709 1716 out: 1710 1717 drm_sysfs_connector_add(connector); 1711 1718 }