Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of Sunxi and Rockchip clk driver fixes and a core framework
one where we need to copy a string because we can't guarantee it isn't
freed sometime later"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: sunxi-ng: fix recalc_rate formula of NKMP clocks
clk: sunxi-ng: Fix div/mult settings for osc12M on A64
clk: rockchip: Make uartpll a child of the gpll on rk3036
clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
clk: core: Copy connection id
dt-bindings: arm: update Armada CP110 system controller binding
clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
clk: sunxi: ccu-sun5i needs nkmp
clk: sunxi-ng: mp: Adjust parent rate for pre-dividers
+25
-8
+3
-3
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+3
-3
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
···
45
45
- 1 15 SATA
46
46
- 1 16 SATA USB
47
47
- 1 17 Main
48
-
- 1 18 SD/MMC
48
+
- 1 18 SD/MMC/GOP
49
49
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
50
50
- 1 22 USB3H0
51
51
- 1 23 USB3H1
···
65
65
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
66
66
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
67
67
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
68
-
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
68
+
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
69
69
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
70
70
71
71
Example:
···
78
78
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
79
79
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
80
80
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
81
-
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
81
+
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
82
82
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
83
83
};
+2
-1
drivers/clk/clk.c
+2
-1
drivers/clk/clk.c
···
2502
2502
2503
2503
clk->core = hw->core;
2504
2504
clk->dev_id = dev_id;
2505
-
clk->con_id = con_id;
2505
+
clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
2506
2506
clk->max_rate = ULONG_MAX;
2507
2507
2508
2508
clk_prepare_lock();
···
2518
2518
hlist_del(&clk->clks_node);
2519
2519
clk_prepare_unlock();
2520
2520
2521
+
kfree_const(clk->con_id);
2521
2522
kfree(clk);
2522
2523
}
2523
2524
+8
-1
drivers/clk/rockchip/clk-rk3036.c
+8
-1
drivers/clk/rockchip/clk-rk3036.c
···
127
127
PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
128
128
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
129
129
130
-
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
130
+
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
131
131
132
132
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
133
133
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
···
449
449
pr_err("%s: could not map cru region\n", __func__);
450
450
return;
451
451
}
452
+
453
+
/*
454
+
* Make uart_pll_clk a child of the gpll, as all other sources are
455
+
* not that usable / stable.
456
+
*/
457
+
writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
458
+
reg_base + RK2928_CLKSEL_CON(13));
452
459
453
460
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
454
461
if (IS_ERR(ctx)) {
+1
drivers/clk/sunxi-ng/Kconfig
+1
drivers/clk/sunxi-ng/Kconfig
+1
-1
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+1
-1
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
···
566
566
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
567
567
568
568
/* Fixed Factor clocks */
569
-
static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);
569
+
static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
570
570
571
571
/* We hardcode the divider to 4 for now */
572
572
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+1
-1
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+1
-1
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
···
608
608
0x150, 0, 4, 24, 2, BIT(31),
609
609
CLK_SET_RATE_PARENT);
610
610
611
-
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);
611
+
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
612
612
613
613
static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
614
614
+8
drivers/clk/sunxi-ng/ccu_mp.c
+8
drivers/clk/sunxi-ng/ccu_mp.c
···
85
85
unsigned int m, p;
86
86
u32 reg;
87
87
88
+
/* Adjust parent_rate according to pre-dividers */
89
+
ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
90
+
-1, &parent_rate);
91
+
88
92
reg = readl(cmp->common.base + cmp->common.reg);
89
93
90
94
m = reg >> cmp->m.shift;
···
120
116
unsigned int max_m, max_p;
121
117
unsigned int m, p;
122
118
u32 reg;
119
+
120
+
/* Adjust parent_rate according to pre-dividers */
121
+
ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
122
+
-1, &parent_rate);
123
123
124
124
max_m = cmp->m.max ?: 1 << cmp->m.width;
125
125
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+1
-1
drivers/clk/sunxi-ng/ccu_nkmp.c
+1
-1
drivers/clk/sunxi-ng/ccu_nkmp.c