Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: retire some unsupport cmd pkt bit for gfx v12_1
Retire some unsupport CP command bit set for gfx v12_1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
426ffb70
f56e29b8
+5
-12
+5
-12
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+5
-12
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
136
136
PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
137
137
PACKET3_MAP_QUEUES_ME((me)) |
138
138
PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
139
-
PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
140
139
PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
141
140
PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
142
141
amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
···
244
245
/* memory (1) or register (0) */
245
246
(WAIT_REG_MEM_MEM_SPACE(mem_space) |
246
247
WAIT_REG_MEM_OPERATION(opt) | /* wait */
247
-
WAIT_REG_MEM_FUNCTION(3) | /* equal */
248
-
WAIT_REG_MEM_ENGINE(eng_sel)));
248
+
WAIT_REG_MEM_FUNCTION(3))); /* equal */
249
249
250
250
if (mem_space)
251
251
BUG_ON(addr0 & 0x3); /* Dword align */
···
3410
3412
3411
3413
static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3412
3414
{
3413
-
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3414
3415
uint32_t seq = ring->fence_drv.sync_seq;
3415
3416
uint64_t addr = ring->fence_drv.gpu_addr;
3416
3417
3417
-
gfx_v12_1_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
3418
+
gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr),
3418
3419
upper_32_bits(addr), seq, 0xffffffff, 4);
3419
3420
}
3420
3421
···
3452
3455
3453
3456
/* write fence seq to the "addr" */
3454
3457
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3455
-
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3456
-
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3458
+
amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3457
3459
amdgpu_ring_write(ring, lower_32_bits(addr));
3458
3460
amdgpu_ring_write(ring, upper_32_bits(addr));
3459
3461
amdgpu_ring_write(ring, lower_32_bits(seq));
···
3460
3464
if (flags & AMDGPU_FENCE_FLAG_INT) {
3461
3465
/* set register to trigger INT */
3462
3466
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3463
-
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3464
-
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3467
+
amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3465
3468
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
3466
3469
amdgpu_ring_write(ring, 0);
3467
3470
amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
···
3519
3524
uint32_t reg0, uint32_t reg1,
3520
3525
uint32_t ref, uint32_t mask)
3521
3526
{
3522
-
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3523
-
3524
-
gfx_v12_1_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
3527
+
gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1,
3525
3528
ref, mask, 0x20);
3526
3529
}
3527
3530