Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Peter Anvin:
"One (hopefully) last batch of x86 fixes. You asked for the patch by
patch justifications, so here they are:
x86, MCE: Retract most UAPI exports
This one unexports from userspace a bunch of definitions which should
never have been exported. We really don't want to create an
accidental legacy here.
x86, doc: Add a bootloader ID for OVMF
This is a documentation-only patch, just recording the official
assignment of a boot loader ID.
x86: Do not leak kernel page mapping locations
Security: avoid making it needlessly easy for user space to probe the
kernel memory layout.
x86/mm: Check if PUD is large when validating a kernel address
Prevent failures using /proc/kcore when using 1G pages.
x86/apic: Work around boot failure on HP ProLiant DL980 G7 Server systems
Works around a BIOS problem causing boot failures on affected hardware."
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mm: Check if PUD is large when validating a kernel address
x86/apic: Work around boot failure on HP ProLiant DL980 G7 Server systems
x86, doc: Add a bootloader ID for OVMF
x86: Do not leak kernel page mapping locations
x86, MCE: Retract most UAPI exports
+110
-101
+1
Documentation/x86/boot.txt
+1
Documentation/x86/boot.txt
+84
arch/x86/include/asm/mce.h
+84
arch/x86/include/asm/mce.h
···
3
3
4
4
#include <uapi/asm/mce.h>
5
5
6
+
/*
7
+
* Machine Check support for x86
8
+
*/
9
+
10
+
/* MCG_CAP register defines */
11
+
#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12
+
#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13
+
#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14
+
#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15
+
#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16
+
#define MCG_EXT_CNT_SHIFT 16
17
+
#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18
+
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
19
+
20
+
/* MCG_STATUS register defines */
21
+
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
22
+
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
23
+
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
24
+
25
+
/* MCi_STATUS register defines */
26
+
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
27
+
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
28
+
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
29
+
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
30
+
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
31
+
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
32
+
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
33
+
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
34
+
#define MCI_STATUS_AR (1ULL<<55) /* Action required */
35
+
#define MCACOD 0xffff /* MCA Error Code */
36
+
37
+
/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
38
+
#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
39
+
#define MCACOD_SCRUBMSK 0xfff0
40
+
#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
41
+
#define MCACOD_DATA 0x0134 /* Data Load */
42
+
#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
43
+
44
+
/* MCi_MISC register defines */
45
+
#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
46
+
#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
47
+
#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
48
+
#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
49
+
#define MCI_MISC_ADDR_PHYS 2 /* physical address */
50
+
#define MCI_MISC_ADDR_MEM 3 /* memory address */
51
+
#define MCI_MISC_ADDR_GENERIC 7 /* generic */
52
+
53
+
/* CTL2 register defines */
54
+
#define MCI_CTL2_CMCI_EN (1ULL << 30)
55
+
#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
56
+
57
+
#define MCJ_CTX_MASK 3
58
+
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
59
+
#define MCJ_CTX_RANDOM 0 /* inject context: random */
60
+
#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
61
+
#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
62
+
#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
63
+
#define MCJ_EXCEPTION 0x8 /* raise as exception */
64
+
#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
65
+
66
+
#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
67
+
68
+
/* Software defined banks */
69
+
#define MCE_EXTENDED_BANK 128
70
+
#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
71
+
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
72
+
73
+
#define MCE_LOG_LEN 32
74
+
#define MCE_LOG_SIGNATURE "MACHINECHECK"
75
+
76
+
/*
77
+
* This structure contains all data related to the MCE log. Also
78
+
* carries a signature to make it easier to find from external
79
+
* debugging tools. Each entry is only valid when its finished flag
80
+
* is set.
81
+
*/
82
+
struct mce_log {
83
+
char signature[12]; /* "MACHINECHECK" */
84
+
unsigned len; /* = MCE_LOG_LEN */
85
+
unsigned next;
86
+
unsigned flags;
87
+
unsigned recordlen; /* length of struct mce */
88
+
struct mce entry[MCE_LOG_LEN];
89
+
};
6
90
7
91
struct mca_config {
8
92
bool dont_log_ce;
+5
arch/x86/include/asm/pgtable.h
+5
arch/x86/include/asm/pgtable.h
···
142
142
return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
143
143
}
144
144
145
+
static inline unsigned long pud_pfn(pud_t pud)
146
+
{
147
+
return (pud_val(pud) & PTE_PFN_MASK) >> PAGE_SHIFT;
148
+
}
149
+
145
150
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
146
151
147
152
static inline int pmd_large(pmd_t pte)
-87
arch/x86/include/uapi/asm/mce.h
-87
arch/x86/include/uapi/asm/mce.h
···
4
4
#include <linux/types.h>
5
5
#include <asm/ioctls.h>
6
6
7
-
/*
8
-
* Machine Check support for x86
9
-
*/
10
-
11
-
/* MCG_CAP register defines */
12
-
#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13
-
#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
14
-
#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15
-
#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
16
-
#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17
-
#define MCG_EXT_CNT_SHIFT 16
18
-
#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19
-
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
20
-
21
-
/* MCG_STATUS register defines */
22
-
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23
-
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24
-
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
25
-
26
-
/* MCi_STATUS register defines */
27
-
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28
-
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29
-
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30
-
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31
-
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32
-
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33
-
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34
-
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35
-
#define MCI_STATUS_AR (1ULL<<55) /* Action required */
36
-
#define MCACOD 0xffff /* MCA Error Code */
37
-
38
-
/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
39
-
#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
40
-
#define MCACOD_SCRUBMSK 0xfff0
41
-
#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
42
-
#define MCACOD_DATA 0x0134 /* Data Load */
43
-
#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
44
-
45
-
/* MCi_MISC register defines */
46
-
#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
47
-
#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
48
-
#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
49
-
#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
50
-
#define MCI_MISC_ADDR_PHYS 2 /* physical address */
51
-
#define MCI_MISC_ADDR_MEM 3 /* memory address */
52
-
#define MCI_MISC_ADDR_GENERIC 7 /* generic */
53
-
54
-
/* CTL2 register defines */
55
-
#define MCI_CTL2_CMCI_EN (1ULL << 30)
56
-
#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
57
-
58
-
#define MCJ_CTX_MASK 3
59
-
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
60
-
#define MCJ_CTX_RANDOM 0 /* inject context: random */
61
-
#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
62
-
#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
63
-
#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
64
-
#define MCJ_EXCEPTION 0x8 /* raise as exception */
65
-
#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
66
-
67
7
/* Fields are zero when not available */
68
8
struct mce {
69
9
__u64 status;
···
27
87
__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
28
88
};
29
89
30
-
/*
31
-
* This structure contains all data related to the MCE log. Also
32
-
* carries a signature to make it easier to find from external
33
-
* debugging tools. Each entry is only valid when its finished flag
34
-
* is set.
35
-
*/
36
-
37
-
#define MCE_LOG_LEN 32
38
-
39
-
struct mce_log {
40
-
char signature[12]; /* "MACHINECHECK" */
41
-
unsigned len; /* = MCE_LOG_LEN */
42
-
unsigned next;
43
-
unsigned flags;
44
-
unsigned recordlen; /* length of struct mce */
45
-
struct mce entry[MCE_LOG_LEN];
46
-
};
47
-
48
-
#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
49
-
50
-
#define MCE_LOG_SIGNATURE "MACHINECHECK"
51
-
52
90
#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
53
91
#define MCE_GET_LOG_LEN _IOR('M', 2, int)
54
92
#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
55
-
56
-
/* Software defined banks */
57
-
#define MCE_EXTENDED_BANK 128
58
-
#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
59
-
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
60
93
61
94
#endif /* _UAPI_ASM_X86_MCE_H */
+12
-11
arch/x86/kernel/apic/x2apic_phys.c
+12
-11
arch/x86/kernel/apic/x2apic_phys.c
···
20
20
}
21
21
early_param("x2apic_phys", set_x2apic_phys_mode);
22
22
23
+
static bool x2apic_fadt_phys(void)
24
+
{
25
+
if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
26
+
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
27
+
printk(KERN_DEBUG "System requires x2apic physical mode\n");
28
+
return true;
29
+
}
30
+
return false;
31
+
}
32
+
23
33
static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
24
34
{
25
-
if (x2apic_phys)
26
-
return x2apic_enabled();
27
-
else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
28
-
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
29
-
x2apic_enabled()) {
30
-
printk(KERN_DEBUG "System requires x2apic physical mode\n");
31
-
return 1;
32
-
}
33
-
else
34
-
return 0;
35
+
return x2apic_enabled() && (x2apic_phys || x2apic_fadt_phys());
35
36
}
36
37
37
38
static void
···
83
82
84
83
static int x2apic_phys_probe(void)
85
84
{
86
-
if (x2apic_mode && x2apic_phys)
85
+
if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys()))
87
86
return 1;
88
87
89
88
return apic == &apic_x2apic_phys;
+5
-3
arch/x86/mm/fault.c
+5
-3
arch/x86/mm/fault.c
···
748
748
return;
749
749
}
750
750
#endif
751
+
/* Kernel addresses are always protection faults: */
752
+
if (address >= TASK_SIZE)
753
+
error_code |= PF_PROT;
751
754
752
-
if (unlikely(show_unhandled_signals))
755
+
if (likely(show_unhandled_signals))
753
756
show_signal_msg(regs, error_code, address, tsk);
754
757
755
-
/* Kernel addresses are always protection faults: */
756
758
tsk->thread.cr2 = address;
757
-
tsk->thread.error_code = error_code | (address >= TASK_SIZE);
759
+
tsk->thread.error_code = error_code;
758
760
tsk->thread.trap_nr = X86_TRAP_PF;
759
761
760
762
force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0);