tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-07-04' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly drm fixes, bit of a bumper crop, the usual amdgpu/xe/i915
suspects, then there is a large scattering of fixes across core and
drivers. I think the simple panel lookup fix is probably the largest,
the sched race fix is also fun, but I don't see anything standing out
too badly.

dma-buf:
- fix timeout handling

gem:
- fix framebuffer object references

sched:
- fix spsc queue job count race

bridge:
- fix aux hpd bridge of node
- panel: move missing flag handling
- samsung-dsim: fix %pK usage to %p

panel:
- fix problem with simple panel lookup

ttm:
- fix error path handling

amdgpu:
- SDMA 5.x reset fix
- Add missing firmware declaration
- Fix leak in amdgpu_ctx_mgr_entity_fini()
- Freesync fix
- OLED backlight fix

amdkfd:
- mtype fix for ext coherent system memory
- MMU notifier fix
- gfx7/8 fix

xe:
- Fix chunking the PTE updates and overflowing the maximum number of
dwords with with MI_STORE_DATA_IMM
- Move WA BB to the LRC BO to mitigate hangs on context switch
- Fix frequency/flush WAs for BMG
- Fix kconfig prompt title and description
- Do not require kunit
- Extend 14018094691 WA to BMG
- Fix wedging the device on signal

i915:
- Make mei interrupt top half irq disabled to fix RT builds
- Fix timeline left held on VMA alloc error
- Fix NULL pointer deref in vlv_dphy_param_init()
- Fix selftest mock_request() to avoid NULL deref

exynos:
- switch to using %p instead of %pK
- fix vblank NULL ptr race
- fix lockup on samsung peach-pit/pi chromebooks

vesadrm:
- NULL ptr fix

vmwgfx:
- fix encrypted memory allocation bug

v3d:
- fix irq enabled during reset"

* tag 'drm-fixes-2025-07-04' of https://gitlab.freedesktop.org/drm/kernel: (41 commits)
drm/xe: Do not wedge device on killed exec queues
drm/xe: Extend WA 14018094691 to BMG
drm/v3d: Disable interrupts before resetting the GPU
drm/gem: Acquire references on GEM handles for framebuffers
drm/sched: Increment job count before swapping tail spsc queue
drm/xe: Allow dropping kunit dependency as built-in
drm/xe: Fix kconfig prompt
drm/xe/bmg: Update Wa_22019338487
drm/xe/bmg: Update Wa_14022085890
drm/xe: Split xe_device_td_flush()
drm/xe/xe_guc_pc: Lock once to update stashed frequencies
drm/xe/guc_pc: Add _locked variant for min/max freq
drm/xe: Make WA BB part of LRC BO
drm/xe: Fix out-of-bounds field write in MI_STORE_DATA_IMM
drm/i915/gsc: mei interrupt top half should be in irq disabled context
drm/i915/gt: Fix timeline left held on VMA alloc error
drm/vmwgfx: Fix guests running with TDX/SEV
drm/amd/display: Don't allow OLED to go down to fully off
drm/amd/display: Added case for when RR equals panel's max RR using freesync
drm/amdkfd: add hqd_sdma_get_doorbell callbacks for gfx7/8
...

Linus Torvalds 42bb9b63 923d4012

+634 -295
+7 -5
drivers/dma-buf/dma-resv.c
··· 685 685 dma_resv_iter_begin(&cursor, obj, usage); 686 686 dma_resv_for_each_fence_unlocked(&cursor, fence) { 687 687 688 - ret = dma_fence_wait_timeout(fence, intr, ret); 689 - if (ret <= 0) { 690 - dma_resv_iter_end(&cursor); 691 - return ret; 692 - } 688 + ret = dma_fence_wait_timeout(fence, intr, timeout); 689 + if (ret <= 0) 690 + break; 691 + 692 + /* Even for zero timeout the return value is 1 */ 693 + if (timeout) 694 + timeout = ret; 693 695 } 694 696 dma_resv_iter_end(&cursor); 695 697
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
··· 561 561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 562 562 } 563 563 564 + static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev, 565 + int engine, int queue) 566 + 567 + { 568 + return 0; 569 + } 570 + 564 571 const struct kfd2kgd_calls gfx_v7_kfd2kgd = { 565 572 .program_sh_mem_settings = kgd_program_sh_mem_settings, 566 573 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, ··· 585 578 .set_scratch_backing_va = set_scratch_backing_va, 586 579 .set_vm_context_page_table_base = set_vm_context_page_table_base, 587 580 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg, 581 + .hqd_sdma_get_doorbell = kgd_hqd_sdma_get_doorbell, 588 582 };
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
··· 582 582 lower_32_bits(page_table_base)); 583 583 } 584 584 585 + static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev, 586 + int engine, int queue) 587 + 588 + { 589 + return 0; 590 + } 591 + 585 592 const struct kfd2kgd_calls gfx_v8_kfd2kgd = { 586 593 .program_sh_mem_settings = kgd_program_sh_mem_settings, 587 594 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, ··· 606 599 get_atc_vmid_pasid_mapping_info, 607 600 .set_scratch_backing_va = set_scratch_backing_va, 608 601 .set_vm_context_page_table_base = set_vm_context_page_table_base, 602 + .hqd_sdma_get_doorbell = kgd_hqd_sdma_get_doorbell, 609 603 };
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 944 944 drm_sched_entity_fini(entity); 945 945 } 946 946 } 947 + kref_put(&ctx->refcount, amdgpu_ctx_fini); 947 948 } 948 949 } 949 950
+1
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
··· 45 45 #include "amdgpu_ras.h" 46 46 47 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 + MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin"); 48 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 49 50 50 51 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {
+6 -1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1543 1543 { 1544 1544 struct amdgpu_device *adev = ring->adev; 1545 1545 u32 inst_id = ring->me; 1546 + int r; 1546 1547 1547 - return amdgpu_sdma_reset_engine(adev, inst_id); 1548 + amdgpu_amdkfd_suspend(adev, true); 1549 + r = amdgpu_sdma_reset_engine(adev, inst_id); 1550 + amdgpu_amdkfd_resume(adev, true); 1551 + 1552 + return r; 1548 1553 } 1549 1554 1550 1555 static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)
+6 -1
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 1456 1456 { 1457 1457 struct amdgpu_device *adev = ring->adev; 1458 1458 u32 inst_id = ring->me; 1459 + int r; 1459 1460 1460 - return amdgpu_sdma_reset_engine(adev, inst_id); 1461 + amdgpu_amdkfd_suspend(adev, true); 1462 + r = amdgpu_sdma_reset_engine(adev, inst_id); 1463 + amdgpu_amdkfd_resume(adev, true); 1464 + 1465 + return r; 1461 1466 } 1462 1467 1463 1468 static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)
+21 -24
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
··· 1171 1171 } 1172 1172 1173 1173 static void 1174 - svm_range_add_child(struct svm_range *prange, struct mm_struct *mm, 1175 - struct svm_range *pchild, enum svm_work_list_ops op) 1174 + svm_range_add_child(struct svm_range *prange, struct svm_range *pchild, enum svm_work_list_ops op) 1176 1175 { 1177 1176 pr_debug("add child 0x%p [0x%lx 0x%lx] to prange 0x%p child list %d\n", 1178 1177 pchild, pchild->start, pchild->last, prange, op); 1179 1178 1180 - pchild->work_item.mm = mm; 1179 + pchild->work_item.mm = NULL; 1181 1180 pchild->work_item.op = op; 1182 1181 list_add_tail(&pchild->child_list, &prange->child_list); 1183 1182 } ··· 1277 1278 mapping_flags |= ext_coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; 1278 1279 /* system memory accessed by the dGPU */ 1279 1280 } else { 1280 - if (gc_ip_version < IP_VERSION(9, 5, 0)) 1281 + if (gc_ip_version < IP_VERSION(9, 5, 0) || ext_coherent) 1281 1282 mapping_flags |= AMDGPU_VM_MTYPE_UC; 1282 1283 else 1283 1284 mapping_flags |= AMDGPU_VM_MTYPE_NC; ··· 2393 2394 prange->work_item.op != SVM_OP_UNMAP_RANGE) 2394 2395 prange->work_item.op = op; 2395 2396 } else { 2396 - prange->work_item.op = op; 2397 - 2398 - /* Pairs with mmput in deferred_list_work */ 2399 - mmget(mm); 2400 - prange->work_item.mm = mm; 2401 - list_add_tail(&prange->deferred_list, 2402 - &prange->svms->deferred_range_list); 2403 - pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n", 2404 - prange, prange->start, prange->last, op); 2397 + /* Pairs with mmput in deferred_list_work. 2398 + * If process is exiting and mm is gone, don't update mmu notifier. 2399 + */ 2400 + if (mmget_not_zero(mm)) { 2401 + prange->work_item.mm = mm; 2402 + prange->work_item.op = op; 2403 + list_add_tail(&prange->deferred_list, 2404 + &prange->svms->deferred_range_list); 2405 + pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n", 2406 + prange, prange->start, prange->last, op); 2407 + } 2405 2408 } 2406 2409 spin_unlock(&svms->deferred_list_lock); 2407 2410 } ··· 2417 2416 } 2418 2417 2419 2418 static void 2420 - svm_range_unmap_split(struct mm_struct *mm, struct svm_range *parent, 2421 - struct svm_range *prange, unsigned long start, 2419 + svm_range_unmap_split(struct svm_range *parent, struct svm_range *prange, unsigned long start, 2422 2420 unsigned long last) 2423 2421 { 2424 2422 struct svm_range *head; ··· 2438 2438 svm_range_split(tail, last + 1, tail->last, &head); 2439 2439 2440 2440 if (head != prange && tail != prange) { 2441 - svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE); 2442 - svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE); 2441 + svm_range_add_child(parent, head, SVM_OP_UNMAP_RANGE); 2442 + svm_range_add_child(parent, tail, SVM_OP_ADD_RANGE); 2443 2443 } else if (tail != prange) { 2444 - svm_range_add_child(parent, mm, tail, SVM_OP_UNMAP_RANGE); 2444 + svm_range_add_child(parent, tail, SVM_OP_UNMAP_RANGE); 2445 2445 } else if (head != prange) { 2446 - svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE); 2446 + svm_range_add_child(parent, head, SVM_OP_UNMAP_RANGE); 2447 2447 } else if (parent != prange) { 2448 2448 prange->work_item.op = SVM_OP_UNMAP_RANGE; 2449 2449 } ··· 2520 2520 l = min(last, pchild->last); 2521 2521 if (l >= s) 2522 2522 svm_range_unmap_from_gpus(pchild, s, l, trigger); 2523 - svm_range_unmap_split(mm, prange, pchild, start, last); 2523 + svm_range_unmap_split(prange, pchild, start, last); 2524 2524 mutex_unlock(&pchild->lock); 2525 2525 } 2526 2526 s = max(start, prange->start); 2527 2527 l = min(last, prange->last); 2528 2528 if (l >= s) 2529 2529 svm_range_unmap_from_gpus(prange, s, l, trigger); 2530 - svm_range_unmap_split(mm, prange, prange, start, last); 2530 + svm_range_unmap_split(prange, prange, start, last); 2531 2531 2532 2532 if (unmap_parent) 2533 2533 svm_range_add_list_work(svms, prange, mm, SVM_OP_UNMAP_RANGE); ··· 2570 2570 2571 2571 if (range->event == MMU_NOTIFY_RELEASE) 2572 2572 return true; 2573 - if (!mmget_not_zero(mni->mm)) 2574 - return true; 2575 2573 2576 2574 start = mni->interval_tree.start; 2577 2575 last = mni->interval_tree.last; ··· 2596 2598 } 2597 2599 2598 2600 svm_range_unlock(prange); 2599 - mmput(mni->mm); 2600 2601 2601 2602 return true; 2602 2603 }
+7 -5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 3610 3610 3611 3611 luminance_range = &conn_base->display_info.luminance_range; 3612 3612 3613 - if (luminance_range->max_luminance) { 3614 - caps->aux_min_input_signal = luminance_range->min_luminance; 3613 + if (luminance_range->max_luminance) 3615 3614 caps->aux_max_input_signal = luminance_range->max_luminance; 3616 - } else { 3617 - caps->aux_min_input_signal = 0; 3615 + else 3618 3616 caps->aux_max_input_signal = 512; 3619 - } 3617 + 3618 + if (luminance_range->min_luminance) 3619 + caps->aux_min_input_signal = luminance_range->min_luminance; 3620 + else 3621 + caps->aux_min_input_signal = 1; 3620 3622 3621 3623 min_input_signal_override = drm_get_panel_min_brightness_quirk(aconnector->drm_edid); 3622 3624 if (min_input_signal_override >= 0)
+1
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
··· 974 974 uint32_t pix_clk_100hz; 975 975 976 976 uint32_t min_refresh_in_uhz; 977 + uint32_t max_refresh_in_uhz; 977 978 978 979 uint32_t vic; 979 980 uint32_t hdmi_vic;
+8
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
··· 155 155 v_total = div64_u64(div64_u64(((unsigned long long)( 156 156 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 157 157 stream->timing.h_total), 1000000); 158 + } else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) { 159 + /* When the target refresh rate is the maximum panel refresh rate 160 + * round up the vtotal value to prevent off-by-one error causing 161 + * v_total_min to be below the panel's lower bound 162 + */ 163 + v_total = div64_u64(div64_u64(((unsigned long long)( 164 + frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 165 + stream->timing.h_total) + (1000000 - 1), 1000000); 158 166 } else { 159 167 v_total = div64_u64(div64_u64(((unsigned long long)( 160 168 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
+2 -1
drivers/gpu/drm/bridge/aux-hpd-bridge.c
··· 64 64 adev->id = ret; 65 65 adev->name = "dp_hpd_bridge"; 66 66 adev->dev.parent = parent; 67 - adev->dev.of_node = of_node_get(parent->of_node); 68 67 adev->dev.release = drm_aux_hpd_bridge_release; 69 68 adev->dev.platform_data = of_node_get(np); 69 + 70 + device_set_of_node_from_dev(&adev->dev, parent); 70 71 71 72 ret = auxiliary_device_init(adev); 72 73 if (ret) {
+1 -4
drivers/gpu/drm/bridge/panel.c
··· 299 299 panel_bridge->bridge.of_node = panel->dev->of_node; 300 300 panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES; 301 301 panel_bridge->bridge.type = connector_type; 302 + panel_bridge->bridge.pre_enable_prev_first = panel->prepare_prev_first; 302 303 303 304 drm_bridge_add(&panel_bridge->bridge); 304 305 ··· 414 413 return bridge; 415 414 } 416 415 417 - bridge->pre_enable_prev_first = panel->prepare_prev_first; 418 - 419 416 *ptr = bridge; 420 417 devres_add(dev, ptr); 421 418 ··· 454 455 bridge); 455 456 if (ret) 456 457 return ERR_PTR(ret); 457 - 458 - bridge->pre_enable_prev_first = panel->prepare_prev_first; 459 458 460 459 return bridge; 461 460 }
+2 -2
drivers/gpu/drm/bridge/samsung-dsim.c
··· 1095 1095 bool first = !xfer->tx_done; 1096 1096 u32 reg; 1097 1097 1098 - dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 1098 + dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 1099 1099 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1100 1100 1101 1101 if (length > DSI_TX_FIFO_SIZE) ··· 1293 1293 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1294 1294 1295 1295 dev_dbg(dsi->dev, 1296 - "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1296 + "> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1297 1297 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1298 1298 xfer->rx_done); 1299 1299
+40 -4
drivers/gpu/drm/drm_gem.c
··· 212 212 } 213 213 EXPORT_SYMBOL(drm_gem_private_object_fini); 214 214 215 + static void drm_gem_object_handle_get(struct drm_gem_object *obj) 216 + { 217 + struct drm_device *dev = obj->dev; 218 + 219 + drm_WARN_ON(dev, !mutex_is_locked(&dev->object_name_lock)); 220 + 221 + if (obj->handle_count++ == 0) 222 + drm_gem_object_get(obj); 223 + } 224 + 225 + /** 226 + * drm_gem_object_handle_get_unlocked - acquire reference on user-space handles 227 + * @obj: GEM object 228 + * 229 + * Acquires a reference on the GEM buffer object's handle. Required 230 + * to keep the GEM object alive. Call drm_gem_object_handle_put_unlocked() 231 + * to release the reference. 232 + */ 233 + void drm_gem_object_handle_get_unlocked(struct drm_gem_object *obj) 234 + { 235 + struct drm_device *dev = obj->dev; 236 + 237 + guard(mutex)(&dev->object_name_lock); 238 + 239 + drm_WARN_ON(dev, !obj->handle_count); /* first ref taken in create-tail helper */ 240 + drm_gem_object_handle_get(obj); 241 + } 242 + EXPORT_SYMBOL(drm_gem_object_handle_get_unlocked); 243 + 215 244 /** 216 245 * drm_gem_object_handle_free - release resources bound to userspace handles 217 246 * @obj: GEM object to clean up. ··· 271 242 } 272 243 } 273 244 274 - static void 275 - drm_gem_object_handle_put_unlocked(struct drm_gem_object *obj) 245 + /** 246 + * drm_gem_object_handle_put_unlocked - releases reference on user-space handles 247 + * @obj: GEM object 248 + * 249 + * Releases a reference on the GEM buffer object's handle. Possibly releases 250 + * the GEM buffer object and associated dma-buf objects. 251 + */ 252 + void drm_gem_object_handle_put_unlocked(struct drm_gem_object *obj) 276 253 { 277 254 struct drm_device *dev = obj->dev; 278 255 bool final = false; ··· 303 268 if (final) 304 269 drm_gem_object_put(obj); 305 270 } 271 + EXPORT_SYMBOL(drm_gem_object_handle_put_unlocked); 306 272 307 273 /* 308 274 * Called at device or object close to release the file's ··· 425 389 int ret; 426 390 427 391 WARN_ON(!mutex_is_locked(&dev->object_name_lock)); 428 - if (obj->handle_count++ == 0) 429 - drm_gem_object_get(obj); 392 + 393 + drm_gem_object_handle_get(obj); 430 394 431 395 /* 432 396 * Get the user-visible handle using idr. Preload and perform
+9 -7
drivers/gpu/drm/drm_gem_framebuffer_helper.c
··· 99 99 unsigned int i; 100 100 101 101 for (i = 0; i < fb->format->num_planes; i++) 102 - drm_gem_object_put(fb->obj[i]); 102 + drm_gem_object_handle_put_unlocked(fb->obj[i]); 103 103 104 104 drm_framebuffer_cleanup(fb); 105 105 kfree(fb); ··· 182 182 if (!objs[i]) { 183 183 drm_dbg_kms(dev, "Failed to lookup GEM object\n"); 184 184 ret = -ENOENT; 185 - goto err_gem_object_put; 185 + goto err_gem_object_handle_put_unlocked; 186 186 } 187 + drm_gem_object_handle_get_unlocked(objs[i]); 188 + drm_gem_object_put(objs[i]); 187 189 188 190 min_size = (height - 1) * mode_cmd->pitches[i] 189 191 + drm_format_info_min_pitch(info, i, width) ··· 195 193 drm_dbg_kms(dev, 196 194 "GEM object size (%zu) smaller than minimum size (%u) for plane %d\n", 197 195 objs[i]->size, min_size, i); 198 - drm_gem_object_put(objs[i]); 196 + drm_gem_object_handle_put_unlocked(objs[i]); 199 197 ret = -EINVAL; 200 - goto err_gem_object_put; 198 + goto err_gem_object_handle_put_unlocked; 201 199 } 202 200 } 203 201 204 202 ret = drm_gem_fb_init(dev, fb, mode_cmd, objs, i, funcs); 205 203 if (ret) 206 - goto err_gem_object_put; 204 + goto err_gem_object_handle_put_unlocked; 207 205 208 206 return 0; 209 207 210 - err_gem_object_put: 208 + err_gem_object_handle_put_unlocked: 211 209 while (i > 0) { 212 210 --i; 213 - drm_gem_object_put(objs[i]); 211 + drm_gem_object_handle_put_unlocked(objs[i]); 214 212 } 215 213 return ret; 216 214 }
+2
drivers/gpu/drm/drm_internal.h
··· 161 161 162 162 /* drm_gem.c */ 163 163 int drm_gem_init(struct drm_device *dev); 164 + void drm_gem_object_handle_get_unlocked(struct drm_gem_object *obj); 165 + void drm_gem_object_handle_put_unlocked(struct drm_gem_object *obj); 164 166 int drm_gem_handle_create_tail(struct drm_file *file_priv, 165 167 struct drm_gem_object *obj, 166 168 u32 *handlep);
+2 -1
drivers/gpu/drm/drm_mipi_dsi.c
··· 91 91 .restore = pm_generic_restore, 92 92 }; 93 93 94 - static const struct bus_type mipi_dsi_bus_type = { 94 + const struct bus_type mipi_dsi_bus_type = { 95 95 .name = "mipi-dsi", 96 96 .match = mipi_dsi_device_match, 97 97 .uevent = mipi_dsi_uevent, 98 98 .pm = &mipi_dsi_device_pm_ops, 99 99 }; 100 + EXPORT_SYMBOL_GPL(mipi_dsi_bus_type); 100 101 101 102 /** 102 103 * of_find_mipi_dsi_device_by_node() - find the MIPI DSI device matching a
+4
drivers/gpu/drm/exynos/exynos7_drm_decon.c
··· 636 636 if (!ctx->drm_dev) 637 637 goto out; 638 638 639 + /* check if crtc and vblank have been initialized properly */ 640 + if (!drm_dev_has_vblank(ctx->drm_dev)) 641 + goto out; 642 + 639 643 if (!ctx->i80_if) { 640 644 drm_crtc_handle_vblank(&ctx->crtc->base); 641 645
+12
drivers/gpu/drm/exynos/exynos_drm_fimd.c
··· 187 187 u32 i80ifcon; 188 188 bool i80_if; 189 189 bool suspended; 190 + bool dp_clk_enabled; 190 191 wait_queue_head_t wait_vsync_queue; 191 192 atomic_t wait_vsync_event; 192 193 atomic_t win_updated; ··· 1048 1047 struct fimd_context *ctx = container_of(clk, struct fimd_context, 1049 1048 dp_clk); 1050 1049 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 1050 + 1051 + if (enable == ctx->dp_clk_enabled) 1052 + return; 1053 + 1054 + if (enable) 1055 + pm_runtime_resume_and_get(ctx->dev); 1056 + 1057 + ctx->dp_clk_enabled = enable; 1051 1058 writel(val, ctx->regs + DP_MIE_CLKCON); 1059 + 1060 + if (!enable) 1061 + pm_runtime_put(ctx->dev); 1052 1062 } 1053 1063 1054 1064 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
+1 -1
drivers/gpu/drm/exynos/exynos_drm_gem.c
··· 174 174 return ERR_PTR(ret); 175 175 } 176 176 177 - DRM_DEV_DEBUG_KMS(dev->dev, "created file object = %pK\n", obj->filp); 177 + DRM_DEV_DEBUG_KMS(dev->dev, "created file object = %p\n", obj->filp); 178 178 179 179 return exynos_gem; 180 180 }
+16 -16
drivers/gpu/drm/exynos/exynos_drm_ipp.c
··· 271 271 task->src.rect.h = task->dst.rect.h = UINT_MAX; 272 272 task->transform.rotation = DRM_MODE_ROTATE_0; 273 273 274 - DRM_DEV_DEBUG_DRIVER(task->dev, "Allocated task %pK\n", task); 274 + DRM_DEV_DEBUG_DRIVER(task->dev, "Allocated task %p\n", task); 275 275 276 276 return task; 277 277 } ··· 339 339 } 340 340 341 341 DRM_DEV_DEBUG_DRIVER(task->dev, 342 - "Got task %pK configuration from userspace\n", 342 + "Got task %p configuration from userspace\n", 343 343 task); 344 344 return 0; 345 345 } ··· 394 394 static void exynos_drm_ipp_task_free(struct exynos_drm_ipp *ipp, 395 395 struct exynos_drm_ipp_task *task) 396 396 { 397 - DRM_DEV_DEBUG_DRIVER(task->dev, "Freeing task %pK\n", task); 397 + DRM_DEV_DEBUG_DRIVER(task->dev, "Freeing task %p\n", task); 398 398 399 399 exynos_drm_ipp_task_release_buf(&task->src); 400 400 exynos_drm_ipp_task_release_buf(&task->dst); ··· 559 559 DRM_EXYNOS_IPP_FORMAT_DESTINATION); 560 560 if (!fmt) { 561 561 DRM_DEV_DEBUG_DRIVER(task->dev, 562 - "Task %pK: %s format not supported\n", 562 + "Task %p: %s format not supported\n", 563 563 task, buf == src ? "src" : "dst"); 564 564 return -EINVAL; 565 565 } ··· 609 609 bool rotate = (rotation != DRM_MODE_ROTATE_0); 610 610 bool scale = false; 611 611 612 - DRM_DEV_DEBUG_DRIVER(task->dev, "Checking task %pK\n", task); 612 + DRM_DEV_DEBUG_DRIVER(task->dev, "Checking task %p\n", task); 613 613 614 614 if (src->rect.w == UINT_MAX) 615 615 src->rect.w = src->buf.width; ··· 625 625 dst->rect.x + dst->rect.w > (dst->buf.width) || 626 626 dst->rect.y + dst->rect.h > (dst->buf.height)) { 627 627 DRM_DEV_DEBUG_DRIVER(task->dev, 628 - "Task %pK: defined area is outside provided buffers\n", 628 + "Task %p: defined area is outside provided buffers\n", 629 629 task); 630 630 return -EINVAL; 631 631 } ··· 642 642 (!(ipp->capabilities & DRM_EXYNOS_IPP_CAP_SCALE) && scale) || 643 643 (!(ipp->capabilities & DRM_EXYNOS_IPP_CAP_CONVERT) && 644 644 src->buf.fourcc != dst->buf.fourcc)) { 645 - DRM_DEV_DEBUG_DRIVER(task->dev, "Task %pK: hw capabilities exceeded\n", 645 + DRM_DEV_DEBUG_DRIVER(task->dev, "Task %p: hw capabilities exceeded\n", 646 646 task); 647 647 return -EINVAL; 648 648 } ··· 655 655 if (ret) 656 656 return ret; 657 657 658 - DRM_DEV_DEBUG_DRIVER(ipp->dev, "Task %pK: all checks done.\n", 658 + DRM_DEV_DEBUG_DRIVER(ipp->dev, "Task %p: all checks done.\n", 659 659 task); 660 660 661 661 return ret; ··· 667 667 struct exynos_drm_ipp_buffer *src = &task->src, *dst = &task->dst; 668 668 int ret = 0; 669 669 670 - DRM_DEV_DEBUG_DRIVER(task->dev, "Setting buffer for task %pK\n", 670 + DRM_DEV_DEBUG_DRIVER(task->dev, "Setting buffer for task %p\n", 671 671 task); 672 672 673 673 ret = exynos_drm_ipp_task_setup_buffer(src, filp); 674 674 if (ret) { 675 675 DRM_DEV_DEBUG_DRIVER(task->dev, 676 - "Task %pK: src buffer setup failed\n", 676 + "Task %p: src buffer setup failed\n", 677 677 task); 678 678 return ret; 679 679 } 680 680 ret = exynos_drm_ipp_task_setup_buffer(dst, filp); 681 681 if (ret) { 682 682 DRM_DEV_DEBUG_DRIVER(task->dev, 683 - "Task %pK: dst buffer setup failed\n", 683 + "Task %p: dst buffer setup failed\n", 684 684 task); 685 685 return ret; 686 686 } 687 687 688 - DRM_DEV_DEBUG_DRIVER(task->dev, "Task %pK: buffers prepared.\n", 688 + DRM_DEV_DEBUG_DRIVER(task->dev, "Task %p: buffers prepared.\n", 689 689 task); 690 690 691 691 return ret; ··· 764 764 struct exynos_drm_ipp *ipp = task->ipp; 765 765 unsigned long flags; 766 766 767 - DRM_DEV_DEBUG_DRIVER(task->dev, "ipp: %d, task %pK done: %d\n", 767 + DRM_DEV_DEBUG_DRIVER(task->dev, "ipp: %d, task %p done: %d\n", 768 768 ipp->id, task, ret); 769 769 770 770 spin_lock_irqsave(&ipp->lock, flags); ··· 807 807 spin_unlock_irqrestore(&ipp->lock, flags); 808 808 809 809 DRM_DEV_DEBUG_DRIVER(ipp->dev, 810 - "ipp: %d, selected task %pK to run\n", ipp->id, 810 + "ipp: %d, selected task %p to run\n", ipp->id, 811 811 task); 812 812 813 813 ret = ipp->funcs->commit(ipp, task); ··· 917 917 */ 918 918 if (arg->flags & DRM_EXYNOS_IPP_FLAG_NONBLOCK) { 919 919 DRM_DEV_DEBUG_DRIVER(ipp->dev, 920 - "ipp: %d, nonblocking processing task %pK\n", 920 + "ipp: %d, nonblocking processing task %p\n", 921 921 ipp->id, task); 922 922 923 923 task->flags |= DRM_EXYNOS_IPP_TASK_ASYNC; 924 924 exynos_drm_ipp_schedule_task(task->ipp, task); 925 925 ret = 0; 926 926 } else { 927 - DRM_DEV_DEBUG_DRIVER(ipp->dev, "ipp: %d, processing task %pK\n", 927 + DRM_DEV_DEBUG_DRIVER(ipp->dev, "ipp: %d, processing task %p\n", 928 928 ipp->id, task); 929 929 exynos_drm_ipp_schedule_task(ipp, task); 930 930 ret = wait_event_interruptible(ipp->done_wq,
+1 -1
drivers/gpu/drm/i915/display/vlv_dsi.c
··· 1589 1589 1590 1590 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1591 1591 { 1592 + struct intel_display *display = to_intel_display(&intel_dsi->base); 1592 1593 struct intel_connector *connector = intel_dsi->attached_connector; 1593 - struct intel_display *display = to_intel_display(connector); 1594 1594 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1595 1595 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1596 1596 u32 ui_num, ui_den;
+1 -1
drivers/gpu/drm/i915/gt/intel_gsc.c
··· 284 284 if (gt->gsc.intf[intf_id].irq < 0) 285 285 return; 286 286 287 - ret = generic_handle_irq(gt->gsc.intf[intf_id].irq); 287 + ret = generic_handle_irq_safe(gt->gsc.intf[intf_id].irq); 288 288 if (ret) 289 289 gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret); 290 290 }
+2 -1
drivers/gpu/drm/i915/gt/intel_ring_submission.c
··· 610 610 /* One ringbuffer to rule them all */ 611 611 GEM_BUG_ON(!engine->legacy.ring); 612 612 ce->ring = engine->legacy.ring; 613 - ce->timeline = intel_timeline_get(engine->legacy.timeline); 614 613 615 614 GEM_BUG_ON(ce->state); 616 615 if (engine->context_size) { ··· 621 622 622 623 ce->state = vma; 623 624 } 625 + 626 + ce->timeline = intel_timeline_get(engine->legacy.timeline); 624 627 625 628 return 0; 626 629 }
+10 -10
drivers/gpu/drm/i915/selftests/i915_request.c
··· 73 73 /* Basic preliminary test to create a request and let it loose! */ 74 74 75 75 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); 76 - if (!request) 77 - return -ENOMEM; 76 + if (IS_ERR(request)) 77 + return PTR_ERR(request); 78 78 79 79 i915_request_add(request); 80 80 ··· 91 91 /* Submit a request, then wait upon it */ 92 92 93 93 request = mock_request(rcs0(i915)->kernel_context, T); 94 - if (!request) 95 - return -ENOMEM; 94 + if (IS_ERR(request)) 95 + return PTR_ERR(request); 96 96 97 97 i915_request_get(request); 98 98 ··· 160 160 /* Submit a request, treat it as a fence and wait upon it */ 161 161 162 162 request = mock_request(rcs0(i915)->kernel_context, T); 163 - if (!request) 164 - return -ENOMEM; 163 + if (IS_ERR(request)) 164 + return PTR_ERR(request); 165 165 166 166 if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) { 167 167 pr_err("fence wait success before submit (expected timeout)!\n"); ··· 219 219 GEM_BUG_ON(IS_ERR(ce)); 220 220 request = mock_request(ce, 2 * HZ); 221 221 intel_context_put(ce); 222 - if (!request) { 223 - err = -ENOMEM; 222 + if (IS_ERR(request)) { 223 + err = PTR_ERR(request); 224 224 goto err_context_0; 225 225 } 226 226 ··· 237 237 GEM_BUG_ON(IS_ERR(ce)); 238 238 vip = mock_request(ce, 0); 239 239 intel_context_put(ce); 240 - if (!vip) { 241 - err = -ENOMEM; 240 + if (IS_ERR(vip)) { 241 + err = PTR_ERR(vip); 242 242 goto err_context_1; 243 243 } 244 244
+1 -1
drivers/gpu/drm/i915/selftests/mock_request.c
··· 35 35 /* NB the i915->requests slab cache is enlarged to fit mock_request */ 36 36 request = intel_context_create_request(ce); 37 37 if (IS_ERR(request)) 38 - return NULL; 38 + return request; 39 39 40 40 request->mock.delay = delay; 41 41 return request;
+82 -50
drivers/gpu/drm/panel/panel-simple.c
··· 26 26 #include <linux/i2c.h> 27 27 #include <linux/media-bus-format.h> 28 28 #include <linux/module.h> 29 + #include <linux/of_device.h> 29 30 #include <linux/of_platform.h> 30 31 #include <linux/platform_device.h> 31 32 #include <linux/pm_runtime.h> ··· 135 134 136 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 136 int connector_type; 137 + }; 138 + 139 + struct panel_desc_dsi { 140 + struct panel_desc desc; 141 + 142 + unsigned long flags; 143 + enum mipi_dsi_pixel_format format; 144 + unsigned int lanes; 138 145 }; 139 146 140 147 struct panel_simple { ··· 439 430 .get_timings = panel_simple_get_timings, 440 431 }; 441 432 442 - static struct panel_desc panel_dpi; 443 - 444 - static int panel_dpi_probe(struct device *dev, 445 - struct panel_simple *panel) 433 + static struct panel_desc *panel_dpi_probe(struct device *dev) 446 434 { 447 435 struct display_timing *timing; 448 436 const struct device_node *np; ··· 451 445 np = dev->of_node; 452 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 447 if (!desc) 454 - return -ENOMEM; 448 + return ERR_PTR(-ENOMEM); 455 449 456 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 451 if (!timing) 458 - return -ENOMEM; 452 + return ERR_PTR(-ENOMEM); 459 453 460 454 ret = of_get_display_timing(np, "panel-timing", timing); 461 455 if (ret < 0) { 462 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 457 np); 464 - return ret; 458 + return ERR_PTR(ret); 465 459 } 466 460 467 461 desc->timings = timing; ··· 479 473 /* We do not know the connector for the DT node, so guess it */ 480 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 475 482 - panel->desc = desc; 483 - 484 - return 0; 476 + return desc; 485 477 } 486 478 487 479 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ ··· 574 570 return 0; 575 571 } 576 572 577 - static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 573 + static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 574 { 575 + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 576 + dev_is_mipi_dsi(dev)) { 577 + const struct panel_desc_dsi *dsi_desc; 578 + 579 + dsi_desc = of_device_get_match_data(dev); 580 + if (!dsi_desc) 581 + return ERR_PTR(-ENODEV); 582 + 583 + return &dsi_desc->desc; 584 + } 585 + 586 + if (dev_is_platform(dev)) { 587 + const struct panel_desc *desc; 588 + 589 + desc = of_device_get_match_data(dev); 590 + if (!desc) { 591 + /* 592 + * panel-dpi probes without a descriptor and 593 + * panel_dpi_probe() will initialize one for us 594 + * based on the device tree. 595 + */ 596 + if (of_device_is_compatible(dev->of_node, "panel-dpi")) 597 + return panel_dpi_probe(dev); 598 + else 599 + return ERR_PTR(-ENODEV); 600 + } 601 + 602 + return desc; 603 + } 604 + 605 + return ERR_PTR(-ENODEV); 606 + } 607 + 608 + static struct panel_simple *panel_simple_probe(struct device *dev) 609 + { 610 + const struct panel_desc *desc; 579 611 struct panel_simple *panel; 580 612 struct display_timing dt; 581 613 struct device_node *ddc; ··· 619 579 u32 bus_flags; 620 580 int err; 621 581 582 + desc = panel_simple_get_desc(dev); 583 + if (IS_ERR(desc)) 584 + return ERR_CAST(desc); 585 + 622 586 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 623 587 &panel_simple_funcs, desc->connector_type); 624 588 if (IS_ERR(panel)) 625 - return PTR_ERR(panel); 589 + return ERR_CAST(panel); 626 590 627 591 panel->desc = desc; 628 592 629 593 panel->supply = devm_regulator_get(dev, "power"); 630 594 if (IS_ERR(panel->supply)) 631 - return PTR_ERR(panel->supply); 595 + return ERR_CAST(panel->supply); 632 596 633 597 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 634 598 GPIOD_OUT_LOW); 635 599 if (IS_ERR(panel->enable_gpio)) 636 - return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 637 - "failed to request GPIO\n"); 600 + return dev_err_cast_probe(dev, panel->enable_gpio, 601 + "failed to request GPIO\n"); 638 602 639 603 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 640 604 if (err) { 641 605 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 642 - return err; 606 + return ERR_PTR(err); 643 607 } 644 608 645 609 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); ··· 652 608 of_node_put(ddc); 653 609 654 610 if (!panel->ddc) 655 - return -EPROBE_DEFER; 611 + return ERR_PTR(-EPROBE_DEFER); 656 612 } 657 613 658 - if (desc == &panel_dpi) { 659 - /* Handle the generic panel-dpi binding */ 660 - err = panel_dpi_probe(dev, panel); 661 - if (err) 662 - goto free_ddc; 663 - desc = panel->desc; 664 - } else { 665 - if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 666 - panel_simple_parse_panel_timing_node(dev, panel, &dt); 667 - } 614 + if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 615 + !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 616 + panel_simple_parse_panel_timing_node(dev, panel, &dt); 668 617 669 618 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 670 619 /* Optional data-mapping property for overriding bus format */ ··· 740 703 741 704 drm_panel_add(&panel->base); 742 705 743 - return 0; 706 + return panel; 744 707 745 708 disable_pm_runtime: 746 709 pm_runtime_dont_use_autosuspend(dev); ··· 749 712 if (panel->ddc) 750 713 put_device(&panel->ddc->dev); 751 714 752 - return err; 715 + return ERR_PTR(err); 753 716 } 754 717 755 718 static void panel_simple_shutdown(struct device *dev) ··· 5404 5367 }, { 5405 5368 /* Must be the last entry */ 5406 5369 .compatible = "panel-dpi", 5407 - .data = &panel_dpi, 5370 + 5371 + /* 5372 + * Explicitly NULL, the panel_desc structure will be 5373 + * allocated by panel_dpi_probe(). 5374 + */ 5375 + .data = NULL, 5408 5376 }, { 5409 5377 /* sentinel */ 5410 5378 } ··· 5418 5376 5419 5377 static int panel_simple_platform_probe(struct platform_device *pdev) 5420 5378 { 5421 - const struct panel_desc *desc; 5379 + struct panel_simple *panel; 5422 5380 5423 - desc = of_device_get_match_data(&pdev->dev); 5424 - if (!desc) 5425 - return -ENODEV; 5381 + panel = panel_simple_probe(&pdev->dev); 5382 + if (IS_ERR(panel)) 5383 + return PTR_ERR(panel); 5426 5384 5427 - return panel_simple_probe(&pdev->dev, desc); 5385 + return 0; 5428 5386 } 5429 5387 5430 5388 static void panel_simple_platform_remove(struct platform_device *pdev) ··· 5452 5410 .probe = panel_simple_platform_probe, 5453 5411 .remove = panel_simple_platform_remove, 5454 5412 .shutdown = panel_simple_platform_shutdown, 5455 - }; 5456 - 5457 - struct panel_desc_dsi { 5458 - struct panel_desc desc; 5459 - 5460 - unsigned long flags; 5461 - enum mipi_dsi_pixel_format format; 5462 - unsigned int lanes; 5463 5413 }; 5464 5414 5465 5415 static const struct drm_display_mode auo_b080uan01_mode = { ··· 5687 5653 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5688 5654 { 5689 5655 const struct panel_desc_dsi *desc; 5656 + struct panel_simple *panel; 5690 5657 int err; 5691 5658 5692 - desc = of_device_get_match_data(&dsi->dev); 5693 - if (!desc) 5694 - return -ENODEV; 5659 + panel = panel_simple_probe(&dsi->dev); 5660 + if (IS_ERR(panel)) 5661 + return PTR_ERR(panel); 5695 5662 5696 - err = panel_simple_probe(&dsi->dev, &desc->desc); 5697 - if (err < 0) 5698 - return err; 5699 - 5663 + desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5700 5664 dsi->mode_flags = desc->flags; 5701 5665 dsi->format = desc->format; 5702 5666 dsi->lanes = desc->lanes;
+9 -4
drivers/gpu/drm/sysfb/vesadrm.c
··· 362 362 363 363 if (!__screen_info_vbe_mode_nonvga(si)) { 364 364 vesa->cmap_write = vesadrm_vga_cmap_write; 365 - #if defined(CONFIG_X86_32) 366 365 } else { 366 + #if defined(CONFIG_X86_32) 367 367 phys_addr_t pmi_base = __screen_info_vesapm_info_base(si); 368 - const u16 *pmi_addr = phys_to_virt(pmi_base); 369 368 370 - vesa->pmi.PrimaryPalette = (u8 *)pmi_addr + pmi_addr[2]; 371 - vesa->cmap_write = vesadrm_pmi_cmap_write; 369 + if (pmi_base) { 370 + const u16 *pmi_addr = phys_to_virt(pmi_base); 371 + 372 + vesa->pmi.PrimaryPalette = (u8 *)pmi_addr + pmi_addr[2]; 373 + vesa->cmap_write = vesadrm_pmi_cmap_write; 374 + } else 372 375 #endif 376 + if (format->is_color_indexed) 377 + drm_warn(dev, "hardware palette is unchangeable, colors may be incorrect\n"); 373 378 } 374 379 375 380 #ifdef CONFIG_X86
+7 -6
drivers/gpu/drm/ttm/ttm_bo_util.c
··· 254 254 ret = dma_resv_trylock(&fbo->base.base._resv); 255 255 WARN_ON(!ret); 256 256 257 + ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1); 258 + if (ret) { 259 + dma_resv_unlock(&fbo->base.base._resv); 260 + kfree(fbo); 261 + return ret; 262 + } 263 + 257 264 if (fbo->base.resource) { 258 265 ttm_resource_set_bo(fbo->base.resource, &fbo->base); 259 266 bo->resource = NULL; 260 267 ttm_bo_set_bulk_move(&fbo->base, NULL); 261 268 } else { 262 269 fbo->base.bulk_move = NULL; 263 - } 264 - 265 - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1); 266 - if (ret) { 267 - kfree(fbo); 268 - return ret; 269 270 } 270 271 271 272 ttm_bo_get(bo);
+8
drivers/gpu/drm/v3d/v3d_drv.h
··· 101 101 V3D_GEN_71 = 71, 102 102 }; 103 103 104 + enum v3d_irq { 105 + V3D_CORE_IRQ, 106 + V3D_HUB_IRQ, 107 + V3D_MAX_IRQS, 108 + }; 109 + 104 110 struct v3d_dev { 105 111 struct drm_device drm; 106 112 ··· 117 111 int rev; 118 112 119 113 bool single_irq_line; 114 + 115 + int irq[V3D_MAX_IRQS]; 120 116 121 117 struct v3d_perfmon_info perfmon_info; 122 118
+2
drivers/gpu/drm/v3d/v3d_gem.c
··· 134 134 if (false) 135 135 v3d_idle_axi(v3d, 0); 136 136 137 + v3d_irq_disable(v3d); 138 + 137 139 v3d_idle_gca(v3d); 138 140 v3d_reset_sms(v3d); 139 141 v3d_reset_v3d(v3d);
+27 -10
drivers/gpu/drm/v3d/v3d_irq.c
··· 260 260 int 261 261 v3d_irq_init(struct v3d_dev *v3d) 262 262 { 263 - int irq1, ret, core; 263 + int irq, ret, core; 264 264 265 265 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 266 266 ··· 271 271 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); 272 272 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); 273 273 274 - irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 275 - if (irq1 == -EPROBE_DEFER) 276 - return irq1; 277 - if (irq1 > 0) { 278 - ret = devm_request_irq(v3d->drm.dev, irq1, 274 + irq = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 275 + if (irq == -EPROBE_DEFER) 276 + return irq; 277 + if (irq > 0) { 278 + v3d->irq[V3D_CORE_IRQ] = irq; 279 + 280 + ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_CORE_IRQ], 279 281 v3d_irq, IRQF_SHARED, 280 282 "v3d_core0", v3d); 281 283 if (ret) 282 284 goto fail; 283 - ret = devm_request_irq(v3d->drm.dev, 284 - platform_get_irq(v3d_to_pdev(v3d), 0), 285 + 286 + irq = platform_get_irq(v3d_to_pdev(v3d), 0); 287 + if (irq < 0) 288 + return irq; 289 + v3d->irq[V3D_HUB_IRQ] = irq; 290 + 291 + ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_HUB_IRQ], 285 292 v3d_hub_irq, IRQF_SHARED, 286 293 "v3d_hub", v3d); 287 294 if (ret) ··· 296 289 } else { 297 290 v3d->single_irq_line = true; 298 291 299 - ret = devm_request_irq(v3d->drm.dev, 300 - platform_get_irq(v3d_to_pdev(v3d), 0), 292 + irq = platform_get_irq(v3d_to_pdev(v3d), 0); 293 + if (irq < 0) 294 + return irq; 295 + v3d->irq[V3D_CORE_IRQ] = irq; 296 + 297 + ret = devm_request_irq(v3d->drm.dev, v3d->irq[V3D_CORE_IRQ], 301 298 v3d_irq, IRQF_SHARED, 302 299 "v3d", v3d); 303 300 if (ret) ··· 341 330 for (core = 0; core < v3d->cores; core++) 342 331 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 343 332 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 333 + 334 + /* Finish any interrupt handler still in flight. */ 335 + for (int i = 0; i < V3D_MAX_IRQS; i++) { 336 + if (v3d->irq[i]) 337 + synchronize_irq(v3d->irq[i]); 338 + } 344 339 345 340 /* Clear any pending interrupts we might have left. */ 346 341 for (core = 0; core < v3d->cores; core++)
+1 -1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
··· 749 749 dev->fifo_mem = devm_memremap(dev->drm.dev, 750 750 fifo_start, 751 751 fifo_size, 752 - MEMREMAP_WB); 752 + MEMREMAP_WB | MEMREMAP_DEC); 753 753 754 754 if (IS_ERR(dev->fifo_mem)) { 755 755 drm_err(&dev->drm,
+5 -3
drivers/gpu/drm/xe/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 config DRM_XE 3 - tristate "Intel Xe Graphics" 4 - depends on DRM && PCI && (m || (y && KUNIT=y)) 3 + tristate "Intel Xe2 Graphics" 4 + depends on DRM && PCI 5 + depends on KUNIT || !KUNIT 5 6 depends on INTEL_VSEC || !INTEL_VSEC 6 7 depends on X86_PLATFORM_DEVICES || !(X86 && ACPI) 7 8 select INTERVAL_TREE ··· 47 46 select AUXILIARY_BUS 48 47 select HMM_MIRROR 49 48 help 50 - Experimental driver for Intel Xe series GPUs 49 + Driver for Intel Xe2 series GPUs and later. Experimental support 50 + for Xe series is also available. 51 51 52 52 If "M" is selected, the module will be called xe. 53 53
+44 -28
drivers/gpu/drm/xe/xe_device.c
··· 40 40 #include "xe_gt_printk.h" 41 41 #include "xe_gt_sriov_vf.h" 42 42 #include "xe_guc.h" 43 + #include "xe_guc_pc.h" 43 44 #include "xe_hw_engine_group.h" 44 45 #include "xe_hwmon.h" 45 46 #include "xe_irq.h" ··· 987 986 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); 988 987 } 989 988 990 - /** 991 - * xe_device_td_flush() - Flush transient L3 cache entries 992 - * @xe: The device 993 - * 994 - * Display engine has direct access to memory and is never coherent with L3/L4 995 - * caches (or CPU caches), however KMD is responsible for specifically flushing 996 - * transient L3 GPU cache entries prior to the flip sequence to ensure scanout 997 - * can happen from such a surface without seeing corruption. 998 - * 999 - * Display surfaces can be tagged as transient by mapping it using one of the 1000 - * various L3:XD PAT index modes on Xe2. 1001 - * 1002 - * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed 1003 - * at the end of each submission via PIPE_CONTROL for compute/render, since SA 1004 - * Media is not coherent with L3 and we want to support render-vs-media 1005 - * usescases. For other engines like copy/blt the HW internally forces uncached 1006 - * behaviour, hence why we can skip the TDF on such platforms. 989 + /* 990 + * Issue a TRANSIENT_FLUSH_REQUEST and wait for completion on each gt. 1007 991 */ 1008 - void xe_device_td_flush(struct xe_device *xe) 992 + static void tdf_request_sync(struct xe_device *xe) 1009 993 { 1010 - struct xe_gt *gt; 1011 994 unsigned int fw_ref; 995 + struct xe_gt *gt; 1012 996 u8 id; 1013 - 1014 - if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) 1015 - return; 1016 - 1017 - if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) { 1018 - xe_device_l2_flush(xe); 1019 - return; 1020 - } 1021 997 1022 998 for_each_gt(gt, xe, id) { 1023 999 if (xe_gt_is_media_type(gt)) ··· 1005 1027 return; 1006 1028 1007 1029 xe_mmio_write32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); 1030 + 1008 1031 /* 1009 1032 * FIXME: We can likely do better here with our choice of 1010 1033 * timeout. Currently we just assume the worst case, i.e. 150us, ··· 1036 1057 return; 1037 1058 1038 1059 spin_lock(&gt->global_invl_lock); 1039 - xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1); 1040 1060 1061 + xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1); 1041 1062 if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) 1042 1063 xe_gt_err_once(gt, "Global invalidation timeout\n"); 1064 + 1043 1065 spin_unlock(&gt->global_invl_lock); 1044 1066 1045 1067 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1068 + } 1069 + 1070 + /** 1071 + * xe_device_td_flush() - Flush transient L3 cache entries 1072 + * @xe: The device 1073 + * 1074 + * Display engine has direct access to memory and is never coherent with L3/L4 1075 + * caches (or CPU caches), however KMD is responsible for specifically flushing 1076 + * transient L3 GPU cache entries prior to the flip sequence to ensure scanout 1077 + * can happen from such a surface without seeing corruption. 1078 + * 1079 + * Display surfaces can be tagged as transient by mapping it using one of the 1080 + * various L3:XD PAT index modes on Xe2. 1081 + * 1082 + * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed 1083 + * at the end of each submission via PIPE_CONTROL for compute/render, since SA 1084 + * Media is not coherent with L3 and we want to support render-vs-media 1085 + * usescases. For other engines like copy/blt the HW internally forces uncached 1086 + * behaviour, hence why we can skip the TDF on such platforms. 1087 + */ 1088 + void xe_device_td_flush(struct xe_device *xe) 1089 + { 1090 + struct xe_gt *root_gt; 1091 + 1092 + if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) 1093 + return; 1094 + 1095 + root_gt = xe_root_mmio_gt(xe); 1096 + if (XE_WA(root_gt, 16023588340)) { 1097 + /* A transient flush is not sufficient: flush the L2 */ 1098 + xe_device_l2_flush(xe); 1099 + } else { 1100 + xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc); 1101 + tdf_request_sync(xe); 1102 + xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc); 1103 + } 1046 1104 } 1047 1105 1048 1106 u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
+1 -1
drivers/gpu/drm/xe/xe_drv.h
··· 9 9 #include <drm/drm_drv.h> 10 10 11 11 #define DRIVER_NAME "xe" 12 - #define DRIVER_DESC "Intel Xe Graphics" 12 + #define DRIVER_DESC "Intel Xe2 Graphics" 13 13 14 14 /* Interface history: 15 15 *
+217 -71
drivers/gpu/drm/xe/xe_guc_pc.c
··· 5 5 6 6 #include "xe_guc_pc.h" 7 7 8 + #include <linux/cleanup.h> 8 9 #include <linux/delay.h> 10 + #include <linux/jiffies.h> 9 11 #include <linux/ktime.h> 12 + #include <linux/wait_bit.h> 10 13 11 14 #include <drm/drm_managed.h> 12 15 #include <drm/drm_print.h> ··· 54 51 55 52 #define LNL_MERT_FREQ_CAP 800 56 53 #define BMG_MERT_FREQ_CAP 2133 54 + #define BMG_MIN_FREQ 1200 55 + #define BMG_MERT_FLUSH_FREQ_CAP 2600 57 56 58 57 #define SLPC_RESET_TIMEOUT_MS 5 /* roughly 5ms, but no need for precision */ 59 58 #define SLPC_RESET_EXTENDED_TIMEOUT_MS 1000 /* To be used only at pc_start */ 59 + #define SLPC_ACT_FREQ_TIMEOUT_MS 100 60 60 61 61 /** 62 62 * DOC: GuC Power Conservation (PC) ··· 147 141 return -ETIMEDOUT; 148 142 } 149 143 144 + static int wait_for_flush_complete(struct xe_guc_pc *pc) 145 + { 146 + const unsigned long timeout = msecs_to_jiffies(30); 147 + 148 + if (!wait_var_event_timeout(&pc->flush_freq_limit, 149 + !atomic_read(&pc->flush_freq_limit), 150 + timeout)) 151 + return -ETIMEDOUT; 152 + 153 + return 0; 154 + } 155 + 156 + static int wait_for_act_freq_limit(struct xe_guc_pc *pc, u32 freq) 157 + { 158 + int timeout_us = SLPC_ACT_FREQ_TIMEOUT_MS * USEC_PER_MSEC; 159 + int slept, wait = 10; 160 + 161 + for (slept = 0; slept < timeout_us;) { 162 + if (xe_guc_pc_get_act_freq(pc) <= freq) 163 + return 0; 164 + 165 + usleep_range(wait, wait << 1); 166 + slept += wait; 167 + wait <<= 1; 168 + if (slept + wait > timeout_us) 169 + wait = timeout_us - slept; 170 + } 171 + 172 + return -ETIMEDOUT; 173 + } 150 174 static int pc_action_reset(struct xe_guc_pc *pc) 151 175 { 152 176 struct xe_guc_ct *ct = pc_to_ct(pc); ··· 589 553 return pc->rpn_freq; 590 554 } 591 555 556 + static int xe_guc_pc_get_min_freq_locked(struct xe_guc_pc *pc, u32 *freq) 557 + { 558 + int ret; 559 + 560 + lockdep_assert_held(&pc->freq_lock); 561 + 562 + /* Might be in the middle of a gt reset */ 563 + if (!pc->freq_ready) 564 + return -EAGAIN; 565 + 566 + ret = pc_action_query_task_state(pc); 567 + if (ret) 568 + return ret; 569 + 570 + *freq = pc_get_min_freq(pc); 571 + 572 + return 0; 573 + } 574 + 592 575 /** 593 576 * xe_guc_pc_get_min_freq - Get the min operational frequency 594 577 * @pc: The GuC PC ··· 618 563 */ 619 564 int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq) 620 565 { 566 + guard(mutex)(&pc->freq_lock); 567 + 568 + return xe_guc_pc_get_min_freq_locked(pc, freq); 569 + } 570 + 571 + static int xe_guc_pc_set_min_freq_locked(struct xe_guc_pc *pc, u32 freq) 572 + { 621 573 int ret; 622 574 623 - xe_device_assert_mem_access(pc_to_xe(pc)); 575 + lockdep_assert_held(&pc->freq_lock); 624 576 625 - mutex_lock(&pc->freq_lock); 626 - if (!pc->freq_ready) { 627 - /* Might be in the middle of a gt reset */ 628 - ret = -EAGAIN; 629 - goto out; 630 - } 577 + /* Might be in the middle of a gt reset */ 578 + if (!pc->freq_ready) 579 + return -EAGAIN; 631 580 632 - ret = pc_action_query_task_state(pc); 581 + ret = pc_set_min_freq(pc, freq); 633 582 if (ret) 634 - goto out; 583 + return ret; 635 584 636 - *freq = pc_get_min_freq(pc); 585 + pc->user_requested_min = freq; 637 586 638 - out: 639 - mutex_unlock(&pc->freq_lock); 640 - return ret; 587 + return 0; 641 588 } 642 589 643 590 /** ··· 653 596 */ 654 597 int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) 655 598 { 599 + guard(mutex)(&pc->freq_lock); 600 + 601 + return xe_guc_pc_set_min_freq_locked(pc, freq); 602 + } 603 + 604 + static int xe_guc_pc_get_max_freq_locked(struct xe_guc_pc *pc, u32 *freq) 605 + { 656 606 int ret; 657 607 658 - mutex_lock(&pc->freq_lock); 659 - if (!pc->freq_ready) { 660 - /* Might be in the middle of a gt reset */ 661 - ret = -EAGAIN; 662 - goto out; 663 - } 608 + lockdep_assert_held(&pc->freq_lock); 664 609 665 - ret = pc_set_min_freq(pc, freq); 610 + /* Might be in the middle of a gt reset */ 611 + if (!pc->freq_ready) 612 + return -EAGAIN; 613 + 614 + ret = pc_action_query_task_state(pc); 666 615 if (ret) 667 - goto out; 616 + return ret; 668 617 669 - pc->user_requested_min = freq; 618 + *freq = pc_get_max_freq(pc); 670 619 671 - out: 672 - mutex_unlock(&pc->freq_lock); 673 - return ret; 620 + return 0; 674 621 } 675 622 676 623 /** ··· 687 626 */ 688 627 int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq) 689 628 { 629 + guard(mutex)(&pc->freq_lock); 630 + 631 + return xe_guc_pc_get_max_freq_locked(pc, freq); 632 + } 633 + 634 + static int xe_guc_pc_set_max_freq_locked(struct xe_guc_pc *pc, u32 freq) 635 + { 690 636 int ret; 691 637 692 - mutex_lock(&pc->freq_lock); 693 - if (!pc->freq_ready) { 694 - /* Might be in the middle of a gt reset */ 695 - ret = -EAGAIN; 696 - goto out; 697 - } 638 + lockdep_assert_held(&pc->freq_lock); 698 639 699 - ret = pc_action_query_task_state(pc); 640 + /* Might be in the middle of a gt reset */ 641 + if (!pc->freq_ready) 642 + return -EAGAIN; 643 + 644 + ret = pc_set_max_freq(pc, freq); 700 645 if (ret) 701 - goto out; 646 + return ret; 702 647 703 - *freq = pc_get_max_freq(pc); 648 + pc->user_requested_max = freq; 704 649 705 - out: 706 - mutex_unlock(&pc->freq_lock); 707 - return ret; 650 + return 0; 708 651 } 709 652 710 653 /** ··· 722 657 */ 723 658 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) 724 659 { 725 - int ret; 726 - 727 - mutex_lock(&pc->freq_lock); 728 - if (!pc->freq_ready) { 729 - /* Might be in the middle of a gt reset */ 730 - ret = -EAGAIN; 731 - goto out; 660 + if (XE_WA(pc_to_gt(pc), 22019338487)) { 661 + if (wait_for_flush_complete(pc) != 0) 662 + return -EAGAIN; 732 663 } 733 664 734 - ret = pc_set_max_freq(pc, freq); 735 - if (ret) 736 - goto out; 665 + guard(mutex)(&pc->freq_lock); 737 666 738 - pc->user_requested_max = freq; 739 - 740 - out: 741 - mutex_unlock(&pc->freq_lock); 742 - return ret; 667 + return xe_guc_pc_set_max_freq_locked(pc, freq); 743 668 } 744 669 745 670 /** ··· 872 817 873 818 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) 874 819 { 820 + struct xe_tile *tile = gt_to_tile(pc_to_gt(pc)); 875 821 int ret; 876 822 877 823 lockdep_assert_held(&pc->freq_lock); ··· 899 843 if (pc_get_min_freq(pc) > pc->rp0_freq) 900 844 ret = pc_set_min_freq(pc, pc->rp0_freq); 901 845 846 + if (XE_WA(tile->primary_gt, 14022085890)) 847 + ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc))); 848 + 902 849 out: 903 850 return ret; 904 851 } ··· 927 868 return ret; 928 869 } 929 870 930 - static int pc_set_mert_freq_cap(struct xe_guc_pc *pc) 871 + static bool needs_flush_freq_limit(struct xe_guc_pc *pc) 931 872 { 873 + struct xe_gt *gt = pc_to_gt(pc); 874 + 875 + return XE_WA(gt, 22019338487) && 876 + pc->rp0_freq > BMG_MERT_FLUSH_FREQ_CAP; 877 + } 878 + 879 + /** 880 + * xe_guc_pc_apply_flush_freq_limit() - Limit max GT freq during L2 flush 881 + * @pc: the xe_guc_pc object 882 + * 883 + * As per the WA, reduce max GT frequency during L2 cache flush 884 + */ 885 + void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc) 886 + { 887 + struct xe_gt *gt = pc_to_gt(pc); 888 + u32 max_freq; 889 + int ret; 890 + 891 + if (!needs_flush_freq_limit(pc)) 892 + return; 893 + 894 + guard(mutex)(&pc->freq_lock); 895 + 896 + ret = xe_guc_pc_get_max_freq_locked(pc, &max_freq); 897 + if (!ret && max_freq > BMG_MERT_FLUSH_FREQ_CAP) { 898 + ret = pc_set_max_freq(pc, BMG_MERT_FLUSH_FREQ_CAP); 899 + if (ret) { 900 + xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n", 901 + BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret)); 902 + return; 903 + } 904 + 905 + atomic_set(&pc->flush_freq_limit, 1); 906 + 907 + /* 908 + * If user has previously changed max freq, stash that value to 909 + * restore later, otherwise use the current max. New user 910 + * requests wait on flush. 911 + */ 912 + if (pc->user_requested_max != 0) 913 + pc->stashed_max_freq = pc->user_requested_max; 914 + else 915 + pc->stashed_max_freq = max_freq; 916 + } 917 + 918 + /* 919 + * Wait for actual freq to go below the flush cap: even if the previous 920 + * max was below cap, the current one might still be above it 921 + */ 922 + ret = wait_for_act_freq_limit(pc, BMG_MERT_FLUSH_FREQ_CAP); 923 + if (ret) 924 + xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n", 925 + BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret)); 926 + } 927 + 928 + /** 929 + * xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes. 930 + * @pc: the xe_guc_pc object 931 + * 932 + * Retrieve the previous GT max frequency value. 933 + */ 934 + void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc) 935 + { 936 + struct xe_gt *gt = pc_to_gt(pc); 932 937 int ret = 0; 933 938 934 - if (XE_WA(pc_to_gt(pc), 22019338487)) { 935 - /* 936 - * Get updated min/max and stash them. 937 - */ 938 - ret = xe_guc_pc_get_min_freq(pc, &pc->stashed_min_freq); 939 - if (!ret) 940 - ret = xe_guc_pc_get_max_freq(pc, &pc->stashed_max_freq); 941 - if (ret) 942 - return ret; 939 + if (!needs_flush_freq_limit(pc)) 940 + return; 943 941 944 - /* 945 - * Ensure min and max are bound by MERT_FREQ_CAP until driver loads. 946 - */ 947 - mutex_lock(&pc->freq_lock); 948 - ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc))); 949 - if (!ret) 950 - ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc))); 951 - mutex_unlock(&pc->freq_lock); 952 - } 942 + if (!atomic_read(&pc->flush_freq_limit)) 943 + return; 944 + 945 + mutex_lock(&pc->freq_lock); 946 + 947 + ret = pc_set_max_freq(&gt->uc.guc.pc, pc->stashed_max_freq); 948 + if (ret) 949 + xe_gt_err_once(gt, "Failed to restore max freq %u:%d", 950 + pc->stashed_max_freq, ret); 951 + 952 + atomic_set(&pc->flush_freq_limit, 0); 953 + mutex_unlock(&pc->freq_lock); 954 + wake_up_var(&pc->flush_freq_limit); 955 + } 956 + 957 + static int pc_set_mert_freq_cap(struct xe_guc_pc *pc) 958 + { 959 + int ret; 960 + 961 + if (!XE_WA(pc_to_gt(pc), 22019338487)) 962 + return 0; 963 + 964 + guard(mutex)(&pc->freq_lock); 965 + 966 + /* 967 + * Get updated min/max and stash them. 968 + */ 969 + ret = xe_guc_pc_get_min_freq_locked(pc, &pc->stashed_min_freq); 970 + if (!ret) 971 + ret = xe_guc_pc_get_max_freq_locked(pc, &pc->stashed_max_freq); 972 + if (ret) 973 + return ret; 974 + 975 + /* 976 + * Ensure min and max are bound by MERT_FREQ_CAP until driver loads. 977 + */ 978 + ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc))); 979 + if (!ret) 980 + ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc))); 953 981 954 982 return ret; 955 983 }
+2
drivers/gpu/drm/xe/xe_guc_pc.h
··· 38 38 void xe_guc_pc_init_early(struct xe_guc_pc *pc); 39 39 int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc); 40 40 void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc); 41 + void xe_guc_pc_apply_flush_freq_limit(struct xe_guc_pc *pc); 42 + void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc); 41 43 42 44 #endif /* _XE_GUC_PC_H_ */
+2
drivers/gpu/drm/xe/xe_guc_pc_types.h
··· 15 15 struct xe_guc_pc { 16 16 /** @bo: GGTT buffer object that is shared with GuC PC */ 17 17 struct xe_bo *bo; 18 + /** @flush_freq_limit: 1 when max freq changes are limited by driver */ 19 + atomic_t flush_freq_limit; 18 20 /** @rp0_freq: HW RP0 frequency - The Maximum one */ 19 21 u32 rp0_freq; 20 22 /** @rpa_freq: HW RPa frequency - The Achievable one */
+6 -4
drivers/gpu/drm/xe/xe_guc_submit.c
··· 891 891 struct xe_exec_queue *q = ge->q; 892 892 struct xe_guc *guc = exec_queue_to_guc(q); 893 893 struct xe_gpu_scheduler *sched = &ge->sched; 894 - bool wedged; 894 + bool wedged = false; 895 895 896 896 xe_gt_assert(guc_to_gt(guc), xe_exec_queue_is_lr(q)); 897 897 trace_xe_exec_queue_lr_cleanup(q); 898 898 899 - wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 899 + if (!exec_queue_killed(q)) 900 + wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 900 901 901 902 /* Kill the run_job / process_msg entry points */ 902 903 xe_sched_submission_stop(sched); ··· 1071 1070 int err = -ETIME; 1072 1071 pid_t pid = -1; 1073 1072 int i = 0; 1074 - bool wedged, skip_timeout_check; 1073 + bool wedged = false, skip_timeout_check; 1075 1074 1076 1075 /* 1077 1076 * TDR has fired before free job worker. Common if exec queue ··· 1117 1116 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are 1118 1117 * genuine timeouts. 1119 1118 */ 1120 - wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 1119 + if (!exec_queue_killed(q)) 1120 + wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 1121 1121 1122 1122 /* Engine state now stable, disable scheduling to check timestamp */ 1123 1123 if (!wedged && exec_queue_registered(q)) {
+19 -18
drivers/gpu/drm/xe/xe_lrc.c
··· 40 40 41 41 #define LRC_PPHWSP_SIZE SZ_4K 42 42 #define LRC_INDIRECT_RING_STATE_SIZE SZ_4K 43 + #define LRC_WA_BB_SIZE SZ_4K 43 44 44 45 static struct xe_device * 45 46 lrc_to_xe(struct xe_lrc *lrc) ··· 911 910 { 912 911 xe_hw_fence_ctx_finish(&lrc->fence_ctx); 913 912 xe_bo_unpin_map_no_vm(lrc->bo); 914 - xe_bo_unpin_map_no_vm(lrc->bb_per_ctx_bo); 913 + } 914 + 915 + static size_t wa_bb_offset(struct xe_lrc *lrc) 916 + { 917 + return lrc->bo->size - LRC_WA_BB_SIZE; 915 918 } 916 919 917 920 /* ··· 948 943 #define CONTEXT_ACTIVE 1ULL 949 944 static int xe_lrc_setup_utilization(struct xe_lrc *lrc) 950 945 { 946 + const size_t max_size = LRC_WA_BB_SIZE; 951 947 u32 *cmd, *buf = NULL; 952 948 953 - if (lrc->bb_per_ctx_bo->vmap.is_iomem) { 954 - buf = kmalloc(lrc->bb_per_ctx_bo->size, GFP_KERNEL); 949 + if (lrc->bo->vmap.is_iomem) { 950 + buf = kmalloc(max_size, GFP_KERNEL); 955 951 if (!buf) 956 952 return -ENOMEM; 957 953 cmd = buf; 958 954 } else { 959 - cmd = lrc->bb_per_ctx_bo->vmap.vaddr; 955 + cmd = lrc->bo->vmap.vaddr + wa_bb_offset(lrc); 960 956 } 961 957 962 958 *cmd++ = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET; ··· 980 974 *cmd++ = MI_BATCH_BUFFER_END; 981 975 982 976 if (buf) { 983 - xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bb_per_ctx_bo->vmap, 0, 984 - buf, (cmd - buf) * sizeof(*cmd)); 977 + xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bo->vmap, 978 + wa_bb_offset(lrc), buf, 979 + (cmd - buf) * sizeof(*cmd)); 985 980 kfree(buf); 986 981 } 987 982 988 - xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR, 989 - xe_bo_ggtt_addr(lrc->bb_per_ctx_bo) | 1); 983 + xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR, xe_bo_ggtt_addr(lrc->bo) + 984 + wa_bb_offset(lrc) + 1); 990 985 991 986 return 0; 992 987 } ··· 1025 1018 * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address 1026 1019 * via VM bind calls. 1027 1020 */ 1028 - lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, lrc_size, 1021 + lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, 1022 + lrc_size + LRC_WA_BB_SIZE, 1029 1023 ttm_bo_type_kernel, 1030 1024 bo_flags); 1031 1025 if (IS_ERR(lrc->bo)) 1032 1026 return PTR_ERR(lrc->bo); 1033 - 1034 - lrc->bb_per_ctx_bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4K, 1035 - ttm_bo_type_kernel, 1036 - bo_flags); 1037 - if (IS_ERR(lrc->bb_per_ctx_bo)) { 1038 - err = PTR_ERR(lrc->bb_per_ctx_bo); 1039 - goto err_lrc_finish; 1040 - } 1041 1027 1042 1028 lrc->size = lrc_size; 1043 1029 lrc->ring.size = ring_size; ··· 1819 1819 snapshot->seqno = xe_lrc_seqno(lrc); 1820 1820 snapshot->lrc_bo = xe_bo_get(lrc->bo); 1821 1821 snapshot->lrc_offset = xe_lrc_pphwsp_offset(lrc); 1822 - snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset; 1822 + snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset - 1823 + LRC_WA_BB_SIZE; 1823 1824 snapshot->lrc_snapshot = NULL; 1824 1825 snapshot->ctx_timestamp = lower_32_bits(xe_lrc_ctx_timestamp(lrc)); 1825 1826 snapshot->ctx_job_timestamp = xe_lrc_ctx_job_timestamp(lrc);
-3
drivers/gpu/drm/xe/xe_lrc_types.h
··· 53 53 54 54 /** @ctx_timestamp: readout value of CTX_TIMESTAMP on last update */ 55 55 u64 ctx_timestamp; 56 - 57 - /** @bb_per_ctx_bo: buffer object for per context batch wa buffer */ 58 - struct xe_bo *bb_per_ctx_bo; 59 56 }; 60 57 61 58 struct xe_lrc_snapshot;
+10 -8
drivers/gpu/drm/xe/xe_migrate.c
··· 82 82 * of the instruction. Subtracting the instruction header (1 dword) and 83 83 * address (2 dwords), that leaves 0x3FD dwords (0x1FE qwords) for PTE values. 84 84 */ 85 - #define MAX_PTE_PER_SDI 0x1FE 85 + #define MAX_PTE_PER_SDI 0x1FEU 86 86 87 87 /** 88 88 * xe_tile_migrate_exec_queue() - Get this tile's migrate exec queue. ··· 1553 1553 u64 entries = DIV_U64_ROUND_UP(size, XE_PAGE_SIZE); 1554 1554 1555 1555 XE_WARN_ON(size > MAX_PREEMPTDISABLE_TRANSFER); 1556 + 1556 1557 /* 1557 1558 * MI_STORE_DATA_IMM command is used to update page table. Each 1558 - * instruction can update maximumly 0x1ff pte entries. To update 1559 - * n (n <= 0x1ff) pte entries, we need: 1560 - * 1 dword for the MI_STORE_DATA_IMM command header (opcode etc) 1561 - * 2 dword for the page table's physical location 1562 - * 2*n dword for value of pte to fill (each pte entry is 2 dwords) 1559 + * instruction can update maximumly MAX_PTE_PER_SDI pte entries. To 1560 + * update n (n <= MAX_PTE_PER_SDI) pte entries, we need: 1561 + * 1562 + * - 1 dword for the MI_STORE_DATA_IMM command header (opcode etc) 1563 + * - 2 dword for the page table's physical location 1564 + * - 2*n dword for value of pte to fill (each pte entry is 2 dwords) 1563 1565 */ 1564 - num_dword = (1 + 2) * DIV_U64_ROUND_UP(entries, 0x1ff); 1566 + num_dword = (1 + 2) * DIV_U64_ROUND_UP(entries, MAX_PTE_PER_SDI); 1565 1567 num_dword += entries * 2; 1566 1568 1567 1569 return num_dword; ··· 1579 1577 1580 1578 ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE); 1581 1579 while (ptes) { 1582 - u32 chunk = min(0x1ffU, ptes); 1580 + u32 chunk = min(MAX_PTE_PER_SDI, ptes); 1583 1581 1584 1582 bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk); 1585 1583 bb->cs[bb->len++] = pt_offset;
+6 -1
drivers/gpu/drm/xe/xe_wa_oob.rules
··· 21 21 GRAPHICS_VERSION_RANGE(1270, 1274) 22 22 MEDIA_VERSION(1300) 23 23 PLATFORM(DG2) 24 - 14018094691 GRAPHICS_VERSION(2004) 24 + 14018094691 GRAPHICS_VERSION_RANGE(2001, 2002) 25 + GRAPHICS_VERSION(2004) 25 26 14019882105 GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0) 26 27 18024947630 GRAPHICS_VERSION(2001) 27 28 GRAPHICS_VERSION(2004) ··· 60 59 MEDIA_VERSION_RANGE(1301, 3000) 61 60 16026508708 GRAPHICS_VERSION_RANGE(1200, 3001) 62 61 MEDIA_VERSION_RANGE(1300, 3000) 62 + 63 + # SoC workaround - currently applies to all platforms with the following 64 + # primary GT GMDID 65 + 14022085890 GRAPHICS_VERSION(2001)
+3
include/drm/drm_mipi_dsi.h
··· 223 223 224 224 #define to_mipi_dsi_device(__dev) container_of_const(__dev, struct mipi_dsi_device, dev) 225 225 226 + extern const struct bus_type mipi_dsi_bus_type; 227 + #define dev_is_mipi_dsi(dev) ((dev)->bus == &mipi_dsi_bus_type) 228 + 226 229 /** 227 230 * mipi_dsi_pixel_format_to_bpp - obtain the number of bits per pixel for any 228 231 * given pixel format defined by the MIPI DSI
+3 -1
include/drm/spsc_queue.h
··· 70 70 71 71 preempt_disable(); 72 72 73 + atomic_inc(&queue->job_count); 74 + smp_mb__after_atomic(); 75 + 73 76 tail = (struct spsc_node **)atomic_long_xchg(&queue->tail, (long)&node->next); 74 77 WRITE_ONCE(*tail, node); 75 - atomic_inc(&queue->job_count); 76 78 77 79 /* 78 80 * In case of first element verify new node will be visible to the consumer