tjh.dev / kernel
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octeontx2-af: Sync NIX and NPA contexts from NDC to LLC/DRAM

Octeontx2 hardware uses Near Data Cache(NDC) block to cache
contexts in it so that access to LLC/DRAM can be avoided.
It is recommended in HRM to sync the NDC contents before
releasing/resetting LF resources. Hence implement NDC_SYNC
mailbox and sync contexts during driver teardown.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Nithin Dabilpuram and committed by
David S. Miller 42c45ac1 7433d034

+102 -3
+8
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
··· 139 139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140 140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141 141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142 + M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \ 142 143 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 143 144 msg_rsp) \ 144 145 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ ··· 1715 1714 u8 use_local_lmt_region; 1716 1715 u64 lmt_iova; 1717 1716 u64 rsvd[4]; 1717 + }; 1718 + 1719 + struct ndc_sync_op { 1720 + struct mbox_msghdr hdr; 1721 + u8 nix_lf_tx_sync; 1722 + u8 nix_lf_rx_sync; 1723 + u8 npa_lf_sync; 1718 1724 }; 1719 1725 1720 1726 /* CPT mailbox error codes
+66
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
··· 2014 2014 return 0; 2015 2015 } 2016 2016 2017 + int rvu_ndc_sync(struct rvu *rvu, int lfblkaddr, int lfidx, u64 lfoffset) 2018 + { 2019 + /* Sync cached info for this LF in NDC to LLC/DRAM */ 2020 + rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx); 2021 + return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true); 2022 + } 2023 + 2017 2024 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2018 2025 struct get_hw_cap_rsp *rsp) 2019 2026 { ··· 2070 2063 NIXLF_PROMISC_ENTRY, 2071 2064 false); 2072 2065 } 2066 + } 2067 + 2068 + return 0; 2069 + } 2070 + 2071 + int rvu_mbox_handler_ndc_sync_op(struct rvu *rvu, 2072 + struct ndc_sync_op *req, 2073 + struct msg_rsp *rsp) 2074 + { 2075 + struct rvu_hwinfo *hw = rvu->hw; 2076 + u16 pcifunc = req->hdr.pcifunc; 2077 + int err, lfidx, lfblkaddr; 2078 + 2079 + if (req->npa_lf_sync) { 2080 + /* Get NPA LF data */ 2081 + lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); 2082 + if (lfblkaddr < 0) 2083 + return NPA_AF_ERR_AF_LF_INVALID; 2084 + 2085 + lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2086 + if (lfidx < 0) 2087 + return NPA_AF_ERR_AF_LF_INVALID; 2088 + 2089 + /* Sync NPA NDC */ 2090 + err = rvu_ndc_sync(rvu, lfblkaddr, 2091 + lfidx, NPA_AF_NDC_SYNC); 2092 + if (err) 2093 + dev_err(rvu->dev, 2094 + "NDC-NPA sync failed for LF %u\n", lfidx); 2095 + } 2096 + 2097 + if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync) 2098 + return 0; 2099 + 2100 + /* Get NIX LF data */ 2101 + lfblkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2102 + if (lfblkaddr < 0) 2103 + return NIX_AF_ERR_AF_LF_INVALID; 2104 + 2105 + lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); 2106 + if (lfidx < 0) 2107 + return NIX_AF_ERR_AF_LF_INVALID; 2108 + 2109 + if (req->nix_lf_tx_sync) { 2110 + /* Sync NIX TX NDC */ 2111 + err = rvu_ndc_sync(rvu, lfblkaddr, 2112 + lfidx, NIX_AF_NDC_TX_SYNC); 2113 + if (err) 2114 + dev_err(rvu->dev, 2115 + "NDC-NIX-TX sync fail for LF %u\n", lfidx); 2116 + } 2117 + 2118 + if (req->nix_lf_rx_sync) { 2119 + /* Sync NIX RX NDC */ 2120 + err = rvu_ndc_sync(rvu, lfblkaddr, 2121 + lfidx, NIX_AF_NDC_RX_SYNC); 2122 + if (err) 2123 + dev_err(rvu->dev, 2124 + "NDC-NIX-RX sync failed for LF %u\n", lfidx); 2073 2125 } 2074 2126 2075 2127 return 0;
+1
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
··· 800 800 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 801 801 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 802 802 int rvu_get_num_lbk_chans(void); 803 + int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 803 804 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 804 805 u16 global_slot, u16 *slot_in_block); 805 806
+1 -3
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
··· 2497 2497 } 2498 2498 mutex_unlock(&rvu->rsrc_lock); 2499 2499 2500 - /* Sync cached info for this LF in NDC-TX to LLC/DRAM */ 2501 - rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); 2502 - err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); 2500 + err = rvu_ndc_sync(rvu, blkaddr, nixlf, NIX_AF_NDC_TX_SYNC); 2503 2501 if (err) 2504 2502 dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); 2505 2503
+2
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
··· 121 121 #define NPA_AF_LF_RST (0x0020) 122 122 #define NPA_AF_GEN_CFG (0x0030) 123 123 #define NPA_AF_NDC_CFG (0x0040) 124 + #define NPA_AF_NDC_SYNC (0x0050) 124 125 #define NPA_AF_INP_CTL (0x00D0) 125 126 #define NPA_AF_ACTIVE_CYCLES_PC (0x00F0) 126 127 #define NPA_AF_AVG_DELAY (0x0100) ··· 240 239 #define NIX_AF_RX_CPTX_INST_ADDR (0x0310) 241 240 #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3) 242 241 #define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3) 242 + #define NIX_AF_NDC_RX_SYNC (0x03E0) 243 243 #define NIX_AF_NDC_TX_SYNC (0x03F0) 244 244 #define NIX_AF_AQ_CFG (0x0400) 245 245 #define NIX_AF_AQ_BASE (0x0410)
+24
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
··· 3245 3245 return otx2_sriov_enable(pdev, numvfs); 3246 3246 } 3247 3247 3248 + static void otx2_ndc_sync(struct otx2_nic *pf) 3249 + { 3250 + struct mbox *mbox = &pf->mbox; 3251 + struct ndc_sync_op *req; 3252 + 3253 + mutex_lock(&mbox->lock); 3254 + 3255 + req = otx2_mbox_alloc_msg_ndc_sync_op(mbox); 3256 + if (!req) { 3257 + mutex_unlock(&mbox->lock); 3258 + return; 3259 + } 3260 + 3261 + req->nix_lf_tx_sync = 1; 3262 + req->nix_lf_rx_sync = 1; 3263 + req->npa_lf_sync = 1; 3264 + 3265 + if (!otx2_sync_mbox_msg(mbox)) 3266 + dev_err(pf->dev, "NDC sync operation failed\n"); 3267 + 3268 + mutex_unlock(&mbox->lock); 3269 + } 3270 + 3248 3271 static void otx2_remove(struct pci_dev *pdev) 3249 3272 { 3250 3273 struct net_device *netdev = pci_get_drvdata(pdev); ··· 3316 3293 otx2_mcam_flow_del(pf); 3317 3294 otx2_shutdown_tc(pf); 3318 3295 otx2_shutdown_qos(pf); 3296 + otx2_ndc_sync(pf); 3319 3297 otx2_detach_resources(&pf->mbox); 3320 3298 if (pf->hw.lmt_info) 3321 3299 free_percpu(pf->hw.lmt_info);