Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/ras: add read func for pmfw eeprom
add read func for pmfw eeprom, and adapt address converting
for bad pages loaded from pmfw eeprom
v2: change label 'Out' to 'out'
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gangliang Xie
and committed by
Alex Deucher
42c46be2
3972f41b
+101
-9
+1
drivers/gpu/drm/amd/ras/rascore/ras.h
+1
drivers/gpu/drm/amd/ras/rascore/ras.h
+4
-1
drivers/gpu/drm/amd/ras/rascore/ras_core.c
+4
-1
drivers/gpu/drm/amd/ras/rascore/ras_core.c
···
241
241
int count;
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int ret;
243
243
244
-
count = ras_eeprom_get_record_count(ras_core);
244
+
if (ras_fw_eeprom_supported(ras_core))
245
+
count = ras_fw_eeprom_get_record_count(ras_core);
246
+
else
247
+
count = ras_eeprom_get_record_count(ras_core);
245
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if (!count)
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return 0;
247
250
+70
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+70
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
···
259
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mutex_unlock(&control->ras_tbl_mutex);
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return 0;
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}
262
+
263
+
int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
264
+
struct eeprom_umc_record *record_umc,
265
+
struct ras_bank_ecc *ras_ecc,
266
+
u32 rec_idx, const u32 num)
267
+
{
268
+
struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
269
+
int i, ret, end_idx;
270
+
u64 mca, ipid, ts;
271
+
272
+
if (!ras_core->ras_umc.ip_func ||
273
+
!ras_core->ras_umc.ip_func->mca_ipid_parse)
274
+
return -EOPNOTSUPP;
275
+
276
+
mutex_lock(&control->ras_tbl_mutex);
277
+
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+
end_idx = rec_idx + num;
279
+
for (i = rec_idx; i < end_idx; i++) {
280
+
ret = ras_fw_get_badpage_mca_addr(ras_core, i, &mca);
281
+
if (ret)
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+
goto out;
283
+
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+
ret = ras_fw_get_badpage_ipid(ras_core, i, &ipid);
285
+
if (ret)
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+
goto out;
287
+
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+
ret = ras_fw_get_timestamp(ras_core, i, &ts);
289
+
if (ret)
290
+
goto out;
291
+
292
+
if (record_umc) {
293
+
record_umc[i - rec_idx].address = mca;
294
+
/* retired_page (pa) is unused now */
295
+
record_umc[i - rec_idx].retired_row_pfn = 0x1ULL;
296
+
record_umc[i - rec_idx].ts = ts;
297
+
record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE;
298
+
299
+
ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid,
300
+
(uint32_t *)&(record_umc[i - rec_idx].cu),
301
+
(uint32_t *)&(record_umc[i - rec_idx].mem_channel),
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+
(uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL);
303
+
304
+
/* update bad channel bitmap */
305
+
if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
306
+
!(control->bad_channel_bitmap & (1 << record_umc[i - rec_idx].mem_channel))) {
307
+
control->bad_channel_bitmap |= 1 << record_umc[i - rec_idx].mem_channel;
308
+
control->update_channel_flag = true;
309
+
}
310
+
}
311
+
312
+
if (ras_ecc) {
313
+
ras_ecc[i - rec_idx].addr = mca;
314
+
ras_ecc[i - rec_idx].ipid = ipid;
315
+
ras_ecc[i - rec_idx].ts = ts;
316
+
}
317
+
318
+
}
319
+
320
+
out:
321
+
mutex_unlock(&control->ras_tbl_mutex);
322
+
return ret;
323
+
}
324
+
325
+
uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core)
326
+
{
327
+
if (!ras_core)
328
+
return 0;
329
+
330
+
return ras_core->ras_fw_eeprom.ras_num_recs;
331
+
}
+5
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+5
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
···
70
70
bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
71
71
int ras_fw_eeprom_append(struct ras_core_context *ras_core,
72
72
struct eeprom_umc_record *record, const u32 num);
73
+
int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
74
+
struct eeprom_umc_record *record_umc,
75
+
struct ras_bank_ecc *ras_ecc,
76
+
u32 rec_idx, const u32 num);
77
+
uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
73
78
74
79
#endif
+20
-7
drivers/gpu/drm/amd/ras/rascore/ras_umc.c
+20
-7
drivers/gpu/drm/amd/ras/rascore/ras_umc.c
···
448
448
uint32_t ras_num_recs;
449
449
int ret;
450
450
451
-
ras_num_recs = ras_eeprom_get_record_count(ras_core);
452
-
/* no bad page record, skip eeprom access */
453
-
if (!ras_num_recs ||
454
-
ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
455
-
return 0;
451
+
if (ras_fw_eeprom_supported(ras_core)) {
452
+
ras_num_recs = ras_fw_eeprom_get_record_count(ras_core);
453
+
/* no bad page record, skip eeprom access */
454
+
if (!ras_num_recs ||
455
+
ras_core->ras_fw_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
456
+
return 0;
457
+
} else {
458
+
ras_num_recs = ras_eeprom_get_record_count(ras_core);
459
+
if (!ras_num_recs ||
460
+
ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
461
+
return 0;
462
+
}
456
463
457
464
bps = kzalloc_objs(*bps, ras_num_recs);
458
465
if (!bps)
459
466
return -ENOMEM;
460
467
461
-
ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
468
+
if (ras_fw_eeprom_supported(ras_core))
469
+
ret = ras_fw_eeprom_read_idx(ras_core, bps, 0, 0, ras_num_recs);
470
+
else
471
+
ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
462
472
if (ret) {
463
473
RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!");
464
474
} else {
···
496
486
if (!data->bps)
497
487
return 0;
498
488
499
-
eeprom_record_num = ras_eeprom_get_record_count(ras_core);
489
+
if (ras_fw_eeprom_supported(ras_core))
490
+
eeprom_record_num = ras_fw_eeprom_get_record_count(ras_core);
491
+
else
492
+
eeprom_record_num = ras_eeprom_get_record_count(ras_core);
500
493
mutex_lock(&ras_umc->umc_lock);
501
494
save_count = data->count - eeprom_record_num;
502
495
/* only new entries are saved */
+1
-1
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+1
-1
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
···
413
413
uint64_t pa = 0;
414
414
int ret = 0;
415
415
416
-
if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) {
416
+
if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) {
417
417
record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record);
418
418
} else {
419
419
ret = convert_eeprom_record_to_nps_addr(ras_core,