Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"The at91 power management code and the TI AM33 platform each get a few
updates for robustness, the other changes are just minor cleanups"
* tag 'soc-arm-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: versatile: clock: convert from round_rate() to determine_rate()
ARM: rockchip: remove REGULATOR conditional to PM
ARM: at91: pm: Remove 2.5V regulator
ARM: OMAP2+: clock: convert from round_rate() to determine_rate()
ARM: OMAP1: clock: convert from round_rate() to determine_rate()
ARM: mach-hpe: Rework support and directory structure
arm: omap2: use string choices helper
ARM: OMAP2+: pm33xx-core: ix device node reference leaks in amx3_idle_init
ARM: OMAP2+: use IS_ERR_OR_NULL() helper
ARM: AM33xx: Implement TI advisory 1.0.36 (EMU0/EMU1 pins state on reset)
ARM: at91: pm: save and restore ACR during PLL disable/enable
ARM: at91: pm: fix MCKx restore routine
ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs
ARM: shmobile: rcar-gen2: Use SZ_256K definition
+113
-111
-1
MAINTAINERS
-1
MAINTAINERS
···
2737
2737
F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
2738
2738
F: Documentation/hwmon/gxp-fan-ctrl.rst
2739
2739
F: arch/arm/boot/dts/hpe/
2740
-
F: arch/arm/mach-hpe/
2741
2740
F: drivers/clocksource/timer-gxp.c
2742
2741
F: drivers/hwmon/gxp-fan-ctrl.c
2743
2742
F: drivers/i2c/busses/i2c-gxp.c
-2
arch/arm/Kconfig
-2
arch/arm/Kconfig
+25
arch/arm/Kconfig.platforms
+25
arch/arm/Kconfig.platforms
···
87
87
help
88
88
Support for Alphascale ASM9260 based platform.
89
89
90
+
menuconfig ARCH_HPE
91
+
bool "HPE SoC support"
92
+
depends on ARCH_MULTI_V7
93
+
help
94
+
This enables support for HPE ARM based BMC chips.
95
+
96
+
if ARCH_HPE
97
+
98
+
config ARCH_HPE_GXP
99
+
bool "HPE GXP SoC"
100
+
depends on ARCH_MULTI_V7
101
+
select ARM_VIC
102
+
select GENERIC_IRQ_CHIP
103
+
select CLKSRC_MMIO
104
+
help
105
+
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
106
+
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
107
+
A9 core. It is capable of using an AXI bus to which a memory controller
108
+
is attached. It has multiple SPI interfaces to connect boot flash and
109
+
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
110
+
has multiple i2c engines to drive connectivity with a host
111
+
infrastructure.
112
+
113
+
endif
114
+
90
115
menuconfig ARCH_MOXART
91
116
bool "MOXA ART SoC"
92
117
depends on ARCH_MULTI_V4
-1
arch/arm/Makefile
-1
arch/arm/Makefile
···
189
189
machine-$(CONFIG_ARCH_GEMINI) += gemini
190
190
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
191
191
machine-$(CONFIG_ARCH_HISI) += hisi
192
-
machine-$(CONFIG_ARCH_HPE) += hpe
193
192
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
194
193
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
195
194
machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
+1
-1
arch/arm/mach-at91/pm.c
+1
-1
arch/arm/mach-at91/pm.c
+9
-32
arch/arm/mach-at91/pm_suspend.S
+9
-32
arch/arm/mach-at91/pm_suspend.S
···
87
87
88
88
.endm
89
89
90
-
/**
91
-
* Set state for 2.5V low power regulator
92
-
* @ena: 0 - disable regulator
93
-
* 1 - enable regulator
94
-
*
95
-
* Side effects: overwrites r7, r8, r9, r10
96
-
*/
97
-
.macro at91_2_5V_reg_set_low_power ena
98
-
#ifdef CONFIG_SOC_SAMA7
99
-
ldr r7, .sfrbu
100
-
mov r8, #\ena
101
-
ldr r9, [r7, #AT91_SFRBU_25LDOCR]
102
-
orr r9, r9, #AT91_SFRBU_25LDOCR_LP
103
-
cmp r8, #1
104
-
beq lp_done_\ena
105
-
bic r9, r9, #AT91_SFRBU_25LDOCR_LP
106
-
lp_done_\ena:
107
-
ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
108
-
orr r9, r9, r10
109
-
str r9, [r7, #AT91_SFRBU_25LDOCR]
110
-
#endif
111
-
.endm
112
-
113
90
.macro at91_backup_set_lpm reg
114
91
#ifdef CONFIG_SOC_SAMA7
115
92
orr \reg, \reg, #0x200000
···
666
689
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
667
690
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
668
691
692
+
/* save acr */
693
+
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
694
+
str tmp2, .saved_acr
695
+
669
696
/* save div. */
670
697
mov tmp1, #0
671
698
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
···
739
758
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
740
759
741
760
/* step 2. */
742
-
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
761
+
ldr tmp1, .saved_acr
743
762
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
744
763
745
764
/* step 3. */
···
885
904
/**
886
905
* at91_mckx_ps_restore: restore MCKx settings
887
906
*
888
-
* Side effects: overwrites tmp1, tmp2
907
+
* Side effects: overwrites tmp1, tmp2 and tmp3
889
908
*/
890
909
.macro at91_mckx_ps_restore
891
910
#ifdef CONFIG_SOC_SAMA7
···
961
980
bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
962
981
orr tmp3, tmp3, tmp1
963
982
orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
964
-
str tmp2, [pmc, #AT91_PMC_MCR_V2]
983
+
str tmp3, [pmc, #AT91_PMC_MCR_V2]
965
984
966
985
wait_mckrdy tmp1
967
986
···
1000
1019
1001
1020
at91_plla_disable
1002
1021
1003
-
/* Enable low power mode for 2.5V regulator. */
1004
-
at91_2_5V_reg_set_low_power 1
1005
-
1006
1022
ldr tmp3, .pm_mode
1007
1023
cmp tmp3, #AT91_PM_ULP1
1008
1024
beq ulp1_mode
···
1012
1034
b ulp_exit
1013
1035
1014
1036
ulp_exit:
1015
-
/* Disable low power mode for 2.5V regulator. */
1016
-
at91_2_5V_reg_set_low_power 0
1017
-
1018
1037
ldr pmc, .pmc_base
1019
1038
1020
1039
at91_plla_enable
···
1181
1206
.word 0
1182
1207
#endif
1183
1208
.saved_mckr:
1209
+
.word 0
1210
+
.saved_acr:
1184
1211
.word 0
1185
1212
.saved_pllar:
1186
1213
.word 0
-23
arch/arm/mach-hpe/Kconfig
-23
arch/arm/mach-hpe/Kconfig
···
1
-
menuconfig ARCH_HPE
2
-
bool "HPE SoC support"
3
-
depends on ARCH_MULTI_V7
4
-
help
5
-
This enables support for HPE ARM based BMC chips.
6
-
if ARCH_HPE
7
-
8
-
config ARCH_HPE_GXP
9
-
bool "HPE GXP SoC"
10
-
depends on ARCH_MULTI_V7
11
-
select ARM_VIC
12
-
select GENERIC_IRQ_CHIP
13
-
select CLKSRC_MMIO
14
-
help
15
-
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
16
-
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
17
-
A9 core. It is capable of using an AXI bus to which a memory controller
18
-
is attached. It has multiple SPI interfaces to connect boot flash and
19
-
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
20
-
has multiple i2c engines to drive connectivity with a host
21
-
infrastructure.
22
-
23
-
endif
-1
arch/arm/mach-hpe/Makefile
-1
arch/arm/mach-hpe/Makefile
···
1
-
obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o
-15
arch/arm/mach-hpe/gxp.c
-15
arch/arm/mach-hpe/gxp.c
···
1
-
// SPDX-License-Identifier: GPL-2.0
2
-
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
3
-
4
-
#include <asm/mach/arch.h>
5
-
6
-
static const char * const gxp_board_dt_compat[] = {
7
-
"hpe,gxp",
8
-
NULL,
9
-
};
10
-
11
-
DT_MACHINE_START(GXP_DT, "HPE GXP")
12
-
.dt_compat = gxp_board_dt_compat,
13
-
.l2c_aux_val = 0,
14
-
.l2c_aux_mask = ~0,
15
-
MACHINE_END
+13
-6
arch/arm/mach-omap1/clock.c
+13
-6
arch/arm/mach-omap1/clock.c
···
705
705
return clk->rate;
706
706
}
707
707
708
-
static long omap1_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *p_rate)
708
+
static int omap1_clk_determine_rate(struct clk_hw *hw,
709
+
struct clk_rate_request *req)
709
710
{
710
711
struct omap1_clk *clk = to_omap1_clk(hw);
711
712
712
-
if (clk->round_rate != NULL)
713
-
return clk->round_rate(clk, rate, p_rate);
713
+
if (clk->round_rate != NULL) {
714
+
req->rate = clk->round_rate(clk, req->rate,
715
+
&req->best_parent_rate);
714
716
715
-
return omap1_clk_recalc_rate(hw, *p_rate);
717
+
return 0;
718
+
}
719
+
720
+
req->rate = omap1_clk_recalc_rate(hw, req->best_parent_rate);
721
+
722
+
return 0;
716
723
}
717
724
718
725
static int omap1_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
···
778
771
779
772
const struct clk_ops omap1_clk_rate_ops = {
780
773
.recalc_rate = omap1_clk_recalc_rate,
781
-
.round_rate = omap1_clk_round_rate,
774
+
.determine_rate = omap1_clk_determine_rate,
782
775
.set_rate = omap1_clk_set_rate,
783
776
.init = omap1_clk_init_op,
784
777
};
···
791
784
.disable_unused = omap1_clk_disable_unused,
792
785
#endif
793
786
.recalc_rate = omap1_clk_recalc_rate,
794
-
.round_rate = omap1_clk_round_rate,
787
+
.determine_rate = omap1_clk_determine_rate,
795
788
.set_rate = omap1_clk_set_rate,
796
789
.init = omap1_clk_init_op,
797
790
};
+36
arch/arm/mach-omap2/am33xx-restart.c
+36
arch/arm/mach-omap2/am33xx-restart.c
···
2
2
/*
3
3
* am33xx-restart.c - Code common to all AM33xx machines.
4
4
*/
5
+
#include <dt-bindings/pinctrl/am33xx.h>
6
+
#include <linux/delay.h>
5
7
#include <linux/kernel.h>
6
8
#include <linux/reboot.h>
7
9
8
10
#include "common.h"
11
+
#include "control.h"
9
12
#include "prm.h"
13
+
14
+
/*
15
+
* Advisory 1.0.36 EMU0 and EMU1: Terminals Must be Pulled High Before
16
+
* ICEPick Samples
17
+
*
18
+
* If EMU0/EMU1 pins have been used as GPIO outputs and actively driving low
19
+
* level, the device might not reboot in normal mode. We are in a bad position
20
+
* to override GPIO state here, so just switch the pins into EMU input mode
21
+
* (that's what reset will do anyway) and wait a bit, because the state will be
22
+
* latched 190 ns after reset.
23
+
*/
24
+
static void am33xx_advisory_1_0_36(void)
25
+
{
26
+
u32 emu0 = omap_ctrl_readl(AM335X_PIN_EMU0);
27
+
u32 emu1 = omap_ctrl_readl(AM335X_PIN_EMU1);
28
+
29
+
/* If both pins are in EMU mode, nothing to do */
30
+
if (!(emu0 & 7) && !(emu1 & 7))
31
+
return;
32
+
33
+
/* Switch GPIO3_7/GPIO3_8 into EMU0/EMU1 modes respectively */
34
+
omap_ctrl_writel(emu0 & ~7, AM335X_PIN_EMU0);
35
+
omap_ctrl_writel(emu1 & ~7, AM335X_PIN_EMU1);
36
+
37
+
/*
38
+
* Give pull-ups time to load the pin/PCB trace capacity.
39
+
* 5 ms shall be enough to load 1 uF (would be huge capacity for these
40
+
* pins) with TI-recommended 4k7 external pull-ups.
41
+
*/
42
+
mdelay(5);
43
+
}
10
44
11
45
/**
12
46
* am33xx_restart - trigger a software restart of the SoC
···
52
18
*/
53
19
void am33xx_restart(enum reboot_mode mode, const char *cmd)
54
20
{
21
+
am33xx_advisory_1_0_36();
22
+
55
23
/* TODO: Handle cmd if necessary */
56
24
prm_reboot_mode = mode;
57
25
+1
-1
arch/arm/mach-omap2/board-n8x0.c
+1
-1
arch/arm/mach-omap2/board-n8x0.c
+7
-5
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+7
-5
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
···
70
70
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
71
71
* just uses the ARM rates.
72
72
*/
73
-
static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
74
-
unsigned long *parent_rate)
73
+
static int omap2_determine_rate_to_table(struct clk_hw *hw,
74
+
struct clk_rate_request *req)
75
75
{
76
76
const struct prcm_config *ptr;
77
77
long highest_rate;
···
87
87
highest_rate = ptr->mpu_speed;
88
88
89
89
/* Can check only after xtal frequency check */
90
-
if (ptr->mpu_speed <= rate)
90
+
if (ptr->mpu_speed <= req->rate)
91
91
break;
92
92
}
93
-
return highest_rate;
93
+
req->rate = highest_rate;
94
+
95
+
return 0;
94
96
}
95
97
96
98
/* Sets basic clocks based on the specified rate */
···
217
215
static const struct clk_ops virt_prcm_set_ops = {
218
216
.recalc_rate = &omap2_table_mpu_recalc,
219
217
.set_rate = &omap2_select_table_rate,
220
-
.round_rate = &omap2_round_to_table_rate,
218
+
.determine_rate = &omap2_determine_rate_to_table,
221
219
};
222
220
223
221
/**
+5
-1
arch/arm/mach-omap2/pm33xx-core.c
+5
-1
arch/arm/mach-omap2/pm33xx-core.c
···
388
388
if (!state_node)
389
389
break;
390
390
391
-
if (!of_device_is_available(state_node))
391
+
if (!of_device_is_available(state_node)) {
392
+
of_node_put(state_node);
392
393
continue;
394
+
}
393
395
394
396
if (i == CPUIDLE_STATE_MAX) {
395
397
pr_warn("%s: cpuidle states reached max possible\n",
396
398
__func__);
399
+
of_node_put(state_node);
397
400
break;
398
401
}
399
402
···
406
403
states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
407
404
WFI_FLAG_FLUSH_CACHE;
408
405
406
+
of_node_put(state_node);
409
407
state_count++;
410
408
}
411
409
+1
-1
arch/arm/mach-omap2/powerdomain.c
+1
-1
arch/arm/mach-omap2/powerdomain.c
+6
-6
arch/arm/mach-omap2/voltage.c
+6
-6
arch/arm/mach-omap2/voltage.c
···
51
51
*/
52
52
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
53
53
{
54
-
if (!voltdm || IS_ERR(voltdm)) {
54
+
if (IS_ERR_OR_NULL(voltdm)) {
55
55
pr_warn("%s: VDD specified does not exist!\n", __func__);
56
56
return 0;
57
57
}
···
73
73
int ret, i;
74
74
unsigned long volt = 0;
75
75
76
-
if (!voltdm || IS_ERR(voltdm)) {
76
+
if (IS_ERR_OR_NULL(voltdm)) {
77
77
pr_warn("%s: VDD specified does not exist!\n", __func__);
78
78
return -EINVAL;
79
79
}
···
124
124
{
125
125
unsigned long target_volt;
126
126
127
-
if (!voltdm || IS_ERR(voltdm)) {
127
+
if (IS_ERR_OR_NULL(voltdm)) {
128
128
pr_warn("%s: VDD specified does not exist!\n", __func__);
129
129
return;
130
130
}
···
154
154
void omap_voltage_get_volttable(struct voltagedomain *voltdm,
155
155
struct omap_volt_data **volt_data)
156
156
{
157
-
if (!voltdm || IS_ERR(voltdm)) {
157
+
if (IS_ERR_OR_NULL(voltdm)) {
158
158
pr_warn("%s: VDD specified does not exist!\n", __func__);
159
159
return;
160
160
}
···
182
182
{
183
183
int i;
184
184
185
-
if (!voltdm || IS_ERR(voltdm)) {
185
+
if (IS_ERR_OR_NULL(voltdm)) {
186
186
pr_warn("%s: VDD specified does not exist!\n", __func__);
187
187
return ERR_PTR(-EINVAL);
188
188
}
···
216
216
int omap_voltage_register_pmic(struct voltagedomain *voltdm,
217
217
struct omap_voltdm_pmic *pmic)
218
218
{
219
-
if (!voltdm || IS_ERR(voltdm)) {
219
+
if (IS_ERR_OR_NULL(voltdm)) {
220
220
pr_warn("%s: VDD specified does not exist!\n", __func__);
221
221
return -EINVAL;
222
222
}
+2
-2
arch/arm/mach-omap2/vp.c
+2
-2
arch/arm/mach-omap2/vp.c
···
199
199
struct omap_vp_instance *vp;
200
200
u32 vpconfig, volt;
201
201
202
-
if (!voltdm || IS_ERR(voltdm)) {
202
+
if (IS_ERR_OR_NULL(voltdm)) {
203
203
pr_warn("%s: VDD specified does not exist!\n", __func__);
204
204
return;
205
205
}
···
244
244
u32 vpconfig;
245
245
int timeout;
246
246
247
-
if (!voltdm || IS_ERR(voltdm)) {
247
+
if (IS_ERR_OR_NULL(voltdm)) {
248
248
pr_warn("%s: VDD specified does not exist!\n", __func__);
249
249
return;
250
250
}
+1
-1
arch/arm/mach-rockchip/Kconfig
+1
-1
arch/arm/mach-rockchip/Kconfig
+1
-1
arch/arm/mach-shmobile/pm-rcar-gen2.c
+1
-1
arch/arm/mach-shmobile/pm-rcar-gen2.c
+5
-4
arch/arm/mach-versatile/spc.c
+5
-4
arch/arm/mach-versatile/spc.c
···
497
497
return freq * 1000;
498
498
}
499
499
500
-
static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
501
-
unsigned long *parent_rate)
500
+
static int spc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
502
501
{
503
502
struct clk_spc *spc = to_clk_spc(hw);
504
503
505
-
return ve_spc_round_performance(spc->cluster, drate);
504
+
req->rate = ve_spc_round_performance(spc->cluster, req->rate);
505
+
506
+
return 0;
506
507
}
507
508
508
509
static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
···
516
515
517
516
static struct clk_ops clk_spc_ops = {
518
517
.recalc_rate = spc_recalc_rate,
519
-
.round_rate = spc_round_rate,
518
+
.determine_rate = spc_determine_rate,
520
519
.set_rate = spc_set_rate,
521
520
};
522
521
-7
include/soc/at91/sama7-sfrbu.h
-7
include/soc/at91/sama7-sfrbu.h
···
18
18
#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
19
19
#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
20
20
21
-
#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */
22
-
#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
23
-
#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */
24
-
#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */
25
-
#define AT91_SFRBU_PD_VALUE_MSK (0x3)
26
-
#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
27
-
28
21
#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
29
22
#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
30
23