Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
bnge/bng_re: Add a new HSI
The HSI is shared between the firmware and the driver and is
automatically generated.
Add a new HSI for the BNGE driver. The current HSI refers to BNXT,
which will become incompatible with ThorUltra devices as the
BNGE driver adds more features. The BNGE driver will not use the HSI
located in the bnxt folder.
Also, add an HSI for ThorUltra RoCE driver.
Changes in v3:
- Fix in bng_roce_hsi.h reported by Jakub (AI review)
https://lore.kernel.org/netdev/20260207051422.4181717-1-kuba@kernel.org/
- Add an entry in MAINTAINERS
Signed-off-by: Vikas Gupta <vikas.gupta@broadcom.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
Reviewed-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Link: https://patch.msgid.link/20260208172925.1861255-1-vikas.gupta@broadcom.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Vikas Gupta
and committed by
Paolo Abeni
42d1c54d
1abee69a
+19073
-13
+1
MAINTAINERS
+1
MAINTAINERS
+1
-1
drivers/infiniband/hw/bng_re/Makefile
+1
-1
drivers/infiniband/hw/bng_re/Makefile
+1
-1
drivers/infiniband/hw/bng_re/bng_fw.c
+1
-1
drivers/infiniband/hw/bng_re/bng_fw.c
+2
-2
drivers/infiniband/hw/bng_re/bng_res.c
+2
-2
drivers/infiniband/hw/bng_re/bng_res.c
+1
-1
drivers/infiniband/hw/bng_re/bng_res.h
+1
-1
drivers/infiniband/hw/bng_re/bng_res.h
+6450
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
+6450
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
···
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+
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2026 Broadcom */
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/* DO NOT MODIFY!!! This file is automatically generated. */
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#ifndef _BNG_RE_HSI_H_
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#define _BNG_RE_HSI_H_
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#include <linux/bnge/hsi.h>
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/* tx_doorbell (size:32b/4B) */
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struct tx_doorbell {
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__le32 key_idx;
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#define TX_DOORBELL_IDX_MASK 0xffffffUL
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#define TX_DOORBELL_IDX_SFT 0
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#define TX_DOORBELL_KEY_MASK 0xf0000000UL
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#define TX_DOORBELL_KEY_SFT 28
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#define TX_DOORBELL_KEY_TX (0x0UL << 28)
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#define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
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};
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/* rx_doorbell (size:32b/4B) */
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struct rx_doorbell {
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__le32 key_idx;
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#define RX_DOORBELL_IDX_MASK 0xffffffUL
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#define RX_DOORBELL_IDX_SFT 0
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#define RX_DOORBELL_KEY_MASK 0xf0000000UL
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#define RX_DOORBELL_KEY_SFT 28
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#define RX_DOORBELL_KEY_RX (0x1UL << 28)
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#define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
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};
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/* cmpl_doorbell (size:32b/4B) */
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struct cmpl_doorbell {
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__le32 key_mask_valid_idx;
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#define CMPL_DOORBELL_IDX_MASK 0xffffffUL
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#define CMPL_DOORBELL_IDX_SFT 0
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#define CMPL_DOORBELL_IDX_VALID 0x4000000UL
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#define CMPL_DOORBELL_MASK 0x8000000UL
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#define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
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#define CMPL_DOORBELL_KEY_SFT 28
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#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
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#define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL
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};
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/* status_doorbell (size:32b/4B) */
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struct status_doorbell {
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__le32 key_idx;
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#define STATUS_DOORBELL_IDX_MASK 0xffffffUL
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#define STATUS_DOORBELL_IDX_SFT 0
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#define STATUS_DOORBELL_KEY_MASK 0xf0000000UL
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#define STATUS_DOORBELL_KEY_SFT 28
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#define STATUS_DOORBELL_KEY_STAT (0x3UL << 28)
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#define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT
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};
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/* cmdq_init (size:128b/16B) */
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struct cmdq_init {
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__le64 cmdq_pbl;
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__le16 cmdq_size_cmdq_lvl;
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#define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL
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#define CMDQ_INIT_CMDQ_LVL_SFT 0
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#define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL
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#define CMDQ_INIT_CMDQ_SIZE_SFT 2
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__le16 creq_ring_id;
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__le32 prod_idx;
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};
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/* cmdq_base (size:128b/16B) */
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struct cmdq_base {
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u8 opcode;
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#define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL
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#define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL
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#define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL
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#define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL
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#define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL
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#define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL
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#define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL
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#define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL
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#define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL
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#define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL
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#define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL
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#define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL
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#define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL
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#define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL
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#define CMDQ_BASE_OPCODE_ADD_GID 0x11UL
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#define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL
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#define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL
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#define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL
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#define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL
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#define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL
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#define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL
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#define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL
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#define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL
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#define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL
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#define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL
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#define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL
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#define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL
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#define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL
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#define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL
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#define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL
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#define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL
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#define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED 0x89UL
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#define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL
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#define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL
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#define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL
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#define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL
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#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL
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#define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
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#define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL
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#define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL
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#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
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#define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION 0x93UL
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#define CMDQ_BASE_OPCODE_CREATE_QP_BATCH 0x94UL
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#define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH 0x95UL
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#define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL
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#define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL
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#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL
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#define CMDQ_BASE_OPCODE_PNO_STATS_CONFIG 0x99UL
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#define CMDQ_BASE_OPCODE_PNO_DEBUG_TUNNEL_CONFIG 0x9aUL
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#define CMDQ_BASE_OPCODE_SET_PNO_FABRIC_NEXTHOP_MAC 0x9bUL
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#define CMDQ_BASE_OPCODE_PNO_PATH_STRPATH_CONFIG 0x9cUL
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#define CMDQ_BASE_OPCODE_PNO_PATH_QUERY 0x9dUL
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#define CMDQ_BASE_OPCODE_PNO_PATH_ACCESS_CONTROL 0x9eUL
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#define CMDQ_BASE_OPCODE_QUERY_PNO_FABRIC_NEXTHOP_IP 0x9fUL
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#define CMDQ_BASE_OPCODE_PNO_PATH_PLANE_CONFIG 0xa0UL
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#define CMDQ_BASE_OPCODE_PNO_TUNNEL_CLOSE 0xa1UL
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#define CMDQ_BASE_OPCODE_PNO_HOST_PROCESSING_DONE 0xa2UL
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#define CMDQ_BASE_OPCODE_PNO_STATS_QPARAM 0xa3UL
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#define CMDQ_BASE_OPCODE_PATH_PROBE_CFG 0xa4UL
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#define CMDQ_BASE_OPCODE_PATH_PROBE_DISABLE 0xa5UL
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#define CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG 0xa6UL
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#define CMDQ_BASE_OPCODE_ROCE_CFG 0xa7UL
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#define CMDQ_BASE_OPCODE_PNO_EV_MONITORING_CONFIG 0xa8UL
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#define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_PNO_EV_MONITORING_CONFIG
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u8 cmd_size;
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__le16 flags;
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__le16 cookie;
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u8 resp_size;
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u8 reserved8;
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__le64 resp_addr;
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};
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/* creq_base (size:128b/16B) */
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struct creq_base {
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u8 type;
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#define CREQ_BASE_TYPE_MASK 0x3fUL
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#define CREQ_BASE_TYPE_SFT 0
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#define CREQ_BASE_TYPE_QP_EVENT 0x38UL
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#define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL
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#define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT
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u8 reserved56[7];
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u8 v;
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#define CREQ_BASE_V 0x1UL
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u8 event;
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u8 reserved48[6];
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};
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/* roce_stats_ext_ctx (size:1920b/240B) */
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struct roce_stats_ext_ctx {
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__le64 tx_atomic_req_pkts;
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__le64 tx_read_req_pkts;
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__le64 tx_read_res_pkts;
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__le64 tx_write_req_pkts;
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__le64 tx_rc_send_req_pkts;
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__le64 tx_ud_send_req_pkts;
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__le64 tx_cnp_pkts;
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__le64 tx_roce_pkts;
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__le64 tx_roce_bytes;
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__le64 rx_out_of_buffer_pkts;
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__le64 rx_out_of_sequence_pkts;
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__le64 dup_req;
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__le64 missing_resp;
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__le64 seq_err_naks_rcvd;
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__le64 rnr_naks_rcvd;
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__le64 to_retransmits;
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__le64 rx_atomic_req_pkts;
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__le64 rx_read_req_pkts;
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__le64 rx_read_res_pkts;
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__le64 rx_write_req_pkts;
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__le64 rx_rc_send_pkts;
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__le64 rx_ud_send_pkts;
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__le64 rx_dcn_payload_cut;
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__le64 rx_ecn_marked_pkts;
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__le64 rx_cnp_pkts;
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__le64 rx_roce_pkts;
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__le64 rx_roce_bytes;
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__le64 rx_roce_good_pkts;
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__le64 rx_roce_good_bytes;
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__le64 rx_ack_pkts;
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};
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/* cmdq_query_version (size:128b/16B) */
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struct cmdq_query_version {
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u8 opcode;
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#define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL
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#define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION
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u8 cmd_size;
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__le16 flags;
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__le16 cookie;
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u8 resp_size;
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u8 reserved8;
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__le64 resp_addr;
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};
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/* creq_query_version_resp (size:128b/16B) */
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struct creq_query_version_resp {
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u8 type;
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#define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL
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#define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
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#define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL
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#define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT
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u8 status;
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__le16 cookie;
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u8 fw_maj;
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u8 fw_minor;
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u8 fw_bld;
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u8 fw_rsvd;
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u8 v;
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#define CREQ_QUERY_VERSION_RESP_V 0x1UL
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u8 event;
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#define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL
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#define CREQ_QUERY_VERSION_RESP_EVENT_LAST CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION
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__le16 reserved16;
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u8 intf_maj;
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u8 intf_minor;
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u8 intf_bld;
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u8 intf_rsvd;
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};
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/* cmdq_initialize_fw (size:1024b/128B) */
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struct cmdq_initialize_fw {
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u8 opcode;
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#define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL
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#define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW
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u8 cmd_size;
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__le16 flags;
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#define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
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#define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL
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#define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION 0x4UL
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#define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED 0x8UL
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#define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT 0x10UL
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#define CMDQ_INITIALIZE_FW_FLAGS_DESTROY_CONTEXT_SB_SUPPORTED 0x20UL
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#define CMDQ_INITIALIZE_FW_FLAGS_DESTROY_UDCC_SESSION_DATA_SB_SUPPORTED 0x40UL
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#define CMDQ_INITIALIZE_FW_FLAGS_MIRROR_ON_ROCE_SUPPORTED 0x80UL
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__le16 cookie;
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u8 resp_size;
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u8 reserved8;
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__le64 resp_addr;
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u8 qpc_pg_size_qpc_lvl;
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#define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL
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#define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
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#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL
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#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL
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#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL
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#define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4)
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#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G
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u8 mrw_pg_size_mrw_lvl;
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#define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL
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#define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
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#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL
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#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL
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#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL
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#define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2
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#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL
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#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
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#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4)
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#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4)
277
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#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4)
278
+
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4)
279
+
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4)
280
+
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4)
281
+
#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G
282
+
u8 srq_pg_size_srq_lvl;
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+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL
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+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
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+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL
286
+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL
287
+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL
288
+
#define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2
289
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL
290
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
291
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
292
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
293
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
294
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
295
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
296
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
297
+
#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G
298
+
u8 cq_pg_size_cq_lvl;
299
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL
300
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
301
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL
302
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL
303
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL
304
+
#define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2
305
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL
306
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
307
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4)
308
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4)
309
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4)
310
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4)
311
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4)
312
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4)
313
+
#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G
314
+
u8 tqm_pg_size_tqm_lvl;
315
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL
316
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
317
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL
318
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL
319
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL
320
+
#define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2
321
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL
322
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
323
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4)
324
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4)
325
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4)
326
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4)
327
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4)
328
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4)
329
+
#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G
330
+
u8 tim_pg_size_tim_lvl;
331
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL
332
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
333
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL
334
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL
335
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL
336
+
#define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2
337
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL
338
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
339
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4)
340
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4)
341
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4)
342
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4)
343
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4)
344
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4)
345
+
#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G
346
+
__le16 log2_dbr_pg_size;
347
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL
348
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0
349
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL
350
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL
351
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL
352
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL
353
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL
354
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL
355
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL
356
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL
357
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL
358
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL
359
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL
360
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL
361
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL
362
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL
363
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL
364
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL
365
+
#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
366
+
#define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL
367
+
#define CMDQ_INITIALIZE_FW_RSVD_SFT 4
368
+
__le64 qpc_page_dir;
369
+
__le64 mrw_page_dir;
370
+
__le64 srq_page_dir;
371
+
__le64 cq_page_dir;
372
+
__le64 tqm_page_dir;
373
+
__le64 tim_page_dir;
374
+
__le32 number_of_qp;
375
+
__le32 number_of_mrw;
376
+
__le32 number_of_srq;
377
+
__le32 number_of_cq;
378
+
__le32 max_qp_per_vf;
379
+
__le32 max_mrw_per_vf;
380
+
__le32 max_srq_per_vf;
381
+
__le32 max_cq_per_vf;
382
+
__le32 max_gid_per_vf;
383
+
__le32 stat_ctx_id;
384
+
u8 drv_hsi_ver_maj;
385
+
u8 drv_hsi_ver_min;
386
+
u8 drv_hsi_ver_upd;
387
+
u8 unused40[5];
388
+
__le16 drv_build_ver_maj;
389
+
__le16 drv_build_ver_min;
390
+
__le16 drv_build_ver_upd;
391
+
__le16 drv_build_ver_patch;
392
+
};
393
+
394
+
/* creq_initialize_fw_resp (size:128b/16B) */
395
+
struct creq_initialize_fw_resp {
396
+
u8 type;
397
+
#define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
398
+
#define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
399
+
#define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
400
+
#define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT
401
+
u8 status;
402
+
__le16 cookie;
403
+
__le32 reserved32;
404
+
u8 v;
405
+
#define CREQ_INITIALIZE_FW_RESP_V 0x1UL
406
+
u8 event;
407
+
#define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL
408
+
#define CREQ_INITIALIZE_FW_RESP_EVENT_LAST CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW
409
+
u8 udcc_session_size;
410
+
u8 reserved40[5];
411
+
};
412
+
413
+
/* cmdq_deinitialize_fw (size:128b/16B) */
414
+
struct cmdq_deinitialize_fw {
415
+
u8 opcode;
416
+
#define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL
417
+
#define CMDQ_DEINITIALIZE_FW_OPCODE_LAST CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW
418
+
u8 cmd_size;
419
+
__le16 flags;
420
+
__le16 cookie;
421
+
u8 resp_size;
422
+
u8 reserved8;
423
+
__le64 resp_addr;
424
+
};
425
+
426
+
/* creq_deinitialize_fw_resp (size:128b/16B) */
427
+
struct creq_deinitialize_fw_resp {
428
+
u8 type;
429
+
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
430
+
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
431
+
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
432
+
#define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT
433
+
u8 status;
434
+
__le16 cookie;
435
+
__le32 reserved32;
436
+
u8 v;
437
+
#define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL
438
+
u8 event;
439
+
#define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL
440
+
#define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW
441
+
u8 reserved48[6];
442
+
};
443
+
444
+
/* cmdq_create_qp (size:1152b/144B) */
445
+
struct cmdq_create_qp {
446
+
u8 opcode;
447
+
#define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL
448
+
#define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP
449
+
u8 cmd_size;
450
+
__le16 flags;
451
+
__le16 cookie;
452
+
u8 resp_size;
453
+
u8 reserved8;
454
+
__le64 resp_addr;
455
+
__le64 qp_handle;
456
+
__le32 qp_flags;
457
+
#define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL
458
+
#define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL
459
+
#define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
460
+
#define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL
461
+
#define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
462
+
#define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL
463
+
#define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL
464
+
#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL
465
+
#define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL
466
+
#define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL
467
+
#define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL
468
+
#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID 0x800UL
469
+
#define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID 0x1000UL
470
+
#define CMDQ_CREATE_QP_QP_FLAGS_EROCE_VALID 0x2000UL
471
+
#define CMDQ_CREATE_QP_QP_FLAGS_RQ_PBL_PG_SIZE_VALID 0x4000UL
472
+
#define CMDQ_CREATE_QP_QP_FLAGS_SQ_PBL_PG_SIZE_VALID 0x8000UL
473
+
#define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_SQ_PBL_PG_SIZE_VALID
474
+
u8 type;
475
+
#define CMDQ_CREATE_QP_TYPE_RC 0x2UL
476
+
#define CMDQ_CREATE_QP_TYPE_UD 0x4UL
477
+
#define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
478
+
#define CMDQ_CREATE_QP_TYPE_GSI 0x7UL
479
+
#define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI
480
+
u8 sq_pg_size_sq_lvl;
481
+
#define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL
482
+
#define CMDQ_CREATE_QP_SQ_LVL_SFT 0
483
+
#define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL
484
+
#define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL
485
+
#define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL
486
+
#define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2
487
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL
488
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
489
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4)
490
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4)
491
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4)
492
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4)
493
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4)
494
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4)
495
+
#define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G
496
+
u8 rq_pg_size_rq_lvl;
497
+
#define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL
498
+
#define CMDQ_CREATE_QP_RQ_LVL_SFT 0
499
+
#define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL
500
+
#define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL
501
+
#define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL
502
+
#define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2
503
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL
504
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
505
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4)
506
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4)
507
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4)
508
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4)
509
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4)
510
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4)
511
+
#define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G
512
+
u8 unused_0;
513
+
__le32 dpi;
514
+
__le32 sq_size;
515
+
__le32 rq_size;
516
+
__le16 sq_fwo_sq_sge;
517
+
#define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL
518
+
#define CMDQ_CREATE_QP_SQ_SGE_SFT 0
519
+
#define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL
520
+
#define CMDQ_CREATE_QP_SQ_FWO_SFT 4
521
+
__le16 rq_fwo_rq_sge;
522
+
#define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL
523
+
#define CMDQ_CREATE_QP_RQ_SGE_SFT 0
524
+
#define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL
525
+
#define CMDQ_CREATE_QP_RQ_FWO_SFT 4
526
+
__le32 scq_cid;
527
+
__le32 rcq_cid;
528
+
__le32 srq_cid;
529
+
__le32 pd_id;
530
+
__le64 sq_pbl;
531
+
__le64 rq_pbl;
532
+
__le64 irrq_addr;
533
+
__le64 orrq_addr;
534
+
__le32 request_xid;
535
+
__le16 steering_tag;
536
+
__le16 sq_max_num_wqes;
537
+
__le32 ext_stats_ctx_id;
538
+
__le16 schq_id;
539
+
u8 sq_pbl_pg_size;
540
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_MASK 0xfUL
541
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_SFT 0
542
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_4K 0x0UL
543
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_8K 0x1UL
544
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_64K 0x2UL
545
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_2M 0x3UL
546
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_8M 0x4UL
547
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_1G 0x5UL
548
+
#define CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PBL_PG_SIZE_PG_1G
549
+
u8 rq_pbl_pg_size;
550
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_MASK 0xfUL
551
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_SFT 0
552
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_4K 0x0UL
553
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_8K 0x1UL
554
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_64K 0x2UL
555
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_2M 0x3UL
556
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_8M 0x4UL
557
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_1G 0x5UL
558
+
#define CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PBL_PG_SIZE_PG_1G
559
+
__le32 msn_iqp;
560
+
__le32 irrq_iqp;
561
+
__le32 orrq_iqp;
562
+
__le32 msn_size;
563
+
__le32 irrq_size;
564
+
__le32 orrq_size;
565
+
__le16 eroce;
566
+
#define CMDQ_CREATE_QP_EROCE_COS 0x1UL
567
+
#define CMDQ_CREATE_QP_EROCE_RESERVED_0_MASK 0xeUL
568
+
#define CMDQ_CREATE_QP_EROCE_RESERVED_0_SFT 1
569
+
#define CMDQ_CREATE_QP_EROCE_GRP_MASK 0xf0UL
570
+
#define CMDQ_CREATE_QP_EROCE_GRP_SFT 4
571
+
#define CMDQ_CREATE_QP_EROCE_CSIG_ENABLED 0x100UL
572
+
u8 reserved48[6];
573
+
};
574
+
575
+
/* creq_create_qp_resp (size:128b/16B) */
576
+
struct creq_create_qp_resp {
577
+
u8 type;
578
+
#define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL
579
+
#define CREQ_CREATE_QP_RESP_TYPE_SFT 0
580
+
#define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL
581
+
#define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT
582
+
u8 status;
583
+
__le16 cookie;
584
+
__le32 xid;
585
+
u8 v;
586
+
#define CREQ_CREATE_QP_RESP_V 0x1UL
587
+
u8 event;
588
+
#define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL
589
+
#define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP
590
+
u8 optimized_transmit_enabled;
591
+
u8 context_size;
592
+
u8 reserved32[4];
593
+
};
594
+
595
+
/* cmdq_destroy_qp (size:192b/24B) */
596
+
struct cmdq_destroy_qp {
597
+
u8 opcode;
598
+
#define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL
599
+
#define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP
600
+
u8 cmd_size;
601
+
__le16 flags;
602
+
__le16 cookie;
603
+
u8 resp_size;
604
+
u8 reserved8;
605
+
__le64 resp_addr;
606
+
__le32 qp_cid;
607
+
__le32 unused_0;
608
+
};
609
+
610
+
/* creq_destroy_qp_resp (size:128b/16B) */
611
+
struct creq_destroy_qp_resp {
612
+
u8 type;
613
+
#define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL
614
+
#define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
615
+
#define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL
616
+
#define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT
617
+
u8 status;
618
+
__le16 cookie;
619
+
__le32 xid;
620
+
u8 v;
621
+
#define CREQ_DESTROY_QP_RESP_V 0x1UL
622
+
u8 event;
623
+
#define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL
624
+
#define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP
625
+
__le16 udcc_session_id;
626
+
__le16 udcc_session_data_offset;
627
+
u8 flags;
628
+
#define CREQ_DESTROY_QP_RESP_FLAGS_UDCC_SESSION_DATA 0x1UL
629
+
#define CREQ_DESTROY_QP_RESP_FLAGS_UDCC_RTT_DATA 0x2UL
630
+
u8 udcc_session_data_size;
631
+
};
632
+
633
+
/* cmdq_modify_qp (size:1152b/144B) */
634
+
struct cmdq_modify_qp {
635
+
u8 opcode;
636
+
#define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL
637
+
#define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP
638
+
u8 cmd_size;
639
+
__le16 flags;
640
+
#define CMDQ_MODIFY_QP_FLAGS_SRQ_USED 0x1UL
641
+
#define CMDQ_MODIFY_QP_FLAGS_EXCLUDE_QP_UDCC 0x2UL
642
+
__le16 cookie;
643
+
u8 resp_size;
644
+
u8 qp_type;
645
+
#define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL
646
+
#define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL
647
+
#define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL
648
+
#define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL
649
+
#define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI
650
+
__le64 resp_addr;
651
+
__le32 modify_mask;
652
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL
653
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL
654
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL
655
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL
656
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL
657
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL
658
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL
659
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL
660
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL
661
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL
662
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL
663
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL
664
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL
665
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL
666
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL
667
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL
668
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL
669
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL
670
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL
671
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL
672
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL
673
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL
674
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL
675
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL
676
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL
677
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL
678
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL
679
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL
680
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL
681
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL
682
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL
683
+
#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL
684
+
__le32 qp_cid;
685
+
u8 network_type_en_sqd_async_notify_new_state;
686
+
#define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL
687
+
#define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
688
+
#define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL
689
+
#define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL
690
+
#define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL
691
+
#define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL
692
+
#define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL
693
+
#define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL
694
+
#define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL
695
+
#define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR
696
+
#define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL
697
+
#define CMDQ_MODIFY_QP_UNUSED1 0x20UL
698
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL
699
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
700
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6)
701
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6)
702
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6)
703
+
#define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6
704
+
u8 access;
705
+
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
706
+
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
707
+
#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL
708
+
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL
709
+
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL
710
+
#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL
711
+
__le16 pkey;
712
+
__le32 qkey;
713
+
__le32 dgid[4];
714
+
__le32 flow_label;
715
+
__le16 sgid_index;
716
+
u8 hop_limit;
717
+
u8 traffic_class;
718
+
__le16 dest_mac[3];
719
+
u8 tos_dscp_tos_ecn;
720
+
#define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL
721
+
#define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
722
+
#define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL
723
+
#define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
724
+
u8 path_mtu_pingpong_push_enable;
725
+
#define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL
726
+
#define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL
727
+
#define CMDQ_MODIFY_QP_UNUSED3_SFT 1
728
+
#define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL
729
+
#define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
730
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4)
731
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4)
732
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4)
733
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4)
734
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4)
735
+
#define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4)
736
+
#define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192
737
+
u8 timeout;
738
+
u8 retry_cnt;
739
+
u8 rnr_retry;
740
+
u8 min_rnr_timer;
741
+
__le32 rq_psn;
742
+
__le32 sq_psn;
743
+
u8 max_rd_atomic;
744
+
u8 max_dest_rd_atomic;
745
+
__le16 enable_cc;
746
+
#define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL
747
+
#define CMDQ_MODIFY_QP_ENH_MODE_MASK 0x6UL
748
+
#define CMDQ_MODIFY_QP_ENH_MODE_SFT 1
749
+
#define CMDQ_MODIFY_QP_ENH_COS 0x8UL
750
+
#define CMDQ_MODIFY_QP_ENH_GRP_MASK 0xf0UL
751
+
#define CMDQ_MODIFY_QP_ENH_GRP_SFT 4
752
+
#define CMDQ_MODIFY_QP_UNUSED8_MASK 0xff00UL
753
+
#define CMDQ_MODIFY_QP_UNUSED8_SFT 8
754
+
__le32 sq_size;
755
+
__le32 rq_size;
756
+
__le16 sq_sge;
757
+
__le16 rq_sge;
758
+
__le32 max_inline_data;
759
+
__le32 dest_qp_id;
760
+
__le32 pingpong_push_dpi;
761
+
__le16 src_mac[3];
762
+
__le16 vlan_pcp_vlan_dei_vlan_id;
763
+
#define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL
764
+
#define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
765
+
#define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL
766
+
#define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL
767
+
#define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
768
+
__le64 irrq_addr;
769
+
__le64 orrq_addr;
770
+
__le32 ext_modify_mask;
771
+
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL
772
+
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL
773
+
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_UDP_SRC_PORT_VALID 0x4UL
774
+
#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID 0x8UL
775
+
__le32 ext_stats_ctx_id;
776
+
__le16 schq_id;
777
+
__le16 udp_src_port;
778
+
__le32 rate_limit;
779
+
};
780
+
781
+
/* creq_modify_qp_resp (size:128b/16B) */
782
+
struct creq_modify_qp_resp {
783
+
u8 type;
784
+
#define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL
785
+
#define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
786
+
#define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL
787
+
#define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT
788
+
u8 status;
789
+
__le16 cookie;
790
+
__le32 xid;
791
+
u8 v;
792
+
#define CREQ_MODIFY_QP_RESP_V 0x1UL
793
+
u8 event;
794
+
#define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL
795
+
#define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP
796
+
u8 pingpong_push_state_index_enabled;
797
+
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL
798
+
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL
799
+
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1
800
+
#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL
801
+
u8 shaper_allocation_status;
802
+
#define CREQ_MODIFY_QP_RESP_SHAPER_ALLOCATED 0x1UL
803
+
__le16 flags;
804
+
#define CREQ_MODIFY_QP_RESP_SESSION_ELIGIBLE 0x1UL
805
+
__le16 reserved16;
806
+
};
807
+
808
+
/* cmdq_query_qp (size:192b/24B) */
809
+
struct cmdq_query_qp {
810
+
u8 opcode;
811
+
#define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL
812
+
#define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP
813
+
u8 cmd_size;
814
+
__le16 flags;
815
+
__le16 cookie;
816
+
u8 resp_size;
817
+
u8 reserved8;
818
+
__le64 resp_addr;
819
+
__le32 qp_cid;
820
+
__le32 unused_0;
821
+
};
822
+
823
+
/* creq_query_qp_resp (size:128b/16B) */
824
+
struct creq_query_qp_resp {
825
+
u8 type;
826
+
#define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL
827
+
#define CREQ_QUERY_QP_RESP_TYPE_SFT 0
828
+
#define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL
829
+
#define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT
830
+
u8 status;
831
+
__le16 cookie;
832
+
__le32 size;
833
+
u8 v;
834
+
#define CREQ_QUERY_QP_RESP_V 0x1UL
835
+
u8 event;
836
+
#define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL
837
+
#define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP
838
+
u8 reserved48[6];
839
+
};
840
+
841
+
/* creq_query_qp_resp_sb (size:896b/112B) */
842
+
struct creq_query_qp_resp_sb {
843
+
u8 opcode;
844
+
#define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL
845
+
#define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP
846
+
u8 status;
847
+
__le16 cookie;
848
+
__le16 flags;
849
+
u8 resp_size;
850
+
u8 reserved8;
851
+
__le32 xid;
852
+
u8 en_sqd_async_notify_state;
853
+
#define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL
854
+
#define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
855
+
#define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL
856
+
#define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL
857
+
#define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL
858
+
#define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL
859
+
#define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL
860
+
#define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL
861
+
#define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL
862
+
#define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR
863
+
#define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL
864
+
#define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL
865
+
#define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5
866
+
u8 access;
867
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
868
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
869
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL
870
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL
871
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL
872
+
#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL
873
+
__le16 pkey;
874
+
__le32 qkey;
875
+
__le16 udp_src_port;
876
+
__le16 reserved16;
877
+
__le32 dgid[4];
878
+
__le32 flow_label;
879
+
__le16 sgid_index;
880
+
u8 hop_limit;
881
+
u8 traffic_class;
882
+
__le16 dest_mac[3];
883
+
__le16 path_mtu_dest_vlan_id;
884
+
#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL
885
+
#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
886
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL
887
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
888
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12)
889
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12)
890
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12)
891
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12)
892
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12)
893
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12)
894
+
#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192
895
+
u8 timeout;
896
+
u8 retry_cnt;
897
+
u8 rnr_retry;
898
+
u8 min_rnr_timer;
899
+
__le32 rq_psn;
900
+
__le32 sq_psn;
901
+
u8 max_rd_atomic;
902
+
u8 max_dest_rd_atomic;
903
+
u8 tos_dscp_tos_ecn;
904
+
#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL
905
+
#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
906
+
#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL
907
+
#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
908
+
u8 enable_cc;
909
+
#define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL
910
+
__le32 sq_size;
911
+
__le32 rq_size;
912
+
__le16 sq_sge;
913
+
__le16 rq_sge;
914
+
__le32 max_inline_data;
915
+
__le32 dest_qp_id;
916
+
__le16 port_id;
917
+
u8 unused_0;
918
+
u8 stat_collection_id;
919
+
__le16 src_mac[3];
920
+
__le16 vlan_pcp_vlan_dei_vlan_id;
921
+
#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL
922
+
#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
923
+
#define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL
924
+
#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL
925
+
#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
926
+
__le32 rate_limit;
927
+
__le32 reserved32;
928
+
};
929
+
930
+
/* cmdq_query_qp_extend (size:192b/24B) */
931
+
struct cmdq_query_qp_extend {
932
+
u8 opcode;
933
+
#define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL
934
+
#define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND
935
+
u8 cmd_size;
936
+
__le16 flags;
937
+
__le16 cookie;
938
+
u8 resp_size;
939
+
u8 num_qps;
940
+
__le64 resp_addr;
941
+
__le32 function_id;
942
+
#define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL
943
+
#define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0
944
+
#define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL
945
+
#define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8
946
+
#define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL
947
+
__le32 current_index;
948
+
};
949
+
950
+
/* creq_query_qp_extend_resp (size:128b/16B) */
951
+
struct creq_query_qp_extend_resp {
952
+
u8 type;
953
+
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL
954
+
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0
955
+
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL
956
+
#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT
957
+
u8 status;
958
+
__le16 cookie;
959
+
__le32 size;
960
+
u8 v;
961
+
#define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL
962
+
u8 event;
963
+
#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL
964
+
#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND
965
+
__le16 reserved16;
966
+
__le32 current_index;
967
+
};
968
+
969
+
/* creq_query_qp_extend_resp_sb (size:384b/48B) */
970
+
struct creq_query_qp_extend_resp_sb {
971
+
u8 opcode;
972
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL
973
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND
974
+
u8 status;
975
+
__le16 cookie;
976
+
__le16 flags;
977
+
u8 resp_size;
978
+
u8 reserved8;
979
+
__le32 xid;
980
+
u8 state;
981
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL
982
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0
983
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL
984
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL
985
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL
986
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL
987
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL
988
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL
989
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL
990
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR
991
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL
992
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4
993
+
u8 reserved_8;
994
+
__le16 port_id;
995
+
__le32 qkey;
996
+
__le16 sgid_index;
997
+
u8 network_type;
998
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL
999
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
1000
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
1001
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6
1002
+
u8 unused_0;
1003
+
__le32 dgid[4];
1004
+
__le32 dest_qp_id;
1005
+
u8 stat_collection_id;
1006
+
u8 reserved2_8;
1007
+
__le16 reserved_16;
1008
+
};
1009
+
1010
+
/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */
1011
+
struct creq_query_qp_extend_resp_sb_tlv {
1012
+
__le16 cmd_discr;
1013
+
u8 reserved_8b;
1014
+
u8 tlv_flags;
1015
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
1016
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
1017
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
1018
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
1019
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
1020
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
1021
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
1022
+
__le16 tlv_type;
1023
+
__le16 length;
1024
+
u8 total_size;
1025
+
u8 reserved56[7];
1026
+
u8 opcode;
1027
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL
1028
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND
1029
+
u8 status;
1030
+
__le16 cookie;
1031
+
__le16 flags;
1032
+
u8 resp_size;
1033
+
u8 reserved8;
1034
+
__le32 xid;
1035
+
u8 state;
1036
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL
1037
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0
1038
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL
1039
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL
1040
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL
1041
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL
1042
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL
1043
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL
1044
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL
1045
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR
1046
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL
1047
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4
1048
+
u8 reserved_8;
1049
+
__le16 port_id;
1050
+
__le32 qkey;
1051
+
__le16 sgid_index;
1052
+
u8 network_type;
1053
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL
1054
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
1055
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
1056
+
#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6
1057
+
u8 unused_0;
1058
+
__le32 dgid[4];
1059
+
__le32 dest_qp_id;
1060
+
u8 stat_collection_id;
1061
+
u8 reserved2_8;
1062
+
__le16 reserved_16;
1063
+
};
1064
+
1065
+
/* cmdq_create_srq (size:512b/64B) */
1066
+
struct cmdq_create_srq {
1067
+
u8 opcode;
1068
+
#define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL
1069
+
#define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ
1070
+
u8 cmd_size;
1071
+
__le16 flags;
1072
+
#define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL
1073
+
#define CMDQ_CREATE_SRQ_FLAGS_PBL_PG_SIZE_VALID 0x2UL
1074
+
__le16 cookie;
1075
+
u8 resp_size;
1076
+
u8 reserved8;
1077
+
__le64 resp_addr;
1078
+
__le64 srq_handle;
1079
+
__le16 pg_size_lvl;
1080
+
#define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL
1081
+
#define CMDQ_CREATE_SRQ_LVL_SFT 0
1082
+
#define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL
1083
+
#define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL
1084
+
#define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL
1085
+
#define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2
1086
+
#define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL
1087
+
#define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
1088
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2)
1089
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2)
1090
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2)
1091
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2)
1092
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2)
1093
+
#define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2)
1094
+
#define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G
1095
+
#define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL
1096
+
#define CMDQ_CREATE_SRQ_UNUSED11_SFT 5
1097
+
__le16 eventq_id;
1098
+
#define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL
1099
+
#define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
1100
+
#define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL
1101
+
#define CMDQ_CREATE_SRQ_UNUSED4_SFT 12
1102
+
__le16 srq_size;
1103
+
__le16 srq_fwo;
1104
+
#define CMDQ_CREATE_SRQ_SRQ_FWO_MASK 0xfffUL
1105
+
#define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0
1106
+
#define CMDQ_CREATE_SRQ_SRQ_SGE_MASK 0xf000UL
1107
+
#define CMDQ_CREATE_SRQ_SRQ_SGE_SFT 12
1108
+
__le32 dpi;
1109
+
__le32 pd_id;
1110
+
__le64 pbl;
1111
+
__le16 steering_tag;
1112
+
u8 pbl_pg_size;
1113
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_MASK 0x7UL
1114
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_SFT 0
1115
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_4K 0x0UL
1116
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_8K 0x1UL
1117
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_64K 0x2UL
1118
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_2M 0x3UL
1119
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_8M 0x4UL
1120
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_1G 0x5UL
1121
+
#define CMDQ_CREATE_SRQ_PBL_PG_SIZE_LAST CMDQ_CREATE_SRQ_PBL_PG_SIZE_PG_1G
1122
+
u8 reserved40[5];
1123
+
__le64 reserved64;
1124
+
};
1125
+
1126
+
/* creq_create_srq_resp (size:128b/16B) */
1127
+
struct creq_create_srq_resp {
1128
+
u8 type;
1129
+
#define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL
1130
+
#define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
1131
+
#define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1132
+
#define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT
1133
+
u8 status;
1134
+
__le16 cookie;
1135
+
__le32 xid;
1136
+
u8 v;
1137
+
#define CREQ_CREATE_SRQ_RESP_V 0x1UL
1138
+
u8 event;
1139
+
#define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL
1140
+
#define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ
1141
+
u8 context_size;
1142
+
u8 reserved48[5];
1143
+
};
1144
+
1145
+
/* cmdq_destroy_srq (size:192b/24B) */
1146
+
struct cmdq_destroy_srq {
1147
+
u8 opcode;
1148
+
#define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL
1149
+
#define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ
1150
+
u8 cmd_size;
1151
+
__le16 flags;
1152
+
__le16 cookie;
1153
+
u8 resp_size;
1154
+
u8 reserved8;
1155
+
__le64 resp_addr;
1156
+
__le32 srq_cid;
1157
+
__le32 unused_0;
1158
+
};
1159
+
1160
+
/* creq_destroy_srq_resp (size:128b/16B) */
1161
+
struct creq_destroy_srq_resp {
1162
+
u8 type;
1163
+
#define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL
1164
+
#define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
1165
+
#define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1166
+
#define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT
1167
+
u8 status;
1168
+
__le16 cookie;
1169
+
__le32 xid;
1170
+
u8 v;
1171
+
#define CREQ_DESTROY_SRQ_RESP_V 0x1UL
1172
+
u8 event;
1173
+
#define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL
1174
+
#define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ
1175
+
__le16 enable_for_arm[3];
1176
+
#define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL
1177
+
#define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0
1178
+
#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL
1179
+
#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
1180
+
};
1181
+
1182
+
/* cmdq_query_srq (size:192b/24B) */
1183
+
struct cmdq_query_srq {
1184
+
u8 opcode;
1185
+
#define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL
1186
+
#define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ
1187
+
u8 cmd_size;
1188
+
__le16 flags;
1189
+
__le16 cookie;
1190
+
u8 resp_size;
1191
+
u8 reserved8;
1192
+
__le64 resp_addr;
1193
+
__le32 srq_cid;
1194
+
__le32 unused_0;
1195
+
};
1196
+
1197
+
/* creq_query_srq_resp (size:128b/16B) */
1198
+
struct creq_query_srq_resp {
1199
+
u8 type;
1200
+
#define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL
1201
+
#define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
1202
+
#define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1203
+
#define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT
1204
+
u8 status;
1205
+
__le16 cookie;
1206
+
__le32 size;
1207
+
u8 v;
1208
+
#define CREQ_QUERY_SRQ_RESP_V 0x1UL
1209
+
u8 event;
1210
+
#define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL
1211
+
#define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ
1212
+
u8 reserved48[6];
1213
+
};
1214
+
1215
+
/* creq_query_srq_resp_sb (size:256b/32B) */
1216
+
struct creq_query_srq_resp_sb {
1217
+
u8 opcode;
1218
+
#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL
1219
+
#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ
1220
+
u8 status;
1221
+
__le16 cookie;
1222
+
__le16 flags;
1223
+
u8 resp_size;
1224
+
u8 reserved8;
1225
+
__le32 xid;
1226
+
__le16 srq_limit;
1227
+
__le16 reserved16;
1228
+
__le32 data[4];
1229
+
};
1230
+
1231
+
/* cmdq_create_cq (size:512b/64B) */
1232
+
struct cmdq_create_cq {
1233
+
u8 opcode;
1234
+
#define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL
1235
+
#define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ
1236
+
u8 cmd_size;
1237
+
__le16 flags;
1238
+
#define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL
1239
+
#define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL
1240
+
#define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL
1241
+
#define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL
1242
+
#define CMDQ_CREATE_CQ_FLAGS_PBL_PG_SIZE_VALID 0x10UL
1243
+
__le16 cookie;
1244
+
u8 resp_size;
1245
+
u8 reserved8;
1246
+
__le64 resp_addr;
1247
+
__le64 cq_handle;
1248
+
__le32 pg_size_lvl;
1249
+
#define CMDQ_CREATE_CQ_LVL_MASK 0x3UL
1250
+
#define CMDQ_CREATE_CQ_LVL_SFT 0
1251
+
#define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL
1252
+
#define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL
1253
+
#define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL
1254
+
#define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2
1255
+
#define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL
1256
+
#define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
1257
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1258
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1259
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1260
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1261
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1262
+
#define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1263
+
#define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G
1264
+
#define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL
1265
+
#define CMDQ_CREATE_CQ_UNUSED27_SFT 5
1266
+
__le32 cq_fco_cnq_id;
1267
+
#define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL
1268
+
#define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
1269
+
#define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL
1270
+
#define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
1271
+
__le32 dpi;
1272
+
__le32 cq_size;
1273
+
__le64 pbl;
1274
+
__le16 steering_tag;
1275
+
u8 pbl_pg_size;
1276
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_MASK 0x7UL
1277
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_SFT 0
1278
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_4K 0x0UL
1279
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8K 0x1UL
1280
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_64K 0x2UL
1281
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_2M 0x3UL
1282
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_8M 0x4UL
1283
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G 0x5UL
1284
+
#define CMDQ_CREATE_CQ_PBL_PG_SIZE_LAST CMDQ_CREATE_CQ_PBL_PG_SIZE_PG_1G
1285
+
u8 reserved8_1;
1286
+
__le32 coalescing;
1287
+
#define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL
1288
+
#define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0
1289
+
#define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK 0x3e00UL
1290
+
#define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9
1291
+
#define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK 0x7c000UL
1292
+
#define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14
1293
+
#define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE 0x80000UL
1294
+
#define CMDQ_CREATE_CQ_UNUSED12_MASK 0xfff00000UL
1295
+
#define CMDQ_CREATE_CQ_UNUSED12_SFT 20
1296
+
__le64 reserved64;
1297
+
};
1298
+
1299
+
/* creq_create_cq_resp (size:128b/16B) */
1300
+
struct creq_create_cq_resp {
1301
+
u8 type;
1302
+
#define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL
1303
+
#define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
1304
+
#define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1305
+
#define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT
1306
+
u8 status;
1307
+
__le16 cookie;
1308
+
__le32 xid;
1309
+
u8 v;
1310
+
#define CREQ_CREATE_CQ_RESP_V 0x1UL
1311
+
u8 event;
1312
+
#define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL
1313
+
#define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ
1314
+
u8 context_size;
1315
+
u8 reserved48[5];
1316
+
};
1317
+
1318
+
/* cmdq_destroy_cq (size:192b/24B) */
1319
+
struct cmdq_destroy_cq {
1320
+
u8 opcode;
1321
+
#define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL
1322
+
#define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ
1323
+
u8 cmd_size;
1324
+
__le16 flags;
1325
+
__le16 cookie;
1326
+
u8 resp_size;
1327
+
u8 reserved8;
1328
+
__le64 resp_addr;
1329
+
__le32 cq_cid;
1330
+
__le32 unused_0;
1331
+
};
1332
+
1333
+
/* creq_destroy_cq_resp (size:128b/16B) */
1334
+
struct creq_destroy_cq_resp {
1335
+
u8 type;
1336
+
#define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL
1337
+
#define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
1338
+
#define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL
1339
+
#define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT
1340
+
u8 status;
1341
+
__le16 cookie;
1342
+
__le32 xid;
1343
+
u8 v;
1344
+
#define CREQ_DESTROY_CQ_RESP_V 0x1UL
1345
+
u8 event;
1346
+
#define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL
1347
+
#define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ
1348
+
__le16 cq_arm_lvl;
1349
+
#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL
1350
+
#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
1351
+
__le16 total_cnq_events;
1352
+
__le16 reserved16;
1353
+
};
1354
+
1355
+
/* cmdq_resize_cq (size:320b/40B) */
1356
+
struct cmdq_resize_cq {
1357
+
u8 opcode;
1358
+
#define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL
1359
+
#define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ
1360
+
u8 cmd_size;
1361
+
__le16 flags;
1362
+
#define CMDQ_RESIZE_CQ_FLAGS_PBL_PG_SIZE_VALID 0x1UL
1363
+
__le16 cookie;
1364
+
u8 resp_size;
1365
+
u8 reserved8;
1366
+
__le64 resp_addr;
1367
+
__le32 cq_cid;
1368
+
__le32 new_cq_size_pg_size_lvl;
1369
+
#define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL
1370
+
#define CMDQ_RESIZE_CQ_LVL_SFT 0
1371
+
#define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL
1372
+
#define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL
1373
+
#define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL
1374
+
#define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2
1375
+
#define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL
1376
+
#define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
1377
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1378
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1379
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1380
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1381
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1382
+
#define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1383
+
#define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G
1384
+
#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL
1385
+
#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
1386
+
__le64 new_pbl;
1387
+
__le32 new_cq_fco;
1388
+
#define CMDQ_RESIZE_CQ_CQ_FCO_MASK 0xfffffUL
1389
+
#define CMDQ_RESIZE_CQ_CQ_FCO_SFT 0
1390
+
#define CMDQ_RESIZE_CQ_RSVD_MASK 0xfff00000UL
1391
+
#define CMDQ_RESIZE_CQ_RSVD_SFT 20
1392
+
u8 pbl_pg_size;
1393
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_MASK 0x7UL
1394
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_SFT 0
1395
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_4K 0x0UL
1396
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_8K 0x1UL
1397
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_64K 0x2UL
1398
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_2M 0x3UL
1399
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_8M 0x4UL
1400
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_1G 0x5UL
1401
+
#define CMDQ_RESIZE_CQ_PBL_PG_SIZE_LAST CMDQ_RESIZE_CQ_PBL_PG_SIZE_PG_1G
1402
+
u8 unused_0[3];
1403
+
};
1404
+
1405
+
/* creq_resize_cq_resp (size:128b/16B) */
1406
+
struct creq_resize_cq_resp {
1407
+
u8 type;
1408
+
#define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL
1409
+
#define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
1410
+
#define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1411
+
#define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT
1412
+
u8 status;
1413
+
__le16 cookie;
1414
+
__le32 xid;
1415
+
u8 v;
1416
+
#define CREQ_RESIZE_CQ_RESP_V 0x1UL
1417
+
u8 event;
1418
+
#define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL
1419
+
#define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ
1420
+
u8 reserved48[6];
1421
+
};
1422
+
1423
+
/* cmdq_allocate_mrw (size:256b/32B) */
1424
+
struct cmdq_allocate_mrw {
1425
+
u8 opcode;
1426
+
#define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL
1427
+
#define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW
1428
+
u8 cmd_size;
1429
+
__le16 flags;
1430
+
__le16 cookie;
1431
+
u8 resp_size;
1432
+
u8 reserved8;
1433
+
__le64 resp_addr;
1434
+
__le64 mrw_handle;
1435
+
u8 mrw_flags;
1436
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL
1437
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
1438
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL
1439
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL
1440
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL
1441
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL
1442
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL
1443
+
#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B
1444
+
#define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL
1445
+
#define CMDQ_ALLOCATE_MRW_UNUSED3_MASK 0xe0UL
1446
+
#define CMDQ_ALLOCATE_MRW_UNUSED3_SFT 5
1447
+
u8 access;
1448
+
#define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL
1449
+
__le16 steering_tag;
1450
+
__le32 pd_id;
1451
+
};
1452
+
1453
+
/* creq_allocate_mrw_resp (size:128b/16B) */
1454
+
struct creq_allocate_mrw_resp {
1455
+
u8 type;
1456
+
#define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL
1457
+
#define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
1458
+
#define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL
1459
+
#define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT
1460
+
u8 status;
1461
+
__le16 cookie;
1462
+
__le32 xid;
1463
+
u8 v;
1464
+
#define CREQ_ALLOCATE_MRW_RESP_V 0x1UL
1465
+
u8 event;
1466
+
#define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL
1467
+
#define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW
1468
+
u8 context_size;
1469
+
u8 reserved48[5];
1470
+
};
1471
+
1472
+
/* cmdq_deallocate_key (size:192b/24B) */
1473
+
struct cmdq_deallocate_key {
1474
+
u8 opcode;
1475
+
#define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL
1476
+
#define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY
1477
+
u8 cmd_size;
1478
+
__le16 flags;
1479
+
__le16 cookie;
1480
+
u8 resp_size;
1481
+
u8 reserved8;
1482
+
__le64 resp_addr;
1483
+
u8 mrw_flags;
1484
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL
1485
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
1486
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL
1487
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL
1488
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL
1489
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL
1490
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL
1491
+
#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B
1492
+
#define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL
1493
+
#define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4
1494
+
u8 unused24[3];
1495
+
__le32 key;
1496
+
};
1497
+
1498
+
/* creq_deallocate_key_resp (size:128b/16B) */
1499
+
struct creq_deallocate_key_resp {
1500
+
u8 type;
1501
+
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL
1502
+
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
1503
+
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL
1504
+
#define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT
1505
+
u8 status;
1506
+
__le16 cookie;
1507
+
__le32 xid;
1508
+
u8 v;
1509
+
#define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL
1510
+
u8 event;
1511
+
#define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL
1512
+
#define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY
1513
+
__le16 reserved16;
1514
+
__le32 bound_window_info;
1515
+
};
1516
+
1517
+
/* cmdq_register_mr (size:512b/64B) */
1518
+
struct cmdq_register_mr {
1519
+
u8 opcode;
1520
+
#define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL
1521
+
#define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR
1522
+
u8 cmd_size;
1523
+
__le16 flags;
1524
+
#define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL
1525
+
#define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL
1526
+
#define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL
1527
+
#define CMDQ_REGISTER_MR_FLAGS_ENABLE_EROCE 0x8UL
1528
+
__le16 cookie;
1529
+
u8 resp_size;
1530
+
u8 reserved8;
1531
+
__le64 resp_addr;
1532
+
u8 log2_pg_size_lvl;
1533
+
#define CMDQ_REGISTER_MR_LVL_MASK 0x3UL
1534
+
#define CMDQ_REGISTER_MR_LVL_SFT 0
1535
+
#define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL
1536
+
#define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL
1537
+
#define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL
1538
+
#define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2
1539
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL
1540
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
1541
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2)
1542
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2)
1543
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2)
1544
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2)
1545
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2)
1546
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2)
1547
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2)
1548
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2)
1549
+
#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1550
+
#define CMDQ_REGISTER_MR_UNUSED1 0x80UL
1551
+
u8 access;
1552
+
#define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL
1553
+
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL
1554
+
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL
1555
+
#define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL
1556
+
#define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL
1557
+
#define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL
1558
+
__le16 log2_pbl_pg_size;
1559
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL
1560
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
1561
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL
1562
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL
1563
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL
1564
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL
1565
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL
1566
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL
1567
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL
1568
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL
1569
+
#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1570
+
#define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL
1571
+
#define CMDQ_REGISTER_MR_UNUSED11_SFT 5
1572
+
__le32 key;
1573
+
__le64 pbl;
1574
+
__le64 va;
1575
+
__le64 mr_size;
1576
+
__le16 steering_tag;
1577
+
u8 reserved48[6];
1578
+
__le64 reserved64;
1579
+
};
1580
+
1581
+
/* creq_register_mr_resp (size:128b/16B) */
1582
+
struct creq_register_mr_resp {
1583
+
u8 type;
1584
+
#define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL
1585
+
#define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
1586
+
#define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1587
+
#define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT
1588
+
u8 status;
1589
+
__le16 cookie;
1590
+
__le32 xid;
1591
+
u8 v;
1592
+
#define CREQ_REGISTER_MR_RESP_V 0x1UL
1593
+
u8 event;
1594
+
#define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL
1595
+
#define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR
1596
+
u8 context_size;
1597
+
u8 reserved48[5];
1598
+
};
1599
+
1600
+
/* cmdq_deregister_mr (size:192b/24B) */
1601
+
struct cmdq_deregister_mr {
1602
+
u8 opcode;
1603
+
#define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL
1604
+
#define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR
1605
+
u8 cmd_size;
1606
+
__le16 flags;
1607
+
#define CMDQ_DEREGISTER_MR_FLAGS_ENABLE_EROCE 0x1UL
1608
+
__le16 cookie;
1609
+
u8 resp_size;
1610
+
u8 reserved8;
1611
+
__le64 resp_addr;
1612
+
__le32 lkey;
1613
+
__le32 unused_0;
1614
+
};
1615
+
1616
+
/* creq_deregister_mr_resp (size:128b/16B) */
1617
+
struct creq_deregister_mr_resp {
1618
+
u8 type;
1619
+
#define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL
1620
+
#define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
1621
+
#define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1622
+
#define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT
1623
+
u8 status;
1624
+
__le16 cookie;
1625
+
__le32 xid;
1626
+
u8 v;
1627
+
#define CREQ_DEREGISTER_MR_RESP_V 0x1UL
1628
+
u8 event;
1629
+
#define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL
1630
+
#define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR
1631
+
__le16 reserved16;
1632
+
__le32 bound_windows;
1633
+
};
1634
+
1635
+
/* cmdq_add_gid (size:384b/48B) */
1636
+
struct cmdq_add_gid {
1637
+
u8 opcode;
1638
+
#define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL
1639
+
#define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID
1640
+
u8 cmd_size;
1641
+
__le16 flags;
1642
+
__le16 cookie;
1643
+
u8 resp_size;
1644
+
u8 reserved8;
1645
+
__le64 resp_addr;
1646
+
__le32 gid[4];
1647
+
__le16 src_mac[3];
1648
+
__le16 vlan;
1649
+
#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1650
+
#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1651
+
#define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL
1652
+
#define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
1653
+
#define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL
1654
+
#define CMDQ_ADD_GID_VLAN_TPID_SFT 12
1655
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1656
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1657
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1658
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1659
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1660
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1661
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1662
+
#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1663
+
#define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1664
+
#define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL
1665
+
__le16 ipid;
1666
+
__le16 stats_ctx;
1667
+
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL
1668
+
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0
1669
+
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1670
+
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1671
+
#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1672
+
__le16 host_gid_index;
1673
+
__le16 unused_0;
1674
+
};
1675
+
1676
+
/* creq_add_gid_resp (size:128b/16B) */
1677
+
struct creq_add_gid_resp {
1678
+
u8 type;
1679
+
#define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL
1680
+
#define CREQ_ADD_GID_RESP_TYPE_SFT 0
1681
+
#define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL
1682
+
#define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT
1683
+
u8 status;
1684
+
__le16 cookie;
1685
+
__le32 xid;
1686
+
u8 v;
1687
+
#define CREQ_ADD_GID_RESP_V 0x1UL
1688
+
u8 event;
1689
+
#define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL
1690
+
#define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID
1691
+
u8 reserved48[6];
1692
+
};
1693
+
1694
+
/* cmdq_delete_gid (size:192b/24B) */
1695
+
struct cmdq_delete_gid {
1696
+
u8 opcode;
1697
+
#define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL
1698
+
#define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID
1699
+
u8 cmd_size;
1700
+
__le16 flags;
1701
+
__le16 cookie;
1702
+
u8 resp_size;
1703
+
u8 reserved8;
1704
+
__le64 resp_addr;
1705
+
__le16 gid_index;
1706
+
__le16 host_gid_index;
1707
+
u8 unused_0[4];
1708
+
};
1709
+
1710
+
/* creq_delete_gid_resp (size:128b/16B) */
1711
+
struct creq_delete_gid_resp {
1712
+
u8 type;
1713
+
#define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL
1714
+
#define CREQ_DELETE_GID_RESP_TYPE_SFT 0
1715
+
#define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL
1716
+
#define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT
1717
+
u8 status;
1718
+
__le16 cookie;
1719
+
__le32 xid;
1720
+
u8 v;
1721
+
#define CREQ_DELETE_GID_RESP_V 0x1UL
1722
+
u8 event;
1723
+
#define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL
1724
+
#define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID
1725
+
u8 reserved48[6];
1726
+
};
1727
+
1728
+
/* cmdq_modify_gid (size:384b/48B) */
1729
+
struct cmdq_modify_gid {
1730
+
u8 opcode;
1731
+
#define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL
1732
+
#define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID
1733
+
u8 cmd_size;
1734
+
__le16 flags;
1735
+
__le16 cookie;
1736
+
u8 resp_size;
1737
+
u8 reserved8;
1738
+
__le64 resp_addr;
1739
+
__le32 gid[4];
1740
+
__le16 src_mac[3];
1741
+
__le16 vlan;
1742
+
#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL
1743
+
#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
1744
+
#define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL
1745
+
#define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
1746
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1747
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1748
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1749
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1750
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1751
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1752
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1753
+
#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1754
+
#define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1755
+
#define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL
1756
+
__le16 ipid;
1757
+
__le16 gid_index;
1758
+
__le16 stats_ctx;
1759
+
#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1760
+
#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1761
+
#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1762
+
__le16 host_gid_index;
1763
+
};
1764
+
1765
+
/* creq_modify_gid_resp (size:128b/16B) */
1766
+
struct creq_modify_gid_resp {
1767
+
u8 type;
1768
+
#define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL
1769
+
#define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
1770
+
#define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL
1771
+
#define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT
1772
+
u8 status;
1773
+
__le16 cookie;
1774
+
__le32 xid;
1775
+
u8 v;
1776
+
#define CREQ_MODIFY_GID_RESP_V 0x1UL
1777
+
u8 event;
1778
+
#define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL
1779
+
#define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID
1780
+
u8 reserved48[6];
1781
+
};
1782
+
1783
+
/* cmdq_query_gid (size:192b/24B) */
1784
+
struct cmdq_query_gid {
1785
+
u8 opcode;
1786
+
#define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL
1787
+
#define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID
1788
+
u8 cmd_size;
1789
+
__le16 flags;
1790
+
__le16 cookie;
1791
+
u8 resp_size;
1792
+
u8 reserved8;
1793
+
__le64 resp_addr;
1794
+
__le16 gid_index;
1795
+
u8 unused16[6];
1796
+
};
1797
+
1798
+
/* creq_query_gid_resp (size:128b/16B) */
1799
+
struct creq_query_gid_resp {
1800
+
u8 type;
1801
+
#define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL
1802
+
#define CREQ_QUERY_GID_RESP_TYPE_SFT 0
1803
+
#define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL
1804
+
#define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT
1805
+
u8 status;
1806
+
__le16 cookie;
1807
+
__le32 size;
1808
+
u8 v;
1809
+
#define CREQ_QUERY_GID_RESP_V 0x1UL
1810
+
u8 event;
1811
+
#define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL
1812
+
#define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID
1813
+
u8 reserved48[6];
1814
+
};
1815
+
1816
+
/* creq_query_gid_resp_sb (size:320b/40B) */
1817
+
struct creq_query_gid_resp_sb {
1818
+
u8 opcode;
1819
+
#define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL
1820
+
#define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID
1821
+
u8 status;
1822
+
__le16 cookie;
1823
+
__le16 flags;
1824
+
u8 resp_size;
1825
+
u8 reserved8;
1826
+
__le32 gid[4];
1827
+
__le16 src_mac[3];
1828
+
__le16 vlan;
1829
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1830
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1831
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL
1832
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
1833
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL
1834
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
1835
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1836
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12)
1837
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12)
1838
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12)
1839
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12)
1840
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1841
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1842
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1843
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
1844
+
#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL
1845
+
__le16 ipid;
1846
+
__le16 gid_index;
1847
+
__le32 unused_0;
1848
+
};
1849
+
1850
+
/* cmdq_create_qp1 (size:640b/80B) */
1851
+
struct cmdq_create_qp1 {
1852
+
u8 opcode;
1853
+
#define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL
1854
+
#define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1
1855
+
u8 cmd_size;
1856
+
__le16 flags;
1857
+
__le16 cookie;
1858
+
u8 resp_size;
1859
+
u8 reserved8;
1860
+
__le64 resp_addr;
1861
+
__le64 qp_handle;
1862
+
__le32 qp_flags;
1863
+
#define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL
1864
+
#define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL
1865
+
#define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
1866
+
#define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE
1867
+
u8 type;
1868
+
#define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL
1869
+
#define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI
1870
+
u8 sq_pg_size_sq_lvl;
1871
+
#define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL
1872
+
#define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
1873
+
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL
1874
+
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL
1875
+
#define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL
1876
+
#define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2
1877
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL
1878
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
1879
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4)
1880
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4)
1881
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4)
1882
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4)
1883
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4)
1884
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4)
1885
+
#define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G
1886
+
u8 rq_pg_size_rq_lvl;
1887
+
#define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL
1888
+
#define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
1889
+
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL
1890
+
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL
1891
+
#define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL
1892
+
#define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2
1893
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL
1894
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
1895
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4)
1896
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4)
1897
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4)
1898
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4)
1899
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4)
1900
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4)
1901
+
#define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G
1902
+
u8 unused_0;
1903
+
__le32 dpi;
1904
+
__le32 sq_size;
1905
+
__le32 rq_size;
1906
+
__le16 sq_fwo_sq_sge;
1907
+
#define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL
1908
+
#define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
1909
+
#define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL
1910
+
#define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
1911
+
__le16 rq_fwo_rq_sge;
1912
+
#define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL
1913
+
#define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
1914
+
#define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL
1915
+
#define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
1916
+
__le32 scq_cid;
1917
+
__le32 rcq_cid;
1918
+
__le32 srq_cid;
1919
+
__le32 pd_id;
1920
+
__le64 sq_pbl;
1921
+
__le64 rq_pbl;
1922
+
};
1923
+
1924
+
/* creq_create_qp1_resp (size:128b/16B) */
1925
+
struct creq_create_qp1_resp {
1926
+
u8 type;
1927
+
#define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL
1928
+
#define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
1929
+
#define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL
1930
+
#define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT
1931
+
u8 status;
1932
+
__le16 cookie;
1933
+
__le32 xid;
1934
+
u8 v;
1935
+
#define CREQ_CREATE_QP1_RESP_V 0x1UL
1936
+
u8 event;
1937
+
#define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL
1938
+
#define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1
1939
+
u8 reserved48[6];
1940
+
};
1941
+
1942
+
/* cmdq_destroy_qp1 (size:192b/24B) */
1943
+
struct cmdq_destroy_qp1 {
1944
+
u8 opcode;
1945
+
#define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL
1946
+
#define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1
1947
+
u8 cmd_size;
1948
+
__le16 flags;
1949
+
__le16 cookie;
1950
+
u8 resp_size;
1951
+
u8 reserved8;
1952
+
__le64 resp_addr;
1953
+
__le32 qp1_cid;
1954
+
__le32 unused_0;
1955
+
};
1956
+
1957
+
/* creq_destroy_qp1_resp (size:128b/16B) */
1958
+
struct creq_destroy_qp1_resp {
1959
+
u8 type;
1960
+
#define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL
1961
+
#define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
1962
+
#define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL
1963
+
#define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT
1964
+
u8 status;
1965
+
__le16 cookie;
1966
+
__le32 xid;
1967
+
u8 v;
1968
+
#define CREQ_DESTROY_QP1_RESP_V 0x1UL
1969
+
u8 event;
1970
+
#define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL
1971
+
#define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1
1972
+
u8 reserved48[6];
1973
+
};
1974
+
1975
+
/* cmdq_create_ah (size:512b/64B) */
1976
+
struct cmdq_create_ah {
1977
+
u8 opcode;
1978
+
#define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL
1979
+
#define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH
1980
+
u8 cmd_size;
1981
+
__le16 flags;
1982
+
__le16 cookie;
1983
+
u8 resp_size;
1984
+
u8 reserved8;
1985
+
__le64 resp_addr;
1986
+
__le64 ah_handle;
1987
+
__le32 dgid[4];
1988
+
u8 type;
1989
+
#define CMDQ_CREATE_AH_TYPE_V1 0x0UL
1990
+
#define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL
1991
+
#define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL
1992
+
#define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6
1993
+
u8 hop_limit;
1994
+
__le16 sgid_index;
1995
+
__le32 dest_vlan_id_flow_label;
1996
+
#define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL
1997
+
#define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
1998
+
#define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL
1999
+
#define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
2000
+
__le32 pd_id;
2001
+
__le32 unused_0;
2002
+
__le16 dest_mac[3];
2003
+
u8 traffic_class;
2004
+
u8 enable_cc;
2005
+
#define CMDQ_CREATE_AH_ENABLE_CC 0x1UL
2006
+
};
2007
+
2008
+
/* creq_create_ah_resp (size:128b/16B) */
2009
+
struct creq_create_ah_resp {
2010
+
u8 type;
2011
+
#define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL
2012
+
#define CREQ_CREATE_AH_RESP_TYPE_SFT 0
2013
+
#define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL
2014
+
#define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT
2015
+
u8 status;
2016
+
__le16 cookie;
2017
+
__le32 xid;
2018
+
u8 v;
2019
+
#define CREQ_CREATE_AH_RESP_V 0x1UL
2020
+
u8 event;
2021
+
#define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL
2022
+
#define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH
2023
+
u8 reserved48[6];
2024
+
};
2025
+
2026
+
/* cmdq_destroy_ah (size:192b/24B) */
2027
+
struct cmdq_destroy_ah {
2028
+
u8 opcode;
2029
+
#define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL
2030
+
#define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH
2031
+
u8 cmd_size;
2032
+
__le16 flags;
2033
+
__le16 cookie;
2034
+
u8 resp_size;
2035
+
u8 reserved8;
2036
+
__le64 resp_addr;
2037
+
__le32 ah_cid;
2038
+
__le32 unused_0;
2039
+
};
2040
+
2041
+
/* creq_destroy_ah_resp (size:128b/16B) */
2042
+
struct creq_destroy_ah_resp {
2043
+
u8 type;
2044
+
#define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL
2045
+
#define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
2046
+
#define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL
2047
+
#define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT
2048
+
u8 status;
2049
+
__le16 cookie;
2050
+
__le32 xid;
2051
+
u8 v;
2052
+
#define CREQ_DESTROY_AH_RESP_V 0x1UL
2053
+
u8 event;
2054
+
#define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL
2055
+
#define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH
2056
+
u8 reserved48[6];
2057
+
};
2058
+
2059
+
/* cmdq_query_roce_stats (size:192b/24B) */
2060
+
struct cmdq_query_roce_stats {
2061
+
u8 opcode;
2062
+
#define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
2063
+
#define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
2064
+
u8 cmd_size;
2065
+
__le16 flags;
2066
+
#define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL
2067
+
#define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL
2068
+
__le16 cookie;
2069
+
u8 resp_size;
2070
+
u8 collection_id;
2071
+
__le64 resp_addr;
2072
+
__le32 function_id;
2073
+
#define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL
2074
+
#define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0
2075
+
#define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL
2076
+
#define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8
2077
+
#define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL
2078
+
__le32 reserved32;
2079
+
};
2080
+
2081
+
/* creq_query_roce_stats_resp (size:128b/16B) */
2082
+
struct creq_query_roce_stats_resp {
2083
+
u8 type;
2084
+
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL
2085
+
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0
2086
+
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL
2087
+
#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
2088
+
u8 status;
2089
+
__le16 cookie;
2090
+
__le32 size;
2091
+
u8 v;
2092
+
#define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL
2093
+
u8 event;
2094
+
#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
2095
+
#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
2096
+
u8 reserved48[6];
2097
+
};
2098
+
2099
+
/* creq_query_roce_stats_resp_sb (size:3072b/384B) */
2100
+
struct creq_query_roce_stats_resp_sb {
2101
+
u8 opcode;
2102
+
#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
2103
+
#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
2104
+
u8 status;
2105
+
__le16 cookie;
2106
+
__le16 flags;
2107
+
u8 resp_size;
2108
+
u8 rsvd;
2109
+
__le32 num_counters;
2110
+
__le32 rsvd1;
2111
+
__le64 to_retransmits;
2112
+
__le64 seq_err_naks_rcvd;
2113
+
__le64 max_retry_exceeded;
2114
+
__le64 rnr_naks_rcvd;
2115
+
__le64 missing_resp;
2116
+
__le64 unrecoverable_err;
2117
+
__le64 bad_resp_err;
2118
+
__le64 local_qp_op_err;
2119
+
__le64 local_protection_err;
2120
+
__le64 mem_mgmt_op_err;
2121
+
__le64 remote_invalid_req_err;
2122
+
__le64 remote_access_err;
2123
+
__le64 remote_op_err;
2124
+
__le64 dup_req;
2125
+
__le64 res_exceed_max;
2126
+
__le64 res_length_mismatch;
2127
+
__le64 res_exceeds_wqe;
2128
+
__le64 res_opcode_err;
2129
+
__le64 res_rx_invalid_rkey;
2130
+
__le64 res_rx_domain_err;
2131
+
__le64 res_rx_no_perm;
2132
+
__le64 res_rx_range_err;
2133
+
__le64 res_tx_invalid_rkey;
2134
+
__le64 res_tx_domain_err;
2135
+
__le64 res_tx_no_perm;
2136
+
__le64 res_tx_range_err;
2137
+
__le64 res_irrq_oflow;
2138
+
__le64 res_unsup_opcode;
2139
+
__le64 res_unaligned_atomic;
2140
+
__le64 res_rem_inv_err;
2141
+
__le64 res_mem_error;
2142
+
__le64 res_srq_err;
2143
+
__le64 res_cmp_err;
2144
+
__le64 res_invalid_dup_rkey;
2145
+
__le64 res_wqe_format_err;
2146
+
__le64 res_cq_load_err;
2147
+
__le64 res_srq_load_err;
2148
+
__le64 res_tx_pci_err;
2149
+
__le64 res_rx_pci_err;
2150
+
__le64 res_oos_drop_count;
2151
+
__le64 active_qp_count_p0;
2152
+
__le64 active_qp_count_p1;
2153
+
__le64 active_qp_count_p2;
2154
+
__le64 active_qp_count_p3;
2155
+
__le64 xp_sq_overflow_err;
2156
+
__le64 xp_rq_overflow_error;
2157
+
};
2158
+
2159
+
/* cmdq_query_roce_stats_ext (size:192b/24B) */
2160
+
struct cmdq_query_roce_stats_ext {
2161
+
u8 opcode;
2162
+
#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL
2163
+
#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS
2164
+
u8 cmd_size;
2165
+
__le16 flags;
2166
+
#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL
2167
+
#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL
2168
+
__le16 cookie;
2169
+
u8 resp_size;
2170
+
u8 collection_id;
2171
+
__le64 resp_addr;
2172
+
__le32 function_id;
2173
+
#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL
2174
+
#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0
2175
+
#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL
2176
+
#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8
2177
+
#define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL
2178
+
__le32 reserved32;
2179
+
};
2180
+
2181
+
/* creq_query_roce_stats_ext_resp (size:128b/16B) */
2182
+
struct creq_query_roce_stats_ext_resp {
2183
+
u8 type;
2184
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL
2185
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0
2186
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL
2187
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT
2188
+
u8 status;
2189
+
__le16 cookie;
2190
+
__le32 size;
2191
+
u8 v;
2192
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL
2193
+
u8 event;
2194
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL
2195
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT
2196
+
u8 reserved48[6];
2197
+
};
2198
+
2199
+
/* creq_query_roce_stats_ext_resp_sb (size:2368b/296B) */
2200
+
struct creq_query_roce_stats_ext_resp_sb {
2201
+
u8 opcode;
2202
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
2203
+
#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT
2204
+
u8 status;
2205
+
__le16 cookie;
2206
+
__le16 flags;
2207
+
u8 resp_size;
2208
+
u8 rsvd;
2209
+
__le64 rx_ack_pkts;
2210
+
__le64 tx_atomic_req_pkts;
2211
+
__le64 tx_read_req_pkts;
2212
+
__le64 tx_read_res_pkts;
2213
+
__le64 tx_write_req_pkts;
2214
+
__le64 tx_send_req_pkts;
2215
+
__le64 tx_roce_pkts;
2216
+
__le64 tx_roce_bytes;
2217
+
__le64 rx_atomic_req_pkts;
2218
+
__le64 rx_read_req_pkts;
2219
+
__le64 rx_read_res_pkts;
2220
+
__le64 rx_write_req_pkts;
2221
+
__le64 rx_send_req_pkts;
2222
+
__le64 rx_roce_pkts;
2223
+
__le64 rx_roce_bytes;
2224
+
__le64 rx_roce_good_pkts;
2225
+
__le64 rx_roce_good_bytes;
2226
+
__le64 rx_out_of_buffer_pkts;
2227
+
__le64 rx_out_of_sequence_pkts;
2228
+
__le64 tx_cnp_pkts;
2229
+
__le64 rx_cnp_pkts;
2230
+
__le64 rx_ecn_marked_pkts;
2231
+
__le64 tx_cnp_bytes;
2232
+
__le64 rx_cnp_bytes;
2233
+
__le64 seq_err_naks_rcvd;
2234
+
__le64 rnr_naks_rcvd;
2235
+
__le64 missing_resp;
2236
+
__le64 to_retransmit;
2237
+
__le64 dup_req;
2238
+
__le64 rx_dcn_payload_cut;
2239
+
__le64 te_bypassed;
2240
+
__le64 tx_dcn_cnp;
2241
+
__le64 rx_dcn_cnp;
2242
+
__le64 rx_payload_cut;
2243
+
__le64 rx_payload_cut_ignored;
2244
+
__le64 rx_dcn_cnp_ignored;
2245
+
};
2246
+
2247
+
/* cmdq_query_func (size:128b/16B) */
2248
+
struct cmdq_query_func {
2249
+
u8 opcode;
2250
+
#define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL
2251
+
#define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC
2252
+
u8 cmd_size;
2253
+
__le16 flags;
2254
+
__le16 cookie;
2255
+
u8 resp_size;
2256
+
u8 reserved8;
2257
+
__le64 resp_addr;
2258
+
};
2259
+
2260
+
/* creq_query_func_resp (size:128b/16B) */
2261
+
struct creq_query_func_resp {
2262
+
u8 type;
2263
+
#define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL
2264
+
#define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
2265
+
#define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL
2266
+
#define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT
2267
+
u8 status;
2268
+
__le16 cookie;
2269
+
__le32 size;
2270
+
u8 v;
2271
+
#define CREQ_QUERY_FUNC_RESP_V 0x1UL
2272
+
u8 event;
2273
+
#define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL
2274
+
#define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC
2275
+
u8 reserved48[6];
2276
+
};
2277
+
2278
+
/* creq_query_func_resp_sb (size:1728b/216B) */
2279
+
struct creq_query_func_resp_sb {
2280
+
u8 opcode;
2281
+
#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL
2282
+
#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC
2283
+
u8 status;
2284
+
__le16 cookie;
2285
+
__le16 flags;
2286
+
u8 resp_size;
2287
+
u8 reserved8;
2288
+
__le64 max_mr_size;
2289
+
__le32 max_qp;
2290
+
__le16 max_qp_wr;
2291
+
__le16 dev_cap_flags;
2292
+
#define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL
2293
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL
2294
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1
2295
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1)
2296
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1)
2297
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1)
2298
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (0x3UL << 1)
2299
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2_EXT (0x4UL << 1)
2300
+
#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2_EXT
2301
+
#define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL
2302
+
#define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL
2303
+
#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL
2304
+
#define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL
2305
+
#define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL
2306
+
#define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL
2307
+
#define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL
2308
+
#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED 0x800UL
2309
+
#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID 0x1000UL
2310
+
#define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED 0x2000UL
2311
+
#define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED 0x4000UL
2312
+
#define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY 0x8000UL
2313
+
__le32 max_cq;
2314
+
__le32 max_cqe;
2315
+
__le32 max_pd;
2316
+
u8 max_sge;
2317
+
u8 max_srq_sge;
2318
+
u8 max_qp_rd_atom;
2319
+
u8 max_qp_init_rd_atom;
2320
+
__le32 max_mr;
2321
+
__le32 max_mw;
2322
+
__le32 max_raw_eth_qp;
2323
+
__le32 max_ah;
2324
+
__le32 max_fmr;
2325
+
__le32 max_srq_wr;
2326
+
__le32 max_pkeys;
2327
+
__le32 max_inline_data;
2328
+
u8 max_map_per_fmr;
2329
+
u8 l2_db_space_size;
2330
+
__le16 max_srq;
2331
+
__le32 max_gid;
2332
+
__le32 tqm_alloc_reqs[12];
2333
+
__le32 max_dpi;
2334
+
u8 max_sge_var_wqe;
2335
+
u8 dev_cap_ext_flags;
2336
+
#define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL
2337
+
#define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL
2338
+
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL
2339
+
#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL
2340
+
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL
2341
+
#define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL
2342
+
#define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL
2343
+
#define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL
2344
+
__le16 max_inline_data_var_wqe;
2345
+
__le32 start_qid;
2346
+
u8 max_msn_table_size;
2347
+
u8 dev_cap_ext_flags_1;
2348
+
#define CREQ_QUERY_FUNC_RESP_SB_PBL_PAGE_SIZE_SUPPORTED 0x1UL
2349
+
#define CREQ_QUERY_FUNC_RESP_SB_INFINITE_RETRY_TO_RETX_SUPPORTED 0x2UL
2350
+
__le16 dev_cap_ext_flags_2;
2351
+
#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL
2352
+
#define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL
2353
+
#define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL
2354
+
#define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL
2355
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL
2356
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4
2357
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4)
2358
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4)
2359
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4)
2360
+
#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE
2361
+
#define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL
2362
+
#define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_SUPPORTED 0x80UL
2363
+
#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_CONTEXT_SB_SUPPORTED 0x100UL
2364
+
#define CREQ_QUERY_FUNC_RESP_SB_DEFAULT_ROCE_CC_PARAMS_SUPPORTED 0x200UL
2365
+
#define CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED 0x400UL
2366
+
#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_UDCC_SESSION_SB_SUPPORTED 0x800UL
2367
+
#define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL
2368
+
#define CREQ_QUERY_FUNC_RESP_SB_CQ_OVERFLOW_DETECTION_ENABLED 0x2000UL
2369
+
#define CREQ_QUERY_FUNC_RESP_SB_ICRC_CHECK_DISABLE_SUPPORTED 0x4000UL
2370
+
#define CREQ_QUERY_FUNC_RESP_SB_FORCE_MIRROR_ENABLE_SUPPORTED 0x8000UL
2371
+
__le16 max_xp_qp_size;
2372
+
__le16 create_qp_batch_size;
2373
+
__le16 destroy_qp_batch_size;
2374
+
__le16 max_srq_ext;
2375
+
__le16 roce_cc_tlv_en_flags;
2376
+
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN2_TLV_EN 0x1UL
2377
+
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN1_EXT_TLV_EN 0x2UL
2378
+
#define CREQ_QUERY_FUNC_RESP_SB_ROCE_CC_GEN2_EXT_TLV_EN 0x4UL
2379
+
__le16 pno_flags;
2380
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_ENABLED 0x1UL
2381
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_ENABLED_ON_PF 0x2UL
2382
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_EXT_ENABLED 0x4UL
2383
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PNO_EXT_ENABLED_ON_PF 0x8UL
2384
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PSP_ENABLED 0x10UL
2385
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PSP_ENABLED_ON_PF 0x20UL
2386
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_DYNAMIC_TUNNELS_ENABLED 0x40UL
2387
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_PER_TUNNEL_EV_MONITORING_SUPPORTED 0x80UL
2388
+
u8 pno_tnl_dest_grp_auto;
2389
+
u8 pno_max_tnl_per_endpoint;
2390
+
u8 pno_cc_algo;
2391
+
u8 pno_pf_num;
2392
+
__le32 pno_max_endpoints;
2393
+
u8 eroce_spec_dscp[2];
2394
+
u8 eroce_pull_dscp[2];
2395
+
u8 eroce_retx_dscp[2];
2396
+
u8 eroce_rts_dscp[2];
2397
+
u8 eroce_rerouted_dscp[2];
2398
+
u8 eroce_trim_dscp;
2399
+
u8 eroce_trim_last_hop_dscp;
2400
+
u8 eroce_control_dscp;
2401
+
u8 reserved24[3];
2402
+
__le16 pno_num_debug_tunnels;
2403
+
u8 pno_num_cos;
2404
+
u8 reserved40[5];
2405
+
__le32 pno_flags_ext;
2406
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_UPDATE_RTS 0x1UL
2407
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EVENT 0x2UL
2408
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EXP_ARRAY 0x4UL
2409
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_GEN_ARRAY 0x8UL
2410
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EXP_ARRAY_RANGE 0x10UL
2411
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_PROBE 0x20UL
2412
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_EVENT_PRECISE_CNT 0x40UL
2413
+
#define CREQ_QUERY_FUNC_RESP_SB_PNO_FLAGS_EXT_PATH_SPRAYING_DISABLE 0x80UL
2414
+
__le16 max_mpr;
2415
+
u8 max_paths_per_path_ctx;
2416
+
u8 max_plane;
2417
+
u8 max_paths_per_plane;
2418
+
u8 max_strpath_tiers;
2419
+
u8 pno_telemetry_type;
2420
+
u8 reserved9_8b;
2421
+
__le32 max_path_ctx_strpath;
2422
+
__le32 max_path_ctx_srv6;
2423
+
__le32 rate_limit_max;
2424
+
__le32 rate_limit_min;
2425
+
};
2426
+
2427
+
/* cmdq_set_func_resources (size:448b/56B) */
2428
+
struct cmdq_set_func_resources {
2429
+
u8 opcode;
2430
+
#define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
2431
+
#define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES
2432
+
u8 cmd_size;
2433
+
__le16 flags;
2434
+
#define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
2435
+
__le16 cookie;
2436
+
u8 resp_size;
2437
+
u8 reserved8;
2438
+
__le64 resp_addr;
2439
+
__le32 number_of_qp;
2440
+
__le32 number_of_mrw;
2441
+
__le32 number_of_srq;
2442
+
__le32 number_of_cq;
2443
+
__le32 max_qp_per_vf;
2444
+
__le32 max_mrw_per_vf;
2445
+
__le32 max_srq_per_vf;
2446
+
__le32 max_cq_per_vf;
2447
+
__le32 max_gid_per_vf;
2448
+
__le32 stat_ctx_id;
2449
+
};
2450
+
2451
+
/* creq_set_func_resources_resp (size:128b/16B) */
2452
+
struct creq_set_func_resources_resp {
2453
+
u8 type;
2454
+
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL
2455
+
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
2456
+
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL
2457
+
#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT
2458
+
u8 status;
2459
+
__le16 cookie;
2460
+
__le32 reserved32;
2461
+
u8 v;
2462
+
#define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL
2463
+
u8 event;
2464
+
#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2465
+
#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \
2466
+
CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES
2467
+
u8 reserved48[6];
2468
+
};
2469
+
2470
+
/* cmdq_read_context (size:192b/24B) */
2471
+
struct cmdq_read_context {
2472
+
u8 opcode;
2473
+
#define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL
2474
+
#define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT
2475
+
u8 cmd_size;
2476
+
__le16 flags;
2477
+
__le16 cookie;
2478
+
u8 resp_size;
2479
+
u8 reserved8;
2480
+
__le64 resp_addr;
2481
+
__le32 xid;
2482
+
u8 type;
2483
+
#define CMDQ_READ_CONTEXT_TYPE_QPC 0x0UL
2484
+
#define CMDQ_READ_CONTEXT_TYPE_CQ 0x1UL
2485
+
#define CMDQ_READ_CONTEXT_TYPE_MRW 0x2UL
2486
+
#define CMDQ_READ_CONTEXT_TYPE_SRQ 0x3UL
2487
+
#define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ
2488
+
u8 unused_0[3];
2489
+
};
2490
+
2491
+
/* creq_read_context (size:128b/16B) */
2492
+
struct creq_read_context {
2493
+
u8 type;
2494
+
#define CREQ_READ_CONTEXT_TYPE_MASK 0x3fUL
2495
+
#define CREQ_READ_CONTEXT_TYPE_SFT 0
2496
+
#define CREQ_READ_CONTEXT_TYPE_QP_EVENT 0x38UL
2497
+
#define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT
2498
+
u8 status;
2499
+
__le16 cookie;
2500
+
__le32 reserved32;
2501
+
u8 v;
2502
+
#define CREQ_READ_CONTEXT_V 0x1UL
2503
+
u8 event;
2504
+
#define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 0x85UL
2505
+
#define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT
2506
+
__le16 reserved16;
2507
+
__le32 reserved_32;
2508
+
};
2509
+
2510
+
/* cmdq_map_tc_to_cos (size:192b/24B) */
2511
+
struct cmdq_map_tc_to_cos {
2512
+
u8 opcode;
2513
+
#define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL
2514
+
#define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS
2515
+
u8 cmd_size;
2516
+
__le16 flags;
2517
+
__le16 cookie;
2518
+
u8 resp_size;
2519
+
u8 reserved8;
2520
+
__le64 resp_addr;
2521
+
__le16 cos0;
2522
+
#define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL
2523
+
#define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE
2524
+
__le16 cos1;
2525
+
#define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL
2526
+
#define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL
2527
+
#define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE
2528
+
__le32 unused_0;
2529
+
};
2530
+
2531
+
/* creq_map_tc_to_cos_resp (size:128b/16B) */
2532
+
struct creq_map_tc_to_cos_resp {
2533
+
u8 type;
2534
+
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL
2535
+
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
2536
+
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL
2537
+
#define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT
2538
+
u8 status;
2539
+
__le16 cookie;
2540
+
__le32 reserved32;
2541
+
u8 v;
2542
+
#define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL
2543
+
u8 event;
2544
+
#define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL
2545
+
#define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS
2546
+
u8 reserved48[6];
2547
+
};
2548
+
2549
+
/* cmdq_query_roce_cc (size:128b/16B) */
2550
+
struct cmdq_query_roce_cc {
2551
+
u8 opcode;
2552
+
#define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL
2553
+
#define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC
2554
+
u8 cmd_size;
2555
+
__le16 flags;
2556
+
__le16 cookie;
2557
+
u8 resp_size;
2558
+
u8 reserved8;
2559
+
__le64 resp_addr;
2560
+
};
2561
+
2562
+
/* creq_query_roce_cc_resp (size:128b/16B) */
2563
+
struct creq_query_roce_cc_resp {
2564
+
u8 type;
2565
+
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2566
+
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
2567
+
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2568
+
#define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT
2569
+
u8 status;
2570
+
__le16 cookie;
2571
+
__le32 size;
2572
+
u8 v;
2573
+
#define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL
2574
+
u8 event;
2575
+
#define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL
2576
+
#define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC
2577
+
u8 reserved48[6];
2578
+
};
2579
+
2580
+
/* creq_query_roce_cc_resp_sb (size:256b/32B) */
2581
+
struct creq_query_roce_cc_resp_sb {
2582
+
u8 opcode;
2583
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL
2584
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC
2585
+
u8 status;
2586
+
__le16 cookie;
2587
+
__le16 flags;
2588
+
u8 resp_size;
2589
+
u8 reserved8;
2590
+
u8 enable_cc;
2591
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL
2592
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL
2593
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1
2594
+
u8 tos_dscp_tos_ecn;
2595
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL
2596
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
2597
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL
2598
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
2599
+
u8 g;
2600
+
u8 num_phases_per_state;
2601
+
__le16 init_cr;
2602
+
__le16 init_tr;
2603
+
u8 alt_vlan_pcp;
2604
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL
2605
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
2606
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL
2607
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
2608
+
u8 alt_tos_dscp;
2609
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL
2610
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
2611
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL
2612
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
2613
+
u8 cc_mode;
2614
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL
2615
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL
2616
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC
2617
+
u8 tx_queue;
2618
+
__le16 rtt;
2619
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL
2620
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
2621
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL
2622
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
2623
+
__le16 tcp_cp;
2624
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL
2625
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
2626
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL
2627
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
2628
+
__le16 inactivity_th;
2629
+
u8 pkts_per_phase;
2630
+
u8 time_per_phase;
2631
+
__le32 reserved32;
2632
+
};
2633
+
2634
+
/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */
2635
+
struct creq_query_roce_cc_resp_sb_tlv {
2636
+
__le16 cmd_discr;
2637
+
u8 reserved_8b;
2638
+
u8 tlv_flags;
2639
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2640
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2641
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2642
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2643
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2644
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2645
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2646
+
__le16 tlv_type;
2647
+
__le16 length;
2648
+
u8 total_size;
2649
+
u8 reserved56[7];
2650
+
u8 opcode;
2651
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL
2652
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC
2653
+
u8 status;
2654
+
__le16 cookie;
2655
+
__le16 flags;
2656
+
u8 resp_size;
2657
+
u8 reserved8;
2658
+
u8 enable_cc;
2659
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL
2660
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL
2661
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1
2662
+
u8 tos_dscp_tos_ecn;
2663
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL
2664
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0
2665
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL
2666
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2
2667
+
u8 g;
2668
+
u8 num_phases_per_state;
2669
+
__le16 init_cr;
2670
+
__le16 init_tr;
2671
+
u8 alt_vlan_pcp;
2672
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL
2673
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
2674
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL
2675
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3
2676
+
u8 alt_tos_dscp;
2677
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2678
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
2679
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL
2680
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6
2681
+
u8 cc_mode;
2682
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL
2683
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL
2684
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC
2685
+
u8 tx_queue;
2686
+
__le16 rtt;
2687
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL
2688
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0
2689
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL
2690
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14
2691
+
__le16 tcp_cp;
2692
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL
2693
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
2694
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL
2695
+
#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10
2696
+
__le16 inactivity_th;
2697
+
u8 pkts_per_phase;
2698
+
u8 time_per_phase;
2699
+
__le32 reserved32;
2700
+
};
2701
+
2702
+
/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */
2703
+
struct creq_query_roce_cc_gen1_resp_sb_tlv {
2704
+
__le16 cmd_discr;
2705
+
u8 reserved_8b;
2706
+
u8 tlv_flags;
2707
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2708
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2709
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2710
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2711
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2712
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2713
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2714
+
__le16 tlv_type;
2715
+
__le16 length;
2716
+
__le64 reserved64;
2717
+
__le16 inactivity_th_hi;
2718
+
__le16 min_time_between_cnps;
2719
+
__le16 init_cp;
2720
+
u8 tr_update_mode;
2721
+
u8 tr_update_cycles;
2722
+
u8 fr_num_rtts;
2723
+
u8 ai_rate_increase;
2724
+
__le16 reduction_relax_rtts_th;
2725
+
__le16 additional_relax_cr_th;
2726
+
__le16 cr_min_th;
2727
+
u8 bw_avg_weight;
2728
+
u8 actual_cr_factor;
2729
+
__le16 max_cp_cr_th;
2730
+
u8 cp_bias_en;
2731
+
u8 cp_bias;
2732
+
u8 cnp_ecn;
2733
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL
2734
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL
2735
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL
2736
+
#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0
2737
+
u8 rtt_jitter_en;
2738
+
__le16 link_bytes_per_usec;
2739
+
__le16 reset_cc_cr_th;
2740
+
u8 cr_width;
2741
+
u8 quota_period_min;
2742
+
u8 quota_period_max;
2743
+
u8 quota_period_abs_max;
2744
+
__le16 tr_lower_bound;
2745
+
u8 cr_prob_factor;
2746
+
u8 tr_prob_factor;
2747
+
__le16 fairness_cr_th;
2748
+
u8 red_div;
2749
+
u8 cnp_ratio_th;
2750
+
__le16 exp_ai_rtts;
2751
+
u8 exp_ai_cr_cp_ratio;
2752
+
u8 use_rate_table;
2753
+
__le16 cp_exp_update_th;
2754
+
__le16 high_exp_ai_rtts_th1;
2755
+
__le16 high_exp_ai_rtts_th2;
2756
+
__le16 actual_cr_cong_free_rtts_th;
2757
+
__le16 severe_cong_cr_th1;
2758
+
__le16 severe_cong_cr_th2;
2759
+
__le32 link64B_per_rtt;
2760
+
u8 cc_ack_bytes;
2761
+
u8 reduce_init_en;
2762
+
__le16 reduce_init_cong_free_rtts_th;
2763
+
u8 random_no_red_en;
2764
+
u8 actual_cr_shift_correction_en;
2765
+
u8 quota_period_adjust_en;
2766
+
u8 reserved[5];
2767
+
};
2768
+
2769
+
/* creq_query_roce_cc_gen2_resp_sb_tlv (size:512b/64B) */
2770
+
struct creq_query_roce_cc_gen2_resp_sb_tlv {
2771
+
__le16 cmd_discr;
2772
+
u8 reserved_8b;
2773
+
u8 tlv_flags;
2774
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2775
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2776
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2777
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2778
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2779
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2780
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2781
+
__le16 tlv_type;
2782
+
__le16 length;
2783
+
__le64 reserved64;
2784
+
__le16 dcn_qlevel_tbl_thr[8];
2785
+
__le32 dcn_qlevel_tbl_act[8];
2786
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK 0x3fffUL
2787
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0
2788
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP 0x4000UL
2789
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM 0x8000UL
2790
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK 0x3fff0000UL
2791
+
#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16
2792
+
};
2793
+
2794
+
/* creq_query_roce_cc_gen1_ext_resp_sb_tlv (size:896b/112B) */
2795
+
struct creq_query_roce_cc_gen1_ext_resp_sb_tlv {
2796
+
__le16 cmd_discr;
2797
+
u8 reserved_8b;
2798
+
u8 tlv_flags;
2799
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2800
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2801
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2802
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2803
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2804
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2805
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2806
+
__le16 tlv_type;
2807
+
__le16 length;
2808
+
__le64 reserved64;
2809
+
__le16 rnd_no_red_mult;
2810
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RND_NO_RED_MULT_MASK 0x3ffUL
2811
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RND_NO_RED_MULT_SFT 0
2812
+
__le16 no_red_offset;
2813
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_NO_RED_OFFSET_MASK 0x7ffUL
2814
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_NO_RED_OFFSET_SFT 0
2815
+
__le16 reduce2_init_cong_free_rtts_th;
2816
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_MASK 0x3ffUL
2817
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_SFT 0
2818
+
u8 reduce2_init_en;
2819
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_REDUCE2_INIT_EN 0x1UL
2820
+
u8 period_adjust_count;
2821
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_PERIOD_ADJUST_COUNT_MASK 0xffUL
2822
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_PERIOD_ADJUST_COUNT_SFT 0
2823
+
__le16 current_rate_threshold_1;
2824
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_1_MASK 0x3fffUL
2825
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_1_SFT 0
2826
+
__le16 current_rate_threshold_2;
2827
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_2_MASK 0x3fffUL
2828
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_CURRENT_RATE_THRESHOLD_2_SFT 0
2829
+
__le32 reserved32;
2830
+
__le64 reserved64_1;
2831
+
u8 rate_table_quota_period[24];
2832
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_QUOTA_PERIOD_MASK 0xffUL
2833
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_QUOTA_PERIOD_SFT 0
2834
+
__le16 rate_table_byte_quota[24];
2835
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_BYTE_QUOTA_MASK 0xffffUL
2836
+
#define CREQ_QUERY_ROCE_CC_GEN1_EXT_RESP_SB_TLV_RATE_TABLE_BYTE_QUOTA_SFT 0
2837
+
};
2838
+
2839
+
/* creq_query_roce_cc_gen2_ext_resp_sb_tlv (size:256b/32B) */
2840
+
struct creq_query_roce_cc_gen2_ext_resp_sb_tlv {
2841
+
__le16 cmd_discr;
2842
+
u8 reserved_8b;
2843
+
u8 tlv_flags;
2844
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2845
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2846
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2847
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2848
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2849
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2850
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2851
+
__le16 tlv_type;
2852
+
__le16 length;
2853
+
__le64 reserved64;
2854
+
__le16 cr2bw_64b_ratio;
2855
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_CR2BW_64B_RATIO_MASK 0x3ffUL
2856
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_CR2BW_64B_RATIO_SFT 0
2857
+
u8 sr2_cc_first_cnp_en;
2858
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_SR2_CC_FIRST_CNP_EN 0x1UL
2859
+
u8 sr2_cc_actual_cr_en;
2860
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_SR2_CC_ACTUAL_CR_EN 0x1UL
2861
+
__le16 retx_cp;
2862
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CP_MASK 0x3ffUL
2863
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CP_SFT 0
2864
+
__le16 retx_cr;
2865
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CR_MASK 0x3fffUL
2866
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_CR_SFT 0
2867
+
__le16 retx_tr;
2868
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_TR_MASK 0x3fffUL
2869
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RETX_TR_SFT 0
2870
+
u8 hw_retx_cc_reset_en;
2871
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_ACK_TIMEOUT_EN 0x1UL
2872
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RX_NAK_EN 0x2UL
2873
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_RX_RNR_NAK_EN 0x4UL
2874
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_MISSING_RESPONSE_EN 0x8UL
2875
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_DUPLICATE_READ_EN 0x10UL
2876
+
u8 reserved8;
2877
+
__le16 hw_retx_reset_cc_cr_th;
2878
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_HW_RETX_RESET_CC_CR_TH_MASK 0x3fffUL
2879
+
#define CREQ_QUERY_ROCE_CC_GEN2_EXT_RESP_SB_TLV_HW_RETX_RESET_CC_CR_TH_SFT 0
2880
+
__le16 reserved16;
2881
+
};
2882
+
2883
+
/* cmdq_modify_roce_cc (size:448b/56B) */
2884
+
struct cmdq_modify_roce_cc {
2885
+
u8 opcode;
2886
+
#define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL
2887
+
#define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC
2888
+
u8 cmd_size;
2889
+
__le16 flags;
2890
+
__le16 cookie;
2891
+
u8 resp_size;
2892
+
u8 reserved8;
2893
+
__le64 resp_addr;
2894
+
__le32 modify_mask;
2895
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL
2896
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL
2897
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2898
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL
2899
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL
2900
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL
2901
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL
2902
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2903
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2904
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL
2905
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL
2906
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL
2907
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL
2908
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2909
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2910
+
#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2911
+
u8 enable_cc;
2912
+
#define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL
2913
+
#define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL
2914
+
#define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
2915
+
u8 g;
2916
+
u8 num_phases_per_state;
2917
+
u8 pkts_per_phase;
2918
+
__le16 init_cr;
2919
+
__le16 init_tr;
2920
+
u8 tos_dscp_tos_ecn;
2921
+
#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL
2922
+
#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
2923
+
#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL
2924
+
#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
2925
+
u8 alt_vlan_pcp;
2926
+
#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL
2927
+
#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
2928
+
#define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL
2929
+
#define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
2930
+
__le16 alt_tos_dscp;
2931
+
#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL
2932
+
#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
2933
+
#define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL
2934
+
#define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
2935
+
__le16 rtt;
2936
+
#define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL
2937
+
#define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
2938
+
#define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL
2939
+
#define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
2940
+
__le16 tcp_cp;
2941
+
#define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL
2942
+
#define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
2943
+
#define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL
2944
+
#define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
2945
+
u8 cc_mode;
2946
+
#define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL
2947
+
#define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2948
+
#define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE
2949
+
u8 tx_queue;
2950
+
__le16 inactivity_th;
2951
+
u8 time_per_phase;
2952
+
u8 reserved8_1;
2953
+
__le16 reserved16;
2954
+
__le32 reserved32;
2955
+
__le64 reserved64;
2956
+
};
2957
+
2958
+
/* cmdq_modify_roce_cc_tlv (size:640b/80B) */
2959
+
struct cmdq_modify_roce_cc_tlv {
2960
+
__le16 cmd_discr;
2961
+
u8 reserved_8b;
2962
+
u8 tlv_flags;
2963
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL
2964
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2965
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2966
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL
2967
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2968
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2969
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES
2970
+
__le16 tlv_type;
2971
+
__le16 length;
2972
+
u8 total_size;
2973
+
u8 reserved56[7];
2974
+
u8 opcode;
2975
+
#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL
2976
+
#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC
2977
+
u8 cmd_size;
2978
+
__le16 flags;
2979
+
__le16 cookie;
2980
+
u8 resp_size;
2981
+
u8 reserved8;
2982
+
__le64 resp_addr;
2983
+
__le32 modify_mask;
2984
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL
2985
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL
2986
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2987
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL
2988
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL
2989
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL
2990
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL
2991
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2992
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2993
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL
2994
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL
2995
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL
2996
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL
2997
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2998
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2999
+
#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
3000
+
u8 enable_cc;
3001
+
#define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL
3002
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL
3003
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1
3004
+
u8 g;
3005
+
u8 num_phases_per_state;
3006
+
u8 pkts_per_phase;
3007
+
__le16 init_cr;
3008
+
__le16 init_tr;
3009
+
u8 tos_dscp_tos_ecn;
3010
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL
3011
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0
3012
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL
3013
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2
3014
+
u8 alt_vlan_pcp;
3015
+
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL
3016
+
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
3017
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL
3018
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3
3019
+
__le16 alt_tos_dscp;
3020
+
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL
3021
+
#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
3022
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL
3023
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6
3024
+
__le16 rtt;
3025
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL
3026
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0
3027
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL
3028
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14
3029
+
__le16 tcp_cp;
3030
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL
3031
+
#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
3032
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL
3033
+
#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10
3034
+
u8 cc_mode;
3035
+
#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL
3036
+
#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
3037
+
#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE
3038
+
u8 tx_queue;
3039
+
__le16 inactivity_th;
3040
+
u8 time_per_phase;
3041
+
u8 reserved8_1;
3042
+
__le16 reserved16;
3043
+
__le32 reserved32;
3044
+
__le64 reserved64;
3045
+
__le64 reservedtlvpad;
3046
+
};
3047
+
3048
+
/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */
3049
+
struct cmdq_modify_roce_cc_gen1_tlv {
3050
+
__le16 cmd_discr;
3051
+
u8 reserved_8b;
3052
+
u8 tlv_flags;
3053
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL
3054
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL
3055
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
3056
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL
3057
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
3058
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
3059
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES
3060
+
__le16 tlv_type;
3061
+
__le16 length;
3062
+
__le64 reserved64;
3063
+
__le64 modify_mask;
3064
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL
3065
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL
3066
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL
3067
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL
3068
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL
3069
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL
3070
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL
3071
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL
3072
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL
3073
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL
3074
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL
3075
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL
3076
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL
3077
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL
3078
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL
3079
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL
3080
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL
3081
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL
3082
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL
3083
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL
3084
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL
3085
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL
3086
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL
3087
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL
3088
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL
3089
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL
3090
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL
3091
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL
3092
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL
3093
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL
3094
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL
3095
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL
3096
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL
3097
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL
3098
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL
3099
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL
3100
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL
3101
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL
3102
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL
3103
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL
3104
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH 0x10000000000ULL
3105
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL
3106
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN 0x40000000000ULL
3107
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL
3108
+
__le16 inactivity_th_hi;
3109
+
__le16 min_time_between_cnps;
3110
+
__le16 init_cp;
3111
+
u8 tr_update_mode;
3112
+
u8 tr_update_cycles;
3113
+
u8 fr_num_rtts;
3114
+
u8 ai_rate_increase;
3115
+
__le16 reduction_relax_rtts_th;
3116
+
__le16 additional_relax_cr_th;
3117
+
__le16 cr_min_th;
3118
+
u8 bw_avg_weight;
3119
+
u8 actual_cr_factor;
3120
+
__le16 max_cp_cr_th;
3121
+
u8 cp_bias_en;
3122
+
u8 cp_bias;
3123
+
u8 cnp_ecn;
3124
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL
3125
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL
3126
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL
3127
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0
3128
+
u8 rtt_jitter_en;
3129
+
__le16 link_bytes_per_usec;
3130
+
__le16 reset_cc_cr_th;
3131
+
u8 cr_width;
3132
+
u8 quota_period_min;
3133
+
u8 quota_period_max;
3134
+
u8 quota_period_abs_max;
3135
+
__le16 tr_lower_bound;
3136
+
u8 cr_prob_factor;
3137
+
u8 tr_prob_factor;
3138
+
__le16 fairness_cr_th;
3139
+
u8 red_div;
3140
+
u8 cnp_ratio_th;
3141
+
__le16 exp_ai_rtts;
3142
+
u8 exp_ai_cr_cp_ratio;
3143
+
u8 use_rate_table;
3144
+
__le16 cp_exp_update_th;
3145
+
__le16 high_exp_ai_rtts_th1;
3146
+
__le16 high_exp_ai_rtts_th2;
3147
+
__le16 actual_cr_cong_free_rtts_th;
3148
+
__le16 severe_cong_cr_th1;
3149
+
__le16 severe_cong_cr_th2;
3150
+
__le32 link64B_per_rtt;
3151
+
u8 cc_ack_bytes;
3152
+
u8 reduce_init_en;
3153
+
__le16 reduce_init_cong_free_rtts_th;
3154
+
u8 random_no_red_en;
3155
+
u8 actual_cr_shift_correction_en;
3156
+
u8 quota_period_adjust_en;
3157
+
u8 reserved[5];
3158
+
};
3159
+
3160
+
/* cmdq_modify_roce_cc_gen2_tlv (size:256b/32B) */
3161
+
struct cmdq_modify_roce_cc_gen2_tlv {
3162
+
__le16 cmd_discr;
3163
+
u8 reserved_8b;
3164
+
u8 tlv_flags;
3165
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE 0x1UL
3166
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST 0x0UL
3167
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
3168
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED 0x2UL
3169
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
3170
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
3171
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES
3172
+
__le16 tlv_type;
3173
+
__le16 length;
3174
+
__le64 reserved64;
3175
+
__le64 modify_mask;
3176
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX 0x1UL
3177
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR 0x2UL
3178
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR 0x4UL
3179
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP 0x8UL
3180
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM 0x10UL
3181
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR 0x20UL
3182
+
u8 dcn_qlevel_tbl_idx;
3183
+
u8 reserved8;
3184
+
__le16 dcn_qlevel_tbl_thr;
3185
+
__le32 dcn_qlevel_tbl_act;
3186
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK 0x3fffUL
3187
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0
3188
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP 0x4000UL
3189
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM 0x8000UL
3190
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK 0x3fff0000UL
3191
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16
3192
+
};
3193
+
3194
+
/* cmdq_modify_roce_cc_gen1_ext_tlv (size:384b/48B) */
3195
+
struct cmdq_modify_roce_cc_gen1_ext_tlv {
3196
+
__le16 cmd_discr;
3197
+
u8 reserved_8b;
3198
+
u8 tlv_flags;
3199
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE 0x1UL
3200
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE_LAST 0x0UL
3201
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
3202
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED 0x2UL
3203
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
3204
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
3205
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_TLV_FLAGS_REQUIRED_YES
3206
+
__le16 tlv_type;
3207
+
__le16 length;
3208
+
__le64 reserved64;
3209
+
__le64 modify_mask;
3210
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RND_NO_RED_MULT 0x1UL
3211
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_NO_RED_OFFSET 0x2UL
3212
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_REDUCE2_INIT_CONG_FREE_RTTS_TH 0x4UL
3213
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_REDUCE2_INIT_EN 0x8UL
3214
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_PERIOD_ADJUST_COUNT 0x10UL
3215
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_CURRENT_RATE_THRESHOLD_1 0x20UL
3216
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_CURRENT_RATE_THRESHOLD_2 0x40UL
3217
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_IDX 0x80UL
3218
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_QUOTA_PERIOD 0x100UL
3219
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_MODIFY_MASK_RATE_TABLE_BYTE_QUOTA 0x200UL
3220
+
__le16 rnd_no_red_mult;
3221
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RND_NO_RED_MULT_MASK 0x3ffUL
3222
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RND_NO_RED_MULT_SFT 0
3223
+
__le16 no_red_offset;
3224
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_NO_RED_OFFSET_MASK 0x7ffUL
3225
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_NO_RED_OFFSET_SFT 0
3226
+
__le16 reduce2_init_cong_free_rtts_th;
3227
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_MASK 0x3ffUL
3228
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_CONG_FREE_RTTS_TH_SFT 0
3229
+
u8 reduce2_init_en;
3230
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_REDUCE2_INIT_EN 0x1UL
3231
+
u8 period_adjust_count;
3232
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_PERIOD_ADJUST_COUNT_MASK 0xffUL
3233
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_PERIOD_ADJUST_COUNT_SFT 0
3234
+
__le16 current_rate_threshold_1;
3235
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_1_MASK 0x3fffUL
3236
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_1_SFT 0
3237
+
__le16 current_rate_threshold_2;
3238
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_2_MASK 0x3fffUL
3239
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_CURRENT_RATE_THRESHOLD_2_SFT 0
3240
+
u8 rate_table_idx;
3241
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_IDX_MASK 0xffUL
3242
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_IDX_SFT 0
3243
+
u8 rate_table_quota_period;
3244
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_QUOTA_PERIOD_MASK 0xffUL
3245
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_QUOTA_PERIOD_SFT 0
3246
+
__le16 rate_table_byte_quota;
3247
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_BYTE_QUOTA_MASK 0xffffUL
3248
+
#define CMDQ_MODIFY_ROCE_CC_GEN1_EXT_TLV_RATE_TABLE_BYTE_QUOTA_SFT 0
3249
+
__le64 reserved64_1;
3250
+
};
3251
+
3252
+
/* cmdq_modify_roce_cc_gen2_ext_tlv (size:384b/48B) */
3253
+
struct cmdq_modify_roce_cc_gen2_ext_tlv {
3254
+
__le16 cmd_discr;
3255
+
u8 reserved_8b;
3256
+
u8 tlv_flags;
3257
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE 0x1UL
3258
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE_LAST 0x0UL
3259
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
3260
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED 0x2UL
3261
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
3262
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
3263
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_TLV_FLAGS_REQUIRED_YES
3264
+
__le16 tlv_type;
3265
+
__le16 length;
3266
+
__le64 reserved64;
3267
+
__le64 modify_mask;
3268
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_CR2BW_64B_RATIO 0x1UL
3269
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_SR2_CC_FIRST_CNP_EN 0x2UL
3270
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_SR2_CC_ACTUAL_CR_EN 0x4UL
3271
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_CP 0x8UL
3272
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_CR 0x10UL
3273
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_RETX_TR 0x20UL
3274
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_HW_RETX_CC_RESET_EN 0x40UL
3275
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MODIFY_MASK_HW_RETX_RESET_CC_CR_TH 0x80UL
3276
+
__le64 reserved64_1;
3277
+
__le16 cr2bw_64b_ratio;
3278
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_CR2BW_64B_RATIO_MASK 0x3ffUL
3279
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_CR2BW_64B_RATIO_SFT 0
3280
+
u8 sr2_cc_first_cnp_en;
3281
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_SR2_CC_FIRST_CNP_EN 0x1UL
3282
+
u8 sr2_cc_actual_cr_en;
3283
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_SR2_CC_ACTUAL_CR_EN 0x1UL
3284
+
__le16 retx_cp;
3285
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CP_MASK 0x3ffUL
3286
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CP_SFT 0
3287
+
__le16 retx_cr;
3288
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CR_MASK 0x3fffUL
3289
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_CR_SFT 0
3290
+
__le16 retx_tr;
3291
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_TR_MASK 0x3fffUL
3292
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RETX_TR_SFT 0
3293
+
u8 hw_retx_cc_reset_en;
3294
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_ACK_TIMEOUT_EN 0x1UL
3295
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RX_NAK_EN 0x2UL
3296
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_RX_RNR_NAK_EN 0x4UL
3297
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_MISSING_RESPONSE_EN 0x8UL
3298
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_DUPLICATE_READ_EN 0x10UL
3299
+
u8 reserved8;
3300
+
__le16 hw_retx_reset_cc_cr_th;
3301
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_HW_RETX_RESET_CC_CR_TH_MASK 0x3fffUL
3302
+
#define CMDQ_MODIFY_ROCE_CC_GEN2_EXT_TLV_HW_RETX_RESET_CC_CR_TH_SFT 0
3303
+
__le16 reserved16;
3304
+
};
3305
+
3306
+
/* creq_modify_roce_cc_resp (size:128b/16B) */
3307
+
struct creq_modify_roce_cc_resp {
3308
+
u8 type;
3309
+
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
3310
+
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
3311
+
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
3312
+
#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT
3313
+
u8 status;
3314
+
__le16 cookie;
3315
+
__le32 reserved32;
3316
+
u8 v;
3317
+
#define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL
3318
+
u8 event;
3319
+
#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL
3320
+
#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC
3321
+
u8 reserved48[6];
3322
+
};
3323
+
3324
+
/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */
3325
+
struct cmdq_set_link_aggr_mode_cc {
3326
+
u8 opcode;
3327
+
#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
3328
+
#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE
3329
+
u8 cmd_size;
3330
+
__le16 flags;
3331
+
__le16 cookie;
3332
+
u8 resp_size;
3333
+
u8 reserved8;
3334
+
__le64 resp_addr;
3335
+
__le32 modify_mask;
3336
+
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL
3337
+
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL
3338
+
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL
3339
+
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL
3340
+
#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL
3341
+
u8 aggr_enable;
3342
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL
3343
+
#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL
3344
+
#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1
3345
+
u8 active_port_map;
3346
+
#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL
3347
+
#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
3348
+
#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL
3349
+
#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4
3350
+
u8 member_port_map;
3351
+
u8 link_aggr_mode;
3352
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL
3353
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL
3354
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL
3355
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL
3356
+
#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD
3357
+
__le16 stat_ctx_id[4];
3358
+
__le64 rsvd1;
3359
+
};
3360
+
3361
+
/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */
3362
+
struct creq_set_link_aggr_mode_resources_resp {
3363
+
u8 type;
3364
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL
3365
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0
3366
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL
3367
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT
3368
+
u8 status;
3369
+
__le16 cookie;
3370
+
__le32 reserved32;
3371
+
u8 v;
3372
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL
3373
+
u8 event;
3374
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL
3375
+
#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE
3376
+
u8 reserved48[6];
3377
+
};
3378
+
3379
+
/* cmdq_allocate_roce_stats_ext_ctx (size:256b/32B) */
3380
+
struct cmdq_allocate_roce_stats_ext_ctx {
3381
+
u8 opcode;
3382
+
#define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL
3383
+
#define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX
3384
+
u8 cmd_size;
3385
+
__le16 flags;
3386
+
#define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_FLAGS_PER_FUNC 0x1UL
3387
+
__le16 cookie;
3388
+
u8 resp_size;
3389
+
u8 reserved8;
3390
+
__le64 resp_addr;
3391
+
__le64 stats_dma_addr;
3392
+
__le32 update_period_ms;
3393
+
__le16 steering_tag;
3394
+
__le16 reserved16;
3395
+
};
3396
+
3397
+
/* creq_allocate_roce_stats_ext_ctx_resp (size:128b/16B) */
3398
+
struct creq_allocate_roce_stats_ext_ctx_resp {
3399
+
u8 type;
3400
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK 0x3fUL
3401
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0
3402
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 0x38UL
3403
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT
3404
+
u8 status;
3405
+
__le16 cookie;
3406
+
__le32 roce_stats_ext_xid;
3407
+
u8 v;
3408
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V 0x1UL
3409
+
u8 event;
3410
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX 0x96UL
3411
+
#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX
3412
+
u8 reserved48[6];
3413
+
};
3414
+
3415
+
/* cmdq_deallocate_roce_stats_ext_ctx (size:256b/32B) */
3416
+
struct cmdq_deallocate_roce_stats_ext_ctx {
3417
+
u8 opcode;
3418
+
#define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL
3419
+
#define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX
3420
+
u8 cmd_size;
3421
+
__le16 flags;
3422
+
__le16 cookie;
3423
+
u8 resp_size;
3424
+
u8 reserved8;
3425
+
__le64 resp_addr;
3426
+
__le32 roce_stats_ext_xid;
3427
+
__le32 reserved32;
3428
+
__le64 reserved64;
3429
+
};
3430
+
3431
+
/* creq_deallocate_roce_stats_ext_ctx_resp (size:128b/16B) */
3432
+
struct creq_deallocate_roce_stats_ext_ctx_resp {
3433
+
u8 type;
3434
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK 0x3fUL
3435
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0
3436
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT 0x38UL
3437
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT
3438
+
u8 status;
3439
+
__le16 cookie;
3440
+
__le32 roce_stats_ext_xid;
3441
+
u8 v;
3442
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V 0x1UL
3443
+
u8 event;
3444
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX 0x97UL
3445
+
#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX
3446
+
u8 reserved48[6];
3447
+
};
3448
+
3449
+
/* cmdq_query_roce_stats_ext_v2 (size:256b/32B) */
3450
+
struct cmdq_query_roce_stats_ext_v2 {
3451
+
u8 opcode;
3452
+
#define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL
3453
+
#define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2
3454
+
u8 cmd_size;
3455
+
__le16 flags;
3456
+
__le16 cookie;
3457
+
u8 resp_size;
3458
+
u8 reserved8;
3459
+
__le64 resp_addr;
3460
+
__le32 roce_stats_ext_xid;
3461
+
__le32 reserved32;
3462
+
__le64 reserved64;
3463
+
};
3464
+
3465
+
/* creq_query_roce_stats_ext_v2_resp (size:128b/16B) */
3466
+
struct creq_query_roce_stats_ext_v2_resp {
3467
+
u8 type;
3468
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK 0x3fUL
3469
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT 0
3470
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT 0x38UL
3471
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT
3472
+
u8 status;
3473
+
__le16 cookie;
3474
+
__le32 size;
3475
+
u8 v;
3476
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V 0x1UL
3477
+
u8 event;
3478
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 0x98UL
3479
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2
3480
+
u8 reserved48[6];
3481
+
};
3482
+
3483
+
/* creq_query_roce_stats_ext_v2_resp_sb (size:2304b/288B) */
3484
+
struct creq_query_roce_stats_ext_v2_resp_sb {
3485
+
u8 opcode;
3486
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 0x98UL
3487
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2
3488
+
u8 status;
3489
+
__le16 cookie;
3490
+
__le16 flags;
3491
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_TS_VALID 0x1UL
3492
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_RSVD_MASK 0xfffeUL
3493
+
#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_RSVD_SFT 1
3494
+
u8 resp_size;
3495
+
u8 offset;
3496
+
__le64 timestamp;
3497
+
__le32 rsvd[8];
3498
+
__le64 tx_atomic_req_pkts;
3499
+
__le64 tx_read_req_pkts;
3500
+
__le64 tx_read_res_pkts;
3501
+
__le64 tx_write_req_pkts;
3502
+
__le64 tx_rc_send_req_pkts;
3503
+
__le64 tx_ud_send_req_pkts;
3504
+
__le64 tx_cnp_pkts;
3505
+
__le64 tx_roce_pkts;
3506
+
__le64 tx_roce_bytes;
3507
+
__le64 rx_out_of_buffer_pkts;
3508
+
__le64 rx_out_of_sequence_pkts;
3509
+
__le64 dup_req;
3510
+
__le64 missing_resp;
3511
+
__le64 seq_err_naks_rcvd;
3512
+
__le64 rnr_naks_rcvd;
3513
+
__le64 to_retransmits;
3514
+
__le64 rx_atomic_req_pkts;
3515
+
__le64 rx_read_req_pkts;
3516
+
__le64 rx_read_res_pkts;
3517
+
__le64 rx_write_req_pkts;
3518
+
__le64 rx_rc_send_pkts;
3519
+
__le64 rx_ud_send_pkts;
3520
+
__le64 rx_dcn_payload_cut;
3521
+
__le64 rx_ecn_marked_pkts;
3522
+
__le64 rx_cnp_pkts;
3523
+
__le64 rx_roce_pkts;
3524
+
__le64 rx_roce_bytes;
3525
+
__le64 rx_roce_good_pkts;
3526
+
__le64 rx_roce_good_bytes;
3527
+
__le64 rx_ack_pkts;
3528
+
};
3529
+
3530
+
/* cmdq_roce_mirror_cfg (size:192b/24B) */
3531
+
struct cmdq_roce_mirror_cfg {
3532
+
u8 opcode;
3533
+
#define CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 0xa6UL
3534
+
#define CMDQ_ROCE_MIRROR_CFG_OPCODE_LAST CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG
3535
+
u8 cmd_size;
3536
+
__le16 flags;
3537
+
__le16 cookie;
3538
+
u8 resp_size;
3539
+
u8 reserved8;
3540
+
__le64 resp_addr;
3541
+
u8 mirror_flags;
3542
+
#define CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE 0x1UL
3543
+
u8 rsvd[7];
3544
+
};
3545
+
3546
+
/* creq_roce_mirror_cfg_resp (size:128b/16B) */
3547
+
struct creq_roce_mirror_cfg_resp {
3548
+
u8 type;
3549
+
#define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_MASK 0x3fUL
3550
+
#define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_SFT 0
3551
+
#define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 0x38UL
3552
+
#define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_LAST CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT
3553
+
u8 status;
3554
+
__le16 cookie;
3555
+
__le32 reserved32;
3556
+
u8 v;
3557
+
#define CREQ_ROCE_MIRROR_CFG_RESP_V 0x1UL
3558
+
u8 event;
3559
+
#define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 0xa6UL
3560
+
#define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_LAST CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG
3561
+
u8 reserved48[6];
3562
+
};
3563
+
3564
+
/* cmdq_roce_cfg (size:192b/24B) */
3565
+
struct cmdq_roce_cfg {
3566
+
u8 opcode;
3567
+
#define CMDQ_ROCE_CFG_OPCODE_ROCE_CFG 0xa7UL
3568
+
#define CMDQ_ROCE_CFG_OPCODE_LAST CMDQ_ROCE_CFG_OPCODE_ROCE_CFG
3569
+
u8 cmd_size;
3570
+
__le16 flags;
3571
+
__le16 cookie;
3572
+
u8 resp_size;
3573
+
u8 reserved8;
3574
+
__le64 resp_addr;
3575
+
__le32 feat_cfg;
3576
+
#define CMDQ_ROCE_CFG_FEAT_CFG_ICRC_CHECK_DISABLE 0x1UL
3577
+
#define CMDQ_ROCE_CFG_FEAT_CFG_FORCE_MIRROR_ENABLE 0x2UL
3578
+
#define CMDQ_ROCE_CFG_FEAT_CFG_RSVD_MASK 0xfffffffcUL
3579
+
#define CMDQ_ROCE_CFG_FEAT_CFG_RSVD_SFT 2
3580
+
__le32 feat_enables;
3581
+
#define CMDQ_ROCE_CFG_FEAT_ENABLES_ICRC_CHECK_DISABLE 0x1UL
3582
+
#define CMDQ_ROCE_CFG_FEAT_ENABLES_FORCE_MIRROR_ENABLE 0x2UL
3583
+
#define CMDQ_ROCE_CFG_FEAT_ENABLES_RSVD_MASK 0xfffffffcUL
3584
+
#define CMDQ_ROCE_CFG_FEAT_ENABLES_RSVD_SFT 2
3585
+
};
3586
+
3587
+
/* creq_roce_cfg_resp (size:128b/16B) */
3588
+
struct creq_roce_cfg_resp {
3589
+
u8 type;
3590
+
#define CREQ_ROCE_CFG_RESP_TYPE_MASK 0x3fUL
3591
+
#define CREQ_ROCE_CFG_RESP_TYPE_SFT 0
3592
+
#define CREQ_ROCE_CFG_RESP_TYPE_QP_EVENT 0x38UL
3593
+
#define CREQ_ROCE_CFG_RESP_TYPE_LAST CREQ_ROCE_CFG_RESP_TYPE_QP_EVENT
3594
+
u8 status;
3595
+
__le16 cookie;
3596
+
__le32 reserved04;
3597
+
u8 v;
3598
+
#define CREQ_ROCE_CFG_RESP_V 0x1UL
3599
+
u8 event;
3600
+
#define CREQ_ROCE_CFG_RESP_EVENT_ROCE_CFG 0xa7UL
3601
+
#define CREQ_ROCE_CFG_RESP_EVENT_LAST CREQ_ROCE_CFG_RESP_EVENT_ROCE_CFG
3602
+
__le16 reserved0A;
3603
+
__le32 feat_cfg_cur;
3604
+
#define CREQ_ROCE_CFG_RESP_ICRC_CHECK_DISABLED 0x1UL
3605
+
#define CREQ_ROCE_CFG_RESP_FORCE_MIRROR_ENABLE 0x2UL
3606
+
#define CREQ_ROCE_CFG_RESP_RSVD_MASK 0xfffffffcUL
3607
+
#define CREQ_ROCE_CFG_RESP_RSVD_SFT 2
3608
+
};
3609
+
3610
+
/* creq_func_event (size:128b/16B) */
3611
+
struct creq_func_event {
3612
+
u8 type;
3613
+
#define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL
3614
+
#define CREQ_FUNC_EVENT_TYPE_SFT 0
3615
+
#define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL
3616
+
#define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT
3617
+
u8 reserved56[7];
3618
+
u8 v;
3619
+
#define CREQ_FUNC_EVENT_V 0x1UL
3620
+
u8 event;
3621
+
#define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL
3622
+
#define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL
3623
+
#define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL
3624
+
#define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL
3625
+
#define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL
3626
+
#define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL
3627
+
#define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL
3628
+
#define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL
3629
+
#define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL
3630
+
#define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL
3631
+
#define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL
3632
+
#define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL
3633
+
#define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL
3634
+
#define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED
3635
+
u8 reserved48[6];
3636
+
};
3637
+
3638
+
/* creq_qp_event (size:128b/16B) */
3639
+
struct creq_qp_event {
3640
+
u8 type;
3641
+
#define CREQ_QP_EVENT_TYPE_MASK 0x3fUL
3642
+
#define CREQ_QP_EVENT_TYPE_SFT 0
3643
+
#define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL
3644
+
#define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT
3645
+
u8 status;
3646
+
#define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL
3647
+
#define CREQ_QP_EVENT_STATUS_FAIL 0x1UL
3648
+
#define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL
3649
+
#define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL
3650
+
#define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL
3651
+
#define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL
3652
+
#define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL
3653
+
#define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL
3654
+
#define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR
3655
+
__le16 cookie;
3656
+
__le32 reserved32;
3657
+
u8 v;
3658
+
#define CREQ_QP_EVENT_V 0x1UL
3659
+
u8 event;
3660
+
#define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL
3661
+
#define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL
3662
+
#define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL
3663
+
#define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL
3664
+
#define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL
3665
+
#define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL
3666
+
#define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL
3667
+
#define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL
3668
+
#define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL
3669
+
#define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL
3670
+
#define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL
3671
+
#define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL
3672
+
#define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL
3673
+
#define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL
3674
+
#define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL
3675
+
#define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL
3676
+
#define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL
3677
+
#define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL
3678
+
#define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL
3679
+
#define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL
3680
+
#define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL
3681
+
#define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL
3682
+
#define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL
3683
+
#define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL
3684
+
#define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL
3685
+
#define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL
3686
+
#define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL
3687
+
#define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL
3688
+
#define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL
3689
+
#define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL
3690
+
#define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL
3691
+
#define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL
3692
+
#define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL
3693
+
#define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL
3694
+
#define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL
3695
+
#define CREQ_QP_EVENT_EVENT_PNO_STATS_CONFIG 0x99UL
3696
+
#define CREQ_QP_EVENT_EVENT_PNO_DEBUG_TUNNEL_CONFIG 0x9aUL
3697
+
#define CREQ_QP_EVENT_EVENT_SET_PNO_FABRIC_NEXTHOP_MAC 0x9bUL
3698
+
#define CREQ_QP_EVENT_EVENT_PNO_PATH_STRPATH_CONFIG 0x9cUL
3699
+
#define CREQ_QP_EVENT_EVENT_PNO_PATH_QUERY 0x9dUL
3700
+
#define CREQ_QP_EVENT_EVENT_PNO_PATH_ACCESS_CONTROL 0x9eUL
3701
+
#define CREQ_QP_EVENT_EVENT_QUERY_PNO_FABRIC_NEXTHOP_IP 0x9fUL
3702
+
#define CREQ_QP_EVENT_EVENT_PNO_PATH_PLANE_CONFIG 0xa0UL
3703
+
#define CREQ_QP_EVENT_EVENT_PNO_TUNNEL_CLOSE 0xa1UL
3704
+
#define CREQ_QP_EVENT_EVENT_ROCE_MIRROR_CFG 0xa6UL
3705
+
#define CREQ_QP_EVENT_EVENT_ROCE_CFG 0xa7UL
3706
+
#define CREQ_QP_EVENT_EVENT_PNO_EV_MONITORING_CONFIG 0xa8UL
3707
+
#define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3708
+
#define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3709
+
#define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION
3710
+
u8 reserved48[6];
3711
+
};
3712
+
3713
+
/* creq_qp_error_notification (size:128b/16B) */
3714
+
struct creq_qp_error_notification {
3715
+
u8 type;
3716
+
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3717
+
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
3718
+
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL
3719
+
#define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT
3720
+
u8 status;
3721
+
u8 req_slow_path_state;
3722
+
u8 req_err_state_reason;
3723
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0x0UL
3724
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0x1UL
3725
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0x2UL
3726
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0x3UL
3727
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0x4UL
3728
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0x5UL
3729
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0x6UL
3730
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0x7UL
3731
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0x8UL
3732
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0x9UL
3733
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0xaUL
3734
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0xbUL
3735
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0xcUL
3736
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0xdUL
3737
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0xeUL
3738
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0xfUL
3739
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0x10UL
3740
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0x11UL
3741
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0x12UL
3742
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0x13UL
3743
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0x14UL
3744
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0x15UL
3745
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0x16UL
3746
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0x17UL
3747
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0x18UL
3748
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0x19UL
3749
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0x1aUL
3750
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0x1bUL
3751
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0x1cUL
3752
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW 0x1dUL
3753
+
#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW
3754
+
__le32 xid;
3755
+
u8 v;
3756
+
#define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL
3757
+
u8 event;
3758
+
#define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3759
+
#define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION
3760
+
u8 res_slow_path_state;
3761
+
u8 res_err_state_reason;
3762
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL
3763
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL
3764
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL
3765
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL
3766
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL
3767
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL
3768
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL
3769
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL
3770
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL
3771
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL
3772
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL
3773
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL
3774
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL
3775
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL
3776
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL
3777
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL
3778
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL
3779
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL
3780
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL
3781
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL
3782
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL
3783
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL
3784
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL
3785
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL
3786
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL
3787
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL
3788
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL
3789
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL
3790
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL
3791
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW 0x1eUL
3792
+
#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW
3793
+
__le16 sq_cons_idx;
3794
+
__le16 rq_cons_idx;
3795
+
};
3796
+
3797
+
/* creq_cq_error_notification (size:128b/16B) */
3798
+
struct creq_cq_error_notification {
3799
+
u8 type;
3800
+
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3801
+
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0
3802
+
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL
3803
+
#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT
3804
+
u8 status;
3805
+
u8 cq_err_reason;
3806
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL
3807
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL
3808
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL
3809
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL
3810
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL
3811
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL
3812
+
#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR
3813
+
u8 reserved8;
3814
+
__le32 xid;
3815
+
u8 v;
3816
+
#define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL
3817
+
u8 event;
3818
+
#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3819
+
#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION
3820
+
u8 reserved48[6];
3821
+
};
3822
+
3823
+
/* sq_base (size:64b/8B) */
3824
+
struct sq_base {
3825
+
u8 wqe_type;
3826
+
#define SQ_BASE_WQE_TYPE_SEND 0x0UL
3827
+
#define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3828
+
#define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL
3829
+
#define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL
3830
+
#define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3831
+
#define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL
3832
+
#define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL
3833
+
#define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL
3834
+
#define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL
3835
+
#define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL
3836
+
#define SQ_BASE_WQE_TYPE_BIND 0xeUL
3837
+
#define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL
3838
+
#define SQ_BASE_WQE_TYPE_SEND_V3 0x10UL
3839
+
#define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 0x11UL
3840
+
#define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 0x12UL
3841
+
#define SQ_BASE_WQE_TYPE_UDSEND_V3 0x13UL
3842
+
#define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL
3843
+
#define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 0x15UL
3844
+
#define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL
3845
+
#define SQ_BASE_WQE_TYPE_READ_WQE_V3 0x17UL
3846
+
#define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 0x18UL
3847
+
#define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 0x19UL
3848
+
#define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL
3849
+
#define SQ_BASE_WQE_TYPE_FR_PMR_V3 0x1bUL
3850
+
#define SQ_BASE_WQE_TYPE_BIND_V3 0x1cUL
3851
+
#define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 0x1dUL
3852
+
#define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL
3853
+
#define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3
3854
+
u8 unused_0[7];
3855
+
};
3856
+
3857
+
/* sq_sge (size:128b/16B) */
3858
+
struct sq_sge {
3859
+
__le64 va_or_pa;
3860
+
__le32 l_key;
3861
+
__le32 size;
3862
+
};
3863
+
3864
+
/* sq_psn_search (size:64b/8B) */
3865
+
struct sq_psn_search {
3866
+
__le32 opcode_start_psn;
3867
+
#define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL
3868
+
#define SQ_PSN_SEARCH_START_PSN_SFT 0
3869
+
#define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL
3870
+
#define SQ_PSN_SEARCH_OPCODE_SFT 24
3871
+
__le32 flags_next_psn;
3872
+
#define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL
3873
+
#define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
3874
+
#define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL
3875
+
#define SQ_PSN_SEARCH_FLAGS_SFT 24
3876
+
};
3877
+
3878
+
/* sq_psn_search_ext (size:128b/16B) */
3879
+
struct sq_psn_search_ext {
3880
+
__le32 opcode_start_psn;
3881
+
#define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL
3882
+
#define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
3883
+
#define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL
3884
+
#define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24
3885
+
__le32 flags_next_psn;
3886
+
#define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL
3887
+
#define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
3888
+
#define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL
3889
+
#define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24
3890
+
__le16 start_slot_idx;
3891
+
__le16 reserved16;
3892
+
__le32 reserved32;
3893
+
};
3894
+
3895
+
/* sq_msn_search (size:64b/8B) */
3896
+
struct sq_msn_search {
3897
+
__le64 start_idx_next_psn_start_psn;
3898
+
#define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL
3899
+
#define SQ_MSN_SEARCH_START_PSN_SFT 0
3900
+
#define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
3901
+
#define SQ_MSN_SEARCH_NEXT_PSN_SFT 24
3902
+
#define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
3903
+
#define SQ_MSN_SEARCH_START_IDX_SFT 48
3904
+
};
3905
+
3906
+
/* sq_send (size:1024b/128B) */
3907
+
struct sq_send {
3908
+
u8 wqe_type;
3909
+
#define SQ_SEND_WQE_TYPE_SEND 0x0UL
3910
+
#define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3911
+
#define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL
3912
+
#define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID
3913
+
u8 flags;
3914
+
#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3915
+
#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3916
+
#define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL
3917
+
#define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3918
+
#define SQ_SEND_FLAGS_UC_FENCE 0x4UL
3919
+
#define SQ_SEND_FLAGS_SE 0x8UL
3920
+
#define SQ_SEND_FLAGS_INLINE 0x10UL
3921
+
#define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL
3922
+
#define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL
3923
+
u8 wqe_size;
3924
+
u8 reserved8_1;
3925
+
__le32 inv_key_or_imm_data;
3926
+
__le32 length;
3927
+
__le32 q_key;
3928
+
__le32 dst_qp;
3929
+
#define SQ_SEND_DST_QP_MASK 0xffffffUL
3930
+
#define SQ_SEND_DST_QP_SFT 0
3931
+
__le32 avid;
3932
+
#define SQ_SEND_AVID_MASK 0xfffffUL
3933
+
#define SQ_SEND_AVID_SFT 0
3934
+
__le32 reserved32;
3935
+
__le32 timestamp;
3936
+
#define SQ_SEND_TIMESTAMP_MASK 0xffffffUL
3937
+
#define SQ_SEND_TIMESTAMP_SFT 0
3938
+
__le32 data[24];
3939
+
};
3940
+
3941
+
/* sq_send_hdr (size:256b/32B) */
3942
+
struct sq_send_hdr {
3943
+
u8 wqe_type;
3944
+
#define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL
3945
+
#define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3946
+
#define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL
3947
+
#define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID
3948
+
u8 flags;
3949
+
#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3950
+
#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3951
+
#define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3952
+
#define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3953
+
#define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL
3954
+
#define SQ_SEND_HDR_FLAGS_SE 0x8UL
3955
+
#define SQ_SEND_HDR_FLAGS_INLINE 0x10UL
3956
+
#define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL
3957
+
#define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3958
+
u8 wqe_size;
3959
+
u8 reserved8_1;
3960
+
__le32 inv_key_or_imm_data;
3961
+
__le32 length;
3962
+
__le32 q_key;
3963
+
__le32 dst_qp;
3964
+
#define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL
3965
+
#define SQ_SEND_HDR_DST_QP_SFT 0
3966
+
__le32 avid;
3967
+
#define SQ_SEND_HDR_AVID_MASK 0xfffffUL
3968
+
#define SQ_SEND_HDR_AVID_SFT 0
3969
+
__le32 reserved32;
3970
+
__le32 timestamp;
3971
+
#define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL
3972
+
#define SQ_SEND_HDR_TIMESTAMP_SFT 0
3973
+
};
3974
+
3975
+
/* sq_send_raweth_qp1 (size:1024b/128B) */
3976
+
struct sq_send_raweth_qp1 {
3977
+
u8 wqe_type;
3978
+
#define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL
3979
+
#define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND
3980
+
u8 flags;
3981
+
#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3982
+
#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3983
+
#define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL
3984
+
#define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3985
+
#define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL
3986
+
#define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL
3987
+
#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL
3988
+
#define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL
3989
+
#define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL
3990
+
u8 wqe_size;
3991
+
u8 reserved8;
3992
+
__le16 lflags;
3993
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3994
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL
3995
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL
3996
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL
3997
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL
3998
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL
3999
+
#define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL
4000
+
__le16 cfa_action;
4001
+
__le32 length;
4002
+
__le32 reserved32_1;
4003
+
__le32 cfa_meta;
4004
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL
4005
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
4006
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL
4007
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL
4008
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
4009
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL
4010
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
4011
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
4012
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
4013
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
4014
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
4015
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
4016
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
4017
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
4018
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
4019
+
#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
4020
+
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL
4021
+
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
4022
+
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28)
4023
+
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
4024
+
#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
4025
+
__le32 reserved32_2;
4026
+
__le32 reserved32_3;
4027
+
__le32 timestamp;
4028
+
#define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL
4029
+
#define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
4030
+
__le32 data[24];
4031
+
};
4032
+
4033
+
/* sq_send_raweth_qp1_hdr (size:256b/32B) */
4034
+
struct sq_send_raweth_qp1_hdr {
4035
+
u8 wqe_type;
4036
+
#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL
4037
+
#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND
4038
+
u8 flags;
4039
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4040
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4041
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL
4042
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4043
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL
4044
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL
4045
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL
4046
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL
4047
+
#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL
4048
+
u8 wqe_size;
4049
+
u8 reserved8;
4050
+
__le16 lflags;
4051
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL
4052
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL
4053
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL
4054
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL
4055
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL
4056
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL
4057
+
#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL
4058
+
__le16 cfa_action;
4059
+
__le32 length;
4060
+
__le32 reserved32_1;
4061
+
__le32 cfa_meta;
4062
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL
4063
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0
4064
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL
4065
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL
4066
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13
4067
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL
4068
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16
4069
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
4070
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
4071
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
4072
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
4073
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
4074
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
4075
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG
4076
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
4077
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19
4078
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL
4079
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28
4080
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28)
4081
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
4082
+
#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG
4083
+
__le32 reserved32_2;
4084
+
__le32 reserved32_3;
4085
+
__le32 timestamp;
4086
+
#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL
4087
+
#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
4088
+
};
4089
+
4090
+
/* sq_rdma (size:1024b/128B) */
4091
+
struct sq_rdma {
4092
+
u8 wqe_type;
4093
+
#define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL
4094
+
#define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
4095
+
#define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL
4096
+
#define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE
4097
+
u8 flags;
4098
+
#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4099
+
#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4100
+
#define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL
4101
+
#define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4102
+
#define SQ_RDMA_FLAGS_UC_FENCE 0x4UL
4103
+
#define SQ_RDMA_FLAGS_SE 0x8UL
4104
+
#define SQ_RDMA_FLAGS_INLINE 0x10UL
4105
+
#define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL
4106
+
#define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL
4107
+
u8 wqe_size;
4108
+
u8 reserved8;
4109
+
__le32 imm_data;
4110
+
__le32 length;
4111
+
__le32 reserved32_1;
4112
+
__le64 remote_va;
4113
+
__le32 remote_key;
4114
+
__le32 timestamp;
4115
+
#define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL
4116
+
#define SQ_RDMA_TIMESTAMP_SFT 0
4117
+
__le32 data[24];
4118
+
};
4119
+
4120
+
/* sq_rdma_hdr (size:256b/32B) */
4121
+
struct sq_rdma_hdr {
4122
+
u8 wqe_type;
4123
+
#define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL
4124
+
#define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
4125
+
#define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL
4126
+
#define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE
4127
+
u8 flags;
4128
+
#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4129
+
#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4130
+
#define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL
4131
+
#define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4132
+
#define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL
4133
+
#define SQ_RDMA_HDR_FLAGS_SE 0x8UL
4134
+
#define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL
4135
+
#define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL
4136
+
#define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL
4137
+
u8 wqe_size;
4138
+
u8 reserved8;
4139
+
__le32 imm_data;
4140
+
__le32 length;
4141
+
__le32 reserved32_1;
4142
+
__le64 remote_va;
4143
+
__le32 remote_key;
4144
+
__le32 timestamp;
4145
+
#define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL
4146
+
#define SQ_RDMA_HDR_TIMESTAMP_SFT 0
4147
+
};
4148
+
4149
+
/* sq_atomic (size:1024b/128B) */
4150
+
struct sq_atomic {
4151
+
u8 wqe_type;
4152
+
#define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL
4153
+
#define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL
4154
+
#define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA
4155
+
u8 flags;
4156
+
#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4157
+
#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4158
+
#define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL
4159
+
#define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4160
+
#define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL
4161
+
#define SQ_ATOMIC_FLAGS_SE 0x8UL
4162
+
#define SQ_ATOMIC_FLAGS_INLINE 0x10UL
4163
+
#define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL
4164
+
#define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL
4165
+
__le16 reserved16;
4166
+
__le32 remote_key;
4167
+
__le64 remote_va;
4168
+
__le64 swap_data;
4169
+
__le64 cmp_data;
4170
+
__le32 data[24];
4171
+
};
4172
+
4173
+
/* sq_atomic_hdr (size:256b/32B) */
4174
+
struct sq_atomic_hdr {
4175
+
u8 wqe_type;
4176
+
#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL
4177
+
#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL
4178
+
#define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA
4179
+
u8 flags;
4180
+
#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4181
+
#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4182
+
#define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL
4183
+
#define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4184
+
#define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL
4185
+
#define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL
4186
+
#define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL
4187
+
#define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL
4188
+
#define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL
4189
+
__le16 reserved16;
4190
+
__le32 remote_key;
4191
+
__le64 remote_va;
4192
+
__le64 swap_data;
4193
+
__le64 cmp_data;
4194
+
};
4195
+
4196
+
/* sq_localinvalidate (size:1024b/128B) */
4197
+
struct sq_localinvalidate {
4198
+
u8 wqe_type;
4199
+
#define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL
4200
+
#define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID
4201
+
u8 flags;
4202
+
#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4203
+
#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4204
+
#define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL
4205
+
#define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4206
+
#define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL
4207
+
#define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL
4208
+
#define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL
4209
+
#define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL
4210
+
#define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL
4211
+
__le16 reserved16;
4212
+
__le32 inv_l_key;
4213
+
__le64 reserved64;
4214
+
u8 reserved128[16];
4215
+
__le32 data[24];
4216
+
};
4217
+
4218
+
/* sq_localinvalidate_hdr (size:256b/32B) */
4219
+
struct sq_localinvalidate_hdr {
4220
+
u8 wqe_type;
4221
+
#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL
4222
+
#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID
4223
+
u8 flags;
4224
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4225
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4226
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL
4227
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4228
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL
4229
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL
4230
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL
4231
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL
4232
+
#define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL
4233
+
__le16 reserved16;
4234
+
__le32 inv_l_key;
4235
+
__le64 reserved64;
4236
+
u8 reserved128[16];
4237
+
};
4238
+
4239
+
/* sq_fr_pmr (size:1024b/128B) */
4240
+
struct sq_fr_pmr {
4241
+
u8 wqe_type;
4242
+
#define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL
4243
+
#define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR
4244
+
u8 flags;
4245
+
#define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL
4246
+
#define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4247
+
#define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL
4248
+
#define SQ_FR_PMR_FLAGS_SE 0x8UL
4249
+
#define SQ_FR_PMR_FLAGS_INLINE 0x10UL
4250
+
#define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL
4251
+
#define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL
4252
+
u8 access_cntl;
4253
+
#define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
4254
+
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL
4255
+
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
4256
+
#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
4257
+
#define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL
4258
+
u8 zero_based_page_size_log;
4259
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL
4260
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
4261
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
4262
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
4263
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
4264
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
4265
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
4266
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
4267
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
4268
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
4269
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
4270
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
4271
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
4272
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
4273
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
4274
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
4275
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
4276
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
4277
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
4278
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
4279
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
4280
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
4281
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
4282
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
4283
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
4284
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
4285
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
4286
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
4287
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
4288
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
4289
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
4290
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
4291
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
4292
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
4293
+
#define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T
4294
+
#define SQ_FR_PMR_ZERO_BASED 0x20UL
4295
+
__le32 l_key;
4296
+
u8 length[5];
4297
+
u8 reserved8_1;
4298
+
u8 reserved8_2;
4299
+
u8 numlevels_pbl_page_size_log;
4300
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
4301
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
4302
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
4303
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
4304
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
4305
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
4306
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
4307
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
4308
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
4309
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
4310
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
4311
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
4312
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
4313
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
4314
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
4315
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
4316
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
4317
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
4318
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
4319
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
4320
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
4321
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
4322
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
4323
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
4324
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
4325
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
4326
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
4327
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
4328
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
4329
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
4330
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
4331
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
4332
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
4333
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
4334
+
#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T
4335
+
#define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL
4336
+
#define SQ_FR_PMR_NUMLEVELS_SFT 6
4337
+
#define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6)
4338
+
#define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6)
4339
+
#define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6)
4340
+
#define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2
4341
+
__le64 pblptr;
4342
+
__le64 va;
4343
+
__le32 data[24];
4344
+
};
4345
+
4346
+
/* sq_fr_pmr_hdr (size:256b/32B) */
4347
+
struct sq_fr_pmr_hdr {
4348
+
u8 wqe_type;
4349
+
#define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL
4350
+
#define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR
4351
+
u8 flags;
4352
+
#define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL
4353
+
#define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4354
+
#define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL
4355
+
#define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL
4356
+
#define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL
4357
+
#define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL
4358
+
#define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL
4359
+
u8 access_cntl;
4360
+
#define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
4361
+
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
4362
+
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
4363
+
#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
4364
+
#define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
4365
+
u8 zero_based_page_size_log;
4366
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL
4367
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0
4368
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
4369
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
4370
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
4371
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
4372
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
4373
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
4374
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
4375
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
4376
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
4377
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
4378
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
4379
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
4380
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
4381
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
4382
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
4383
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
4384
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
4385
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
4386
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
4387
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
4388
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
4389
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
4390
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
4391
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
4392
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
4393
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
4394
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
4395
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
4396
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
4397
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
4398
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
4399
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
4400
+
#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T
4401
+
#define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL
4402
+
__le32 l_key;
4403
+
u8 length[5];
4404
+
u8 reserved8_1;
4405
+
u8 reserved8_2;
4406
+
u8 numlevels_pbl_page_size_log;
4407
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
4408
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
4409
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
4410
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
4411
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
4412
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
4413
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
4414
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
4415
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
4416
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
4417
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
4418
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
4419
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
4420
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
4421
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
4422
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
4423
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
4424
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
4425
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
4426
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
4427
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
4428
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
4429
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
4430
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
4431
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
4432
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
4433
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
4434
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
4435
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
4436
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
4437
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
4438
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
4439
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
4440
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
4441
+
#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T
4442
+
#define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL
4443
+
#define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6
4444
+
#define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6)
4445
+
#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6)
4446
+
#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6)
4447
+
#define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2
4448
+
__le64 pblptr;
4449
+
__le64 va;
4450
+
};
4451
+
4452
+
/* sq_bind (size:1024b/128B) */
4453
+
struct sq_bind {
4454
+
u8 wqe_type;
4455
+
#define SQ_BIND_WQE_TYPE_BIND 0xeUL
4456
+
#define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND
4457
+
u8 flags;
4458
+
#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4459
+
#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4460
+
#define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL
4461
+
#define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4462
+
#define SQ_BIND_FLAGS_UC_FENCE 0x4UL
4463
+
#define SQ_BIND_FLAGS_SE 0x8UL
4464
+
#define SQ_BIND_FLAGS_INLINE 0x10UL
4465
+
#define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL
4466
+
#define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL
4467
+
u8 access_cntl;
4468
+
#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK 0xffUL
4469
+
#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
4470
+
#define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL
4471
+
#define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL
4472
+
#define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL
4473
+
#define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
4474
+
#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL
4475
+
u8 reserved8_1;
4476
+
u8 mw_type_zero_based;
4477
+
#define SQ_BIND_ZERO_BASED 0x1UL
4478
+
#define SQ_BIND_MW_TYPE 0x2UL
4479
+
#define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1)
4480
+
#define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1)
4481
+
#define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2
4482
+
u8 reserved8_2;
4483
+
__le16 reserved16;
4484
+
__le32 parent_l_key;
4485
+
__le32 l_key;
4486
+
__le64 va;
4487
+
u8 length[5];
4488
+
u8 reserved24[3];
4489
+
__le32 data[24];
4490
+
};
4491
+
4492
+
/* sq_bind_hdr (size:256b/32B) */
4493
+
struct sq_bind_hdr {
4494
+
u8 wqe_type;
4495
+
#define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL
4496
+
#define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND
4497
+
u8 flags;
4498
+
#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
4499
+
#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
4500
+
#define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL
4501
+
#define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4502
+
#define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL
4503
+
#define SQ_BIND_HDR_FLAGS_SE 0x8UL
4504
+
#define SQ_BIND_HDR_FLAGS_INLINE 0x10UL
4505
+
#define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL
4506
+
#define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL
4507
+
u8 access_cntl;
4508
+
#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK 0xffUL
4509
+
#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
4510
+
#define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
4511
+
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
4512
+
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
4513
+
#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
4514
+
#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
4515
+
u8 reserved8_1;
4516
+
u8 mw_type_zero_based;
4517
+
#define SQ_BIND_HDR_ZERO_BASED 0x1UL
4518
+
#define SQ_BIND_HDR_MW_TYPE 0x2UL
4519
+
#define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1)
4520
+
#define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1)
4521
+
#define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2
4522
+
u8 reserved8_2;
4523
+
__le16 reserved16;
4524
+
__le32 parent_l_key;
4525
+
__le32 l_key;
4526
+
__le64 va;
4527
+
u8 length[5];
4528
+
u8 reserved24[3];
4529
+
};
4530
+
4531
+
/* sq_msn_search_v3 (size:128b/16B) */
4532
+
struct sq_msn_search_v3 {
4533
+
__le64 idx_psn;
4534
+
#define SQ_MSN_SEARCH_V3_START_PSN_MASK 0xffffffUL
4535
+
#define SQ_MSN_SEARCH_V3_START_PSN_SFT 0
4536
+
#define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK 0xffffff000000ULL
4537
+
#define SQ_MSN_SEARCH_V3_NEXT_PSN_SFT 24
4538
+
#define SQ_MSN_SEARCH_V3_START_IDX_MASK 0xffff000000000000ULL
4539
+
#define SQ_MSN_SEARCH_V3_START_IDX_SFT 48
4540
+
__le32 wqe_opaque;
4541
+
u8 wqe_size;
4542
+
u8 signal;
4543
+
#define SQ_MSN_SEARCH_V3_SGNLD 0x1UL
4544
+
#define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE 0x2UL
4545
+
__le16 reserved;
4546
+
};
4547
+
4548
+
/* sq_send_v3 (size:1024b/128B) */
4549
+
struct sq_send_v3 {
4550
+
u8 wqe_type;
4551
+
#define SQ_SEND_V3_WQE_TYPE_SEND_V3 0x10UL
4552
+
#define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 0x11UL
4553
+
#define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 0x12UL
4554
+
#define SQ_SEND_V3_WQE_TYPE_LAST SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3
4555
+
u8 flags;
4556
+
#define SQ_SEND_V3_FLAGS_SIGNAL_COMP 0x1UL
4557
+
#define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4558
+
#define SQ_SEND_V3_FLAGS_UC_FENCE 0x4UL
4559
+
#define SQ_SEND_V3_FLAGS_SE 0x8UL
4560
+
#define SQ_SEND_V3_FLAGS_INLINE 0x10UL
4561
+
#define SQ_SEND_V3_FLAGS_WQE_TS_EN 0x20UL
4562
+
#define SQ_SEND_V3_FLAGS_DEBUG_TRACE 0x40UL
4563
+
u8 wqe_size;
4564
+
#define SQ_SEND_V3_WQE_SIZE_MASK 0x3fUL
4565
+
#define SQ_SEND_V3_WQE_SIZE_SFT 0
4566
+
u8 inline_length;
4567
+
#define SQ_SEND_V3_INLINE_LENGTH_MASK 0xfUL
4568
+
#define SQ_SEND_V3_INLINE_LENGTH_SFT 0
4569
+
__le32 opaque;
4570
+
__le32 inv_key_or_imm_data;
4571
+
__le32 timestamp;
4572
+
#define SQ_SEND_V3_TIMESTAMP_MASK 0xffffffUL
4573
+
#define SQ_SEND_V3_TIMESTAMP_SFT 0
4574
+
__le32 data[28];
4575
+
};
4576
+
4577
+
/* sq_send_hdr_v3 (size:128b/16B) */
4578
+
struct sq_send_hdr_v3 {
4579
+
u8 wqe_type;
4580
+
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 0x10UL
4581
+
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 0x11UL
4582
+
#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 0x12UL
4583
+
#define SQ_SEND_HDR_V3_WQE_TYPE_LAST SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3
4584
+
u8 flags;
4585
+
#define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4586
+
#define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4587
+
#define SQ_SEND_HDR_V3_FLAGS_UC_FENCE 0x4UL
4588
+
#define SQ_SEND_HDR_V3_FLAGS_SE 0x8UL
4589
+
#define SQ_SEND_HDR_V3_FLAGS_INLINE 0x10UL
4590
+
#define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4591
+
#define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4592
+
u8 wqe_size;
4593
+
#define SQ_SEND_HDR_V3_WQE_SIZE_MASK 0x3fUL
4594
+
#define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0
4595
+
u8 inline_length;
4596
+
#define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL
4597
+
#define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0
4598
+
__le32 opaque;
4599
+
__le32 inv_key_or_imm_data;
4600
+
__le32 timestamp;
4601
+
#define SQ_SEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL
4602
+
#define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0
4603
+
};
4604
+
4605
+
/* sq_rawqp1send_v3 (size:1024b/128B) */
4606
+
struct sq_rawqp1send_v3 {
4607
+
u8 wqe_type;
4608
+
#define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 0x1dUL
4609
+
#define SQ_RAWQP1SEND_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3
4610
+
u8 flags;
4611
+
#define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP 0x1UL
4612
+
#define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4613
+
#define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE 0x4UL
4614
+
#define SQ_RAWQP1SEND_V3_FLAGS_SE 0x8UL
4615
+
#define SQ_RAWQP1SEND_V3_FLAGS_INLINE 0x10UL
4616
+
#define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN 0x20UL
4617
+
#define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE 0x40UL
4618
+
u8 wqe_size;
4619
+
#define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK 0x3fUL
4620
+
#define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0
4621
+
u8 inline_length;
4622
+
#define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK 0xfUL
4623
+
#define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0
4624
+
__le32 opaque;
4625
+
__le16 lflags;
4626
+
#define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM 0x1UL
4627
+
#define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM 0x2UL
4628
+
#define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC 0x4UL
4629
+
#define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM 0x10UL
4630
+
#define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM 0x20UL
4631
+
#define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC 0x100UL
4632
+
#define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC 0x200UL
4633
+
__le16 cfa_action;
4634
+
__le16 cfa_action_high;
4635
+
#define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK 0x3ffUL
4636
+
#define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0
4637
+
__le16 reserved_2;
4638
+
__le32 cfa_meta;
4639
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK 0xfffUL
4640
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT 0
4641
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE 0x1000UL
4642
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK 0xe000UL
4643
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_SFT 13
4644
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK 0x70000UL
4645
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_SFT 16
4646
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
4647
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
4648
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
4649
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
4650
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
4651
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
4652
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG
4653
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
4654
+
#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_SFT 19
4655
+
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK 0xf0000000UL
4656
+
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_SFT 28
4657
+
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (0x0UL << 28)
4658
+
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
4659
+
#define SQ_RAWQP1SEND_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG
4660
+
__le32 timestamp;
4661
+
#define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK 0xffffffUL
4662
+
#define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0
4663
+
__le64 reserved_3;
4664
+
__le32 data[24];
4665
+
};
4666
+
4667
+
/* sq_rawqp1send_hdr_v3 (size:256b/32B) */
4668
+
struct sq_rawqp1send_hdr_v3 {
4669
+
u8 wqe_type;
4670
+
#define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 0x1dUL
4671
+
#define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3
4672
+
u8 flags;
4673
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4674
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4675
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE 0x4UL
4676
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE 0x8UL
4677
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE 0x10UL
4678
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4679
+
#define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4680
+
u8 wqe_size;
4681
+
#define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK 0x3fUL
4682
+
#define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0
4683
+
u8 inline_length;
4684
+
#define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL
4685
+
#define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0
4686
+
__le32 opaque;
4687
+
__le16 lflags;
4688
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM 0x1UL
4689
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM 0x2UL
4690
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC 0x4UL
4691
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM 0x10UL
4692
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM 0x20UL
4693
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC 0x100UL
4694
+
#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC 0x200UL
4695
+
__le16 cfa_action;
4696
+
__le16 cfa_action_high;
4697
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK 0x3ffUL
4698
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0
4699
+
__le16 reserved_2;
4700
+
__le32 cfa_meta;
4701
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK 0xfffUL
4702
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT 0
4703
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE 0x1000UL
4704
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK 0xe000UL
4705
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_SFT 13
4706
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK 0x70000UL
4707
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_SFT 16
4708
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
4709
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
4710
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
4711
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
4712
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
4713
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
4714
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG
4715
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
4716
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_SFT 19
4717
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK 0xf0000000UL
4718
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_SFT 28
4719
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (0x0UL << 28)
4720
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
4721
+
#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG
4722
+
__le32 timestamp;
4723
+
#define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL
4724
+
#define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0
4725
+
__le64 reserved_3;
4726
+
};
4727
+
4728
+
/* sq_udsend_v3 (size:1024b/128B) */
4729
+
struct sq_udsend_v3 {
4730
+
u8 wqe_type;
4731
+
#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 0x13UL
4732
+
#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL
4733
+
#define SQ_UDSEND_V3_WQE_TYPE_LAST SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3
4734
+
u8 flags;
4735
+
#define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP 0x1UL
4736
+
#define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4737
+
#define SQ_UDSEND_V3_FLAGS_UC_FENCE 0x4UL
4738
+
#define SQ_UDSEND_V3_FLAGS_SE 0x8UL
4739
+
#define SQ_UDSEND_V3_FLAGS_INLINE 0x10UL
4740
+
#define SQ_UDSEND_V3_FLAGS_WQE_TS_EN 0x20UL
4741
+
#define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE 0x40UL
4742
+
u8 wqe_size;
4743
+
#define SQ_UDSEND_V3_WQE_SIZE_MASK 0x3fUL
4744
+
#define SQ_UDSEND_V3_WQE_SIZE_SFT 0
4745
+
u8 inline_length;
4746
+
#define SQ_UDSEND_V3_INLINE_LENGTH_MASK 0xfUL
4747
+
#define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0
4748
+
__le32 opaque;
4749
+
__le32 imm_data;
4750
+
__le32 q_key;
4751
+
__le32 dst_qp;
4752
+
#define SQ_UDSEND_V3_DST_QP_MASK 0xffffffUL
4753
+
#define SQ_UDSEND_V3_DST_QP_SFT 0
4754
+
__le32 avid;
4755
+
#define SQ_UDSEND_V3_AVID_MASK 0xfffffUL
4756
+
#define SQ_UDSEND_V3_AVID_SFT 0
4757
+
__le32 reserved2;
4758
+
__le32 timestamp;
4759
+
#define SQ_UDSEND_V3_TIMESTAMP_MASK 0xffffffUL
4760
+
#define SQ_UDSEND_V3_TIMESTAMP_SFT 0
4761
+
__le32 data[24];
4762
+
};
4763
+
4764
+
/* sq_udsend_hdr_v3 (size:256b/32B) */
4765
+
struct sq_udsend_hdr_v3 {
4766
+
u8 wqe_type;
4767
+
#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 0x13UL
4768
+
#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 0x14UL
4769
+
#define SQ_UDSEND_HDR_V3_WQE_TYPE_LAST SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3
4770
+
u8 flags;
4771
+
#define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4772
+
#define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4773
+
#define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE 0x4UL
4774
+
#define SQ_UDSEND_HDR_V3_FLAGS_SE 0x8UL
4775
+
#define SQ_UDSEND_HDR_V3_FLAGS_INLINE 0x10UL
4776
+
#define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4777
+
#define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4778
+
u8 wqe_size;
4779
+
#define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK 0x3fUL
4780
+
#define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0
4781
+
u8 inline_length;
4782
+
#define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK 0xfUL
4783
+
#define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0
4784
+
__le32 opaque;
4785
+
__le32 imm_data;
4786
+
__le32 q_key;
4787
+
__le32 dst_qp;
4788
+
#define SQ_UDSEND_HDR_V3_DST_QP_MASK 0xffffffUL
4789
+
#define SQ_UDSEND_HDR_V3_DST_QP_SFT 0
4790
+
__le32 avid;
4791
+
#define SQ_UDSEND_HDR_V3_AVID_MASK 0xfffffUL
4792
+
#define SQ_UDSEND_HDR_V3_AVID_SFT 0
4793
+
__le32 reserved2;
4794
+
__le32 timestamp;
4795
+
#define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK 0xffffffUL
4796
+
#define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0
4797
+
};
4798
+
4799
+
/* sq_rdma_v3 (size:1024b/128B) */
4800
+
struct sq_rdma_v3 {
4801
+
u8 wqe_type;
4802
+
#define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 0x15UL
4803
+
#define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL
4804
+
#define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 0x17UL
4805
+
#define SQ_RDMA_V3_WQE_TYPE_LAST SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3
4806
+
u8 flags;
4807
+
#define SQ_RDMA_V3_FLAGS_SIGNAL_COMP 0x1UL
4808
+
#define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4809
+
#define SQ_RDMA_V3_FLAGS_UC_FENCE 0x4UL
4810
+
#define SQ_RDMA_V3_FLAGS_SE 0x8UL
4811
+
#define SQ_RDMA_V3_FLAGS_INLINE 0x10UL
4812
+
#define SQ_RDMA_V3_FLAGS_WQE_TS_EN 0x20UL
4813
+
#define SQ_RDMA_V3_FLAGS_DEBUG_TRACE 0x40UL
4814
+
u8 wqe_size;
4815
+
#define SQ_RDMA_V3_WQE_SIZE_MASK 0x3fUL
4816
+
#define SQ_RDMA_V3_WQE_SIZE_SFT 0
4817
+
u8 inline_length;
4818
+
#define SQ_RDMA_V3_INLINE_LENGTH_MASK 0xfUL
4819
+
#define SQ_RDMA_V3_INLINE_LENGTH_SFT 0
4820
+
__le32 opaque;
4821
+
__le32 imm_data;
4822
+
__le32 reserved2;
4823
+
__le64 remote_va;
4824
+
__le32 remote_key;
4825
+
__le32 timestamp;
4826
+
#define SQ_RDMA_V3_TIMESTAMP_MASK 0xffffffUL
4827
+
#define SQ_RDMA_V3_TIMESTAMP_SFT 0
4828
+
__le32 data[24];
4829
+
};
4830
+
4831
+
/* sq_rdma_hdr_v3 (size:256b/32B) */
4832
+
struct sq_rdma_hdr_v3 {
4833
+
u8 wqe_type;
4834
+
#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 0x15UL
4835
+
#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 0x16UL
4836
+
#define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 0x17UL
4837
+
#define SQ_RDMA_HDR_V3_WQE_TYPE_LAST SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3
4838
+
u8 flags;
4839
+
#define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4840
+
#define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4841
+
#define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE 0x4UL
4842
+
#define SQ_RDMA_HDR_V3_FLAGS_SE 0x8UL
4843
+
#define SQ_RDMA_HDR_V3_FLAGS_INLINE 0x10UL
4844
+
#define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4845
+
#define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4846
+
u8 wqe_size;
4847
+
#define SQ_RDMA_HDR_V3_WQE_SIZE_MASK 0x3fUL
4848
+
#define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0
4849
+
u8 inline_length;
4850
+
#define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK 0xfUL
4851
+
#define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0
4852
+
__le32 opaque;
4853
+
__le32 imm_data;
4854
+
__le32 reserved2;
4855
+
__le64 remote_va;
4856
+
__le32 remote_key;
4857
+
__le32 timestamp;
4858
+
#define SQ_RDMA_HDR_V3_TIMESTAMP_MASK 0xffffffUL
4859
+
#define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0
4860
+
};
4861
+
4862
+
/* sq_atomic_v3 (size:448b/56B) */
4863
+
struct sq_atomic_v3 {
4864
+
u8 wqe_type;
4865
+
#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 0x18UL
4866
+
#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 0x19UL
4867
+
#define SQ_ATOMIC_V3_WQE_TYPE_LAST SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3
4868
+
u8 flags;
4869
+
#define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP 0x1UL
4870
+
#define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4871
+
#define SQ_ATOMIC_V3_FLAGS_UC_FENCE 0x4UL
4872
+
#define SQ_ATOMIC_V3_FLAGS_SE 0x8UL
4873
+
#define SQ_ATOMIC_V3_FLAGS_INLINE 0x10UL
4874
+
#define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN 0x20UL
4875
+
#define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE 0x40UL
4876
+
u8 wqe_size;
4877
+
#define SQ_ATOMIC_V3_WQE_SIZE_MASK 0x3fUL
4878
+
#define SQ_ATOMIC_V3_WQE_SIZE_SFT 0
4879
+
u8 reserved1;
4880
+
__le32 opaque;
4881
+
__le32 remote_key;
4882
+
__le32 reserved2;
4883
+
__le64 remote_va;
4884
+
__le64 swap_data;
4885
+
__le64 cmp_data;
4886
+
__le64 va_or_pa;
4887
+
__le32 l_key;
4888
+
__le32 size;
4889
+
};
4890
+
4891
+
/* sq_atomic_hdr_v3 (size:320b/40B) */
4892
+
struct sq_atomic_hdr_v3 {
4893
+
u8 wqe_type;
4894
+
#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 0x18UL
4895
+
#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 0x19UL
4896
+
#define SQ_ATOMIC_HDR_V3_WQE_TYPE_LAST SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3
4897
+
u8 flags;
4898
+
#define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4899
+
#define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4900
+
#define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE 0x4UL
4901
+
#define SQ_ATOMIC_HDR_V3_FLAGS_SE 0x8UL
4902
+
#define SQ_ATOMIC_HDR_V3_FLAGS_INLINE 0x10UL
4903
+
#define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4904
+
#define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4905
+
u8 wqe_size;
4906
+
#define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK 0x3fUL
4907
+
#define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0
4908
+
u8 reserved1;
4909
+
__le32 opaque;
4910
+
__le32 remote_key;
4911
+
__le32 reserved2;
4912
+
__le64 remote_va;
4913
+
__le64 swap_data;
4914
+
__le64 cmp_data;
4915
+
};
4916
+
4917
+
/* sq_localinvalidate_v3 (size:128b/16B) */
4918
+
struct sq_localinvalidate_v3 {
4919
+
u8 wqe_type;
4920
+
#define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL
4921
+
#define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3
4922
+
u8 flags;
4923
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP 0x1UL
4924
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4925
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE 0x4UL
4926
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_SE 0x8UL
4927
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE 0x10UL
4928
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN 0x20UL
4929
+
#define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE 0x40UL
4930
+
u8 wqe_size;
4931
+
#define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK 0x3fUL
4932
+
#define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0
4933
+
u8 reserved1;
4934
+
__le32 opaque;
4935
+
__le32 inv_l_key;
4936
+
__le32 reserved2;
4937
+
};
4938
+
4939
+
/* sq_localinvalidate_hdr_v3 (size:128b/16B) */
4940
+
struct sq_localinvalidate_hdr_v3 {
4941
+
u8 wqe_type;
4942
+
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 0x1aUL
4943
+
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3
4944
+
u8 flags;
4945
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
4946
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4947
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE 0x4UL
4948
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE 0x8UL
4949
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE 0x10UL
4950
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
4951
+
#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
4952
+
u8 wqe_size;
4953
+
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK 0x3fUL
4954
+
#define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0
4955
+
u8 reserved1;
4956
+
__le32 opaque;
4957
+
__le32 inv_l_key;
4958
+
__le32 reserved2;
4959
+
};
4960
+
4961
+
/* sq_fr_pmr_v3 (size:320b/40B) */
4962
+
struct sq_fr_pmr_v3 {
4963
+
u8 wqe_type;
4964
+
#define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 0x1bUL
4965
+
#define SQ_FR_PMR_V3_WQE_TYPE_LAST SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3
4966
+
u8 flags;
4967
+
#define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP 0x1UL
4968
+
#define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
4969
+
#define SQ_FR_PMR_V3_FLAGS_UC_FENCE 0x4UL
4970
+
#define SQ_FR_PMR_V3_FLAGS_SE 0x8UL
4971
+
#define SQ_FR_PMR_V3_FLAGS_INLINE 0x10UL
4972
+
#define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN 0x20UL
4973
+
#define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE 0x40UL
4974
+
u8 wqe_size_zero_based;
4975
+
#define SQ_FR_PMR_V3_WQE_SIZE_MASK 0x3fUL
4976
+
#define SQ_FR_PMR_V3_WQE_SIZE_SFT 0
4977
+
#define SQ_FR_PMR_V3_ZERO_BASED 0x40UL
4978
+
u8 access_cntl;
4979
+
#define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL
4980
+
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL
4981
+
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL
4982
+
#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
4983
+
#define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL
4984
+
__le32 opaque;
4985
+
__le32 l_key;
4986
+
__le16 page_size_log;
4987
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK 0x1fUL
4988
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT 0
4989
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
4990
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
4991
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
4992
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
4993
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
4994
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
4995
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
4996
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
4997
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
4998
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
4999
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
5000
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
5001
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
5002
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
5003
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
5004
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
5005
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
5006
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
5007
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
5008
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
5009
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
5010
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
5011
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
5012
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
5013
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
5014
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
5015
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
5016
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
5017
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
5018
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
5019
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
5020
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
5021
+
#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T
5022
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK 0x3e0UL
5023
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_SFT 5
5024
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (0x0UL << 5)
5025
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (0x1UL << 5)
5026
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (0x2UL << 5)
5027
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (0x3UL << 5)
5028
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (0x4UL << 5)
5029
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (0x5UL << 5)
5030
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (0x6UL << 5)
5031
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (0x7UL << 5)
5032
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (0x8UL << 5)
5033
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (0x9UL << 5)
5034
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (0xaUL << 5)
5035
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (0xbUL << 5)
5036
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (0xcUL << 5)
5037
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (0xdUL << 5)
5038
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (0xeUL << 5)
5039
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (0xfUL << 5)
5040
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (0x10UL << 5)
5041
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (0x11UL << 5)
5042
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (0x12UL << 5)
5043
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (0x13UL << 5)
5044
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (0x14UL << 5)
5045
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (0x15UL << 5)
5046
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (0x16UL << 5)
5047
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (0x17UL << 5)
5048
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (0x18UL << 5)
5049
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (0x19UL << 5)
5050
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (0x1aUL << 5)
5051
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (0x1bUL << 5)
5052
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (0x1cUL << 5)
5053
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (0x1dUL << 5)
5054
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (0x1eUL << 5)
5055
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (0x1fUL << 5)
5056
+
#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T
5057
+
#define SQ_FR_PMR_V3_NUMLEVELS_MASK 0xc00UL
5058
+
#define SQ_FR_PMR_V3_NUMLEVELS_SFT 10
5059
+
#define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (0x0UL << 10)
5060
+
#define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (0x1UL << 10)
5061
+
#define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (0x2UL << 10)
5062
+
#define SQ_FR_PMR_V3_NUMLEVELS_LAST SQ_FR_PMR_V3_NUMLEVELS_LAYER2
5063
+
__le16 reserved;
5064
+
__le64 va;
5065
+
__le64 length;
5066
+
__le64 pbl_ptr;
5067
+
};
5068
+
5069
+
/* sq_fr_pmr_hdr_v3 (size:320b/40B) */
5070
+
struct sq_fr_pmr_hdr_v3 {
5071
+
u8 wqe_type;
5072
+
#define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 0x1bUL
5073
+
#define SQ_FR_PMR_HDR_V3_WQE_TYPE_LAST SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3
5074
+
u8 flags;
5075
+
#define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
5076
+
#define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
5077
+
#define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE 0x4UL
5078
+
#define SQ_FR_PMR_HDR_V3_FLAGS_SE 0x8UL
5079
+
#define SQ_FR_PMR_HDR_V3_FLAGS_INLINE 0x10UL
5080
+
#define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
5081
+
#define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
5082
+
u8 wqe_size_zero_based;
5083
+
#define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK 0x3fUL
5084
+
#define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT 0
5085
+
#define SQ_FR_PMR_HDR_V3_ZERO_BASED 0x40UL
5086
+
u8 access_cntl;
5087
+
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL
5088
+
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL
5089
+
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL
5090
+
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
5091
+
#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL
5092
+
__le32 opaque;
5093
+
__le32 l_key;
5094
+
__le16 page_size_log;
5095
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK 0x1fUL
5096
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT 0
5097
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
5098
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
5099
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
5100
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
5101
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
5102
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
5103
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
5104
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
5105
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
5106
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
5107
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
5108
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
5109
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
5110
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
5111
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
5112
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
5113
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
5114
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
5115
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
5116
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
5117
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
5118
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
5119
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
5120
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
5121
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
5122
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
5123
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
5124
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
5125
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
5126
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
5127
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
5128
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
5129
+
#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T
5130
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK 0x3e0UL
5131
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_SFT 5
5132
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (0x0UL << 5)
5133
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (0x1UL << 5)
5134
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (0x2UL << 5)
5135
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (0x3UL << 5)
5136
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (0x4UL << 5)
5137
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (0x5UL << 5)
5138
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (0x6UL << 5)
5139
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (0x7UL << 5)
5140
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (0x8UL << 5)
5141
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (0x9UL << 5)
5142
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (0xaUL << 5)
5143
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (0xbUL << 5)
5144
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (0xcUL << 5)
5145
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (0xdUL << 5)
5146
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (0xeUL << 5)
5147
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (0xfUL << 5)
5148
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (0x10UL << 5)
5149
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (0x11UL << 5)
5150
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (0x12UL << 5)
5151
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (0x13UL << 5)
5152
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (0x14UL << 5)
5153
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (0x15UL << 5)
5154
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (0x16UL << 5)
5155
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (0x17UL << 5)
5156
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (0x18UL << 5)
5157
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (0x19UL << 5)
5158
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (0x1aUL << 5)
5159
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (0x1bUL << 5)
5160
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (0x1cUL << 5)
5161
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (0x1dUL << 5)
5162
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (0x1eUL << 5)
5163
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (0x1fUL << 5)
5164
+
#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T
5165
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK 0xc00UL
5166
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_SFT 10
5167
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (0x0UL << 10)
5168
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (0x1UL << 10)
5169
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (0x2UL << 10)
5170
+
#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAST SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2
5171
+
__le16 reserved;
5172
+
__le64 va;
5173
+
__le64 length;
5174
+
__le64 pbl_ptr;
5175
+
};
5176
+
5177
+
/* sq_bind_v3 (size:256b/32B) */
5178
+
struct sq_bind_v3 {
5179
+
u8 wqe_type;
5180
+
#define SQ_BIND_V3_WQE_TYPE_BIND_V3 0x1cUL
5181
+
#define SQ_BIND_V3_WQE_TYPE_LAST SQ_BIND_V3_WQE_TYPE_BIND_V3
5182
+
u8 flags;
5183
+
#define SQ_BIND_V3_FLAGS_SIGNAL_COMP 0x1UL
5184
+
#define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
5185
+
#define SQ_BIND_V3_FLAGS_UC_FENCE 0x4UL
5186
+
#define SQ_BIND_V3_FLAGS_SE 0x8UL
5187
+
#define SQ_BIND_V3_FLAGS_INLINE 0x10UL
5188
+
#define SQ_BIND_V3_FLAGS_WQE_TS_EN 0x20UL
5189
+
#define SQ_BIND_V3_FLAGS_DEBUG_TRACE 0x40UL
5190
+
u8 wqe_size_zero_based_mw_type;
5191
+
#define SQ_BIND_V3_WQE_SIZE_MASK 0x3fUL
5192
+
#define SQ_BIND_V3_WQE_SIZE_SFT 0
5193
+
#define SQ_BIND_V3_ZERO_BASED 0x40UL
5194
+
#define SQ_BIND_V3_MW_TYPE 0x80UL
5195
+
#define SQ_BIND_V3__TYPE1 (0x0UL << 7)
5196
+
#define SQ_BIND_V3__TYPE2 (0x1UL << 7)
5197
+
#define SQ_BIND_V3__LAST SQ_BIND_V3__TYPE2
5198
+
u8 access_cntl;
5199
+
#define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL
5200
+
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ 0x2UL
5201
+
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL
5202
+
#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
5203
+
#define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL
5204
+
__le32 opaque;
5205
+
__le32 parent_l_key;
5206
+
__le32 l_key;
5207
+
__le64 va;
5208
+
__le64 length;
5209
+
};
5210
+
5211
+
/* sq_bind_hdr_v3 (size:256b/32B) */
5212
+
struct sq_bind_hdr_v3 {
5213
+
u8 wqe_type;
5214
+
#define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 0x1cUL
5215
+
#define SQ_BIND_HDR_V3_WQE_TYPE_LAST SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3
5216
+
u8 flags;
5217
+
#define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
5218
+
#define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
5219
+
#define SQ_BIND_HDR_V3_FLAGS_UC_FENCE 0x4UL
5220
+
#define SQ_BIND_HDR_V3_FLAGS_SE 0x8UL
5221
+
#define SQ_BIND_HDR_V3_FLAGS_INLINE 0x10UL
5222
+
#define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
5223
+
#define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
5224
+
u8 wqe_size_zero_based_mw_type;
5225
+
#define SQ_BIND_HDR_V3_WQE_SIZE_MASK 0x3fUL
5226
+
#define SQ_BIND_HDR_V3_WQE_SIZE_SFT 0
5227
+
#define SQ_BIND_HDR_V3_ZERO_BASED 0x40UL
5228
+
#define SQ_BIND_HDR_V3_MW_TYPE 0x80UL
5229
+
#define SQ_BIND_HDR_V3__TYPE1 (0x0UL << 7)
5230
+
#define SQ_BIND_HDR_V3__TYPE2 (0x1UL << 7)
5231
+
#define SQ_BIND_HDR_V3__LAST SQ_BIND_HDR_V3__TYPE2
5232
+
u8 access_cntl;
5233
+
#define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE 0x1UL
5234
+
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ 0x2UL
5235
+
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE 0x4UL
5236
+
#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
5237
+
#define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND 0x10UL
5238
+
__le32 opaque;
5239
+
__le32 parent_l_key;
5240
+
__le32 l_key;
5241
+
__le64 va;
5242
+
__le64 length;
5243
+
};
5244
+
5245
+
/* sq_change_udpsrcport_v3 (size:128b/16B) */
5246
+
struct sq_change_udpsrcport_v3 {
5247
+
u8 wqe_type;
5248
+
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL
5249
+
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3
5250
+
u8 flags;
5251
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP 0x1UL
5252
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
5253
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE 0x4UL
5254
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE 0x8UL
5255
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE 0x10UL
5256
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN 0x20UL
5257
+
#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE 0x40UL
5258
+
u8 wqe_size;
5259
+
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK 0x3fUL
5260
+
#define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0
5261
+
u8 reserved_1;
5262
+
__le32 opaque;
5263
+
__le16 udp_src_port;
5264
+
__le16 reserved_2;
5265
+
__le32 reserved_3;
5266
+
};
5267
+
5268
+
/* sq_change_udpsrcport_hdr_v3 (size:128b/16B) */
5269
+
struct sq_change_udpsrcport_hdr_v3 {
5270
+
u8 wqe_type;
5271
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 0x1eUL
5272
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3
5273
+
u8 flags;
5274
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP 0x1UL
5275
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
5276
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE 0x4UL
5277
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE 0x8UL
5278
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE 0x10UL
5279
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN 0x20UL
5280
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE 0x40UL
5281
+
u8 wqe_size;
5282
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK 0x3fUL
5283
+
#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0
5284
+
u8 reserved_1;
5285
+
__le32 opaque;
5286
+
__le16 udp_src_port;
5287
+
__le16 reserved_2;
5288
+
__le32 reserved_3;
5289
+
};
5290
+
5291
+
/* rq_wqe (size:1024b/128B) */
5292
+
struct rq_wqe {
5293
+
u8 wqe_type;
5294
+
#define RQ_WQE_WQE_TYPE_RCV 0x80UL
5295
+
#define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV
5296
+
u8 flags;
5297
+
u8 wqe_size;
5298
+
u8 reserved8;
5299
+
__le32 reserved32;
5300
+
__le32 wr_id[2];
5301
+
#define RQ_WQE_WR_ID_MASK 0xfffffUL
5302
+
#define RQ_WQE_WR_ID_SFT 0
5303
+
u8 reserved128[16];
5304
+
__le32 data[24];
5305
+
};
5306
+
5307
+
/* rq_wqe_hdr (size:256b/32B) */
5308
+
struct rq_wqe_hdr {
5309
+
u8 wqe_type;
5310
+
#define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL
5311
+
#define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV
5312
+
u8 flags;
5313
+
u8 wqe_size;
5314
+
u8 reserved8;
5315
+
__le32 reserved32;
5316
+
__le32 wr_id[2];
5317
+
#define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL
5318
+
#define RQ_WQE_HDR_WR_ID_SFT 0
5319
+
u8 reserved128[16];
5320
+
};
5321
+
5322
+
/* rq_wqe_v3 (size:4096b/512B) */
5323
+
struct rq_wqe_v3 {
5324
+
u8 wqe_type;
5325
+
#define RQ_WQE_V3_WQE_TYPE_RCV_V3 0x90UL
5326
+
#define RQ_WQE_V3_WQE_TYPE_LAST RQ_WQE_V3_WQE_TYPE_RCV_V3
5327
+
u8 flags;
5328
+
u8 wqe_size;
5329
+
u8 reserved1;
5330
+
__le32 opaque;
5331
+
__le64 reserved2;
5332
+
__le32 data[124];
5333
+
};
5334
+
5335
+
/* rq_wqe_hdr_v3 (size:128b/16B) */
5336
+
struct rq_wqe_hdr_v3 {
5337
+
u8 wqe_type;
5338
+
#define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 0x90UL
5339
+
#define RQ_WQE_HDR_V3_WQE_TYPE_LAST RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3
5340
+
u8 flags;
5341
+
u8 wqe_size;
5342
+
u8 reserved1;
5343
+
__le32 opaque;
5344
+
__le64 reserved2;
5345
+
};
5346
+
5347
+
/* cq_base (size:256b/32B) */
5348
+
struct cq_base {
5349
+
__le64 reserved64_1;
5350
+
__le64 reserved64_2;
5351
+
__le64 reserved64_3;
5352
+
u8 cqe_type_toggle;
5353
+
#define CQ_BASE_TOGGLE 0x1UL
5354
+
#define CQ_BASE_CQE_TYPE_MASK 0x1eUL
5355
+
#define CQ_BASE_CQE_TYPE_SFT 1
5356
+
#define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1)
5357
+
#define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1)
5358
+
#define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1)
5359
+
#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
5360
+
#define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
5361
+
#define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1)
5362
+
#define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1)
5363
+
#define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1)
5364
+
#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1)
5365
+
#define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1)
5366
+
#define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1)
5367
+
#define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1)
5368
+
#define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1)
5369
+
#define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF
5370
+
u8 status;
5371
+
#define CQ_BASE_STATUS_OK 0x0UL
5372
+
#define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL
5373
+
#define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL
5374
+
#define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
5375
+
#define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5376
+
#define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL
5377
+
#define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL
5378
+
#define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL
5379
+
#define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
5380
+
#define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL
5381
+
#define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL
5382
+
#define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL
5383
+
#define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL
5384
+
#define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
5385
+
#define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL
5386
+
#define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL
5387
+
#define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR
5388
+
__le16 reserved16;
5389
+
__le32 opaque;
5390
+
};
5391
+
5392
+
/* cq_req (size:256b/32B) */
5393
+
struct cq_req {
5394
+
__le64 qp_handle;
5395
+
__le16 sq_cons_idx;
5396
+
__le16 reserved16_1;
5397
+
__le32 reserved32_2;
5398
+
__le64 reserved64;
5399
+
u8 cqe_type_toggle;
5400
+
#define CQ_REQ_TOGGLE 0x1UL
5401
+
#define CQ_REQ_CQE_TYPE_MASK 0x1eUL
5402
+
#define CQ_REQ_CQE_TYPE_SFT 1
5403
+
#define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1)
5404
+
#define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ
5405
+
#define CQ_REQ_PUSH 0x20UL
5406
+
u8 status;
5407
+
#define CQ_REQ_STATUS_OK 0x0UL
5408
+
#define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL
5409
+
#define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL
5410
+
#define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL
5411
+
#define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL
5412
+
#define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5413
+
#define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
5414
+
#define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL
5415
+
#define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL
5416
+
#define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL
5417
+
#define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL
5418
+
#define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL
5419
+
#define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR
5420
+
__le16 reserved16_2;
5421
+
__le32 reserved32_1;
5422
+
};
5423
+
5424
+
/* cq_res_rc (size:256b/32B) */
5425
+
struct cq_res_rc {
5426
+
__le32 length;
5427
+
__le32 imm_data_or_inv_r_key;
5428
+
__le64 qp_handle;
5429
+
__le64 mr_handle;
5430
+
u8 cqe_type_toggle;
5431
+
#define CQ_RES_RC_TOGGLE 0x1UL
5432
+
#define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL
5433
+
#define CQ_RES_RC_CQE_TYPE_SFT 1
5434
+
#define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1)
5435
+
#define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC
5436
+
u8 status;
5437
+
#define CQ_RES_RC_STATUS_OK 0x0UL
5438
+
#define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5439
+
#define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL
5440
+
#define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5441
+
#define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5442
+
#define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5443
+
#define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
5444
+
#define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5445
+
#define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL
5446
+
#define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR
5447
+
__le16 flags;
5448
+
#define CQ_RES_RC_FLAGS_SRQ 0x1UL
5449
+
#define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL
5450
+
#define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL
5451
+
#define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
5452
+
#define CQ_RES_RC_FLAGS_IMM 0x2UL
5453
+
#define CQ_RES_RC_FLAGS_INV 0x4UL
5454
+
#define CQ_RES_RC_FLAGS_RDMA 0x8UL
5455
+
#define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3)
5456
+
#define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3)
5457
+
#define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
5458
+
__le32 srq_or_rq_wr_id;
5459
+
#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5460
+
#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
5461
+
};
5462
+
5463
+
/* cq_res_ud (size:256b/32B) */
5464
+
struct cq_res_ud {
5465
+
__le16 length;
5466
+
#define CQ_RES_UD_LENGTH_MASK 0x3fffUL
5467
+
#define CQ_RES_UD_LENGTH_SFT 0
5468
+
__le16 cfa_metadata;
5469
+
#define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL
5470
+
#define CQ_RES_UD_CFA_METADATA_VID_SFT 0
5471
+
#define CQ_RES_UD_CFA_METADATA_DE 0x1000UL
5472
+
#define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL
5473
+
#define CQ_RES_UD_CFA_METADATA_PRI_SFT 13
5474
+
__le32 imm_data;
5475
+
__le64 qp_handle;
5476
+
__le16 src_mac[3];
5477
+
__le16 src_qp_low;
5478
+
u8 cqe_type_toggle;
5479
+
#define CQ_RES_UD_TOGGLE 0x1UL
5480
+
#define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
5481
+
#define CQ_RES_UD_CQE_TYPE_SFT 1
5482
+
#define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1)
5483
+
#define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD
5484
+
u8 status;
5485
+
#define CQ_RES_UD_STATUS_OK 0x0UL
5486
+
#define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5487
+
#define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5488
+
#define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5489
+
#define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5490
+
#define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5491
+
#define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5492
+
#define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL
5493
+
#define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR
5494
+
__le16 flags;
5495
+
#define CQ_RES_UD_FLAGS_SRQ 0x1UL
5496
+
#define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL
5497
+
#define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL
5498
+
#define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
5499
+
#define CQ_RES_UD_FLAGS_IMM 0x2UL
5500
+
#define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL
5501
+
#define CQ_RES_UD_FLAGS_UNUSED_SFT 2
5502
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL
5503
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4
5504
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
5505
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
5506
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
5507
+
#define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
5508
+
#define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL
5509
+
#define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6
5510
+
#define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6)
5511
+
#define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
5512
+
#define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
5513
+
#define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
5514
+
#define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
5515
+
#define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
5516
+
#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
5517
+
#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10
5518
+
__le32 src_qp_high_srq_or_rq_wr_id;
5519
+
#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5520
+
#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
5521
+
#define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL
5522
+
#define CQ_RES_UD_SRC_QP_HIGH_SFT 24
5523
+
};
5524
+
5525
+
/* cq_res_ud_v2 (size:256b/32B) */
5526
+
struct cq_res_ud_v2 {
5527
+
__le16 length;
5528
+
#define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL
5529
+
#define CQ_RES_UD_V2_LENGTH_SFT 0
5530
+
__le16 cfa_metadata0;
5531
+
#define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL
5532
+
#define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
5533
+
#define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL
5534
+
#define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL
5535
+
#define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13
5536
+
__le32 imm_data;
5537
+
__le64 qp_handle;
5538
+
__le16 src_mac[3];
5539
+
__le16 src_qp_low;
5540
+
u8 cqe_type_toggle;
5541
+
#define CQ_RES_UD_V2_TOGGLE 0x1UL
5542
+
#define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL
5543
+
#define CQ_RES_UD_V2_CQE_TYPE_SFT 1
5544
+
#define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1)
5545
+
#define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD
5546
+
u8 status;
5547
+
#define CQ_RES_UD_V2_STATUS_OK 0x0UL
5548
+
#define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5549
+
#define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5550
+
#define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5551
+
#define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5552
+
#define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5553
+
#define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5554
+
#define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL
5555
+
#define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR
5556
+
__le16 flags;
5557
+
#define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL
5558
+
#define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL
5559
+
#define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL
5560
+
#define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ
5561
+
#define CQ_RES_UD_V2_FLAGS_IMM 0x2UL
5562
+
#define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL
5563
+
#define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2
5564
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
5565
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4
5566
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
5567
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
5568
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
5569
+
#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6
5570
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
5571
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6
5572
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
5573
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
5574
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
5575
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
5576
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
5577
+
#define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET
5578
+
__le32 src_qp_high_srq_or_rq_wr_id;
5579
+
#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5580
+
#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0
5581
+
#define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL
5582
+
#define CQ_RES_UD_V2_CFA_METADATA1_SFT 20
5583
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
5584
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20
5585
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
5586
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
5587
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
5588
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
5589
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
5590
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
5591
+
#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
5592
+
#define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL
5593
+
#define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL
5594
+
#define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24
5595
+
};
5596
+
5597
+
/* cq_res_ud_cfa (size:256b/32B) */
5598
+
struct cq_res_ud_cfa {
5599
+
__le16 length;
5600
+
#define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL
5601
+
#define CQ_RES_UD_CFA_LENGTH_SFT 0
5602
+
__le16 cfa_code;
5603
+
__le32 imm_data;
5604
+
__le32 qid;
5605
+
#define CQ_RES_UD_CFA_QID_MASK 0xfffffUL
5606
+
#define CQ_RES_UD_CFA_QID_SFT 0
5607
+
__le32 cfa_metadata;
5608
+
#define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL
5609
+
#define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0
5610
+
#define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL
5611
+
#define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL
5612
+
#define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13
5613
+
#define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL
5614
+
#define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16
5615
+
__le16 src_mac[3];
5616
+
__le16 src_qp_low;
5617
+
u8 cqe_type_toggle;
5618
+
#define CQ_RES_UD_CFA_TOGGLE 0x1UL
5619
+
#define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL
5620
+
#define CQ_RES_UD_CFA_CQE_TYPE_SFT 1
5621
+
#define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
5622
+
#define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA
5623
+
u8 status;
5624
+
#define CQ_RES_UD_CFA_STATUS_OK 0x0UL
5625
+
#define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5626
+
#define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5627
+
#define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5628
+
#define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5629
+
#define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5630
+
#define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5631
+
#define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL
5632
+
#define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR
5633
+
__le16 flags;
5634
+
#define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL
5635
+
#define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL
5636
+
#define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL
5637
+
#define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ
5638
+
#define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL
5639
+
#define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL
5640
+
#define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2
5641
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL
5642
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4
5643
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
5644
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
5645
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
5646
+
#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6
5647
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL
5648
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6
5649
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6)
5650
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
5651
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
5652
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
5653
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
5654
+
#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET
5655
+
#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
5656
+
#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10
5657
+
__le32 src_qp_high_srq_or_rq_wr_id;
5658
+
#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5659
+
#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
5660
+
#define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL
5661
+
#define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24
5662
+
};
5663
+
5664
+
/* cq_res_ud_cfa_v2 (size:256b/32B) */
5665
+
struct cq_res_ud_cfa_v2 {
5666
+
__le16 length;
5667
+
#define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL
5668
+
#define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
5669
+
__le16 cfa_metadata0;
5670
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL
5671
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
5672
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL
5673
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL
5674
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13
5675
+
__le32 imm_data;
5676
+
__le32 qid;
5677
+
#define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL
5678
+
#define CQ_RES_UD_CFA_V2_QID_SFT 0
5679
+
__le32 cfa_metadata2;
5680
+
__le16 src_mac[3];
5681
+
__le16 src_qp_low;
5682
+
u8 cqe_type_toggle;
5683
+
#define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL
5684
+
#define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL
5685
+
#define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1
5686
+
#define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
5687
+
#define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA
5688
+
u8 status;
5689
+
#define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL
5690
+
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5691
+
#define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5692
+
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5693
+
#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5694
+
#define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5695
+
#define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5696
+
#define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL
5697
+
#define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR
5698
+
__le16 flags;
5699
+
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL
5700
+
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL
5701
+
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL
5702
+
#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ
5703
+
#define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL
5704
+
#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL
5705
+
#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2
5706
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
5707
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4
5708
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
5709
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
5710
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
5711
+
#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6
5712
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
5713
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6
5714
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
5715
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
5716
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
5717
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
5718
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
5719
+
#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET
5720
+
__le32 src_qp_high_srq_or_rq_wr_id;
5721
+
#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5722
+
#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0
5723
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL
5724
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20
5725
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
5726
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20
5727
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
5728
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
5729
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
5730
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
5731
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
5732
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
5733
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
5734
+
#define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL
5735
+
#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL
5736
+
#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24
5737
+
};
5738
+
5739
+
/* cq_res_raweth_qp1 (size:256b/32B) */
5740
+
struct cq_res_raweth_qp1 {
5741
+
__le16 length;
5742
+
#define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL
5743
+
#define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
5744
+
__le16 raweth_qp1_flags;
5745
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL
5746
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
5747
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL
5748
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
5749
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
5750
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
5751
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
5752
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
5753
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
5754
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
5755
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
5756
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
5757
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
5758
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
5759
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
5760
+
__le16 raweth_qp1_errors;
5761
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
5762
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
5763
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
5764
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
5765
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
5766
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
5767
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
5768
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
5769
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
5770
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
5771
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
5772
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
5773
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
5774
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
5775
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
5776
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
5777
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
5778
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
5779
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
5780
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
5781
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
5782
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
5783
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
5784
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
5785
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
5786
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
5787
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
5788
+
__le16 raweth_qp1_cfa_code;
5789
+
__le64 qp_handle;
5790
+
__le32 raweth_qp1_flags2;
5791
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL
5792
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL
5793
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL
5794
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL
5795
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
5796
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
5797
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
5798
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4)
5799
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
5800
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
5801
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
5802
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
5803
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
5804
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
5805
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL
5806
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10
5807
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
5808
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5809
+
__le32 raweth_qp1_metadata;
5810
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL
5811
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0
5812
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL
5813
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
5814
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL
5815
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL
5816
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
5817
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL
5818
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
5819
+
u8 cqe_type_toggle;
5820
+
#define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL
5821
+
#define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL
5822
+
#define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
5823
+
#define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
5824
+
#define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1
5825
+
u8 status;
5826
+
#define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL
5827
+
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5828
+
#define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5829
+
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5830
+
#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5831
+
#define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5832
+
#define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5833
+
#define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL
5834
+
#define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR
5835
+
__le16 flags;
5836
+
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL
5837
+
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL
5838
+
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL
5839
+
#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
5840
+
__le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
5841
+
#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5842
+
#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
5843
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
5844
+
#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
5845
+
};
5846
+
5847
+
/* cq_res_raweth_qp1_v2 (size:256b/32B) */
5848
+
struct cq_res_raweth_qp1_v2 {
5849
+
__le16 length;
5850
+
#define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL
5851
+
#define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
5852
+
__le16 raweth_qp1_flags;
5853
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL
5854
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0
5855
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL
5856
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
5857
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6
5858
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
5859
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
5860
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
5861
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
5862
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
5863
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
5864
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
5865
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
5866
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
5867
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
5868
+
__le16 raweth_qp1_errors;
5869
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
5870
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
5871
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
5872
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
5873
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
5874
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
5875
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
5876
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
5877
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
5878
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
5879
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
5880
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
5881
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
5882
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
5883
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
5884
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
5885
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
5886
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
5887
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
5888
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
5889
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
5890
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
5891
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
5892
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
5893
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
5894
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
5895
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
5896
+
__le16 cfa_metadata0;
5897
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL
5898
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
5899
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL
5900
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL
5901
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13
5902
+
__le64 qp_handle;
5903
+
__le32 raweth_qp1_flags2;
5904
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL
5905
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
5906
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
5907
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
5908
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
5909
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
5910
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
5911
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
5912
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
5913
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
5914
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
5915
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL
5916
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10
5917
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
5918
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5919
+
__le32 cfa_metadata2;
5920
+
u8 cqe_type_toggle;
5921
+
#define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL
5922
+
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL
5923
+
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1
5924
+
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
5925
+
#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1
5926
+
u8 status;
5927
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL
5928
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
5929
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
5930
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
5931
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
5932
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
5933
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
5934
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL
5935
+
#define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR
5936
+
__le16 flags;
5937
+
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL
5938
+
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL
5939
+
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL
5940
+
#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ
5941
+
__le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
5942
+
#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
5943
+
#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0
5944
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL
5945
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20
5946
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
5947
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20
5948
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
5949
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
5950
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
5951
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
5952
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
5953
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
5954
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
5955
+
#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL
5956
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
5957
+
#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
5958
+
};
5959
+
5960
+
/* cq_terminal (size:256b/32B) */
5961
+
struct cq_terminal {
5962
+
__le64 qp_handle;
5963
+
__le16 sq_cons_idx;
5964
+
__le16 rq_cons_idx;
5965
+
__le32 reserved32_1;
5966
+
__le64 reserved64_3;
5967
+
u8 cqe_type_toggle;
5968
+
#define CQ_TERMINAL_TOGGLE 0x1UL
5969
+
#define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL
5970
+
#define CQ_TERMINAL_CQE_TYPE_SFT 1
5971
+
#define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1)
5972
+
#define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL
5973
+
u8 status;
5974
+
#define CQ_TERMINAL_STATUS_OK 0x0UL
5975
+
#define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK
5976
+
__le16 reserved16;
5977
+
__le32 reserved32_2;
5978
+
};
5979
+
5980
+
/* cq_cutoff (size:256b/32B) */
5981
+
struct cq_cutoff {
5982
+
__le64 reserved64_1;
5983
+
__le64 reserved64_2;
5984
+
__le64 reserved64_3;
5985
+
u8 cqe_type_toggle;
5986
+
#define CQ_CUTOFF_TOGGLE 0x1UL
5987
+
#define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL
5988
+
#define CQ_CUTOFF_CQE_TYPE_SFT 1
5989
+
#define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1)
5990
+
#define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF
5991
+
#define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL
5992
+
#define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5
5993
+
u8 status;
5994
+
#define CQ_CUTOFF_STATUS_OK 0x0UL
5995
+
#define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK
5996
+
__le16 reserved16;
5997
+
__le32 reserved32;
5998
+
};
5999
+
6000
+
/* cq_req_v3 (size:256b/32B) */
6001
+
struct cq_req_v3 {
6002
+
__le64 qp_handle;
6003
+
__le16 sq_cons_idx;
6004
+
__le16 reserved1;
6005
+
__le32 reserved2;
6006
+
__le64 reserved3;
6007
+
u8 cqe_type_toggle;
6008
+
#define CQ_REQ_V3_TOGGLE 0x1UL
6009
+
#define CQ_REQ_V3_CQE_TYPE_MASK 0x1eUL
6010
+
#define CQ_REQ_V3_CQE_TYPE_SFT 1
6011
+
#define CQ_REQ_V3_CQE_TYPE_REQ_V3 (0x8UL << 1)
6012
+
#define CQ_REQ_V3_CQE_TYPE_LAST CQ_REQ_V3_CQE_TYPE_REQ_V3
6013
+
#define CQ_REQ_V3_PUSH 0x20UL
6014
+
u8 status;
6015
+
#define CQ_REQ_V3_STATUS_OK 0x0UL
6016
+
#define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR 0x1UL
6017
+
#define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR 0x2UL
6018
+
#define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
6019
+
#define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL
6020
+
#define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL
6021
+
#define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
6022
+
#define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR 0x9UL
6023
+
#define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR 0xaUL
6024
+
#define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL
6025
+
#define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL
6026
+
#define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
6027
+
#define CQ_REQ_V3_STATUS_OVERFLOW_ERR 0xfUL
6028
+
#define CQ_REQ_V3_STATUS_LAST CQ_REQ_V3_STATUS_OVERFLOW_ERR
6029
+
__le16 reserved4;
6030
+
__le32 opaque;
6031
+
};
6032
+
6033
+
/* cq_res_rc_v3 (size:256b/32B) */
6034
+
struct cq_res_rc_v3 {
6035
+
__le32 length;
6036
+
__le32 imm_data_or_inv_r_key;
6037
+
__le64 qp_handle;
6038
+
__le64 mr_handle;
6039
+
u8 cqe_type_toggle;
6040
+
#define CQ_RES_RC_V3_TOGGLE 0x1UL
6041
+
#define CQ_RES_RC_V3_CQE_TYPE_MASK 0x1eUL
6042
+
#define CQ_RES_RC_V3_CQE_TYPE_SFT 1
6043
+
#define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (0x9UL << 1)
6044
+
#define CQ_RES_RC_V3_CQE_TYPE_LAST CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3
6045
+
u8 status;
6046
+
#define CQ_RES_RC_V3_STATUS_OK 0x0UL
6047
+
#define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR 0x2UL
6048
+
#define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
6049
+
#define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL
6050
+
#define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR 0x6UL
6051
+
#define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
6052
+
#define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
6053
+
#define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR 0xeUL
6054
+
#define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR 0xfUL
6055
+
#define CQ_RES_RC_V3_STATUS_LAST CQ_RES_RC_V3_STATUS_OVERFLOW_ERR
6056
+
__le16 flags;
6057
+
#define CQ_RES_RC_V3_FLAGS_SRQ 0x1UL
6058
+
#define CQ_RES_RC_V3_FLAGS_SRQ_RQ 0x0UL
6059
+
#define CQ_RES_RC_V3_FLAGS_SRQ_SRQ 0x1UL
6060
+
#define CQ_RES_RC_V3_FLAGS_SRQ_LAST CQ_RES_RC_V3_FLAGS_SRQ_SRQ
6061
+
#define CQ_RES_RC_V3_FLAGS_IMM 0x2UL
6062
+
#define CQ_RES_RC_V3_FLAGS_INV 0x4UL
6063
+
#define CQ_RES_RC_V3_FLAGS_RDMA 0x8UL
6064
+
#define CQ_RES_RC_V3_FLAGS_RDMA_SEND (0x0UL << 3)
6065
+
#define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3)
6066
+
#define CQ_RES_RC_V3_FLAGS_RDMA_LAST CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE
6067
+
__le32 opaque;
6068
+
};
6069
+
6070
+
/* cq_res_ud_v3 (size:256b/32B) */
6071
+
struct cq_res_ud_v3 {
6072
+
__le16 length;
6073
+
#define CQ_RES_UD_V3_LENGTH_MASK 0x3fffUL
6074
+
#define CQ_RES_UD_V3_LENGTH_SFT 0
6075
+
u8 reserved1;
6076
+
u8 src_qp_high;
6077
+
__le32 imm_data;
6078
+
__le64 qp_handle;
6079
+
__le16 src_mac[3];
6080
+
__le16 src_qp_low;
6081
+
u8 cqe_type_toggle;
6082
+
#define CQ_RES_UD_V3_TOGGLE 0x1UL
6083
+
#define CQ_RES_UD_V3_CQE_TYPE_MASK 0x1eUL
6084
+
#define CQ_RES_UD_V3_CQE_TYPE_SFT 1
6085
+
#define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (0xaUL << 1)
6086
+
#define CQ_RES_UD_V3_CQE_TYPE_LAST CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3
6087
+
u8 status;
6088
+
#define CQ_RES_UD_V3_STATUS_OK 0x0UL
6089
+
#define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
6090
+
#define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
6091
+
#define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL
6092
+
#define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
6093
+
#define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR 0xeUL
6094
+
#define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR 0xfUL
6095
+
#define CQ_RES_UD_V3_STATUS_LAST CQ_RES_UD_V3_STATUS_OVERFLOW_ERR
6096
+
__le16 flags;
6097
+
#define CQ_RES_UD_V3_FLAGS_SRQ 0x1UL
6098
+
#define CQ_RES_UD_V3_FLAGS_SRQ_RQ 0x0UL
6099
+
#define CQ_RES_UD_V3_FLAGS_SRQ_SRQ 0x1UL
6100
+
#define CQ_RES_UD_V3_FLAGS_SRQ_LAST CQ_RES_UD_V3_FLAGS_SRQ_SRQ
6101
+
#define CQ_RES_UD_V3_FLAGS_IMM 0x2UL
6102
+
#define CQ_RES_UD_V3_FLAGS_UNUSED_MASK 0xcUL
6103
+
#define CQ_RES_UD_V3_FLAGS_UNUSED_SFT 2
6104
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK 0x30UL
6105
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_SFT 4
6106
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
6107
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
6108
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
6109
+
#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6
6110
+
__le32 opaque;
6111
+
};
6112
+
6113
+
/* cq_res_raweth_qp1_v3 (size:256b/32B) */
6114
+
struct cq_res_raweth_qp1_v3 {
6115
+
__le16 length;
6116
+
#define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK 0x3fffUL
6117
+
#define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0
6118
+
__le16 raweth_qp1_flags_cfa_metadata1;
6119
+
#define CQ_RES_RAWETH_QP1_V3_ERROR 0x1UL
6120
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK 0x3c0UL
6121
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_SFT 6
6122
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (0x0UL << 6)
6123
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (0x1UL << 6)
6124
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (0x2UL << 6)
6125
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (0x3UL << 6)
6126
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (0x4UL << 6)
6127
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (0x5UL << 6)
6128
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (0x7UL << 6)
6129
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
6130
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
6131
+
#define CQ_RES_RAWETH_QP1_V3_ITYPE_LAST CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP
6132
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK 0xf000UL
6133
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_SFT 12
6134
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK 0x7000UL
6135
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_SFT 12
6136
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID 0x8000UL
6137
+
__le16 raweth_qp1_errors;
6138
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
6139
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
6140
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
6141
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
6142
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
6143
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
6144
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
6145
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
6146
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
6147
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
6148
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x3UL << 9)
6149
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x4UL << 9)
6150
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x5UL << 9)
6151
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (0x6UL << 9)
6152
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR
6153
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
6154
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
6155
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
6156
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
6157
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
6158
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
6159
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
6160
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
6161
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
6162
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
6163
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
6164
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_SUPAR_CRC (0x9UL << 12)
6165
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_SUPAR_CRC
6166
+
__le16 cfa_metadata0;
6167
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK 0xfffUL
6168
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0
6169
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE 0x1000UL
6170
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK 0xe000UL
6171
+
#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_SFT 13
6172
+
__le64 qp_handle;
6173
+
__le32 raweth_qp1_flags2;
6174
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL
6175
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL
6176
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL
6177
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL
6178
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
6179
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
6180
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
6181
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
6182
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
6183
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
6184
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
6185
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_VNIC_ID (0x5UL << 4)
6186
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_VNIC_ID
6187
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
6188
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
6189
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE 0x400UL
6190
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (0x0UL << 10)
6191
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (0x1UL << 10)
6192
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6
6193
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
6194
+
#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6195
+
__le32 cfa_metadata2;
6196
+
u8 cqe_type_toggle;
6197
+
#define CQ_RES_RAWETH_QP1_V3_TOGGLE 0x1UL
6198
+
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK 0x1eUL
6199
+
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_SFT 1
6200
+
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1)
6201
+
#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3
6202
+
u8 status;
6203
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_OK 0x0UL
6204
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
6205
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
6206
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL
6207
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
6208
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR 0xeUL
6209
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR 0xfUL
6210
+
#define CQ_RES_RAWETH_QP1_V3_STATUS_LAST CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR
6211
+
u8 flags;
6212
+
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ 0x1UL
6213
+
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ 0x0UL
6214
+
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ 0x1UL
6215
+
#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ
6216
+
u8 raweth_qp1_payload_offset;
6217
+
__le32 opaque;
6218
+
};
6219
+
6220
+
/* cq_res_ud_cfa_v3 (size:256b/32B) */
6221
+
struct cq_res_ud_cfa_v3 {
6222
+
__le16 length;
6223
+
#define CQ_RES_UD_CFA_V3_LENGTH_MASK 0x3fffUL
6224
+
#define CQ_RES_UD_CFA_V3_LENGTH_SFT 0
6225
+
__le16 cfa_metadata0;
6226
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK 0xfffUL
6227
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0
6228
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE 0x1000UL
6229
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK 0xe000UL
6230
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_SFT 13
6231
+
__le32 imm_data;
6232
+
__le32 qid_cfa_metadata1_src_qp_high;
6233
+
#define CQ_RES_UD_CFA_V3_QID_MASK 0x7ffUL
6234
+
#define CQ_RES_UD_CFA_V3_QID_SFT 0
6235
+
#define CQ_RES_UD_CFA_V3_UNUSED_MASK 0xff800UL
6236
+
#define CQ_RES_UD_CFA_V3_UNUSED_SFT 11
6237
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK 0xf00000UL
6238
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_SFT 20
6239
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
6240
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_SFT 20
6241
+
#define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID 0x800000UL
6242
+
#define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK 0xff000000UL
6243
+
#define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_SFT 24
6244
+
__le32 cfa_metadata2;
6245
+
__le16 src_mac[3];
6246
+
__le16 src_qp_low;
6247
+
u8 cqe_type_toggle;
6248
+
#define CQ_RES_UD_CFA_V3_TOGGLE 0x1UL
6249
+
#define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK 0x1eUL
6250
+
#define CQ_RES_UD_CFA_V3_CQE_TYPE_SFT 1
6251
+
#define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1)
6252
+
#define CQ_RES_UD_CFA_V3_CQE_TYPE_LAST CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3
6253
+
u8 status;
6254
+
#define CQ_RES_UD_CFA_V3_STATUS_OK 0x0UL
6255
+
#define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
6256
+
#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
6257
+
#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR 0x5UL
6258
+
#define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
6259
+
#define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR 0xeUL
6260
+
#define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR 0xfUL
6261
+
#define CQ_RES_UD_CFA_V3_STATUS_LAST CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR
6262
+
__le16 flags;
6263
+
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ 0x1UL
6264
+
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ 0x0UL
6265
+
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ 0x1UL
6266
+
#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ
6267
+
#define CQ_RES_UD_CFA_V3_FLAGS_IMM 0x2UL
6268
+
#define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK 0xcUL
6269
+
#define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_SFT 2
6270
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK 0x30UL
6271
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_SFT 4
6272
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
6273
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
6274
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
6275
+
#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6
6276
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK 0x3c0UL
6277
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_SFT 6
6278
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (0x0UL << 6)
6279
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
6280
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
6281
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
6282
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
6283
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_VNIC_ID (0x5UL << 6)
6284
+
#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_VNIC_ID
6285
+
__le32 opaque;
6286
+
};
6287
+
6288
+
/* nq_base (size:128b/16B) */
6289
+
struct nq_base {
6290
+
__le16 info10_type;
6291
+
#define NQ_BASE_TYPE_MASK 0x3fUL
6292
+
#define NQ_BASE_TYPE_SFT 0
6293
+
#define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL
6294
+
#define NQ_BASE_TYPE_SRQ_EVENT 0x32UL
6295
+
#define NQ_BASE_TYPE_DBQ_EVENT 0x34UL
6296
+
#define NQ_BASE_TYPE_QP_EVENT 0x38UL
6297
+
#define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL
6298
+
#define NQ_BASE_TYPE_NQ_REASSIGN 0x3cUL
6299
+
#define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_NQ_REASSIGN
6300
+
#define NQ_BASE_INFO10_MASK 0xffc0UL
6301
+
#define NQ_BASE_INFO10_SFT 6
6302
+
__le16 info16;
6303
+
__le32 info32;
6304
+
__le32 info63_v[2];
6305
+
#define NQ_BASE_V 0x1UL
6306
+
#define NQ_BASE_INFO63_MASK 0xfffffffeUL
6307
+
#define NQ_BASE_INFO63_SFT 1
6308
+
};
6309
+
6310
+
/* nq_cn (size:128b/16B) */
6311
+
struct nq_cn {
6312
+
__le16 type;
6313
+
#define NQ_CN_TYPE_MASK 0x3fUL
6314
+
#define NQ_CN_TYPE_SFT 0
6315
+
#define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
6316
+
#define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
6317
+
#define NQ_CN_TOGGLE_MASK 0xc0UL
6318
+
#define NQ_CN_TOGGLE_SFT 6
6319
+
__le16 reserved16;
6320
+
__le32 cq_handle_low;
6321
+
__le32 v;
6322
+
#define NQ_CN_V 0x1UL
6323
+
__le32 cq_handle_high;
6324
+
};
6325
+
6326
+
/* nq_srq_event (size:128b/16B) */
6327
+
struct nq_srq_event {
6328
+
u8 type;
6329
+
#define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL
6330
+
#define NQ_SRQ_EVENT_TYPE_SFT 0
6331
+
#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL
6332
+
#define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT
6333
+
#define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL
6334
+
#define NQ_SRQ_EVENT_TOGGLE_SFT 6
6335
+
u8 event;
6336
+
#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL
6337
+
#define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT
6338
+
__le16 reserved16;
6339
+
__le32 srq_handle_low;
6340
+
__le32 v;
6341
+
#define NQ_SRQ_EVENT_V 0x1UL
6342
+
__le32 srq_handle_high;
6343
+
};
6344
+
6345
+
/* nq_dbq_event (size:128b/16B) */
6346
+
struct nq_dbq_event {
6347
+
u8 type;
6348
+
#define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL
6349
+
#define NQ_DBQ_EVENT_TYPE_SFT 0
6350
+
#define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL
6351
+
#define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT
6352
+
u8 event;
6353
+
#define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL
6354
+
#define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT
6355
+
__le16 db_pfid;
6356
+
#define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL
6357
+
#define NQ_DBQ_EVENT_DB_PFID_SFT 0
6358
+
__le32 db_dpi;
6359
+
#define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL
6360
+
#define NQ_DBQ_EVENT_DB_DPI_SFT 0
6361
+
__le32 v;
6362
+
#define NQ_DBQ_EVENT_V 0x1UL
6363
+
__le32 db_type_db_xid;
6364
+
#define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL
6365
+
#define NQ_DBQ_EVENT_DB_XID_SFT 0
6366
+
#define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL
6367
+
#define NQ_DBQ_EVENT_DB_TYPE_SFT 28
6368
+
};
6369
+
6370
+
/* nq_reassign (size:128b/16B) */
6371
+
struct nq_reassign {
6372
+
__le16 type;
6373
+
#define NQ_REASSIGN_TYPE_MASK 0x3fUL
6374
+
#define NQ_REASSIGN_TYPE_SFT 0
6375
+
#define NQ_REASSIGN_TYPE_NQ_REASSIGN 0x3cUL
6376
+
#define NQ_REASSIGN_TYPE_LAST NQ_REASSIGN_TYPE_NQ_REASSIGN
6377
+
__le16 reserved16;
6378
+
__le32 cq_handle_low;
6379
+
__le32 v;
6380
+
#define NQ_REASSIGN_V 0x1UL
6381
+
__le32 cq_handle_high;
6382
+
};
6383
+
6384
+
/* xrrq_irrq (size:256b/32B) */
6385
+
struct xrrq_irrq {
6386
+
__le16 credits_type;
6387
+
#define XRRQ_IRRQ_TYPE 0x1UL
6388
+
#define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL
6389
+
#define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL
6390
+
#define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ
6391
+
#define XRRQ_IRRQ_CREDITS_MASK 0xf800UL
6392
+
#define XRRQ_IRRQ_CREDITS_SFT 11
6393
+
__le16 reserved16;
6394
+
__le32 reserved32;
6395
+
__le32 psn;
6396
+
#define XRRQ_IRRQ_PSN_MASK 0xffffffUL
6397
+
#define XRRQ_IRRQ_PSN_SFT 0
6398
+
__le32 msn;
6399
+
#define XRRQ_IRRQ_MSN_MASK 0xffffffUL
6400
+
#define XRRQ_IRRQ_MSN_SFT 0
6401
+
__le64 va_or_atomic_result;
6402
+
__le32 rdma_r_key;
6403
+
__le32 length;
6404
+
};
6405
+
6406
+
/* xrrq_orrq (size:256b/32B) */
6407
+
struct xrrq_orrq {
6408
+
__le16 num_sges_type;
6409
+
#define XRRQ_ORRQ_TYPE 0x1UL
6410
+
#define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL
6411
+
#define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL
6412
+
#define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ
6413
+
#define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL
6414
+
#define XRRQ_ORRQ_NUM_SGES_SFT 11
6415
+
__le16 reserved16;
6416
+
__le32 length;
6417
+
__le32 psn;
6418
+
#define XRRQ_ORRQ_PSN_MASK 0xffffffUL
6419
+
#define XRRQ_ORRQ_PSN_SFT 0
6420
+
__le32 end_psn;
6421
+
#define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL
6422
+
#define XRRQ_ORRQ_END_PSN_SFT 0
6423
+
__le64 first_sge_phy_or_sing_sge_va;
6424
+
__le32 single_sge_l_key;
6425
+
__le32 single_sge_size;
6426
+
};
6427
+
6428
+
/* ptu_pte (size:64b/8B) */
6429
+
struct ptu_pte {
6430
+
__le32 page_next_to_last_last_valid[2];
6431
+
#define PTU_PTE_VALID 0x1UL
6432
+
#define PTU_PTE_LAST 0x2UL
6433
+
#define PTU_PTE_NEXT_TO_LAST 0x4UL
6434
+
#define PTU_PTE_UNUSED_MASK 0xff8UL
6435
+
#define PTU_PTE_UNUSED_SFT 3
6436
+
#define PTU_PTE_PAGE_MASK 0xfffffffffffff000ULL
6437
+
#define PTU_PTE_PAGE_SFT 12
6438
+
};
6439
+
6440
+
/* ptu_pde (size:64b/8B) */
6441
+
struct ptu_pde {
6442
+
__le32 page_valid[2];
6443
+
#define PTU_PDE_VALID 0x1UL
6444
+
#define PTU_PDE_UNUSED_MASK 0xffeUL
6445
+
#define PTU_PDE_UNUSED_SFT 1
6446
+
#define PTU_PDE_PAGE_MASK 0xfffffffffffff000ULL
6447
+
#define PTU_PDE_PAGE_SFT 12
6448
+
};
6449
+
6450
+
#endif /* _BNG_RE_HSI_H_ */
+1
-1
drivers/infiniband/hw/bng_re/bng_tlv.h
+1
-1
drivers/infiniband/hw/bng_re/bng_tlv.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_auxr.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_auxr.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_hwrm.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_hwrm_lib.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_rmem.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_rmem.c
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
+1
-1
drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
+12609
include/linux/bnge/hsi.h
+12609
include/linux/bnge/hsi.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* Copyright (c) 2026 Broadcom */
3
+
4
+
/* DO NOT MODIFY!!! This file is automatically generated. */
5
+
6
+
#ifndef _BNGE_HSI_H_
7
+
#define _BNGE_HSI_H_
8
+
9
+
/* hwrm_cmd_hdr (size:128b/16B) */
10
+
struct hwrm_cmd_hdr {
11
+
__le16 req_type;
12
+
__le16 cmpl_ring;
13
+
__le16 seq_id;
14
+
__le16 target_id;
15
+
__le64 resp_addr;
16
+
};
17
+
18
+
/* hwrm_resp_hdr (size:64b/8B) */
19
+
struct hwrm_resp_hdr {
20
+
__le16 error_code;
21
+
__le16 req_type;
22
+
__le16 seq_id;
23
+
__le16 resp_len;
24
+
};
25
+
26
+
#define CMD_DISCR_TLV_ENCAP 0x8000UL
27
+
#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
28
+
29
+
#define TLV_TYPE_HWRM_REQUEST 0x1UL
30
+
#define TLV_TYPE_HWRM_RESPONSE 0x2UL
31
+
#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
32
+
#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
33
+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
34
+
#define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL
35
+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL
36
+
#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL
37
+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL
38
+
#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL
39
+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL
40
+
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
41
+
#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
42
+
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
43
+
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
44
+
#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
45
+
#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
46
+
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
47
+
#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
48
+
#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
49
+
#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
50
+
51
+
/* tlv (size:64b/8B) */
52
+
struct tlv {
53
+
__le16 cmd_discr;
54
+
u8 reserved_8b;
55
+
u8 flags;
56
+
#define TLV_FLAGS_MORE 0x1UL
57
+
#define TLV_FLAGS_MORE_LAST 0x0UL
58
+
#define TLV_FLAGS_MORE_NOT_LAST 0x1UL
59
+
#define TLV_FLAGS_REQUIRED 0x2UL
60
+
#define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
61
+
#define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
62
+
#define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
63
+
__le16 tlv_type;
64
+
__le16 length;
65
+
};
66
+
67
+
/* input (size:128b/16B) */
68
+
struct input {
69
+
__le16 req_type;
70
+
__le16 cmpl_ring;
71
+
__le16 seq_id;
72
+
__le16 target_id;
73
+
__le64 resp_addr;
74
+
};
75
+
76
+
/* output (size:64b/8B) */
77
+
struct output {
78
+
__le16 error_code;
79
+
__le16 req_type;
80
+
__le16 seq_id;
81
+
__le16 resp_len;
82
+
};
83
+
84
+
/* hwrm_short_input (size:128b/16B) */
85
+
struct hwrm_short_input {
86
+
__le16 req_type;
87
+
__le16 signature;
88
+
#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89
+
#define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
90
+
__le16 target_id;
91
+
#define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
92
+
#define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
93
+
#define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
94
+
__le16 size;
95
+
__le64 req_addr;
96
+
};
97
+
98
+
/* cmd_nums (size:64b/8B) */
99
+
struct cmd_nums {
100
+
__le16 req_type;
101
+
#define HWRM_VER_GET 0x0UL
102
+
#define HWRM_FUNC_ECHO_RESPONSE 0xbUL
103
+
#define HWRM_ERROR_RECOVERY_QCFG 0xcUL
104
+
#define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
105
+
#define HWRM_FUNC_BUF_UNRGTR 0xeUL
106
+
#define HWRM_FUNC_VF_CFG 0xfUL
107
+
#define HWRM_RESERVED1 0x10UL
108
+
#define HWRM_FUNC_RESET 0x11UL
109
+
#define HWRM_FUNC_GETFID 0x12UL
110
+
#define HWRM_FUNC_VF_ALLOC 0x13UL
111
+
#define HWRM_FUNC_VF_FREE 0x14UL
112
+
#define HWRM_FUNC_QCAPS 0x15UL
113
+
#define HWRM_FUNC_QCFG 0x16UL
114
+
#define HWRM_FUNC_CFG 0x17UL
115
+
#define HWRM_FUNC_QSTATS 0x18UL
116
+
#define HWRM_FUNC_CLR_STATS 0x19UL
117
+
#define HWRM_FUNC_DRV_UNRGTR 0x1aUL
118
+
#define HWRM_FUNC_VF_RESC_FREE 0x1bUL
119
+
#define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
120
+
#define HWRM_FUNC_DRV_RGTR 0x1dUL
121
+
#define HWRM_FUNC_DRV_QVER 0x1eUL
122
+
#define HWRM_FUNC_BUF_RGTR 0x1fUL
123
+
#define HWRM_PORT_PHY_CFG 0x20UL
124
+
#define HWRM_PORT_MAC_CFG 0x21UL
125
+
#define HWRM_PORT_TS_QUERY 0x22UL
126
+
#define HWRM_PORT_QSTATS 0x23UL
127
+
#define HWRM_PORT_LPBK_QSTATS 0x24UL
128
+
#define HWRM_PORT_CLR_STATS 0x25UL
129
+
#define HWRM_PORT_LPBK_CLR_STATS 0x26UL
130
+
#define HWRM_PORT_PHY_QCFG 0x27UL
131
+
#define HWRM_PORT_MAC_QCFG 0x28UL
132
+
#define HWRM_PORT_MAC_PTP_QCFG 0x29UL
133
+
#define HWRM_PORT_PHY_QCAPS 0x2aUL
134
+
#define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
135
+
#define HWRM_PORT_PHY_I2C_READ 0x2cUL
136
+
#define HWRM_PORT_LED_CFG 0x2dUL
137
+
#define HWRM_PORT_LED_QCFG 0x2eUL
138
+
#define HWRM_PORT_LED_QCAPS 0x2fUL
139
+
#define HWRM_QUEUE_QPORTCFG 0x30UL
140
+
#define HWRM_QUEUE_QCFG 0x31UL
141
+
#define HWRM_QUEUE_CFG 0x32UL
142
+
#define HWRM_FUNC_VLAN_CFG 0x33UL
143
+
#define HWRM_FUNC_VLAN_QCFG 0x34UL
144
+
#define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
145
+
#define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
146
+
#define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
147
+
#define HWRM_QUEUE_PRI2COS_CFG 0x38UL
148
+
#define HWRM_QUEUE_COS2BW_QCFG 0x39UL
149
+
#define HWRM_QUEUE_COS2BW_CFG 0x3aUL
150
+
#define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
151
+
#define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
152
+
#define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
153
+
#define HWRM_VNIC_ALLOC 0x40UL
154
+
#define HWRM_VNIC_FREE 0x41UL
155
+
#define HWRM_VNIC_CFG 0x42UL
156
+
#define HWRM_VNIC_QCFG 0x43UL
157
+
#define HWRM_VNIC_TPA_CFG 0x44UL
158
+
#define HWRM_VNIC_TPA_QCFG 0x45UL
159
+
#define HWRM_VNIC_RSS_CFG 0x46UL
160
+
#define HWRM_VNIC_RSS_QCFG 0x47UL
161
+
#define HWRM_VNIC_PLCMODES_CFG 0x48UL
162
+
#define HWRM_VNIC_PLCMODES_QCFG 0x49UL
163
+
#define HWRM_VNIC_QCAPS 0x4aUL
164
+
#define HWRM_VNIC_UPDATE 0x4bUL
165
+
#define HWRM_RING_ALLOC 0x50UL
166
+
#define HWRM_RING_FREE 0x51UL
167
+
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
168
+
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
169
+
#define HWRM_RING_AGGINT_QCAPS 0x54UL
170
+
#define HWRM_RING_SCHQ_ALLOC 0x55UL
171
+
#define HWRM_RING_SCHQ_CFG 0x56UL
172
+
#define HWRM_RING_SCHQ_FREE 0x57UL
173
+
#define HWRM_RING_RESET 0x5eUL
174
+
#define HWRM_RING_GRP_ALLOC 0x60UL
175
+
#define HWRM_RING_GRP_FREE 0x61UL
176
+
#define HWRM_RING_CFG 0x62UL
177
+
#define HWRM_RING_QCFG 0x63UL
178
+
#define HWRM_RESERVED5 0x64UL
179
+
#define HWRM_RESERVED6 0x65UL
180
+
#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
181
+
#define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
182
+
#define HWRM_PSP_CFG 0x72UL
183
+
#define HWRM_QUEUE_MPLS_QCAPS 0x80UL
184
+
#define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
185
+
#define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
186
+
#define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL
187
+
#define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL
188
+
#define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL
189
+
#define HWRM_QUEUE_GLOBAL_CFG 0x86UL
190
+
#define HWRM_QUEUE_GLOBAL_QCFG 0x87UL
191
+
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL
192
+
#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL
193
+
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL
194
+
#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL
195
+
#define HWRM_QUEUE_QCAPS 0x8cUL
196
+
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL
197
+
#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL
198
+
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL
199
+
#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
200
+
#define HWRM_CFA_L2_FILTER_FREE 0x91UL
201
+
#define HWRM_CFA_L2_FILTER_CFG 0x92UL
202
+
#define HWRM_CFA_L2_SET_RX_MASK 0x93UL
203
+
#define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
204
+
#define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
205
+
#define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
206
+
#define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
207
+
#define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
208
+
#define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
209
+
#define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
210
+
#define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
211
+
#define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
212
+
#define HWRM_CFA_EM_FLOW_FREE 0x9dUL
213
+
#define HWRM_CFA_EM_FLOW_CFG 0x9eUL
214
+
#define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
215
+
#define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
216
+
#define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
217
+
#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL
218
+
#define HWRM_STAT_CTX_ENG_QUERY 0xafUL
219
+
#define HWRM_STAT_CTX_ALLOC 0xb0UL
220
+
#define HWRM_STAT_CTX_FREE 0xb1UL
221
+
#define HWRM_STAT_CTX_QUERY 0xb2UL
222
+
#define HWRM_STAT_CTX_CLR_STATS 0xb3UL
223
+
#define HWRM_PORT_QSTATS_EXT 0xb4UL
224
+
#define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
225
+
#define HWRM_PORT_PHY_MDIO_READ 0xb6UL
226
+
#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
227
+
#define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
228
+
#define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL
229
+
#define HWRM_PORT_QSTATS_EXT_PFC_ADV 0xbaUL
230
+
#define HWRM_PORT_TX_FIR_CFG 0xbbUL
231
+
#define HWRM_PORT_TX_FIR_QCFG 0xbcUL
232
+
#define HWRM_PORT_ECN_QSTATS 0xbdUL
233
+
#define HWRM_FW_LIVEPATCH_QUERY 0xbeUL
234
+
#define HWRM_FW_LIVEPATCH 0xbfUL
235
+
#define HWRM_FW_RESET 0xc0UL
236
+
#define HWRM_FW_QSTATUS 0xc1UL
237
+
#define HWRM_FW_HEALTH_CHECK 0xc2UL
238
+
#define HWRM_FW_SYNC 0xc3UL
239
+
#define HWRM_FW_STATE_QCAPS 0xc4UL
240
+
#define HWRM_FW_STATE_QUIESCE 0xc5UL
241
+
#define HWRM_FW_STATE_BACKUP 0xc6UL
242
+
#define HWRM_FW_STATE_RESTORE 0xc7UL
243
+
#define HWRM_FW_SET_TIME 0xc8UL
244
+
#define HWRM_FW_GET_TIME 0xc9UL
245
+
#define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
246
+
#define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
247
+
#define HWRM_FW_IPC_MAILBOX 0xccUL
248
+
#define HWRM_FW_ECN_CFG 0xcdUL
249
+
#define HWRM_FW_ECN_QCFG 0xceUL
250
+
#define HWRM_FW_SECURE_CFG 0xcfUL
251
+
#define HWRM_EXEC_FWD_RESP 0xd0UL
252
+
#define HWRM_REJECT_FWD_RESP 0xd1UL
253
+
#define HWRM_FWD_RESP 0xd2UL
254
+
#define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
255
+
#define HWRM_OEM_CMD 0xd4UL
256
+
#define HWRM_PORT_PRBS_TEST 0xd5UL
257
+
#define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
258
+
#define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
259
+
#define HWRM_FW_STATE_UNQUIESCE 0xd8UL
260
+
#define HWRM_PORT_DSC_DUMP 0xd9UL
261
+
#define HWRM_PORT_EP_TX_QCFG 0xdaUL
262
+
#define HWRM_PORT_EP_TX_CFG 0xdbUL
263
+
#define HWRM_PORT_CFG 0xdcUL
264
+
#define HWRM_PORT_QCFG 0xddUL
265
+
#define HWRM_PORT_MAC_QCAPS 0xdfUL
266
+
#define HWRM_TEMP_MONITOR_QUERY 0xe0UL
267
+
#define HWRM_REG_POWER_QUERY 0xe1UL
268
+
#define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
269
+
#define HWRM_REG_POWER_HISTOGRAM 0xe3UL
270
+
#define HWRM_MONITOR_PAX_HISTOGRAM_START 0xe4UL
271
+
#define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL
272
+
#define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL
273
+
#define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL
274
+
#define HWRM_WOL_FILTER_ALLOC 0xf0UL
275
+
#define HWRM_WOL_FILTER_FREE 0xf1UL
276
+
#define HWRM_WOL_FILTER_QCFG 0xf2UL
277
+
#define HWRM_WOL_REASON_QCFG 0xf3UL
278
+
#define HWRM_CFA_METER_QCAPS 0xf4UL
279
+
#define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
280
+
#define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
281
+
#define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
282
+
#define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
283
+
#define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
284
+
#define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
285
+
#define HWRM_CFA_VFR_ALLOC 0xfdUL
286
+
#define HWRM_CFA_VFR_FREE 0xfeUL
287
+
#define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
288
+
#define HWRM_CFA_VF_PAIR_FREE 0x101UL
289
+
#define HWRM_CFA_VF_PAIR_INFO 0x102UL
290
+
#define HWRM_CFA_FLOW_ALLOC 0x103UL
291
+
#define HWRM_CFA_FLOW_FREE 0x104UL
292
+
#define HWRM_CFA_FLOW_FLUSH 0x105UL
293
+
#define HWRM_CFA_FLOW_STATS 0x106UL
294
+
#define HWRM_CFA_FLOW_INFO 0x107UL
295
+
#define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
296
+
#define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
297
+
#define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
298
+
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
299
+
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
300
+
#define HWRM_CFA_PAIR_ALLOC 0x10dUL
301
+
#define HWRM_CFA_PAIR_FREE 0x10eUL
302
+
#define HWRM_CFA_PAIR_INFO 0x10fUL
303
+
#define HWRM_FW_IPC_MSG 0x110UL
304
+
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
305
+
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
306
+
#define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
307
+
#define HWRM_CFA_FLOW_AGING_CFG 0x114UL
308
+
#define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
309
+
#define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
310
+
#define HWRM_CFA_CTX_MEM_RGTR 0x117UL
311
+
#define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
312
+
#define HWRM_CFA_CTX_MEM_QCTX 0x119UL
313
+
#define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
314
+
#define HWRM_CFA_COUNTER_QCAPS 0x11bUL
315
+
#define HWRM_CFA_COUNTER_CFG 0x11cUL
316
+
#define HWRM_CFA_COUNTER_QCFG 0x11dUL
317
+
#define HWRM_CFA_COUNTER_QSTATS 0x11eUL
318
+
#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
319
+
#define HWRM_CFA_EEM_QCAPS 0x120UL
320
+
#define HWRM_CFA_EEM_CFG 0x121UL
321
+
#define HWRM_CFA_EEM_QCFG 0x122UL
322
+
#define HWRM_CFA_EEM_OP 0x123UL
323
+
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
324
+
#define HWRM_CFA_TFLIB 0x125UL
325
+
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL
326
+
#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL
327
+
#define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL
328
+
#define HWRM_CFA_TLS_FILTER_FREE 0x129UL
329
+
#define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL
330
+
#define HWRM_ENGINE_CKV_STATUS 0x12eUL
331
+
#define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
332
+
#define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
333
+
#define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
334
+
#define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
335
+
#define HWRM_ENGINE_CKV_FLUSH 0x133UL
336
+
#define HWRM_ENGINE_CKV_RNG_GET 0x134UL
337
+
#define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
338
+
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
339
+
#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
340
+
#define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
341
+
#define HWRM_ENGINE_QG_QUERY 0x13dUL
342
+
#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
343
+
#define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
344
+
#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
345
+
#define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
346
+
#define HWRM_ENGINE_QG_METER_QUERY 0x142UL
347
+
#define HWRM_ENGINE_QG_METER_BIND 0x143UL
348
+
#define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
349
+
#define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
350
+
#define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
351
+
#define HWRM_ENGINE_SG_QUERY 0x147UL
352
+
#define HWRM_ENGINE_SG_METER_QUERY 0x148UL
353
+
#define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
354
+
#define HWRM_ENGINE_SG_QG_BIND 0x14aUL
355
+
#define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
356
+
#define HWRM_ENGINE_CONFIG_QUERY 0x154UL
357
+
#define HWRM_ENGINE_STATS_CONFIG 0x155UL
358
+
#define HWRM_ENGINE_STATS_CLEAR 0x156UL
359
+
#define HWRM_ENGINE_STATS_QUERY 0x157UL
360
+
#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
361
+
#define HWRM_ENGINE_RQ_ALLOC 0x15eUL
362
+
#define HWRM_ENGINE_RQ_FREE 0x15fUL
363
+
#define HWRM_ENGINE_CQ_ALLOC 0x160UL
364
+
#define HWRM_ENGINE_CQ_FREE 0x161UL
365
+
#define HWRM_ENGINE_NQ_ALLOC 0x162UL
366
+
#define HWRM_ENGINE_NQ_FREE 0x163UL
367
+
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
368
+
#define HWRM_ENGINE_FUNC_QCFG 0x165UL
369
+
#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
370
+
#define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
371
+
#define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
372
+
#define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
373
+
#define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
374
+
#define HWRM_FUNC_VF_BW_CFG 0x195UL
375
+
#define HWRM_FUNC_VF_BW_QCFG 0x196UL
376
+
#define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
377
+
#define HWRM_FUNC_QSTATS_EXT 0x198UL
378
+
#define HWRM_STAT_EXT_CTX_QUERY 0x199UL
379
+
#define HWRM_FUNC_SPD_CFG 0x19aUL
380
+
#define HWRM_FUNC_SPD_QCFG 0x19bUL
381
+
#define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL
382
+
#define HWRM_FUNC_PTP_PIN_CFG 0x19dUL
383
+
#define HWRM_FUNC_PTP_CFG 0x19eUL
384
+
#define HWRM_FUNC_PTP_TS_QUERY 0x19fUL
385
+
#define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL
386
+
#define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL
387
+
#define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL
388
+
#define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL
389
+
#define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL
390
+
#define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL
391
+
#define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL
392
+
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL
393
+
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL
394
+
#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL
395
+
#define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL
396
+
#define HWRM_FUNC_SYNCE_CFG 0x1abUL
397
+
#define HWRM_FUNC_SYNCE_QCFG 0x1acUL
398
+
#define HWRM_FUNC_KEY_CTX_FREE 0x1adUL
399
+
#define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL
400
+
#define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL
401
+
#define HWRM_FUNC_LAG_CREATE 0x1b0UL
402
+
#define HWRM_FUNC_LAG_UPDATE 0x1b1UL
403
+
#define HWRM_FUNC_LAG_FREE 0x1b2UL
404
+
#define HWRM_FUNC_LAG_QCFG 0x1b3UL
405
+
#define HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY 0x1c3UL
406
+
#define HWRM_FUNC_TTX_PACING_RATE_QUERY 0x1c4UL
407
+
#define HWRM_FUNC_PTP_QCFG 0x1c5UL
408
+
#define HWRM_SELFTEST_QLIST 0x200UL
409
+
#define HWRM_SELFTEST_EXEC 0x201UL
410
+
#define HWRM_SELFTEST_IRQ 0x202UL
411
+
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
412
+
#define HWRM_PCIE_QSTATS 0x204UL
413
+
#define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
414
+
#define HWRM_MFG_TIMERS_QUERY 0x206UL
415
+
#define HWRM_MFG_OTP_CFG 0x207UL
416
+
#define HWRM_MFG_OTP_QCFG 0x208UL
417
+
#define HWRM_MFG_HDMA_TEST 0x209UL
418
+
#define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL
419
+
#define HWRM_MFG_FRU_EEPROM_READ 0x20bUL
420
+
#define HWRM_MFG_SOC_IMAGE 0x20cUL
421
+
#define HWRM_MFG_SOC_QSTATUS 0x20dUL
422
+
#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL
423
+
#define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL
424
+
#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL
425
+
#define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL
426
+
#define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL
427
+
#define HWRM_MFG_PRVSN_GET_STATE 0x213UL
428
+
#define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL
429
+
#define HWRM_MFG_PSOC_QSTATUS 0x215UL
430
+
#define HWRM_MFG_SELFTEST_QLIST 0x216UL
431
+
#define HWRM_MFG_SELFTEST_EXEC 0x217UL
432
+
#define HWRM_STAT_GENERIC_QSTATS 0x218UL
433
+
#define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL
434
+
#define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL
435
+
#define HWRM_MFG_TESTS 0x21bUL
436
+
#define HWRM_MFG_WRITE_CERT_NVM 0x21cUL
437
+
#define HWRM_PORT_POE_CFG 0x230UL
438
+
#define HWRM_PORT_POE_QCFG 0x231UL
439
+
#define HWRM_PORT_PHY_FDRSTAT 0x232UL
440
+
#define HWRM_PORT_PHY_DBG 0x23aUL
441
+
#define HWRM_UDCC_QCAPS 0x258UL
442
+
#define HWRM_UDCC_CFG 0x259UL
443
+
#define HWRM_UDCC_QCFG 0x25aUL
444
+
#define HWRM_UDCC_SESSION_CFG 0x25bUL
445
+
#define HWRM_UDCC_SESSION_QCFG 0x25cUL
446
+
#define HWRM_UDCC_SESSION_QUERY 0x25dUL
447
+
#define HWRM_UDCC_COMP_CFG 0x25eUL
448
+
#define HWRM_UDCC_COMP_QCFG 0x25fUL
449
+
#define HWRM_UDCC_COMP_QUERY 0x260UL
450
+
#define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL
451
+
#define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL
452
+
#define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL
453
+
#define HWRM_QUEUE_ADPTV_QOS_RX_QCFG 0x264UL
454
+
#define HWRM_QUEUE_ADPTV_QOS_TX_QCFG 0x265UL
455
+
#define HWRM_TF 0x2bcUL
456
+
#define HWRM_TF_VERSION_GET 0x2bdUL
457
+
#define HWRM_TF_SESSION_OPEN 0x2c6UL
458
+
#define HWRM_TF_SESSION_REGISTER 0x2c8UL
459
+
#define HWRM_TF_SESSION_UNREGISTER 0x2c9UL
460
+
#define HWRM_TF_SESSION_CLOSE 0x2caUL
461
+
#define HWRM_TF_SESSION_QCFG 0x2cbUL
462
+
#define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL
463
+
#define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
464
+
#define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
465
+
#define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
466
+
#define HWRM_TF_SESSION_RESC_INFO 0x2d0UL
467
+
#define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL
468
+
#define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL
469
+
#define HWRM_TF_TBL_TYPE_GET 0x2daUL
470
+
#define HWRM_TF_TBL_TYPE_SET 0x2dbUL
471
+
#define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
472
+
#define HWRM_TF_EM_INSERT 0x2eaUL
473
+
#define HWRM_TF_EM_DELETE 0x2ebUL
474
+
#define HWRM_TF_EM_HASH_INSERT 0x2ecUL
475
+
#define HWRM_TF_EM_MOVE 0x2edUL
476
+
#define HWRM_TF_TCAM_SET 0x2f8UL
477
+
#define HWRM_TF_TCAM_GET 0x2f9UL
478
+
#define HWRM_TF_TCAM_MOVE 0x2faUL
479
+
#define HWRM_TF_TCAM_FREE 0x2fbUL
480
+
#define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL
481
+
#define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL
482
+
#define HWRM_TF_IF_TBL_SET 0x2feUL
483
+
#define HWRM_TF_IF_TBL_GET 0x2ffUL
484
+
#define HWRM_TF_RESC_USAGE_SET 0x300UL
485
+
#define HWRM_TF_RESC_USAGE_QUERY 0x301UL
486
+
#define HWRM_TF_TBL_TYPE_ALLOC 0x302UL
487
+
#define HWRM_TF_TBL_TYPE_FREE 0x303UL
488
+
#define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL
489
+
#define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL
490
+
#define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL
491
+
#define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL
492
+
#define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL
493
+
#define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL
494
+
#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL
495
+
#define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL
496
+
#define HWRM_TFC_SESSION_ID_ALLOC 0x388UL
497
+
#define HWRM_TFC_SESSION_FID_ADD 0x389UL
498
+
#define HWRM_TFC_SESSION_FID_REM 0x38aUL
499
+
#define HWRM_TFC_IDENT_ALLOC 0x38bUL
500
+
#define HWRM_TFC_IDENT_FREE 0x38cUL
501
+
#define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL
502
+
#define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL
503
+
#define HWRM_TFC_IDX_TBL_SET 0x38fUL
504
+
#define HWRM_TFC_IDX_TBL_GET 0x390UL
505
+
#define HWRM_TFC_IDX_TBL_FREE 0x391UL
506
+
#define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL
507
+
#define HWRM_TFC_TCAM_SET 0x393UL
508
+
#define HWRM_TFC_TCAM_GET 0x394UL
509
+
#define HWRM_TFC_TCAM_ALLOC 0x395UL
510
+
#define HWRM_TFC_TCAM_ALLOC_SET 0x396UL
511
+
#define HWRM_TFC_TCAM_FREE 0x397UL
512
+
#define HWRM_TFC_IF_TBL_SET 0x398UL
513
+
#define HWRM_TFC_IF_TBL_GET 0x399UL
514
+
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
515
+
#define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL
516
+
#define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL
517
+
#define HWRM_TFC_TCAM_PRI_UPDATE 0x39dUL
518
+
#define HWRM_TFC_HOT_UPGRADE_PROCESS 0x3a0UL
519
+
#define HWRM_TFC_SPR_BA_SET 0x3a1UL
520
+
#define HWRM_TFC_SPR_BA_GET 0x3a2UL
521
+
#define HWRM_MGMT_FILTER_ALLOC 0x3e8UL
522
+
#define HWRM_MGMT_FILTER_FREE 0x3e9UL
523
+
#define HWRM_MGMT_FILTER_CFG 0x3eaUL
524
+
#define HWRM_SV 0x400UL
525
+
#define HWRM_DBG_SERDES_TEST 0xff0eUL
526
+
#define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL
527
+
#define HWRM_DBG_READ_DIRECT 0xff10UL
528
+
#define HWRM_DBG_READ_INDIRECT 0xff11UL
529
+
#define HWRM_DBG_WRITE_DIRECT 0xff12UL
530
+
#define HWRM_DBG_WRITE_INDIRECT 0xff13UL
531
+
#define HWRM_DBG_DUMP 0xff14UL
532
+
#define HWRM_DBG_ERASE_NVM 0xff15UL
533
+
#define HWRM_DBG_CFG 0xff16UL
534
+
#define HWRM_DBG_COREDUMP_LIST 0xff17UL
535
+
#define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
536
+
#define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
537
+
#define HWRM_DBG_FW_CLI 0xff1aUL
538
+
#define HWRM_DBG_I2C_CMD 0xff1bUL
539
+
#define HWRM_DBG_RING_INFO_GET 0xff1cUL
540
+
#define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
541
+
#define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
542
+
#define HWRM_DBG_DRV_TRACE 0xff1fUL
543
+
#define HWRM_DBG_QCAPS 0xff20UL
544
+
#define HWRM_DBG_QCFG 0xff21UL
545
+
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
546
+
#define HWRM_DBG_USEQ_ALLOC 0xff23UL
547
+
#define HWRM_DBG_USEQ_FREE 0xff24UL
548
+
#define HWRM_DBG_USEQ_FLUSH 0xff25UL
549
+
#define HWRM_DBG_USEQ_QCAPS 0xff26UL
550
+
#define HWRM_DBG_USEQ_CW_CFG 0xff27UL
551
+
#define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL
552
+
#define HWRM_DBG_USEQ_RUN 0xff29UL
553
+
#define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL
554
+
#define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL
555
+
#define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL
556
+
#define HWRM_DBG_PTRACE 0xff2dUL
557
+
#define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL
558
+
#define HWRM_DBG_TOKEN_QUERY_AUTH_IDS 0xff2fUL
559
+
#define HWRM_DBG_TOKEN_CFG 0xff30UL
560
+
#define HWRM_DBG_TRACE_TRIGGER 0xff31UL
561
+
#define HWRM_DBG_TRACE_TRIGGER_STATUS 0xff32UL
562
+
#define HWRM_NVM_SET_PROFILE 0xffe9UL
563
+
#define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL
564
+
#define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL
565
+
#define HWRM_NVM_DEFRAG 0xffecUL
566
+
#define HWRM_NVM_REQ_ARBITRATION 0xffedUL
567
+
#define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
568
+
#define HWRM_NVM_VALIDATE_OPTION 0xffefUL
569
+
#define HWRM_NVM_FLUSH 0xfff0UL
570
+
#define HWRM_NVM_GET_VARIABLE 0xfff1UL
571
+
#define HWRM_NVM_SET_VARIABLE 0xfff2UL
572
+
#define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
573
+
#define HWRM_NVM_MODIFY 0xfff4UL
574
+
#define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
575
+
#define HWRM_NVM_GET_DEV_INFO 0xfff6UL
576
+
#define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
577
+
#define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
578
+
#define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
579
+
#define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
580
+
#define HWRM_NVM_GET_DIR_INFO 0xfffbUL
581
+
#define HWRM_NVM_RAW_DUMP 0xfffcUL
582
+
#define HWRM_NVM_READ 0xfffdUL
583
+
#define HWRM_NVM_WRITE 0xfffeUL
584
+
#define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
585
+
#define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
586
+
__le16 unused_0[3];
587
+
};
588
+
589
+
/* ret_codes (size:64b/8B) */
590
+
struct ret_codes {
591
+
__le16 error_code;
592
+
#define HWRM_ERR_CODE_SUCCESS 0x0UL
593
+
#define HWRM_ERR_CODE_FAIL 0x1UL
594
+
#define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
595
+
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
596
+
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
597
+
#define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
598
+
#define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
599
+
#define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
600
+
#define HWRM_ERR_CODE_NO_BUFFER 0x8UL
601
+
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
602
+
#define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
603
+
#define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
604
+
#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
605
+
#define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
606
+
#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
607
+
#define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
608
+
#define HWRM_ERR_CODE_BUSY 0x10UL
609
+
#define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
610
+
#define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL
611
+
#define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL
612
+
#define HWRM_ERR_CODE_SECURE_SOC_ERROR 0x14UL
613
+
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
614
+
#define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
615
+
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
616
+
#define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
617
+
__le16 unused_0[3];
618
+
};
619
+
620
+
/* hwrm_err_output (size:128b/16B) */
621
+
struct hwrm_err_output {
622
+
__le16 error_code;
623
+
__le16 req_type;
624
+
__le16 seq_id;
625
+
__le16 resp_len;
626
+
__le32 opaque_0;
627
+
__le16 opaque_1;
628
+
u8 cmd_err;
629
+
u8 valid;
630
+
};
631
+
632
+
#define HWRM_NA_SIGNATURE ((__le32)(-1))
633
+
#define HWRM_MAX_REQ_LEN 128
634
+
#define HWRM_MAX_RESP_LEN 704
635
+
#define HW_HASH_INDEX_SIZE 0x80
636
+
#define HW_HASH_KEY_SIZE 40
637
+
#define HWRM_RESP_VALID_KEY 1
638
+
#define HWRM_TARGET_ID_BONO 0xFFF8
639
+
#define HWRM_TARGET_ID_KONG 0xFFF9
640
+
#define HWRM_TARGET_ID_APE 0xFFFA
641
+
#define HWRM_TARGET_ID_TOOLS 0xFFFD
642
+
#define HWRM_VERSION_MAJOR 1
643
+
#define HWRM_VERSION_MINOR 15
644
+
#define HWRM_VERSION_UPDATE 1
645
+
#define HWRM_VERSION_RSVD 1
646
+
#define HWRM_VERSION_STR "1.15.1.1"
647
+
648
+
/* hwrm_ver_get_input (size:192b/24B) */
649
+
struct hwrm_ver_get_input {
650
+
__le16 req_type;
651
+
__le16 cmpl_ring;
652
+
__le16 seq_id;
653
+
__le16 target_id;
654
+
__le64 resp_addr;
655
+
u8 hwrm_intf_maj;
656
+
u8 hwrm_intf_min;
657
+
u8 hwrm_intf_upd;
658
+
u8 unused_0[5];
659
+
};
660
+
661
+
/* hwrm_ver_get_output (size:1472b/184B) */
662
+
struct hwrm_ver_get_output {
663
+
__le16 error_code;
664
+
__le16 req_type;
665
+
__le16 seq_id;
666
+
__le16 resp_len;
667
+
u8 hwrm_intf_maj_8b;
668
+
u8 hwrm_intf_min_8b;
669
+
u8 hwrm_intf_upd_8b;
670
+
u8 hwrm_intf_rsvd_8b;
671
+
u8 hwrm_fw_maj_8b;
672
+
u8 hwrm_fw_min_8b;
673
+
u8 hwrm_fw_bld_8b;
674
+
u8 hwrm_fw_rsvd_8b;
675
+
u8 mgmt_fw_maj_8b;
676
+
u8 mgmt_fw_min_8b;
677
+
u8 mgmt_fw_bld_8b;
678
+
u8 mgmt_fw_rsvd_8b;
679
+
u8 netctrl_fw_maj_8b;
680
+
u8 netctrl_fw_min_8b;
681
+
u8 netctrl_fw_bld_8b;
682
+
u8 netctrl_fw_rsvd_8b;
683
+
__le32 dev_caps_cfg;
684
+
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
685
+
#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
686
+
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
687
+
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
688
+
#define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
689
+
#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
690
+
#define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
691
+
#define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
692
+
#define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
693
+
#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
694
+
#define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
695
+
#define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
696
+
#define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
697
+
#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
698
+
#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL
699
+
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL
700
+
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL
701
+
#define VER_GET_RESP_DEV_CAPS_CFG_DEBUG_TOKEN_SUPPORTED 0x20000UL
702
+
#define VER_GET_RESP_DEV_CAPS_CFG_PSP_SUPPORTED 0x40000UL
703
+
#define VER_GET_RESP_DEV_CAPS_CFG_ROCE_COUNTERSET_SUPPORTED 0x80000UL
704
+
u8 roce_fw_maj_8b;
705
+
u8 roce_fw_min_8b;
706
+
u8 roce_fw_bld_8b;
707
+
u8 roce_fw_rsvd_8b;
708
+
char hwrm_fw_name[16];
709
+
char mgmt_fw_name[16];
710
+
char netctrl_fw_name[16];
711
+
char active_pkg_name[16];
712
+
char roce_fw_name[16];
713
+
__le16 chip_num;
714
+
u8 chip_rev;
715
+
u8 chip_metal;
716
+
u8 chip_bond_id;
717
+
u8 chip_platform_type;
718
+
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
719
+
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
720
+
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
721
+
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
722
+
__le16 max_req_win_len;
723
+
__le16 max_resp_len;
724
+
__le16 def_req_timeout;
725
+
u8 flags;
726
+
#define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
727
+
#define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
728
+
#define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL
729
+
u8 unused_0[2];
730
+
u8 always_1;
731
+
__le16 hwrm_intf_major;
732
+
__le16 hwrm_intf_minor;
733
+
__le16 hwrm_intf_build;
734
+
__le16 hwrm_intf_patch;
735
+
__le16 hwrm_fw_major;
736
+
__le16 hwrm_fw_minor;
737
+
__le16 hwrm_fw_build;
738
+
__le16 hwrm_fw_patch;
739
+
__le16 mgmt_fw_major;
740
+
__le16 mgmt_fw_minor;
741
+
__le16 mgmt_fw_build;
742
+
__le16 mgmt_fw_patch;
743
+
__le16 netctrl_fw_major;
744
+
__le16 netctrl_fw_minor;
745
+
__le16 netctrl_fw_build;
746
+
__le16 netctrl_fw_patch;
747
+
__le16 roce_fw_major;
748
+
__le16 roce_fw_minor;
749
+
__le16 roce_fw_build;
750
+
__le16 roce_fw_patch;
751
+
__le16 max_ext_req_len;
752
+
__le16 max_req_timeout;
753
+
__le16 max_psp_supported_pfs;
754
+
__le16 max_psp_supported_vfs;
755
+
__le16 max_roce_countersets;
756
+
__le16 max_ext_req_timeout;
757
+
u8 unused_1[3];
758
+
u8 valid;
759
+
};
760
+
761
+
/* eject_cmpl (size:128b/16B) */
762
+
struct eject_cmpl {
763
+
__le16 type;
764
+
#define EJECT_CMPL_TYPE_MASK 0x3fUL
765
+
#define EJECT_CMPL_TYPE_SFT 0
766
+
#define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
767
+
#define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
768
+
#define EJECT_CMPL_FLAGS_MASK 0xffc0UL
769
+
#define EJECT_CMPL_FLAGS_SFT 6
770
+
#define EJECT_CMPL_FLAGS_ERROR 0x40UL
771
+
__le16 len;
772
+
__le32 opaque;
773
+
__le16 v;
774
+
#define EJECT_CMPL_V 0x1UL
775
+
#define EJECT_CMPL_ERRORS_MASK 0xfffeUL
776
+
#define EJECT_CMPL_ERRORS_SFT 1
777
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
778
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
779
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
780
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
781
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
782
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
783
+
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
784
+
__le16 reserved16;
785
+
__le32 unused_2;
786
+
};
787
+
788
+
/* hwrm_cmpl (size:128b/16B) */
789
+
struct hwrm_cmpl {
790
+
__le16 type;
791
+
#define CMPL_TYPE_MASK 0x3fUL
792
+
#define CMPL_TYPE_SFT 0
793
+
#define CMPL_TYPE_HWRM_DONE 0x20UL
794
+
#define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
795
+
__le16 sequence_id;
796
+
__le32 unused_1;
797
+
__le32 v;
798
+
#define CMPL_V 0x1UL
799
+
__le32 unused_3;
800
+
};
801
+
802
+
/* hwrm_fwd_req_cmpl (size:128b/16B) */
803
+
struct hwrm_fwd_req_cmpl {
804
+
__le16 req_len_type;
805
+
#define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
806
+
#define FWD_REQ_CMPL_TYPE_SFT 0
807
+
#define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
808
+
#define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
809
+
#define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
810
+
#define FWD_REQ_CMPL_REQ_LEN_SFT 6
811
+
__le16 source_id;
812
+
__le32 unused0;
813
+
__le32 req_buf_addr_v[2];
814
+
#define FWD_REQ_CMPL_V 0x1UL
815
+
#define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
816
+
#define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
817
+
};
818
+
819
+
/* hwrm_fwd_resp_cmpl (size:128b/16B) */
820
+
struct hwrm_fwd_resp_cmpl {
821
+
__le16 type;
822
+
#define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
823
+
#define FWD_RESP_CMPL_TYPE_SFT 0
824
+
#define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
825
+
#define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
826
+
__le16 source_id;
827
+
__le16 resp_len;
828
+
__le16 unused_1;
829
+
__le32 resp_buf_addr_v[2];
830
+
#define FWD_RESP_CMPL_V 0x1UL
831
+
#define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
832
+
#define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
833
+
};
834
+
835
+
/* hwrm_async_event_cmpl (size:128b/16B) */
836
+
struct hwrm_async_event_cmpl {
837
+
__le16 type;
838
+
#define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
839
+
#define ASYNC_EVENT_CMPL_TYPE_SFT 0
840
+
#define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
841
+
#define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
842
+
__le16 event_id;
843
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
844
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
845
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
846
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
847
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
848
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
849
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
850
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
851
+
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
852
+
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
853
+
#define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL
854
+
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
855
+
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
856
+
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
857
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
858
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
859
+
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
860
+
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
861
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
862
+
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
863
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
864
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
865
+
#define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
866
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
867
+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
868
+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
869
+
#define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
870
+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
871
+
#define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
872
+
#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
873
+
#define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
874
+
#define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
875
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
876
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
877
+
#define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL
878
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL
879
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL
880
+
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL
881
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL
882
+
#define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL
883
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL
884
+
#define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL
885
+
#define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL
886
+
#define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL
887
+
#define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL
888
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL
889
+
#define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL
890
+
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL
891
+
#define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL
892
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PNO_HOST_DMA_COMPLETE 0x51UL
893
+
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_GID_UPDATE 0x52UL
894
+
#define ASYNC_EVENT_CMPL_EVENT_ID_ADPTV_QOS 0x53UL
895
+
#define ASYNC_EVENT_CMPL_EVENT_ID_FABRIC_NEXT_HOP_IP_UPDATED 0x54UL
896
+
#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x55UL
897
+
#define ASYNC_EVENT_CMPL_EVENT_ID_PSP_SM_KEY_ROTATE_NOTIFY 0x56UL
898
+
#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
899
+
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
900
+
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
901
+
__le32 event_data2;
902
+
u8 opaque_v;
903
+
#define ASYNC_EVENT_CMPL_V 0x1UL
904
+
#define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
905
+
#define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
906
+
u8 timestamp_lo;
907
+
__le16 timestamp_hi;
908
+
__le32 event_data1;
909
+
};
910
+
911
+
/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
912
+
struct hwrm_async_event_cmpl_link_status_change {
913
+
__le16 type;
914
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
915
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
916
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
917
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
918
+
__le16 event_id;
919
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
920
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
921
+
__le32 event_data2;
922
+
u8 opaque_v;
923
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
924
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
925
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
926
+
u8 timestamp_lo;
927
+
__le16 timestamp_hi;
928
+
__le32 event_data1;
929
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
930
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
931
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
932
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
933
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
934
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
935
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
936
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
937
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
938
+
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
939
+
};
940
+
941
+
/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
942
+
struct hwrm_async_event_cmpl_port_conn_not_allowed {
943
+
__le16 type;
944
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
945
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
946
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
947
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
948
+
__le16 event_id;
949
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
950
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
951
+
__le32 event_data2;
952
+
u8 opaque_v;
953
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
954
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
955
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
956
+
u8 timestamp_lo;
957
+
__le16 timestamp_hi;
958
+
__le32 event_data1;
959
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
960
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
961
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
962
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
963
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
964
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
965
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
966
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
967
+
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
968
+
};
969
+
970
+
/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
971
+
struct hwrm_async_event_cmpl_link_speed_cfg_change {
972
+
__le16 type;
973
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
974
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
975
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
976
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
977
+
__le16 event_id;
978
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
979
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
980
+
__le32 event_data2;
981
+
u8 opaque_v;
982
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
983
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
984
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
985
+
u8 timestamp_lo;
986
+
__le16 timestamp_hi;
987
+
__le32 event_data1;
988
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
989
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
990
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
991
+
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
992
+
};
993
+
994
+
/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
995
+
struct hwrm_async_event_cmpl_reset_notify {
996
+
__le16 type;
997
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
998
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
999
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1000
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
1001
+
__le16 event_id;
1002
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
1003
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
1004
+
__le32 event_data2;
1005
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
1006
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
1007
+
u8 opaque_v;
1008
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
1009
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
1010
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
1011
+
u8 timestamp_lo;
1012
+
__le16 timestamp_hi;
1013
+
__le32 event_data1;
1014
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
1015
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
1016
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
1017
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
1018
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
1019
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
1020
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
1021
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
1022
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
1023
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
1024
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8)
1025
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8)
1026
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
1027
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
1028
+
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
1029
+
};
1030
+
1031
+
/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
1032
+
struct hwrm_async_event_cmpl_error_recovery {
1033
+
__le16 type;
1034
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
1035
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
1036
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1037
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
1038
+
__le16 event_id;
1039
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
1040
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
1041
+
__le32 event_data2;
1042
+
u8 opaque_v;
1043
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
1044
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
1045
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
1046
+
u8 timestamp_lo;
1047
+
__le16 timestamp_hi;
1048
+
__le32 event_data1;
1049
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
1050
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
1051
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
1052
+
#define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
1053
+
};
1054
+
1055
+
/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
1056
+
struct hwrm_async_event_cmpl_ring_monitor_msg {
1057
+
__le16 type;
1058
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL
1059
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
1060
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1061
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
1062
+
__le16 event_id;
1063
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
1064
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
1065
+
__le32 event_data2;
1066
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
1067
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
1068
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL
1069
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL
1070
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL
1071
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
1072
+
u8 opaque_v;
1073
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL
1074
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
1075
+
#define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
1076
+
u8 timestamp_lo;
1077
+
__le16 timestamp_hi;
1078
+
__le32 event_data1;
1079
+
};
1080
+
1081
+
/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
1082
+
struct hwrm_async_event_cmpl_vf_cfg_change {
1083
+
__le16 type;
1084
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
1085
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
1086
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1087
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
1088
+
__le16 event_id;
1089
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
1090
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
1091
+
__le32 event_data2;
1092
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
1093
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
1094
+
u8 opaque_v;
1095
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
1096
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1097
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1098
+
u8 timestamp_lo;
1099
+
__le16 timestamp_hi;
1100
+
__le32 event_data1;
1101
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
1102
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
1103
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
1104
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
1105
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
1106
+
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL
1107
+
};
1108
+
1109
+
/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1110
+
struct hwrm_async_event_cmpl_default_vnic_change {
1111
+
__le16 type;
1112
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
1113
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
1114
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1115
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1116
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
1117
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
1118
+
__le16 event_id;
1119
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1120
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1121
+
__le32 event_data2;
1122
+
u8 opaque_v;
1123
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
1124
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1125
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1126
+
u8 timestamp_lo;
1127
+
__le16 timestamp_hi;
1128
+
__le32 event_data1;
1129
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
1130
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
1131
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
1132
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
1133
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1134
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
1135
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
1136
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
1137
+
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
1138
+
};
1139
+
1140
+
/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1141
+
struct hwrm_async_event_cmpl_hw_flow_aged {
1142
+
__le16 type;
1143
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
1144
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
1145
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1146
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1147
+
__le16 event_id;
1148
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1149
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1150
+
__le32 event_data2;
1151
+
u8 opaque_v;
1152
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
1153
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1154
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1155
+
u8 timestamp_lo;
1156
+
__le16 timestamp_hi;
1157
+
__le32 event_data1;
1158
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
1159
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
1160
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
1161
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
1162
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
1163
+
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1164
+
};
1165
+
1166
+
/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
1167
+
struct hwrm_async_event_cmpl_eem_cache_flush_req {
1168
+
__le16 type;
1169
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
1170
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
1171
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1172
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
1173
+
__le16 event_id;
1174
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
1175
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
1176
+
__le32 event_data2;
1177
+
u8 opaque_v;
1178
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
1179
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
1180
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
1181
+
u8 timestamp_lo;
1182
+
__le16 timestamp_hi;
1183
+
__le32 event_data1;
1184
+
};
1185
+
1186
+
/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
1187
+
struct hwrm_async_event_cmpl_eem_cache_flush_done {
1188
+
__le16 type;
1189
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
1190
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
1191
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1192
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
1193
+
__le16 event_id;
1194
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1195
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1196
+
__le32 event_data2;
1197
+
u8 opaque_v;
1198
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
1199
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1200
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1201
+
u8 timestamp_lo;
1202
+
__le16 timestamp_hi;
1203
+
__le32 event_data1;
1204
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1205
+
#define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1206
+
};
1207
+
1208
+
/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1209
+
struct hwrm_async_event_cmpl_deferred_response {
1210
+
__le16 type;
1211
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL
1212
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
1213
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1214
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1215
+
__le16 event_id;
1216
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1217
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1218
+
__le32 event_data2;
1219
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1220
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1221
+
u8 opaque_v;
1222
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL
1223
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1224
+
#define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1225
+
u8 timestamp_lo;
1226
+
__le16 timestamp_hi;
1227
+
__le32 event_data1;
1228
+
};
1229
+
1230
+
/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
1231
+
struct hwrm_async_event_cmpl_echo_request {
1232
+
__le16 type;
1233
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL
1234
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
1235
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1236
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
1237
+
__le16 event_id;
1238
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
1239
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
1240
+
__le32 event_data2;
1241
+
u8 opaque_v;
1242
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL
1243
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
1244
+
#define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
1245
+
u8 timestamp_lo;
1246
+
__le16 timestamp_hi;
1247
+
__le32 event_data1;
1248
+
};
1249
+
1250
+
/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
1251
+
struct hwrm_async_event_cmpl_phc_update {
1252
+
__le16 type;
1253
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL
1254
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
1255
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1256
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
1257
+
__le16 event_id;
1258
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
1259
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
1260
+
__le32 event_data2;
1261
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
1262
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
1263
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
1264
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16
1265
+
u8 opaque_v;
1266
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL
1267
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
1268
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
1269
+
u8 timestamp_lo;
1270
+
__le16 timestamp_hi;
1271
+
__le32 event_data1;
1272
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL
1273
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0
1274
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
1275
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
1276
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
1277
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL
1278
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
1279
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL
1280
+
#define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4
1281
+
};
1282
+
1283
+
/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
1284
+
struct hwrm_async_event_cmpl_pps_timestamp {
1285
+
__le16 type;
1286
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL
1287
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
1288
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1289
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
1290
+
__le16 event_id;
1291
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
1292
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
1293
+
__le32 event_data2;
1294
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL
1295
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL
1296
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL
1297
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
1298
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL
1299
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1
1300
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
1301
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
1302
+
u8 opaque_v;
1303
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL
1304
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
1305
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
1306
+
u8 timestamp_lo;
1307
+
__le16 timestamp_hi;
1308
+
__le32 event_data1;
1309
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
1310
+
#define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
1311
+
};
1312
+
1313
+
/* hwrm_async_event_cmpl_error_report (size:128b/16B) */
1314
+
struct hwrm_async_event_cmpl_error_report {
1315
+
__le16 type;
1316
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL
1317
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
1318
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1319
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
1320
+
__le16 event_id;
1321
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
1322
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
1323
+
__le32 event_data2;
1324
+
u8 opaque_v;
1325
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL
1326
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
1327
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
1328
+
u8 timestamp_lo;
1329
+
__le16 timestamp_hi;
1330
+
__le32 event_data1;
1331
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1332
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
1333
+
};
1334
+
1335
+
/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */
1336
+
struct hwrm_async_event_cmpl_dbg_buf_producer {
1337
+
__le16 type;
1338
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL
1339
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0
1340
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1341
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT
1342
+
__le16 event_id;
1343
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL
1344
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER
1345
+
__le32 event_data2;
1346
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL
1347
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0
1348
+
u8 opaque_v;
1349
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL
1350
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL
1351
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1
1352
+
u8 timestamp_lo;
1353
+
__le16 timestamp_hi;
1354
+
__le32 event_data1;
1355
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL
1356
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0
1357
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL
1358
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL
1359
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL
1360
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL
1361
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL
1362
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL
1363
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL
1364
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL
1365
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL
1366
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL
1367
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL
1368
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL
1369
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 0xcUL
1370
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MPRT_TRACE 0xdUL
1371
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RERT_TRACE 0xeUL
1372
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MPC_MSG_TRACE 0xfUL
1373
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MPC_CMPL_TRACE 0x10UL
1374
+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MPC_CMPL_TRACE
1375
+
};
1376
+
1377
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1378
+
struct hwrm_async_event_cmpl_hwrm_error {
1379
+
__le16 type;
1380
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
1381
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
1382
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1383
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1384
+
__le16 event_id;
1385
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1386
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1387
+
__le32 event_data2;
1388
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
1389
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
1390
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
1391
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
1392
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
1393
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1394
+
u8 opaque_v;
1395
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
1396
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1397
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1398
+
u8 timestamp_lo;
1399
+
__le16 timestamp_hi;
1400
+
__le32 event_data1;
1401
+
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
1402
+
};
1403
+
1404
+
/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
1405
+
struct hwrm_async_event_cmpl_error_report_base {
1406
+
__le16 type;
1407
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL
1408
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
1409
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1410
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
1411
+
__le16 event_id;
1412
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
1413
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
1414
+
__le32 event_data2;
1415
+
u8 opaque_v;
1416
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL
1417
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
1418
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
1419
+
u8 timestamp_lo;
1420
+
__le16 timestamp_hi;
1421
+
__le32 event_data1;
1422
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1423
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0
1424
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL
1425
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1426
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1427
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL
1428
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1429
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL
1430
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL
1431
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUP_UDCC_SES 0x7UL
1432
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL
1433
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL
1434
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL
1435
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR
1436
+
};
1437
+
1438
+
/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
1439
+
struct hwrm_async_event_cmpl_error_report_pause_storm {
1440
+
__le16 type;
1441
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL
1442
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0
1443
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1444
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
1445
+
__le16 event_id;
1446
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
1447
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
1448
+
__le32 event_data2;
1449
+
u8 opaque_v;
1450
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL
1451
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
1452
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
1453
+
u8 timestamp_lo;
1454
+
__le16 timestamp_hi;
1455
+
__le32 event_data1;
1456
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1457
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0
1458
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1459
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
1460
+
};
1461
+
1462
+
/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
1463
+
struct hwrm_async_event_cmpl_error_report_invalid_signal {
1464
+
__le16 type;
1465
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL
1466
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0
1467
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1468
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
1469
+
__le16 event_id;
1470
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
1471
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
1472
+
__le32 event_data2;
1473
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
1474
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
1475
+
u8 opaque_v;
1476
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL
1477
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
1478
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
1479
+
u8 timestamp_lo;
1480
+
__le16 timestamp_hi;
1481
+
__le32 event_data1;
1482
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1483
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0
1484
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1485
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
1486
+
};
1487
+
1488
+
/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
1489
+
struct hwrm_async_event_cmpl_error_report_nvm {
1490
+
__le16 type;
1491
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL
1492
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
1493
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1494
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
1495
+
__le16 event_id;
1496
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
1497
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
1498
+
__le32 event_data2;
1499
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
1500
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
1501
+
u8 opaque_v;
1502
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL
1503
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
1504
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
1505
+
u8 timestamp_lo;
1506
+
__le16 timestamp_hi;
1507
+
__le32 event_data1;
1508
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1509
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0
1510
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL
1511
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
1512
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL
1513
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8
1514
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8)
1515
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8)
1516
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
1517
+
};
1518
+
1519
+
/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
1520
+
struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
1521
+
__le16 type;
1522
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL
1523
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0
1524
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1525
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
1526
+
__le16 event_id;
1527
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL
1528
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
1529
+
__le32 event_data2;
1530
+
u8 opaque_v;
1531
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL
1532
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL
1533
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1
1534
+
u8 timestamp_lo;
1535
+
__le16 timestamp_hi;
1536
+
__le32 event_data1;
1537
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1538
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0
1539
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1540
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
1541
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL
1542
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8
1543
+
};
1544
+
1545
+
/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */
1546
+
struct hwrm_async_event_cmpl_error_report_thermal {
1547
+
__le16 type;
1548
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL
1549
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0
1550
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1551
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT
1552
+
__le16 event_id;
1553
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL
1554
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT
1555
+
__le32 event_data2;
1556
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL
1557
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0
1558
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL
1559
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8
1560
+
u8 opaque_v;
1561
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL
1562
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL
1563
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1
1564
+
u8 timestamp_lo;
1565
+
__le16 timestamp_hi;
1566
+
__le32 event_data1;
1567
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1568
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0
1569
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL
1570
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT
1571
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL
1572
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8
1573
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8)
1574
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8)
1575
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8)
1576
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8)
1577
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN
1578
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL
1579
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11)
1580
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11)
1581
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING
1582
+
};
1583
+
1584
+
/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */
1585
+
struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported {
1586
+
__le16 type;
1587
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL
1588
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0
1589
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1590
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT
1591
+
__le16 event_id;
1592
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL
1593
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT
1594
+
__le32 event_data2;
1595
+
u8 opaque_v;
1596
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL
1597
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL
1598
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1
1599
+
u8 timestamp_lo;
1600
+
__le16 timestamp_hi;
1601
+
__le32 event_data1;
1602
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1603
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0
1604
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL
1605
+
#define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED
1606
+
};
1607
+
1608
+
/* hwrm_func_reset_input (size:192b/24B) */
1609
+
struct hwrm_func_reset_input {
1610
+
__le16 req_type;
1611
+
__le16 cmpl_ring;
1612
+
__le16 seq_id;
1613
+
__le16 target_id;
1614
+
__le64 resp_addr;
1615
+
__le32 enables;
1616
+
#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1617
+
__le16 vf_id;
1618
+
u8 func_reset_level;
1619
+
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1620
+
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1621
+
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1622
+
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1623
+
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1624
+
u8 unused_0;
1625
+
};
1626
+
1627
+
/* hwrm_func_reset_output (size:128b/16B) */
1628
+
struct hwrm_func_reset_output {
1629
+
__le16 error_code;
1630
+
__le16 req_type;
1631
+
__le16 seq_id;
1632
+
__le16 resp_len;
1633
+
u8 unused_0[7];
1634
+
u8 valid;
1635
+
};
1636
+
1637
+
/* hwrm_func_getfid_input (size:192b/24B) */
1638
+
struct hwrm_func_getfid_input {
1639
+
__le16 req_type;
1640
+
__le16 cmpl_ring;
1641
+
__le16 seq_id;
1642
+
__le16 target_id;
1643
+
__le64 resp_addr;
1644
+
__le32 enables;
1645
+
#define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1646
+
__le16 pci_id;
1647
+
u8 unused_0[2];
1648
+
};
1649
+
1650
+
/* hwrm_func_getfid_output (size:128b/16B) */
1651
+
struct hwrm_func_getfid_output {
1652
+
__le16 error_code;
1653
+
__le16 req_type;
1654
+
__le16 seq_id;
1655
+
__le16 resp_len;
1656
+
__le16 fid;
1657
+
u8 unused_0[5];
1658
+
u8 valid;
1659
+
};
1660
+
1661
+
/* hwrm_func_vf_alloc_input (size:192b/24B) */
1662
+
struct hwrm_func_vf_alloc_input {
1663
+
__le16 req_type;
1664
+
__le16 cmpl_ring;
1665
+
__le16 seq_id;
1666
+
__le16 target_id;
1667
+
__le64 resp_addr;
1668
+
__le32 enables;
1669
+
#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1670
+
__le16 first_vf_id;
1671
+
__le16 num_vfs;
1672
+
};
1673
+
1674
+
/* hwrm_func_vf_alloc_output (size:128b/16B) */
1675
+
struct hwrm_func_vf_alloc_output {
1676
+
__le16 error_code;
1677
+
__le16 req_type;
1678
+
__le16 seq_id;
1679
+
__le16 resp_len;
1680
+
__le16 first_vf_id;
1681
+
u8 unused_0[5];
1682
+
u8 valid;
1683
+
};
1684
+
1685
+
/* hwrm_func_vf_free_input (size:192b/24B) */
1686
+
struct hwrm_func_vf_free_input {
1687
+
__le16 req_type;
1688
+
__le16 cmpl_ring;
1689
+
__le16 seq_id;
1690
+
__le16 target_id;
1691
+
__le64 resp_addr;
1692
+
__le32 enables;
1693
+
#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1694
+
__le16 first_vf_id;
1695
+
__le16 num_vfs;
1696
+
};
1697
+
1698
+
/* hwrm_func_vf_free_output (size:128b/16B) */
1699
+
struct hwrm_func_vf_free_output {
1700
+
__le16 error_code;
1701
+
__le16 req_type;
1702
+
__le16 seq_id;
1703
+
__le16 resp_len;
1704
+
u8 unused_0[7];
1705
+
u8 valid;
1706
+
};
1707
+
1708
+
/* hwrm_func_vf_cfg_input (size:576b/72B) */
1709
+
struct hwrm_func_vf_cfg_input {
1710
+
__le16 req_type;
1711
+
__le16 cmpl_ring;
1712
+
__le16 seq_id;
1713
+
__le16 target_id;
1714
+
__le64 resp_addr;
1715
+
__le32 enables;
1716
+
#define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1717
+
#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1718
+
#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1719
+
#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1720
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1721
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1722
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1723
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1724
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1725
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1726
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1727
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1728
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL
1729
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL
1730
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL
1731
+
#define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL
1732
+
__le16 mtu;
1733
+
__le16 guest_vlan;
1734
+
__le16 async_event_cr;
1735
+
u8 dflt_mac_addr[6];
1736
+
__le32 flags;
1737
+
#define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1738
+
#define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1739
+
#define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1740
+
#define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1741
+
#define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1742
+
#define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1743
+
#define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1744
+
#define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1745
+
#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL
1746
+
#define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL
1747
+
__le16 num_rsscos_ctxs;
1748
+
__le16 num_cmpl_rings;
1749
+
__le16 num_tx_rings;
1750
+
__le16 num_rx_rings;
1751
+
__le16 num_l2_ctxs;
1752
+
__le16 num_vnics;
1753
+
__le16 num_stat_ctxs;
1754
+
__le16 num_hw_ring_grps;
1755
+
__le32 num_ktls_tx_key_ctxs;
1756
+
__le32 num_ktls_rx_key_ctxs;
1757
+
__le16 num_msix;
1758
+
u8 unused[2];
1759
+
__le32 num_quic_tx_key_ctxs;
1760
+
__le32 num_quic_rx_key_ctxs;
1761
+
};
1762
+
1763
+
/* hwrm_func_vf_cfg_output (size:128b/16B) */
1764
+
struct hwrm_func_vf_cfg_output {
1765
+
__le16 error_code;
1766
+
__le16 req_type;
1767
+
__le16 seq_id;
1768
+
__le16 resp_len;
1769
+
u8 unused_0[7];
1770
+
u8 valid;
1771
+
};
1772
+
1773
+
/* hwrm_func_qcaps_input (size:192b/24B) */
1774
+
struct hwrm_func_qcaps_input {
1775
+
__le16 req_type;
1776
+
__le16 cmpl_ring;
1777
+
__le16 seq_id;
1778
+
__le16 target_id;
1779
+
__le64 resp_addr;
1780
+
__le16 fid;
1781
+
u8 unused_0[6];
1782
+
};
1783
+
1784
+
/* hwrm_func_qcaps_output (size:1152b/144B) */
1785
+
struct hwrm_func_qcaps_output {
1786
+
__le16 error_code;
1787
+
__le16 req_type;
1788
+
__le16 seq_id;
1789
+
__le16 resp_len;
1790
+
__le16 fid;
1791
+
__le16 port_id;
1792
+
__le32 flags;
1793
+
#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1794
+
#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1795
+
#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1796
+
#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1797
+
#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1798
+
#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1799
+
#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1800
+
#define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1801
+
#define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1802
+
#define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1803
+
#define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1804
+
#define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1805
+
#define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1806
+
#define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1807
+
#define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1808
+
#define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1809
+
#define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1810
+
#define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1811
+
#define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1812
+
#define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1813
+
#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1814
+
#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1815
+
#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1816
+
#define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
1817
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
1818
+
#define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
1819
+
#define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
1820
+
#define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
1821
+
#define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL
1822
+
#define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL
1823
+
#define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL
1824
+
#define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL
1825
+
u8 mac_address[6];
1826
+
__le16 max_rsscos_ctx;
1827
+
__le16 max_cmpl_rings;
1828
+
__le16 max_tx_rings;
1829
+
__le16 max_rx_rings;
1830
+
__le16 max_l2_ctxs;
1831
+
__le16 max_vnics;
1832
+
__le16 first_vf_id;
1833
+
__le16 max_vfs;
1834
+
__le16 max_stat_ctx;
1835
+
__le32 max_encap_records;
1836
+
__le32 max_decap_records;
1837
+
__le32 max_tx_em_flows;
1838
+
__le32 max_tx_wm_flows;
1839
+
__le32 max_rx_em_flows;
1840
+
__le32 max_rx_wm_flows;
1841
+
__le32 max_mcast_filters;
1842
+
__le32 max_flow_id;
1843
+
__le32 max_hw_ring_grps;
1844
+
__le16 max_sp_tx_rings;
1845
+
__le16 max_msix_vfs;
1846
+
__le32 flags_ext;
1847
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
1848
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
1849
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL
1850
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL
1851
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL
1852
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL
1853
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL
1854
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL
1855
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL
1856
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL
1857
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL
1858
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL
1859
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL
1860
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL
1861
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL
1862
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL
1863
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL
1864
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL
1865
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL
1866
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL
1867
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL
1868
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL
1869
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL
1870
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL
1871
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL
1872
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL
1873
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL
1874
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL
1875
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL
1876
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL
1877
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL
1878
+
#define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL
1879
+
u8 max_schqs;
1880
+
u8 mpc_chnls_cap;
1881
+
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
1882
+
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL
1883
+
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL
1884
+
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL
1885
+
#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL
1886
+
__le16 max_key_ctxs_alloc;
1887
+
__le32 flags_ext2;
1888
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL
1889
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL
1890
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL
1891
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL
1892
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL
1893
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL
1894
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL
1895
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL
1896
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL
1897
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL
1898
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL
1899
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL
1900
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL
1901
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL
1902
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL
1903
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL
1904
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL
1905
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL
1906
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL
1907
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL
1908
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL
1909
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL
1910
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL
1911
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL
1912
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL
1913
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL
1914
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL
1915
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL
1916
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL
1917
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED 0x20000000UL
1918
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED 0x40000000UL
1919
+
#define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED 0x80000000UL
1920
+
__le16 tunnel_disable_flag;
1921
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL
1922
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL
1923
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL
1924
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL
1925
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL
1926
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL
1927
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL
1928
+
#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL
1929
+
__le16 xid_partition_cap;
1930
+
#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL
1931
+
#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL
1932
+
u8 device_serial_number[8];
1933
+
__le16 ctxs_per_partition;
1934
+
__le16 max_tso_segs;
1935
+
__le32 roce_vf_max_av;
1936
+
__le32 roce_vf_max_cq;
1937
+
__le32 roce_vf_max_mrw;
1938
+
__le32 roce_vf_max_qp;
1939
+
__le32 roce_vf_max_srq;
1940
+
__le32 roce_vf_max_gid;
1941
+
__le32 flags_ext3;
1942
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1943
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1944
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1945
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL
1946
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL
1947
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL
1948
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT 0x40UL
1949
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_CHANGE_UDP_SRCPORT_SUPPORT 0x80UL
1950
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL
1951
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL
1952
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL
1953
+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_DATA_SUPPORTED 0x800UL
1954
+
__le16 max_roce_vfs;
1955
+
__le16 max_crypto_rx_flow_filters;
1956
+
u8 unused_3[3];
1957
+
u8 valid;
1958
+
};
1959
+
1960
+
/* hwrm_func_qcfg_input (size:192b/24B) */
1961
+
struct hwrm_func_qcfg_input {
1962
+
__le16 req_type;
1963
+
__le16 cmpl_ring;
1964
+
__le16 seq_id;
1965
+
__le16 target_id;
1966
+
__le64 resp_addr;
1967
+
__le16 fid;
1968
+
u8 unused_0[6];
1969
+
};
1970
+
1971
+
/* hwrm_func_qcfg_output (size:1408b/176B) */
1972
+
struct hwrm_func_qcfg_output {
1973
+
__le16 error_code;
1974
+
__le16 req_type;
1975
+
__le16 seq_id;
1976
+
__le16 resp_len;
1977
+
__le16 fid;
1978
+
__le16 port_id;
1979
+
__le16 vlan;
1980
+
__le16 flags;
1981
+
#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1982
+
#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1983
+
#define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1984
+
#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1985
+
#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1986
+
#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1987
+
#define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1988
+
#define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1989
+
#define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
1990
+
#define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL
1991
+
#define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL
1992
+
#define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
1993
+
#define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL
1994
+
#define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL
1995
+
#define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL
1996
+
#define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL
1997
+
u8 mac_address[6];
1998
+
__le16 pci_id;
1999
+
__le16 alloc_rsscos_ctx;
2000
+
__le16 alloc_cmpl_rings;
2001
+
__le16 alloc_tx_rings;
2002
+
__le16 alloc_rx_rings;
2003
+
__le16 alloc_l2_ctx;
2004
+
__le16 alloc_vnics;
2005
+
__le16 admin_mtu;
2006
+
__le16 mru;
2007
+
__le16 stat_ctx_id;
2008
+
u8 port_partition_type;
2009
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
2010
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
2011
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
2012
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
2013
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
2014
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
2015
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
2016
+
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
2017
+
u8 port_pf_cnt;
2018
+
#define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
2019
+
#define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
2020
+
__le16 dflt_vnic_id;
2021
+
__le16 max_mtu_configured;
2022
+
__le32 min_bw;
2023
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2024
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
2025
+
#define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
2026
+
#define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
2027
+
#define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
2028
+
#define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
2029
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2030
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
2031
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2032
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2033
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2034
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2035
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2036
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2037
+
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
2038
+
__le32 max_bw;
2039
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2040
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
2041
+
#define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
2042
+
#define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
2043
+
#define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
2044
+
#define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
2045
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2046
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
2047
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2048
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2049
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2050
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2051
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2052
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2053
+
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
2054
+
u8 evb_mode;
2055
+
#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
2056
+
#define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
2057
+
#define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
2058
+
#define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
2059
+
u8 options;
2060
+
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
2061
+
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
2062
+
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
2063
+
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
2064
+
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
2065
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
2066
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
2067
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
2068
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
2069
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
2070
+
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
2071
+
#define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
2072
+
#define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
2073
+
__le16 alloc_vfs;
2074
+
__le32 alloc_mcast_filters;
2075
+
__le32 alloc_hw_ring_grps;
2076
+
__le16 alloc_sp_tx_rings;
2077
+
__le16 alloc_stat_ctx;
2078
+
__le16 alloc_msix;
2079
+
__le16 registered_vfs;
2080
+
__le16 l2_doorbell_bar_size_kb;
2081
+
u8 active_endpoints;
2082
+
u8 always_1;
2083
+
__le32 reset_addr_poll;
2084
+
__le16 legacy_l2_db_size_kb;
2085
+
__le16 svif_info;
2086
+
#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL
2087
+
#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0
2088
+
#define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL
2089
+
u8 mpc_chnls;
2090
+
#define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL
2091
+
#define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL
2092
+
#define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
2093
+
#define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
2094
+
#define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
2095
+
u8 db_page_size;
2096
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL
2097
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL
2098
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL
2099
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL
2100
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL
2101
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL
2102
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL
2103
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL
2104
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL
2105
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL
2106
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL
2107
+
#define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB
2108
+
__le16 roce_vnic_id;
2109
+
__le32 partition_min_bw;
2110
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2111
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0
2112
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL
2113
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
2114
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
2115
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
2116
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2117
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
2118
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2119
+
#define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
2120
+
__le32 partition_max_bw;
2121
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2122
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0
2123
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL
2124
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
2125
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
2126
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
2127
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2128
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
2129
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2130
+
#define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
2131
+
__le16 host_mtu;
2132
+
__le16 flags2;
2133
+
#define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL
2134
+
__le16 stag_vid;
2135
+
u8 port_kdnet_mode;
2136
+
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
2137
+
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL
2138
+
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
2139
+
u8 kdnet_pcie_function;
2140
+
__le16 port_kdnet_fid;
2141
+
u8 unused_5;
2142
+
u8 roce_bidi_opt_mode;
2143
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DISABLED 0x1UL
2144
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DEDICATED 0x2UL
2145
+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_SHARED 0x4UL
2146
+
__le32 num_ktls_tx_key_ctxs;
2147
+
__le32 num_ktls_rx_key_ctxs;
2148
+
u8 lag_id;
2149
+
u8 parif;
2150
+
u8 fw_lag_id;
2151
+
u8 unused_6;
2152
+
__le32 num_quic_tx_key_ctxs;
2153
+
__le32 num_quic_rx_key_ctxs;
2154
+
__le32 roce_max_av_per_vf;
2155
+
__le32 roce_max_cq_per_vf;
2156
+
__le32 roce_max_mrw_per_vf;
2157
+
__le32 roce_max_qp_per_vf;
2158
+
__le32 roce_max_srq_per_vf;
2159
+
__le32 roce_max_gid_per_vf;
2160
+
__le16 xid_partition_cfg;
2161
+
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL
2162
+
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL
2163
+
__le16 mirror_vnic_id;
2164
+
u8 max_link_width;
2165
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_UNKNOWN 0x0UL
2166
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X1 0x1UL
2167
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X2 0x2UL
2168
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X4 0x4UL
2169
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X8 0x8UL
2170
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 0x10UL
2171
+
#define FUNC_QCFG_RESP_MAX_LINK_WIDTH_LAST FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16
2172
+
u8 max_link_speed;
2173
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_UNKNOWN 0x0UL
2174
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_G1 0x1UL
2175
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_G2 0x2UL
2176
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_G3 0x3UL
2177
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_G4 0x4UL
2178
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 0x5UL
2179
+
#define FUNC_QCFG_RESP_MAX_LINK_SPEED_LAST FUNC_QCFG_RESP_MAX_LINK_SPEED_G5
2180
+
u8 negotiated_link_width;
2181
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_UNKNOWN 0x0UL
2182
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X1 0x1UL
2183
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X2 0x2UL
2184
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X4 0x4UL
2185
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X8 0x8UL
2186
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 0x10UL
2187
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16
2188
+
u8 negotiated_link_speed;
2189
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_UNKNOWN 0x0UL
2190
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G1 0x1UL
2191
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G2 0x2UL
2192
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G3 0x3UL
2193
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G4 0x4UL
2194
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 0x5UL
2195
+
#define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5
2196
+
u8 unused_7[2];
2197
+
u8 pcie_compliance;
2198
+
u8 unused_8;
2199
+
__le16 l2_db_multi_page_size_kb;
2200
+
u8 unused_9[5];
2201
+
u8 valid;
2202
+
};
2203
+
2204
+
/* hwrm_func_cfg_input (size:1280b/160B) */
2205
+
struct hwrm_func_cfg_input {
2206
+
__le16 req_type;
2207
+
__le16 cmpl_ring;
2208
+
__le16 seq_id;
2209
+
__le16 target_id;
2210
+
__le64 resp_addr;
2211
+
__le16 fid;
2212
+
__le16 num_msix;
2213
+
__le32 flags;
2214
+
#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
2215
+
#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
2216
+
#define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
2217
+
#define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
2218
+
#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
2219
+
#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
2220
+
#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
2221
+
#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
2222
+
#define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
2223
+
#define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
2224
+
#define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
2225
+
#define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
2226
+
#define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
2227
+
#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
2228
+
#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
2229
+
#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
2230
+
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
2231
+
#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
2232
+
#define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
2233
+
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
2234
+
#define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
2235
+
#define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL
2236
+
#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL
2237
+
#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL
2238
+
#define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL
2239
+
#define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL
2240
+
__le32 enables;
2241
+
#define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL
2242
+
#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
2243
+
#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
2244
+
#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
2245
+
#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
2246
+
#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
2247
+
#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
2248
+
#define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
2249
+
#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
2250
+
#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
2251
+
#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
2252
+
#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
2253
+
#define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
2254
+
#define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
2255
+
#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
2256
+
#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
2257
+
#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
2258
+
#define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
2259
+
#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
2260
+
#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
2261
+
#define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
2262
+
#define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
2263
+
#define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
2264
+
#define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
2265
+
#define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
2266
+
#define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
2267
+
#define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL
2268
+
#define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL
2269
+
#define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL
2270
+
#define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL
2271
+
#define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL
2272
+
#define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL
2273
+
__le16 admin_mtu;
2274
+
__le16 mru;
2275
+
__le16 num_rsscos_ctxs;
2276
+
__le16 num_cmpl_rings;
2277
+
__le16 num_tx_rings;
2278
+
__le16 num_rx_rings;
2279
+
__le16 num_l2_ctxs;
2280
+
__le16 num_vnics;
2281
+
__le16 num_stat_ctxs;
2282
+
__le16 num_hw_ring_grps;
2283
+
u8 dflt_mac_addr[6];
2284
+
__le16 dflt_vlan;
2285
+
__be32 dflt_ip_addr[4];
2286
+
__le32 min_bw;
2287
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2288
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
2289
+
#define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
2290
+
#define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
2291
+
#define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
2292
+
#define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
2293
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2294
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
2295
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2296
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2297
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2298
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2299
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2300
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2301
+
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
2302
+
__le32 max_bw;
2303
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2304
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
2305
+
#define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
2306
+
#define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
2307
+
#define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
2308
+
#define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
2309
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2310
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
2311
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2312
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2313
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2314
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2315
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2316
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2317
+
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
2318
+
__le16 async_event_cr;
2319
+
u8 vlan_antispoof_mode;
2320
+
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
2321
+
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
2322
+
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
2323
+
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
2324
+
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
2325
+
u8 allowed_vlan_pris;
2326
+
u8 evb_mode;
2327
+
#define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
2328
+
#define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
2329
+
#define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
2330
+
#define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
2331
+
u8 options;
2332
+
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
2333
+
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
2334
+
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
2335
+
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
2336
+
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
2337
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
2338
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
2339
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
2340
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
2341
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
2342
+
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
2343
+
#define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
2344
+
#define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
2345
+
__le16 num_mcast_filters;
2346
+
__le16 schq_id;
2347
+
__le16 mpc_chnls;
2348
+
#define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL
2349
+
#define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL
2350
+
#define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL
2351
+
#define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL
2352
+
#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL
2353
+
#define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL
2354
+
#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL
2355
+
#define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
2356
+
#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
2357
+
#define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
2358
+
__le32 partition_min_bw;
2359
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2360
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0
2361
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL
2362
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
2363
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
2364
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
2365
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2366
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
2367
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2368
+
#define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
2369
+
__le32 partition_max_bw;
2370
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2371
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0
2372
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL
2373
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
2374
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
2375
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
2376
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2377
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
2378
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2379
+
#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
2380
+
__be16 tpid;
2381
+
__le16 host_mtu;
2382
+
__le32 flags2;
2383
+
#define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL
2384
+
#define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL
2385
+
__le32 enables2;
2386
+
#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
2387
+
#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
2388
+
#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL
2389
+
#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL
2390
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL
2391
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL
2392
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL
2393
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL
2394
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL
2395
+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL
2396
+
#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL
2397
+
#define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL
2398
+
#define FUNC_CFG_REQ_ENABLES2_PCIE_COMPLIANCE 0x1000UL
2399
+
u8 port_kdnet_mode;
2400
+
#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
2401
+
#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL
2402
+
#define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED
2403
+
u8 db_page_size;
2404
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL
2405
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL
2406
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL
2407
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL
2408
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL
2409
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL
2410
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL
2411
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL
2412
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL
2413
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL
2414
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL
2415
+
#define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
2416
+
__le16 physical_slot_number;
2417
+
__le32 num_ktls_tx_key_ctxs;
2418
+
__le32 num_ktls_rx_key_ctxs;
2419
+
__le32 num_quic_tx_key_ctxs;
2420
+
__le32 num_quic_rx_key_ctxs;
2421
+
__le32 roce_max_av_per_vf;
2422
+
__le32 roce_max_cq_per_vf;
2423
+
__le32 roce_max_mrw_per_vf;
2424
+
__le32 roce_max_qp_per_vf;
2425
+
__le32 roce_max_srq_per_vf;
2426
+
__le32 roce_max_gid_per_vf;
2427
+
__le16 xid_partition_cfg;
2428
+
#define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL
2429
+
#define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL
2430
+
u8 pcie_compliance;
2431
+
u8 unused_2;
2432
+
};
2433
+
2434
+
/* hwrm_func_cfg_output (size:128b/16B) */
2435
+
struct hwrm_func_cfg_output {
2436
+
__le16 error_code;
2437
+
__le16 req_type;
2438
+
__le16 seq_id;
2439
+
__le16 resp_len;
2440
+
u8 unused_0[7];
2441
+
u8 valid;
2442
+
};
2443
+
2444
+
/* hwrm_func_cfg_cmd_err (size:64b/8B) */
2445
+
struct hwrm_func_cfg_cmd_err {
2446
+
u8 code;
2447
+
#define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2448
+
#define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_OUT_OF_RANGE 0x1UL
2449
+
#define FUNC_CFG_CMD_ERR_CODE_NPAR_PARTITION_DOWN_FAILED 0x2UL
2450
+
#define FUNC_CFG_CMD_ERR_CODE_TPID_SET_DFLT_VLAN_NOT_SET 0x3UL
2451
+
#define FUNC_CFG_CMD_ERR_CODE_RES_ARRAY_ALLOC_FAILED 0x4UL
2452
+
#define FUNC_CFG_CMD_ERR_CODE_TX_RING_ASSET_TEST_FAILED 0x5UL
2453
+
#define FUNC_CFG_CMD_ERR_CODE_TX_RING_RES_UPDATE_FAILED 0x6UL
2454
+
#define FUNC_CFG_CMD_ERR_CODE_APPLY_MAX_BW_FAILED 0x7UL
2455
+
#define FUNC_CFG_CMD_ERR_CODE_ENABLE_EVB_FAILED 0x8UL
2456
+
#define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_ASSET_TEST_FAILED 0x9UL
2457
+
#define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_RES_UPDATE_FAILED 0xaUL
2458
+
#define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_ASSET_TEST_FAILED 0xbUL
2459
+
#define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_RES_UPDATE_FAILED 0xcUL
2460
+
#define FUNC_CFG_CMD_ERR_CODE_NQ_ASSET_TEST_FAILED 0xdUL
2461
+
#define FUNC_CFG_CMD_ERR_CODE_NQ_RES_UPDATE_FAILED 0xeUL
2462
+
#define FUNC_CFG_CMD_ERR_CODE_RX_RING_ASSET_TEST_FAILED 0xfUL
2463
+
#define FUNC_CFG_CMD_ERR_CODE_RX_RING_RES_UPDATE_FAILED 0x10UL
2464
+
#define FUNC_CFG_CMD_ERR_CODE_VNIC_ASSET_TEST_FAILED 0x11UL
2465
+
#define FUNC_CFG_CMD_ERR_CODE_VNIC_RES_UPDATE_FAILED 0x12UL
2466
+
#define FUNC_CFG_CMD_ERR_CODE_FAILED_TO_START_STATS_THREAD 0x13UL
2467
+
#define FUNC_CFG_CMD_ERR_CODE_RDMA_SRIOV_DISABLED 0x14UL
2468
+
#define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_DISABLED 0x15UL
2469
+
#define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_ASSET_TEST_FAILED 0x16UL
2470
+
#define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_RES_UPDATE_FAILED 0x17UL
2471
+
#define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_DISABLED 0x18UL
2472
+
#define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_ASSET_TEST_FAILED 0x19UL
2473
+
#define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_RES_UPDATE_FAILED 0x1aUL
2474
+
#define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_DISABLED 0x1bUL
2475
+
#define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_ASSET_TEST_FAILED 0x1cUL
2476
+
#define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_RES_UPDATE_FAILED 0x1dUL
2477
+
#define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_DISABLED 0x1eUL
2478
+
#define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_ASSET_TEST_FAILED 0x1fUL
2479
+
#define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED 0x20UL
2480
+
#define FUNC_CFG_CMD_ERR_CODE_INVALID_KDNET_MODE 0x21UL
2481
+
#define FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 0x22UL
2482
+
#define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL
2483
+
u8 unused_0[7];
2484
+
};
2485
+
2486
+
/* hwrm_func_qstats_input (size:192b/24B) */
2487
+
struct hwrm_func_qstats_input {
2488
+
__le16 req_type;
2489
+
__le16 cmpl_ring;
2490
+
__le16 seq_id;
2491
+
__le16 target_id;
2492
+
__le64 resp_addr;
2493
+
__le16 fid;
2494
+
u8 flags;
2495
+
#define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
2496
+
#define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
2497
+
#define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL
2498
+
u8 unused_0[5];
2499
+
};
2500
+
2501
+
/* hwrm_func_qstats_output (size:1408b/176B) */
2502
+
struct hwrm_func_qstats_output {
2503
+
__le16 error_code;
2504
+
__le16 req_type;
2505
+
__le16 seq_id;
2506
+
__le16 resp_len;
2507
+
__le64 tx_ucast_pkts;
2508
+
__le64 tx_mcast_pkts;
2509
+
__le64 tx_bcast_pkts;
2510
+
__le64 tx_discard_pkts;
2511
+
__le64 tx_drop_pkts;
2512
+
__le64 tx_ucast_bytes;
2513
+
__le64 tx_mcast_bytes;
2514
+
__le64 tx_bcast_bytes;
2515
+
__le64 rx_ucast_pkts;
2516
+
__le64 rx_mcast_pkts;
2517
+
__le64 rx_bcast_pkts;
2518
+
__le64 rx_discard_pkts;
2519
+
__le64 rx_drop_pkts;
2520
+
__le64 rx_ucast_bytes;
2521
+
__le64 rx_mcast_bytes;
2522
+
__le64 rx_bcast_bytes;
2523
+
__le64 rx_agg_pkts;
2524
+
__le64 rx_agg_bytes;
2525
+
__le64 rx_agg_events;
2526
+
__le64 rx_agg_aborts;
2527
+
u8 clear_seq;
2528
+
u8 unused_0[6];
2529
+
u8 valid;
2530
+
};
2531
+
2532
+
/* hwrm_func_qstats_ext_input (size:256b/32B) */
2533
+
struct hwrm_func_qstats_ext_input {
2534
+
__le16 req_type;
2535
+
__le16 cmpl_ring;
2536
+
__le16 seq_id;
2537
+
__le16 target_id;
2538
+
__le64 resp_addr;
2539
+
__le16 fid;
2540
+
u8 flags;
2541
+
#define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL
2542
+
#define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
2543
+
u8 unused_0[1];
2544
+
__le32 enables;
2545
+
#define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL
2546
+
__le16 schq_id;
2547
+
__le16 traffic_class;
2548
+
u8 unused_1[4];
2549
+
};
2550
+
2551
+
/* hwrm_func_qstats_ext_output (size:1536b/192B) */
2552
+
struct hwrm_func_qstats_ext_output {
2553
+
__le16 error_code;
2554
+
__le16 req_type;
2555
+
__le16 seq_id;
2556
+
__le16 resp_len;
2557
+
__le64 rx_ucast_pkts;
2558
+
__le64 rx_mcast_pkts;
2559
+
__le64 rx_bcast_pkts;
2560
+
__le64 rx_discard_pkts;
2561
+
__le64 rx_error_pkts;
2562
+
__le64 rx_ucast_bytes;
2563
+
__le64 rx_mcast_bytes;
2564
+
__le64 rx_bcast_bytes;
2565
+
__le64 tx_ucast_pkts;
2566
+
__le64 tx_mcast_pkts;
2567
+
__le64 tx_bcast_pkts;
2568
+
__le64 tx_error_pkts;
2569
+
__le64 tx_discard_pkts;
2570
+
__le64 tx_ucast_bytes;
2571
+
__le64 tx_mcast_bytes;
2572
+
__le64 tx_bcast_bytes;
2573
+
__le64 rx_tpa_eligible_pkt;
2574
+
__le64 rx_tpa_eligible_bytes;
2575
+
__le64 rx_tpa_pkt;
2576
+
__le64 rx_tpa_bytes;
2577
+
__le64 rx_tpa_errors;
2578
+
__le64 rx_tpa_events;
2579
+
u8 unused_0[7];
2580
+
u8 valid;
2581
+
};
2582
+
2583
+
/* hwrm_func_clr_stats_input (size:192b/24B) */
2584
+
struct hwrm_func_clr_stats_input {
2585
+
__le16 req_type;
2586
+
__le16 cmpl_ring;
2587
+
__le16 seq_id;
2588
+
__le16 target_id;
2589
+
__le64 resp_addr;
2590
+
__le16 fid;
2591
+
u8 unused_0[6];
2592
+
};
2593
+
2594
+
/* hwrm_func_clr_stats_output (size:128b/16B) */
2595
+
struct hwrm_func_clr_stats_output {
2596
+
__le16 error_code;
2597
+
__le16 req_type;
2598
+
__le16 seq_id;
2599
+
__le16 resp_len;
2600
+
u8 unused_0[7];
2601
+
u8 valid;
2602
+
};
2603
+
2604
+
/* hwrm_func_vf_resc_free_input (size:192b/24B) */
2605
+
struct hwrm_func_vf_resc_free_input {
2606
+
__le16 req_type;
2607
+
__le16 cmpl_ring;
2608
+
__le16 seq_id;
2609
+
__le16 target_id;
2610
+
__le64 resp_addr;
2611
+
__le16 vf_id;
2612
+
u8 unused_0[6];
2613
+
};
2614
+
2615
+
/* hwrm_func_vf_resc_free_output (size:128b/16B) */
2616
+
struct hwrm_func_vf_resc_free_output {
2617
+
__le16 error_code;
2618
+
__le16 req_type;
2619
+
__le16 seq_id;
2620
+
__le16 resp_len;
2621
+
u8 unused_0[7];
2622
+
u8 valid;
2623
+
};
2624
+
2625
+
/* hwrm_func_drv_rgtr_input (size:896b/112B) */
2626
+
struct hwrm_func_drv_rgtr_input {
2627
+
__le16 req_type;
2628
+
__le16 cmpl_ring;
2629
+
__le16 seq_id;
2630
+
__le16 target_id;
2631
+
__le64 resp_addr;
2632
+
__le32 flags;
2633
+
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
2634
+
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
2635
+
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
2636
+
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
2637
+
#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
2638
+
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
2639
+
#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
2640
+
#define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL
2641
+
#define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL
2642
+
#define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL
2643
+
#define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL
2644
+
#define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL
2645
+
#define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE 0x1000UL
2646
+
__le32 enables;
2647
+
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
2648
+
#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
2649
+
#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
2650
+
#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
2651
+
#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
2652
+
__le16 os_type;
2653
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
2654
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
2655
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
2656
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
2657
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
2658
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
2659
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
2660
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
2661
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
2662
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
2663
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
2664
+
#define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
2665
+
u8 ver_maj_8b;
2666
+
u8 ver_min_8b;
2667
+
u8 ver_upd_8b;
2668
+
u8 unused_0[3];
2669
+
__le32 timestamp;
2670
+
u8 unused_1[4];
2671
+
__le32 vf_req_fwd[8];
2672
+
__le32 async_event_fwd[8];
2673
+
__le16 ver_maj;
2674
+
__le16 ver_min;
2675
+
__le16 ver_upd;
2676
+
__le16 ver_patch;
2677
+
};
2678
+
2679
+
/* hwrm_func_drv_rgtr_output (size:128b/16B) */
2680
+
struct hwrm_func_drv_rgtr_output {
2681
+
__le16 error_code;
2682
+
__le16 req_type;
2683
+
__le16 seq_id;
2684
+
__le16 resp_len;
2685
+
__le32 flags;
2686
+
#define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
2687
+
u8 unused_0[3];
2688
+
u8 valid;
2689
+
};
2690
+
2691
+
/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
2692
+
struct hwrm_func_drv_unrgtr_input {
2693
+
__le16 req_type;
2694
+
__le16 cmpl_ring;
2695
+
__le16 seq_id;
2696
+
__le16 target_id;
2697
+
__le64 resp_addr;
2698
+
__le32 flags;
2699
+
#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
2700
+
u8 unused_0[4];
2701
+
};
2702
+
2703
+
/* hwrm_func_drv_unrgtr_output (size:128b/16B) */
2704
+
struct hwrm_func_drv_unrgtr_output {
2705
+
__le16 error_code;
2706
+
__le16 req_type;
2707
+
__le16 seq_id;
2708
+
__le16 resp_len;
2709
+
u8 unused_0[7];
2710
+
u8 valid;
2711
+
};
2712
+
2713
+
/* hwrm_func_buf_rgtr_input (size:1024b/128B) */
2714
+
struct hwrm_func_buf_rgtr_input {
2715
+
__le16 req_type;
2716
+
__le16 cmpl_ring;
2717
+
__le16 seq_id;
2718
+
__le16 target_id;
2719
+
__le64 resp_addr;
2720
+
__le32 enables;
2721
+
#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
2722
+
#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
2723
+
__le16 vf_id;
2724
+
__le16 req_buf_num_pages;
2725
+
__le16 req_buf_page_size;
2726
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
2727
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
2728
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
2729
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
2730
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
2731
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
2732
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
2733
+
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
2734
+
__le16 req_buf_len;
2735
+
__le16 resp_buf_len;
2736
+
u8 unused_0[2];
2737
+
__le64 req_buf_page_addr0;
2738
+
__le64 req_buf_page_addr1;
2739
+
__le64 req_buf_page_addr2;
2740
+
__le64 req_buf_page_addr3;
2741
+
__le64 req_buf_page_addr4;
2742
+
__le64 req_buf_page_addr5;
2743
+
__le64 req_buf_page_addr6;
2744
+
__le64 req_buf_page_addr7;
2745
+
__le64 req_buf_page_addr8;
2746
+
__le64 req_buf_page_addr9;
2747
+
__le64 error_buf_addr;
2748
+
__le64 resp_buf_addr;
2749
+
};
2750
+
2751
+
/* hwrm_func_buf_rgtr_output (size:128b/16B) */
2752
+
struct hwrm_func_buf_rgtr_output {
2753
+
__le16 error_code;
2754
+
__le16 req_type;
2755
+
__le16 seq_id;
2756
+
__le16 resp_len;
2757
+
u8 unused_0[7];
2758
+
u8 valid;
2759
+
};
2760
+
2761
+
/* hwrm_func_drv_qver_input (size:192b/24B) */
2762
+
struct hwrm_func_drv_qver_input {
2763
+
__le16 req_type;
2764
+
__le16 cmpl_ring;
2765
+
__le16 seq_id;
2766
+
__le16 target_id;
2767
+
__le64 resp_addr;
2768
+
__le32 reserved;
2769
+
__le16 fid;
2770
+
u8 driver_type;
2771
+
#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL
2772
+
#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL
2773
+
#define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE
2774
+
u8 unused_0;
2775
+
};
2776
+
2777
+
/* hwrm_func_drv_qver_output (size:256b/32B) */
2778
+
struct hwrm_func_drv_qver_output {
2779
+
__le16 error_code;
2780
+
__le16 req_type;
2781
+
__le16 seq_id;
2782
+
__le16 resp_len;
2783
+
__le16 os_type;
2784
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
2785
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
2786
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
2787
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
2788
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
2789
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
2790
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
2791
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
2792
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
2793
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
2794
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
2795
+
#define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
2796
+
u8 ver_maj_8b;
2797
+
u8 ver_min_8b;
2798
+
u8 ver_upd_8b;
2799
+
u8 unused_0[3];
2800
+
__le16 ver_maj;
2801
+
__le16 ver_min;
2802
+
__le16 ver_upd;
2803
+
__le16 ver_patch;
2804
+
u8 unused_1[7];
2805
+
u8 valid;
2806
+
};
2807
+
2808
+
/* hwrm_func_resource_qcaps_input (size:192b/24B) */
2809
+
struct hwrm_func_resource_qcaps_input {
2810
+
__le16 req_type;
2811
+
__le16 cmpl_ring;
2812
+
__le16 seq_id;
2813
+
__le16 target_id;
2814
+
__le64 resp_addr;
2815
+
__le16 fid;
2816
+
u8 unused_0[6];
2817
+
};
2818
+
2819
+
/* hwrm_func_resource_qcaps_output (size:704b/88B) */
2820
+
struct hwrm_func_resource_qcaps_output {
2821
+
__le16 error_code;
2822
+
__le16 req_type;
2823
+
__le16 seq_id;
2824
+
__le16 resp_len;
2825
+
__le16 max_vfs;
2826
+
__le16 max_msix;
2827
+
__le16 vf_reservation_strategy;
2828
+
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
2829
+
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
2830
+
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
2831
+
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
2832
+
__le16 min_rsscos_ctx;
2833
+
__le16 max_rsscos_ctx;
2834
+
__le16 min_cmpl_rings;
2835
+
__le16 max_cmpl_rings;
2836
+
__le16 min_tx_rings;
2837
+
__le16 max_tx_rings;
2838
+
__le16 min_rx_rings;
2839
+
__le16 max_rx_rings;
2840
+
__le16 min_l2_ctxs;
2841
+
__le16 max_l2_ctxs;
2842
+
__le16 min_vnics;
2843
+
__le16 max_vnics;
2844
+
__le16 min_stat_ctx;
2845
+
__le16 max_stat_ctx;
2846
+
__le16 min_hw_ring_grps;
2847
+
__le16 max_hw_ring_grps;
2848
+
__le16 max_tx_scheduler_inputs;
2849
+
__le16 flags;
2850
+
#define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
2851
+
__le16 min_msix;
2852
+
__le32 min_ktls_tx_key_ctxs;
2853
+
__le32 max_ktls_tx_key_ctxs;
2854
+
__le32 min_ktls_rx_key_ctxs;
2855
+
__le32 max_ktls_rx_key_ctxs;
2856
+
__le32 min_quic_tx_key_ctxs;
2857
+
__le32 max_quic_tx_key_ctxs;
2858
+
__le32 min_quic_rx_key_ctxs;
2859
+
__le32 max_quic_rx_key_ctxs;
2860
+
u8 unused_0[3];
2861
+
u8 valid;
2862
+
};
2863
+
2864
+
/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */
2865
+
struct hwrm_func_vf_resource_cfg_input {
2866
+
__le16 req_type;
2867
+
__le16 cmpl_ring;
2868
+
__le16 seq_id;
2869
+
__le16 target_id;
2870
+
__le64 resp_addr;
2871
+
__le16 vf_id;
2872
+
__le16 max_msix;
2873
+
__le16 min_rsscos_ctx;
2874
+
__le16 max_rsscos_ctx;
2875
+
__le16 min_cmpl_rings;
2876
+
__le16 max_cmpl_rings;
2877
+
__le16 min_tx_rings;
2878
+
__le16 max_tx_rings;
2879
+
__le16 min_rx_rings;
2880
+
__le16 max_rx_rings;
2881
+
__le16 min_l2_ctxs;
2882
+
__le16 max_l2_ctxs;
2883
+
__le16 min_vnics;
2884
+
__le16 max_vnics;
2885
+
__le16 min_stat_ctx;
2886
+
__le16 max_stat_ctx;
2887
+
__le16 min_hw_ring_grps;
2888
+
__le16 max_hw_ring_grps;
2889
+
__le16 flags;
2890
+
#define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
2891
+
__le16 min_msix;
2892
+
__le32 min_ktls_tx_key_ctxs;
2893
+
__le32 max_ktls_tx_key_ctxs;
2894
+
__le32 min_ktls_rx_key_ctxs;
2895
+
__le32 max_ktls_rx_key_ctxs;
2896
+
__le32 min_quic_tx_key_ctxs;
2897
+
__le32 max_quic_tx_key_ctxs;
2898
+
__le32 min_quic_rx_key_ctxs;
2899
+
__le32 max_quic_rx_key_ctxs;
2900
+
};
2901
+
2902
+
/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */
2903
+
struct hwrm_func_vf_resource_cfg_output {
2904
+
__le16 error_code;
2905
+
__le16 req_type;
2906
+
__le16 seq_id;
2907
+
__le16 resp_len;
2908
+
__le16 reserved_rsscos_ctx;
2909
+
__le16 reserved_cmpl_rings;
2910
+
__le16 reserved_tx_rings;
2911
+
__le16 reserved_rx_rings;
2912
+
__le16 reserved_l2_ctxs;
2913
+
__le16 reserved_vnics;
2914
+
__le16 reserved_stat_ctx;
2915
+
__le16 reserved_hw_ring_grps;
2916
+
__le32 reserved_ktls_tx_key_ctxs;
2917
+
__le32 reserved_ktls_rx_key_ctxs;
2918
+
__le32 reserved_quic_tx_key_ctxs;
2919
+
__le32 reserved_quic_rx_key_ctxs;
2920
+
u8 unused_0[7];
2921
+
u8 valid;
2922
+
};
2923
+
2924
+
/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2925
+
struct hwrm_func_backing_store_qcaps_input {
2926
+
__le16 req_type;
2927
+
__le16 cmpl_ring;
2928
+
__le16 seq_id;
2929
+
__le16 target_id;
2930
+
__le64 resp_addr;
2931
+
};
2932
+
2933
+
/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
2934
+
struct hwrm_func_backing_store_qcaps_output {
2935
+
__le16 error_code;
2936
+
__le16 req_type;
2937
+
__le16 seq_id;
2938
+
__le16 resp_len;
2939
+
__le32 qp_max_entries;
2940
+
__le16 qp_min_qp1_entries;
2941
+
__le16 qp_max_l2_entries;
2942
+
__le16 qp_entry_size;
2943
+
__le16 srq_max_l2_entries;
2944
+
__le32 srq_max_entries;
2945
+
__le16 srq_entry_size;
2946
+
__le16 cq_max_l2_entries;
2947
+
__le32 cq_max_entries;
2948
+
__le16 cq_entry_size;
2949
+
__le16 vnic_max_vnic_entries;
2950
+
__le16 vnic_max_ring_table_entries;
2951
+
__le16 vnic_entry_size;
2952
+
__le32 stat_max_entries;
2953
+
__le16 stat_entry_size;
2954
+
__le16 tqm_entry_size;
2955
+
__le32 tqm_min_entries_per_ring;
2956
+
__le32 tqm_max_entries_per_ring;
2957
+
__le32 mrav_max_entries;
2958
+
__le16 mrav_entry_size;
2959
+
__le16 tim_entry_size;
2960
+
__le32 tim_max_entries;
2961
+
__le16 mrav_num_entries_units;
2962
+
u8 tqm_entries_multiple;
2963
+
u8 ctx_kind_initializer;
2964
+
__le16 ctx_init_mask;
2965
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL
2966
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL
2967
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL
2968
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL
2969
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL
2970
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL
2971
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL
2972
+
#define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL
2973
+
u8 qp_init_offset;
2974
+
u8 srq_init_offset;
2975
+
u8 cq_init_offset;
2976
+
u8 vnic_init_offset;
2977
+
u8 tqm_fp_rings_count;
2978
+
u8 stat_init_offset;
2979
+
u8 mrav_init_offset;
2980
+
u8 tqm_fp_rings_count_ext;
2981
+
u8 tkc_init_offset;
2982
+
u8 rkc_init_offset;
2983
+
__le16 tkc_entry_size;
2984
+
__le16 rkc_entry_size;
2985
+
__le32 tkc_max_entries;
2986
+
__le32 rkc_max_entries;
2987
+
__le16 fast_qpmd_qp_num_entries;
2988
+
u8 rsvd1[5];
2989
+
u8 valid;
2990
+
};
2991
+
2992
+
/* tqm_fp_ring_cfg (size:128b/16B) */
2993
+
struct tqm_fp_ring_cfg {
2994
+
u8 tqm_ring_pg_size_tqm_ring_lvl;
2995
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL
2996
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
2997
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL
2998
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL
2999
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL
3000
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
3001
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL
3002
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
3003
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3004
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3005
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3006
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3007
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3008
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3009
+
#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
3010
+
u8 unused[3];
3011
+
__le32 tqm_ring_num_entries;
3012
+
__le64 tqm_ring_page_dir;
3013
+
};
3014
+
3015
+
/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
3016
+
struct hwrm_func_backing_store_cfg_input {
3017
+
__le16 req_type;
3018
+
__le16 cmpl_ring;
3019
+
__le16 seq_id;
3020
+
__le16 target_id;
3021
+
__le64 resp_addr;
3022
+
__le32 flags;
3023
+
#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
3024
+
#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
3025
+
__le32 enables;
3026
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
3027
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
3028
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
3029
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
3030
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
3031
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
3032
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
3033
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
3034
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
3035
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
3036
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
3037
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
3038
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
3039
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
3040
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
3041
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
3042
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL
3043
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL
3044
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL
3045
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL
3046
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL
3047
+
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL
3048
+
u8 qpc_pg_size_qpc_lvl;
3049
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
3050
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
3051
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
3052
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
3053
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
3054
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
3055
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
3056
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
3057
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
3058
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
3059
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
3060
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
3061
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
3062
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
3063
+
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
3064
+
u8 srq_pg_size_srq_lvl;
3065
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
3066
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
3067
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
3068
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
3069
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
3070
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
3071
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
3072
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
3073
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
3074
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
3075
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
3076
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
3077
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
3078
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
3079
+
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
3080
+
u8 cq_pg_size_cq_lvl;
3081
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
3082
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
3083
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
3084
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
3085
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
3086
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
3087
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
3088
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
3089
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
3090
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
3091
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
3092
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
3093
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
3094
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
3095
+
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
3096
+
u8 vnic_pg_size_vnic_lvl;
3097
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
3098
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
3099
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
3100
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
3101
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
3102
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
3103
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
3104
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
3105
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
3106
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
3107
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
3108
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
3109
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
3110
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
3111
+
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
3112
+
u8 stat_pg_size_stat_lvl;
3113
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
3114
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
3115
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
3116
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
3117
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
3118
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
3119
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
3120
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
3121
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
3122
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
3123
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
3124
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
3125
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
3126
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
3127
+
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
3128
+
u8 tqm_sp_pg_size_tqm_sp_lvl;
3129
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
3130
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
3131
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
3132
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
3133
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
3134
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
3135
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
3136
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
3137
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
3138
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
3139
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
3140
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
3141
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
3142
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
3143
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
3144
+
u8 tqm_ring0_pg_size_tqm_ring0_lvl;
3145
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
3146
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
3147
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
3148
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
3149
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
3150
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
3151
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
3152
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
3153
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
3154
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
3155
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
3156
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
3157
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
3158
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
3159
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
3160
+
u8 tqm_ring1_pg_size_tqm_ring1_lvl;
3161
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
3162
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
3163
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
3164
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
3165
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
3166
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
3167
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
3168
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
3169
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
3170
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
3171
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
3172
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
3173
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
3174
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
3175
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
3176
+
u8 tqm_ring2_pg_size_tqm_ring2_lvl;
3177
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
3178
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
3179
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
3180
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
3181
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
3182
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
3183
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
3184
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
3185
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
3186
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
3187
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
3188
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
3189
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
3190
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
3191
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
3192
+
u8 tqm_ring3_pg_size_tqm_ring3_lvl;
3193
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
3194
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
3195
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
3196
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
3197
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
3198
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
3199
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
3200
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
3201
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
3202
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
3203
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
3204
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
3205
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
3206
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
3207
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
3208
+
u8 tqm_ring4_pg_size_tqm_ring4_lvl;
3209
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
3210
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
3211
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
3212
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
3213
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
3214
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
3215
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
3216
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
3217
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
3218
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
3219
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
3220
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
3221
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
3222
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
3223
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
3224
+
u8 tqm_ring5_pg_size_tqm_ring5_lvl;
3225
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
3226
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
3227
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
3228
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
3229
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
3230
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
3231
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
3232
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
3233
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
3234
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
3235
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
3236
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
3237
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
3238
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
3239
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
3240
+
u8 tqm_ring6_pg_size_tqm_ring6_lvl;
3241
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
3242
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
3243
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
3244
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
3245
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
3246
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
3247
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
3248
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
3249
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
3250
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
3251
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
3252
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
3253
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
3254
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
3255
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
3256
+
u8 tqm_ring7_pg_size_tqm_ring7_lvl;
3257
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
3258
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
3259
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
3260
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
3261
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
3262
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
3263
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
3264
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
3265
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
3266
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
3267
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
3268
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
3269
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
3270
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
3271
+
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
3272
+
u8 mrav_pg_size_mrav_lvl;
3273
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
3274
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
3275
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
3276
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
3277
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
3278
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
3279
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
3280
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
3281
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
3282
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
3283
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
3284
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
3285
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
3286
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
3287
+
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
3288
+
u8 tim_pg_size_tim_lvl;
3289
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
3290
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
3291
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
3292
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
3293
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
3294
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
3295
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
3296
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
3297
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
3298
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
3299
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
3300
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
3301
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
3302
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
3303
+
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
3304
+
__le64 qpc_page_dir;
3305
+
__le64 srq_page_dir;
3306
+
__le64 cq_page_dir;
3307
+
__le64 vnic_page_dir;
3308
+
__le64 stat_page_dir;
3309
+
__le64 tqm_sp_page_dir;
3310
+
__le64 tqm_ring0_page_dir;
3311
+
__le64 tqm_ring1_page_dir;
3312
+
__le64 tqm_ring2_page_dir;
3313
+
__le64 tqm_ring3_page_dir;
3314
+
__le64 tqm_ring4_page_dir;
3315
+
__le64 tqm_ring5_page_dir;
3316
+
__le64 tqm_ring6_page_dir;
3317
+
__le64 tqm_ring7_page_dir;
3318
+
__le64 mrav_page_dir;
3319
+
__le64 tim_page_dir;
3320
+
__le32 qp_num_entries;
3321
+
__le32 srq_num_entries;
3322
+
__le32 cq_num_entries;
3323
+
__le32 stat_num_entries;
3324
+
__le32 tqm_sp_num_entries;
3325
+
__le32 tqm_ring0_num_entries;
3326
+
__le32 tqm_ring1_num_entries;
3327
+
__le32 tqm_ring2_num_entries;
3328
+
__le32 tqm_ring3_num_entries;
3329
+
__le32 tqm_ring4_num_entries;
3330
+
__le32 tqm_ring5_num_entries;
3331
+
__le32 tqm_ring6_num_entries;
3332
+
__le32 tqm_ring7_num_entries;
3333
+
__le32 mrav_num_entries;
3334
+
__le32 tim_num_entries;
3335
+
__le16 qp_num_qp1_entries;
3336
+
__le16 qp_num_l2_entries;
3337
+
__le16 qp_entry_size;
3338
+
__le16 srq_num_l2_entries;
3339
+
__le16 srq_entry_size;
3340
+
__le16 cq_num_l2_entries;
3341
+
__le16 cq_entry_size;
3342
+
__le16 vnic_num_vnic_entries;
3343
+
__le16 vnic_num_ring_table_entries;
3344
+
__le16 vnic_entry_size;
3345
+
__le16 stat_entry_size;
3346
+
__le16 tqm_entry_size;
3347
+
__le16 mrav_entry_size;
3348
+
__le16 tim_entry_size;
3349
+
u8 tqm_ring8_pg_size_tqm_ring_lvl;
3350
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL
3351
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0
3352
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL
3353
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL
3354
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL
3355
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2
3356
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL
3357
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4
3358
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3359
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3360
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3361
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3362
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3363
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3364
+
#define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G
3365
+
u8 ring8_unused[3];
3366
+
__le32 tqm_ring8_num_entries;
3367
+
__le64 tqm_ring8_page_dir;
3368
+
u8 tqm_ring9_pg_size_tqm_ring_lvl;
3369
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL
3370
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0
3371
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL
3372
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL
3373
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL
3374
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2
3375
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL
3376
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4
3377
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3378
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3379
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3380
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3381
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3382
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3383
+
#define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G
3384
+
u8 ring9_unused[3];
3385
+
__le32 tqm_ring9_num_entries;
3386
+
__le64 tqm_ring9_page_dir;
3387
+
u8 tqm_ring10_pg_size_tqm_ring_lvl;
3388
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL
3389
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0
3390
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL
3391
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL
3392
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL
3393
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2
3394
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL
3395
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4
3396
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3397
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3398
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3399
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3400
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3401
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3402
+
#define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G
3403
+
u8 ring10_unused[3];
3404
+
__le32 tqm_ring10_num_entries;
3405
+
__le64 tqm_ring10_page_dir;
3406
+
__le32 tkc_num_entries;
3407
+
__le32 rkc_num_entries;
3408
+
__le64 tkc_page_dir;
3409
+
__le64 rkc_page_dir;
3410
+
__le16 tkc_entry_size;
3411
+
__le16 rkc_entry_size;
3412
+
u8 tkc_pg_size_tkc_lvl;
3413
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL
3414
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0
3415
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL
3416
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL
3417
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL
3418
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
3419
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL
3420
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4
3421
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4)
3422
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4)
3423
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4)
3424
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4)
3425
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4)
3426
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4)
3427
+
#define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
3428
+
u8 rkc_pg_size_rkc_lvl;
3429
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL
3430
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0
3431
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL
3432
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL
3433
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL
3434
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
3435
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL
3436
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4
3437
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4)
3438
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4)
3439
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4)
3440
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4)
3441
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4)
3442
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4)
3443
+
#define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
3444
+
__le16 qp_num_fast_qpmd_entries;
3445
+
};
3446
+
3447
+
/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
3448
+
struct hwrm_func_backing_store_cfg_output {
3449
+
__le16 error_code;
3450
+
__le16 req_type;
3451
+
__le16 seq_id;
3452
+
__le16 resp_len;
3453
+
u8 unused_0[7];
3454
+
u8 valid;
3455
+
};
3456
+
3457
+
/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
3458
+
struct hwrm_error_recovery_qcfg_input {
3459
+
__le16 req_type;
3460
+
__le16 cmpl_ring;
3461
+
__le16 seq_id;
3462
+
__le16 target_id;
3463
+
__le64 resp_addr;
3464
+
u8 unused_0[8];
3465
+
};
3466
+
3467
+
/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
3468
+
struct hwrm_error_recovery_qcfg_output {
3469
+
__le16 error_code;
3470
+
__le16 req_type;
3471
+
__le16 seq_id;
3472
+
__le16 resp_len;
3473
+
__le32 flags;
3474
+
#define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
3475
+
#define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
3476
+
__le32 driver_polling_freq;
3477
+
__le32 master_func_wait_period;
3478
+
__le32 normal_func_wait_period;
3479
+
__le32 master_func_wait_period_after_reset;
3480
+
__le32 max_bailout_time_after_reset;
3481
+
__le32 fw_health_status_reg;
3482
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
3483
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
3484
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3485
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
3486
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
3487
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
3488
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
3489
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
3490
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
3491
+
__le32 fw_heartbeat_reg;
3492
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
3493
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
3494
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3495
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
3496
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
3497
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
3498
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
3499
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
3500
+
#define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
3501
+
__le32 fw_reset_cnt_reg;
3502
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
3503
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
3504
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3505
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
3506
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3507
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3508
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
3509
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
3510
+
#define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
3511
+
__le32 reset_inprogress_reg;
3512
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
3513
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
3514
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3515
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
3516
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
3517
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
3518
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
3519
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
3520
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
3521
+
__le32 reset_inprogress_reg_mask;
3522
+
u8 unused_0[3];
3523
+
u8 reg_array_cnt;
3524
+
__le32 reset_reg[16];
3525
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
3526
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
3527
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3528
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
3529
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
3530
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
3531
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
3532
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
3533
+
#define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
3534
+
__le32 reset_reg_val[16];
3535
+
u8 delay_after_reset[16];
3536
+
__le32 err_recovery_cnt_reg;
3537
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL
3538
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
3539
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3540
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL
3541
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3542
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3543
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
3544
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL
3545
+
#define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2
3546
+
u8 unused_1[3];
3547
+
u8 valid;
3548
+
};
3549
+
3550
+
/* hwrm_func_echo_response_input (size:192b/24B) */
3551
+
struct hwrm_func_echo_response_input {
3552
+
__le16 req_type;
3553
+
__le16 cmpl_ring;
3554
+
__le16 seq_id;
3555
+
__le16 target_id;
3556
+
__le64 resp_addr;
3557
+
__le32 event_data1;
3558
+
__le32 event_data2;
3559
+
};
3560
+
3561
+
/* hwrm_func_echo_response_output (size:128b/16B) */
3562
+
struct hwrm_func_echo_response_output {
3563
+
__le16 error_code;
3564
+
__le16 req_type;
3565
+
__le16 seq_id;
3566
+
__le16 resp_len;
3567
+
u8 unused_0[7];
3568
+
u8 valid;
3569
+
};
3570
+
3571
+
/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
3572
+
struct hwrm_func_ptp_pin_qcfg_input {
3573
+
__le16 req_type;
3574
+
__le16 cmpl_ring;
3575
+
__le16 seq_id;
3576
+
__le16 target_id;
3577
+
__le64 resp_addr;
3578
+
u8 unused_0[8];
3579
+
};
3580
+
3581
+
/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
3582
+
struct hwrm_func_ptp_pin_qcfg_output {
3583
+
__le16 error_code;
3584
+
__le16 req_type;
3585
+
__le16 seq_id;
3586
+
__le16 resp_len;
3587
+
u8 num_pins;
3588
+
u8 state;
3589
+
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL
3590
+
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL
3591
+
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL
3592
+
#define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL
3593
+
u8 pin0_usage;
3594
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL
3595
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL
3596
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL
3597
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL
3598
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
3599
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
3600
+
u8 pin1_usage;
3601
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL
3602
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL
3603
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL
3604
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL
3605
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
3606
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
3607
+
u8 pin2_usage;
3608
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL
3609
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL
3610
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL
3611
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL
3612
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL
3613
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3614
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3615
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3616
+
u8 pin3_usage;
3617
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL
3618
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL
3619
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL
3620
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL
3621
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL
3622
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3623
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3624
+
#define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3625
+
u8 unused_0;
3626
+
u8 valid;
3627
+
};
3628
+
3629
+
/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
3630
+
struct hwrm_func_ptp_pin_cfg_input {
3631
+
__le16 req_type;
3632
+
__le16 cmpl_ring;
3633
+
__le16 seq_id;
3634
+
__le16 target_id;
3635
+
__le64 resp_addr;
3636
+
__le32 enables;
3637
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL
3638
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL
3639
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL
3640
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL
3641
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL
3642
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL
3643
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL
3644
+
#define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL
3645
+
u8 pin0_state;
3646
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
3647
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL
3648
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
3649
+
u8 pin0_usage;
3650
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL
3651
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL
3652
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL
3653
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL
3654
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
3655
+
#define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
3656
+
u8 pin1_state;
3657
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
3658
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL
3659
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
3660
+
u8 pin1_usage;
3661
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL
3662
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL
3663
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL
3664
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL
3665
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
3666
+
#define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
3667
+
u8 pin2_state;
3668
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
3669
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL
3670
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
3671
+
u8 pin2_usage;
3672
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL
3673
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL
3674
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL
3675
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL
3676
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL
3677
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3678
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3679
+
#define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3680
+
u8 pin3_state;
3681
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
3682
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL
3683
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
3684
+
u8 pin3_usage;
3685
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL
3686
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL
3687
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL
3688
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL
3689
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL
3690
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3691
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3692
+
#define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3693
+
u8 unused_0[4];
3694
+
};
3695
+
3696
+
/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
3697
+
struct hwrm_func_ptp_pin_cfg_output {
3698
+
__le16 error_code;
3699
+
__le16 req_type;
3700
+
__le16 seq_id;
3701
+
__le16 resp_len;
3702
+
u8 unused_0[7];
3703
+
u8 valid;
3704
+
};
3705
+
3706
+
/* hwrm_func_ptp_cfg_input (size:384b/48B) */
3707
+
struct hwrm_func_ptp_cfg_input {
3708
+
__le16 req_type;
3709
+
__le16 cmpl_ring;
3710
+
__le16 seq_id;
3711
+
__le16 target_id;
3712
+
__le64 resp_addr;
3713
+
__le16 enables;
3714
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL
3715
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL
3716
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL
3717
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL
3718
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL
3719
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL
3720
+
#define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL
3721
+
u8 ptp_pps_event;
3722
+
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL
3723
+
#define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL
3724
+
u8 ptp_freq_adj_dll_source;
3725
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL
3726
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL
3727
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL
3728
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL
3729
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL
3730
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL
3731
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL
3732
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL
3733
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL
3734
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
3735
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
3736
+
u8 ptp_freq_adj_dll_phase;
3737
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
3738
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL
3739
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL
3740
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL
3741
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL
3742
+
#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M
3743
+
u8 unused_0[3];
3744
+
__le32 ptp_freq_adj_ext_period;
3745
+
__le32 ptp_freq_adj_ext_up;
3746
+
__le32 ptp_freq_adj_ext_phase_lower;
3747
+
__le32 ptp_freq_adj_ext_phase_upper;
3748
+
__le64 ptp_set_time;
3749
+
};
3750
+
3751
+
/* hwrm_func_ptp_cfg_output (size:128b/16B) */
3752
+
struct hwrm_func_ptp_cfg_output {
3753
+
__le16 error_code;
3754
+
__le16 req_type;
3755
+
__le16 seq_id;
3756
+
__le16 resp_len;
3757
+
u8 unused_0[7];
3758
+
u8 valid;
3759
+
};
3760
+
3761
+
/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
3762
+
struct hwrm_func_ptp_ts_query_input {
3763
+
__le16 req_type;
3764
+
__le16 cmpl_ring;
3765
+
__le16 seq_id;
3766
+
__le16 target_id;
3767
+
__le64 resp_addr;
3768
+
__le32 flags;
3769
+
#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL
3770
+
#define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL
3771
+
u8 unused_0[4];
3772
+
};
3773
+
3774
+
/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
3775
+
struct hwrm_func_ptp_ts_query_output {
3776
+
__le16 error_code;
3777
+
__le16 req_type;
3778
+
__le16 seq_id;
3779
+
__le16 resp_len;
3780
+
__le64 pps_event_ts;
3781
+
__le64 ptm_local_ts;
3782
+
__le64 ptm_system_ts;
3783
+
__le32 ptm_link_delay;
3784
+
u8 unused_0[3];
3785
+
u8 valid;
3786
+
};
3787
+
3788
+
/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
3789
+
struct hwrm_func_ptp_ext_cfg_input {
3790
+
__le16 req_type;
3791
+
__le16 cmpl_ring;
3792
+
__le16 seq_id;
3793
+
__le16 target_id;
3794
+
__le64 resp_addr;
3795
+
__le16 enables;
3796
+
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL
3797
+
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL
3798
+
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL
3799
+
#define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL
3800
+
__le16 phc_master_fid;
3801
+
__le16 phc_sec_fid;
3802
+
u8 phc_sec_mode;
3803
+
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL
3804
+
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL
3805
+
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL
3806
+
#define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY
3807
+
u8 unused_0;
3808
+
__le32 failover_timer;
3809
+
u8 unused_1[4];
3810
+
};
3811
+
3812
+
/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
3813
+
struct hwrm_func_ptp_ext_cfg_output {
3814
+
__le16 error_code;
3815
+
__le16 req_type;
3816
+
__le16 seq_id;
3817
+
__le16 resp_len;
3818
+
u8 unused_0[7];
3819
+
u8 valid;
3820
+
};
3821
+
3822
+
/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
3823
+
struct hwrm_func_ptp_ext_qcfg_input {
3824
+
__le16 req_type;
3825
+
__le16 cmpl_ring;
3826
+
__le16 seq_id;
3827
+
__le16 target_id;
3828
+
__le64 resp_addr;
3829
+
u8 unused_0[8];
3830
+
};
3831
+
3832
+
/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
3833
+
struct hwrm_func_ptp_ext_qcfg_output {
3834
+
__le16 error_code;
3835
+
__le16 req_type;
3836
+
__le16 seq_id;
3837
+
__le16 resp_len;
3838
+
__le16 phc_master_fid;
3839
+
__le16 phc_sec_fid;
3840
+
__le16 phc_active_fid0;
3841
+
__le16 phc_active_fid1;
3842
+
__le32 last_failover_event;
3843
+
__le16 from_fid;
3844
+
__le16 to_fid;
3845
+
u8 unused_0[7];
3846
+
u8 valid;
3847
+
};
3848
+
3849
+
/* hwrm_func_ttx_pacing_rate_prof_query_input (size:192b/24B) */
3850
+
struct hwrm_func_ttx_pacing_rate_prof_query_input {
3851
+
__le16 req_type;
3852
+
__le16 cmpl_ring;
3853
+
__le16 seq_id;
3854
+
__le16 target_id;
3855
+
__le64 resp_addr;
3856
+
u8 unused_0[8];
3857
+
};
3858
+
3859
+
/* hwrm_func_ttx_pacing_rate_prof_query_output (size:128b/16B) */
3860
+
struct hwrm_func_ttx_pacing_rate_prof_query_output {
3861
+
__le16 error_code;
3862
+
__le16 req_type;
3863
+
__le16 seq_id;
3864
+
__le16 resp_len;
3865
+
u8 start_prof_id;
3866
+
u8 end_prof_id;
3867
+
u8 active_prof_id;
3868
+
#define FUNC_TTX_PACING_RATE_PROF_QUERY_RESP_60M 0x0UL
3869
+
#define FUNC_TTX_PACING_RATE_PROF_QUERY_RESP_50G 0x1UL
3870
+
#define FUNC_TTX_PACING_RATE_PROF_QUERY_RESP_LAST FUNC_TTX_PACING_RATE_PROF_QUERY_RESP_50G
3871
+
u8 unused_0[4];
3872
+
u8 valid;
3873
+
};
3874
+
3875
+
/* hwrm_func_ttx_pacing_rate_query_input (size:192b/24B) */
3876
+
struct hwrm_func_ttx_pacing_rate_query_input {
3877
+
__le16 req_type;
3878
+
__le16 cmpl_ring;
3879
+
__le16 seq_id;
3880
+
__le16 target_id;
3881
+
__le64 resp_addr;
3882
+
u8 profile_id;
3883
+
u8 unused_0[7];
3884
+
};
3885
+
3886
+
/* hwrm_func_ttx_pacing_rate_query_output (size:4224b/528B) */
3887
+
struct hwrm_func_ttx_pacing_rate_query_output {
3888
+
__le16 error_code;
3889
+
__le16 req_type;
3890
+
__le16 seq_id;
3891
+
__le16 resp_len;
3892
+
__le32 rates[128];
3893
+
u8 profile_id;
3894
+
u8 unused_0[6];
3895
+
u8 valid;
3896
+
};
3897
+
3898
+
/* hwrm_func_key_ctx_alloc_input (size:384b/48B) */
3899
+
struct hwrm_func_key_ctx_alloc_input {
3900
+
__le16 req_type;
3901
+
__le16 cmpl_ring;
3902
+
__le16 seq_id;
3903
+
__le16 target_id;
3904
+
__le64 resp_addr;
3905
+
__le16 fid;
3906
+
__le16 num_key_ctxs;
3907
+
__le32 dma_bufr_size_bytes;
3908
+
u8 key_ctx_type;
3909
+
#define FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_TX 0x0UL
3910
+
#define FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_RX 0x1UL
3911
+
#define FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_QUIC_TX 0x2UL
3912
+
#define FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_QUIC_RX 0x3UL
3913
+
#define FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_LAST FUNC_KEY_CTX_ALLOC_REQ_KEY_CTX_TYPE_QUIC_RX
3914
+
u8 unused_0[7];
3915
+
__le64 host_dma_addr;
3916
+
__le32 partition_start_xid;
3917
+
u8 unused_1[4];
3918
+
};
3919
+
3920
+
/* hwrm_func_key_ctx_alloc_output (size:192b/24B) */
3921
+
struct hwrm_func_key_ctx_alloc_output {
3922
+
__le16 error_code;
3923
+
__le16 req_type;
3924
+
__le16 seq_id;
3925
+
__le16 resp_len;
3926
+
__le16 num_key_ctxs_allocated;
3927
+
u8 flags;
3928
+
#define FUNC_KEY_CTX_ALLOC_RESP_FLAGS_KEY_CTXS_CONTIGUOUS 0x1UL
3929
+
u8 unused_0;
3930
+
__le32 partition_start_xid;
3931
+
u8 unused_1[7];
3932
+
u8 valid;
3933
+
};
3934
+
3935
+
/* hwrm_func_key_ctx_free_input (size:256b/32B) */
3936
+
struct hwrm_func_key_ctx_free_input {
3937
+
__le16 req_type;
3938
+
__le16 cmpl_ring;
3939
+
__le16 seq_id;
3940
+
__le16 target_id;
3941
+
__le64 resp_addr;
3942
+
__le16 fid;
3943
+
u8 key_ctx_type;
3944
+
#define FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_TX 0x0UL
3945
+
#define FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_RX 0x1UL
3946
+
#define FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_QUIC_TX 0x2UL
3947
+
#define FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_QUIC_RX 0x3UL
3948
+
#define FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_LAST FUNC_KEY_CTX_FREE_REQ_KEY_CTX_TYPE_QUIC_RX
3949
+
u8 unused_0;
3950
+
__le32 partition_start_xid;
3951
+
__le16 num_entries;
3952
+
u8 unused_1[6];
3953
+
};
3954
+
3955
+
/* hwrm_func_key_ctx_free_output (size:128b/16B) */
3956
+
struct hwrm_func_key_ctx_free_output {
3957
+
__le16 error_code;
3958
+
__le16 req_type;
3959
+
__le16 seq_id;
3960
+
__le16 resp_len;
3961
+
u8 rsvd0[7];
3962
+
u8 valid;
3963
+
};
3964
+
3965
+
/* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */
3966
+
struct hwrm_func_backing_store_cfg_v2_input {
3967
+
__le16 req_type;
3968
+
__le16 cmpl_ring;
3969
+
__le16 seq_id;
3970
+
__le16 target_id;
3971
+
__le64 resp_addr;
3972
+
__le16 type;
3973
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL
3974
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL
3975
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL
3976
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL
3977
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL
3978
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3979
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3980
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL
3981
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL
3982
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL
3983
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL
3984
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3985
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3986
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3987
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3988
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3989
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
3990
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL
3991
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL
3992
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL
3993
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL
3994
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL
3995
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL
3996
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL
3997
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL
3998
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL
3999
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE 0x26UL
4000
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
4001
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
4002
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
4003
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
4004
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL
4005
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_PNO_TQM_RING 0x2cUL
4006
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MPRT_TRACE 0x2dUL
4007
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RERT_TRACE 0x2eUL
4008
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MR 0x2fUL
4009
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AV 0x30UL
4010
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ 0x31UL
4011
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_IQM 0x32UL
4012
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MPC_MSG_TRACE 0x33UL
4013
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MPC_CMPL_TRACE 0x34UL
4014
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
4015
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
4016
+
__le16 instance;
4017
+
__le32 flags;
4018
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL
4019
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL
4020
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL
4021
+
__le64 page_dir;
4022
+
__le32 num_entries;
4023
+
__le16 entry_size;
4024
+
u8 page_size_pbl_level;
4025
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL
4026
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0
4027
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL
4028
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL
4029
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL
4030
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2
4031
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL
4032
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4
4033
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4)
4034
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4)
4035
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4)
4036
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4)
4037
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4)
4038
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4)
4039
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G
4040
+
u8 subtype_valid_cnt;
4041
+
__le32 split_entry_0;
4042
+
__le32 split_entry_1;
4043
+
__le32 split_entry_2;
4044
+
__le32 split_entry_3;
4045
+
__le32 enables;
4046
+
#define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL
4047
+
__le32 next_bs_offset;
4048
+
};
4049
+
4050
+
/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
4051
+
struct hwrm_func_backing_store_cfg_v2_output {
4052
+
__le16 error_code;
4053
+
__le16 req_type;
4054
+
__le16 seq_id;
4055
+
__le16 resp_len;
4056
+
u8 rsvd0[7];
4057
+
u8 valid;
4058
+
};
4059
+
4060
+
/* hwrm_func_backing_store_cfg_v2_cmd_err (size:64b/8B) */
4061
+
struct hwrm_func_backing_store_cfg_v2_cmd_err {
4062
+
u8 code;
4063
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_UNKNOWN 0x0UL
4064
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_QP_FAIL 0x1UL
4065
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_SRQ_FAIL 0x2UL
4066
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_CQ_FAIL 0x3UL
4067
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_VNIC_FAIL 0x4UL
4068
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_STAT_FAIL 0x5UL
4069
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TQM_SPR_FAIL 0x6UL
4070
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TQM_FPR_FAIL 0x7UL
4071
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_MRAV_FAIL 0x8UL
4072
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TIM_FAIL 0x9UL
4073
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_V2TRACE_FAIL 0xaUL
4074
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TXCK_FAIL 0xbUL
4075
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_RXCK_FAIL 0xcUL
4076
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_MPC_FAIL 0xdUL
4077
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_SHADOW_DB_FAIL 0xeUL
4078
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_XID_FAIL 0xfUL
4079
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TFC_FAIL 0x10UL
4080
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_TTXPACE_FAIL 0x11UL
4081
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_CDU_ENABLE_FAIL 0x12UL
4082
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_SCHQ_ALLOC_FAIL 0x13UL
4083
+
#define FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_LAST FUNC_BACKING_STORE_CFG_V2_CMD_ERR_CODE_SCHQ_ALLOC_FAIL
4084
+
u8 unused_0[7];
4085
+
};
4086
+
4087
+
/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
4088
+
struct hwrm_func_backing_store_qcfg_v2_input {
4089
+
__le16 req_type;
4090
+
__le16 cmpl_ring;
4091
+
__le16 seq_id;
4092
+
__le16 target_id;
4093
+
__le64 resp_addr;
4094
+
__le16 type;
4095
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL
4096
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL
4097
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL
4098
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL
4099
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL
4100
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
4101
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
4102
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL
4103
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL
4104
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL
4105
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL
4106
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
4107
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
4108
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
4109
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
4110
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
4111
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
4112
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL
4113
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL
4114
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL
4115
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL
4116
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL
4117
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL
4118
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL
4119
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL
4120
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL
4121
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE 0x26UL
4122
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
4123
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
4124
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
4125
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
4126
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL
4127
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_PNO_TQM_RING 0x2cUL
4128
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MPRT_TRACE 0x2dUL
4129
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RERT_TRACE 0x2eUL
4130
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MR 0x2fUL
4131
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AV 0x30UL
4132
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ 0x31UL
4133
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_IQM 0x32UL
4134
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MPC_MSG_TRACE 0x33UL
4135
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MPC_CMPL_TRACE 0x34UL
4136
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
4137
+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
4138
+
__le16 instance;
4139
+
u8 rsvd[4];
4140
+
};
4141
+
4142
+
/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
4143
+
struct hwrm_func_backing_store_qcfg_v2_output {
4144
+
__le16 error_code;
4145
+
__le16 req_type;
4146
+
__le16 seq_id;
4147
+
__le16 resp_len;
4148
+
__le16 type;
4149
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL
4150
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL
4151
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL
4152
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL
4153
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL
4154
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL
4155
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL
4156
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL
4157
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL
4158
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL
4159
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL
4160
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL
4161
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL
4162
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL
4163
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL
4164
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL
4165
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL
4166
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL
4167
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL
4168
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL
4169
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL
4170
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL
4171
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE 0x26UL
4172
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL
4173
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL
4174
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL
4175
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ERR_QPC_TRACE 0x2aUL
4176
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_PNO_TQM_RING 0x2cUL
4177
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MPRT_TRACE 0x2dUL
4178
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RERT_TRACE 0x2eUL
4179
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MR 0x2fUL
4180
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_AV 0x30UL
4181
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SQ 0x31UL
4182
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_IQM 0x32UL
4183
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MPC_MSG_TRACE 0x33UL
4184
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MPC_CMPL_TRACE 0x34UL
4185
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL
4186
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID
4187
+
__le16 instance;
4188
+
__le32 flags;
4189
+
__le64 page_dir;
4190
+
__le32 num_entries;
4191
+
u8 page_size_pbl_level;
4192
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL
4193
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0
4194
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL
4195
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL
4196
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL
4197
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2
4198
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL
4199
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4
4200
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4)
4201
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4)
4202
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4)
4203
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4)
4204
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4)
4205
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4)
4206
+
#define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G
4207
+
u8 subtype_valid_cnt;
4208
+
u8 rsvd[2];
4209
+
__le32 split_entry_0;
4210
+
__le32 split_entry_1;
4211
+
__le32 split_entry_2;
4212
+
__le32 split_entry_3;
4213
+
u8 rsvd2[7];
4214
+
u8 valid;
4215
+
};
4216
+
4217
+
/* qpc_split_entries (size:128b/16B) */
4218
+
struct qpc_split_entries {
4219
+
__le32 qp_num_l2_entries;
4220
+
__le32 qp_num_qp1_entries;
4221
+
__le32 qp_num_fast_qpmd_entries;
4222
+
__le32 rsvd;
4223
+
};
4224
+
4225
+
/* srq_split_entries (size:128b/16B) */
4226
+
struct srq_split_entries {
4227
+
__le32 srq_num_l2_entries;
4228
+
__le32 rsvd;
4229
+
__le32 rsvd2[2];
4230
+
};
4231
+
4232
+
/* cq_split_entries (size:128b/16B) */
4233
+
struct cq_split_entries {
4234
+
__le32 cq_num_l2_entries;
4235
+
__le32 rsvd;
4236
+
__le32 rsvd2[2];
4237
+
};
4238
+
4239
+
/* vnic_split_entries (size:128b/16B) */
4240
+
struct vnic_split_entries {
4241
+
__le32 vnic_num_vnic_entries;
4242
+
__le32 rsvd;
4243
+
__le32 rsvd2[2];
4244
+
};
4245
+
4246
+
/* mrav_split_entries (size:128b/16B) */
4247
+
struct mrav_split_entries {
4248
+
__le32 mrav_num_av_entries;
4249
+
__le32 rsvd;
4250
+
__le32 rsvd2[2];
4251
+
};
4252
+
4253
+
/* ts_split_entries (size:128b/16B) */
4254
+
struct ts_split_entries {
4255
+
__le32 region_num_entries;
4256
+
u8 tsid;
4257
+
u8 lkup_static_bkt_cnt_exp[2];
4258
+
u8 locked;
4259
+
__le32 rsvd2[2];
4260
+
};
4261
+
4262
+
/* ck_split_entries (size:128b/16B) */
4263
+
struct ck_split_entries {
4264
+
__le32 num_quic_entries;
4265
+
__le32 rsvd;
4266
+
__le32 rsvd2[2];
4267
+
};
4268
+
4269
+
/* mr_split_entries (size:128b/16B) */
4270
+
struct mr_split_entries {
4271
+
__le32 mr_num_entries;
4272
+
__le32 rsvd;
4273
+
__le32 rsvd2[2];
4274
+
};
4275
+
4276
+
/* av_split_entries (size:128b/16B) */
4277
+
struct av_split_entries {
4278
+
__le32 av_num_entries;
4279
+
__le32 rsvd;
4280
+
__le32 rsvd2[2];
4281
+
};
4282
+
4283
+
/* sq_split_entries (size:128b/16B) */
4284
+
struct sq_split_entries {
4285
+
__le32 sq_num_l2_entries;
4286
+
__le32 rsvd2;
4287
+
__le32 rsvd3[2];
4288
+
};
4289
+
4290
+
/* hwrm_func_backing_store_qcfg_v2_cmd_err (size:64b/8B) */
4291
+
struct hwrm_func_backing_store_qcfg_v2_cmd_err {
4292
+
u8 code;
4293
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_UNKNOWN 0x0UL
4294
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_SHDDB_FAIL 0x1UL
4295
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_XID_FAIL 0x2UL
4296
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_TXPAC_RING_FAIL 0x3UL
4297
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_INVALID_FIELD 0x4UL
4298
+
#define FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_LAST FUNC_BACKING_STORE_QCFG_V2_CMD_ERR_CODE_INVALID_FIELD
4299
+
u8 unused_0[7];
4300
+
};
4301
+
4302
+
/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
4303
+
struct hwrm_func_backing_store_qcaps_v2_input {
4304
+
__le16 req_type;
4305
+
__le16 cmpl_ring;
4306
+
__le16 seq_id;
4307
+
__le16 target_id;
4308
+
__le64 resp_addr;
4309
+
__le16 type;
4310
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL
4311
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL
4312
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL
4313
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL
4314
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL
4315
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL
4316
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL
4317
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL
4318
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL
4319
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL
4320
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL
4321
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL
4322
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
4323
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
4324
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
4325
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
4326
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL
4327
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL
4328
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL
4329
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL
4330
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL
4331
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL
4332
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL
4333
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL
4334
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL
4335
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL
4336
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE 0x26UL
4337
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL
4338
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL
4339
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
4340
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
4341
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL
4342
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_PNO_TQM_RING 0x2cUL
4343
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MPRT_TRACE 0x2dUL
4344
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RERT_TRACE 0x2eUL
4345
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MR 0x2fUL
4346
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AV 0x30UL
4347
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ 0x31UL
4348
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_IQM 0x32UL
4349
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MPC_MSG_TRACE 0x33UL
4350
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MPC_CMPL_TRACE 0x34UL
4351
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
4352
+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
4353
+
u8 rsvd[6];
4354
+
};
4355
+
4356
+
/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
4357
+
struct hwrm_func_backing_store_qcaps_v2_output {
4358
+
__le16 error_code;
4359
+
__le16 req_type;
4360
+
__le16 seq_id;
4361
+
__le16 resp_len;
4362
+
__le16 type;
4363
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL
4364
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL
4365
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL
4366
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL
4367
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL
4368
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL
4369
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL
4370
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL
4371
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL
4372
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL
4373
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL
4374
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL
4375
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL
4376
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL
4377
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL
4378
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL
4379
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL
4380
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL
4381
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL
4382
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL
4383
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL
4384
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL
4385
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL
4386
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL
4387
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL
4388
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL
4389
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE 0x26UL
4390
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL
4391
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL
4392
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL
4393
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
4394
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ERR_QPC_TRACE 0x2bUL
4395
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_PNO_TQM_RING 0x2cUL
4396
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MPRT_TRACE 0x2dUL
4397
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RERT_TRACE 0x2eUL
4398
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MR 0x2fUL
4399
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AV 0x30UL
4400
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ 0x31UL
4401
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_IQM 0x32UL
4402
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MPC_MSG_TRACE 0x33UL
4403
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MPC_CMPL_TRACE 0x34UL
4404
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
4405
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
4406
+
__le16 entry_size;
4407
+
__le32 flags;
4408
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL
4409
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL
4410
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL
4411
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL
4412
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL
4413
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL
4414
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL
4415
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_PHYSICAL_PBL_PREFERRED 0x80UL
4416
+
__le32 instance_bit_map;
4417
+
u8 ctx_init_value;
4418
+
u8 ctx_init_offset;
4419
+
u8 entry_multiple;
4420
+
u8 rsvd;
4421
+
__le32 max_num_entries;
4422
+
__le32 min_num_entries;
4423
+
__le16 next_valid_type;
4424
+
u8 subtype_valid_cnt;
4425
+
u8 exact_cnt_bit_map;
4426
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL
4427
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL
4428
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL
4429
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL
4430
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL
4431
+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4
4432
+
__le32 split_entry_0;
4433
+
__le32 split_entry_1;
4434
+
__le32 split_entry_2;
4435
+
__le32 split_entry_3;
4436
+
__le16 max_instance_count;
4437
+
u8 rsvd3;
4438
+
u8 valid;
4439
+
};
4440
+
4441
+
/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */
4442
+
struct hwrm_func_dbr_pacing_qcfg_input {
4443
+
__le16 req_type;
4444
+
__le16 cmpl_ring;
4445
+
__le16 seq_id;
4446
+
__le16 target_id;
4447
+
__le64 resp_addr;
4448
+
};
4449
+
4450
+
/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */
4451
+
struct hwrm_func_dbr_pacing_qcfg_output {
4452
+
__le16 error_code;
4453
+
__le16 req_type;
4454
+
__le16 seq_id;
4455
+
__le16 resp_len;
4456
+
u8 flags;
4457
+
#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL
4458
+
u8 unused_0[7];
4459
+
__le32 dbr_stat_db_fifo_reg;
4460
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL
4461
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0
4462
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL
4463
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL
4464
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL
4465
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL
4466
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1
4467
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL
4468
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2
4469
+
__le32 dbr_stat_db_fifo_reg_watermark_mask;
4470
+
u8 dbr_stat_db_fifo_reg_watermark_shift;
4471
+
u8 unused_1[3];
4472
+
__le32 dbr_stat_db_fifo_reg_fifo_room_mask;
4473
+
u8 dbr_stat_db_fifo_reg_fifo_room_shift;
4474
+
u8 unused_2[3];
4475
+
__le32 dbr_throttling_aeq_arm_reg;
4476
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL
4477
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0
4478
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL
4479
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL
4480
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL
4481
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL
4482
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1
4483
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL
4484
+
#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2
4485
+
u8 dbr_throttling_aeq_arm_reg_val;
4486
+
u8 unused_3[3];
4487
+
__le32 dbr_stat_db_max_fifo_depth;
4488
+
__le32 primary_nq_id;
4489
+
__le32 pacing_threshold;
4490
+
u8 unused_4[7];
4491
+
u8 valid;
4492
+
};
4493
+
4494
+
/* hwrm_func_drv_if_change_input (size:192b/24B) */
4495
+
struct hwrm_func_drv_if_change_input {
4496
+
__le16 req_type;
4497
+
__le16 cmpl_ring;
4498
+
__le16 seq_id;
4499
+
__le16 target_id;
4500
+
__le64 resp_addr;
4501
+
__le32 flags;
4502
+
#define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
4503
+
__le32 unused;
4504
+
};
4505
+
4506
+
/* hwrm_func_drv_if_change_output (size:128b/16B) */
4507
+
struct hwrm_func_drv_if_change_output {
4508
+
__le16 error_code;
4509
+
__le16 req_type;
4510
+
__le16 seq_id;
4511
+
__le16 resp_len;
4512
+
__le32 flags;
4513
+
#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
4514
+
#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
4515
+
#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL
4516
+
u8 unused_0[3];
4517
+
u8 valid;
4518
+
};
4519
+
4520
+
/* hwrm_port_phy_cfg_input (size:512b/64B) */
4521
+
struct hwrm_port_phy_cfg_input {
4522
+
__le16 req_type;
4523
+
__le16 cmpl_ring;
4524
+
__le16 seq_id;
4525
+
__le16 target_id;
4526
+
__le64 resp_addr;
4527
+
__le32 flags;
4528
+
#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
4529
+
#define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
4530
+
#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
4531
+
#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
4532
+
#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
4533
+
#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
4534
+
#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
4535
+
#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
4536
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
4537
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
4538
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
4539
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
4540
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
4541
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
4542
+
#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
4543
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
4544
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
4545
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
4546
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
4547
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
4548
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
4549
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
4550
+
#define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
4551
+
#define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_ENABLE 0x800000UL
4552
+
#define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_DISABLE 0x1000000UL
4553
+
#define PORT_PHY_CFG_REQ_FLAGS_PRECODING_ENABLE 0x2000000UL
4554
+
#define PORT_PHY_CFG_REQ_FLAGS_PRECODING_DISABLE 0x4000000UL
4555
+
__le32 enables;
4556
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
4557
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
4558
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
4559
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
4560
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
4561
+
#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
4562
+
#define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
4563
+
#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
4564
+
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
4565
+
#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
4566
+
#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
4567
+
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
4568
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
4569
+
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL
4570
+
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL
4571
+
__le16 port_id;
4572
+
__le16 force_link_speed;
4573
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
4574
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
4575
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
4576
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
4577
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
4578
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
4579
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
4580
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
4581
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
4582
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
4583
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
4584
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
4585
+
u8 auto_mode;
4586
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
4587
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
4588
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
4589
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
4590
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
4591
+
#define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
4592
+
u8 auto_duplex;
4593
+
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
4594
+
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
4595
+
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
4596
+
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
4597
+
u8 auto_pause;
4598
+
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
4599
+
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
4600
+
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
4601
+
u8 mgmt_flag;
4602
+
#define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL
4603
+
#define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL
4604
+
__le16 auto_link_speed;
4605
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
4606
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
4607
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
4608
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
4609
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
4610
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
4611
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
4612
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
4613
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
4614
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
4615
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
4616
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
4617
+
__le16 auto_link_speed_mask;
4618
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
4619
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
4620
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
4621
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
4622
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
4623
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
4624
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
4625
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
4626
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
4627
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
4628
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
4629
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
4630
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
4631
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
4632
+
u8 wirespeed;
4633
+
#define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
4634
+
#define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
4635
+
#define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
4636
+
u8 lpbk;
4637
+
#define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
4638
+
#define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
4639
+
#define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
4640
+
#define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
4641
+
#define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
4642
+
u8 force_pause;
4643
+
#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
4644
+
#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
4645
+
u8 unused_1;
4646
+
__le32 preemphasis;
4647
+
__le16 eee_link_speed_mask;
4648
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4649
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
4650
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4651
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
4652
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4653
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4654
+
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
4655
+
__le16 force_pam4_link_speed;
4656
+
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
4657
+
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
4658
+
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
4659
+
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
4660
+
__le32 tx_lpi_timer;
4661
+
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
4662
+
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
4663
+
__le16 auto_link_pam4_speed_mask;
4664
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
4665
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
4666
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
4667
+
__le16 force_link_speeds2;
4668
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL
4669
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL
4670
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL
4671
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL
4672
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
4673
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
4674
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
4675
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
4676
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
4677
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
4678
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
4679
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
4680
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
4681
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL
4682
+
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112
4683
+
__le16 auto_link_speeds2_mask;
4684
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL
4685
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL
4686
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL
4687
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL
4688
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL
4689
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL
4690
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL
4691
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL
4692
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL
4693
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL
4694
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL
4695
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL
4696
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL
4697
+
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL
4698
+
u8 unused_2[6];
4699
+
};
4700
+
4701
+
/* hwrm_port_phy_cfg_output (size:128b/16B) */
4702
+
struct hwrm_port_phy_cfg_output {
4703
+
__le16 error_code;
4704
+
__le16 req_type;
4705
+
__le16 seq_id;
4706
+
__le16 resp_len;
4707
+
u8 unused_0[7];
4708
+
u8 valid;
4709
+
};
4710
+
4711
+
/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
4712
+
struct hwrm_port_phy_cfg_cmd_err {
4713
+
u8 code;
4714
+
#define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
4715
+
#define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
4716
+
#define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
4717
+
#define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
4718
+
u8 unused_0[7];
4719
+
};
4720
+
4721
+
/* hwrm_port_phy_qcfg_input (size:192b/24B) */
4722
+
struct hwrm_port_phy_qcfg_input {
4723
+
__le16 req_type;
4724
+
__le16 cmpl_ring;
4725
+
__le16 seq_id;
4726
+
__le16 target_id;
4727
+
__le64 resp_addr;
4728
+
__le16 port_id;
4729
+
u8 unused_0[6];
4730
+
};
4731
+
4732
+
/* hwrm_port_phy_qcfg_output (size:832b/104B) */
4733
+
struct hwrm_port_phy_qcfg_output {
4734
+
__le16 error_code;
4735
+
__le16 req_type;
4736
+
__le16 seq_id;
4737
+
__le16 resp_len;
4738
+
u8 link;
4739
+
#define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
4740
+
#define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
4741
+
#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
4742
+
#define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
4743
+
u8 active_fec_signal_mode;
4744
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
4745
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
4746
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
4747
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
4748
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL
4749
+
#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
4750
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
4751
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
4752
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
4753
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
4754
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
4755
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
4756
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
4757
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
4758
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
4759
+
#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
4760
+
__le16 link_speed;
4761
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
4762
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
4763
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
4764
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
4765
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
4766
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
4767
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
4768
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
4769
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
4770
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
4771
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
4772
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL
4773
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL
4774
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
4775
+
#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
4776
+
u8 duplex_cfg;
4777
+
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
4778
+
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
4779
+
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
4780
+
u8 pause;
4781
+
#define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
4782
+
#define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
4783
+
__le16 support_speeds;
4784
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
4785
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
4786
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
4787
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
4788
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
4789
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
4790
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
4791
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
4792
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
4793
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
4794
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
4795
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
4796
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
4797
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
4798
+
__le16 force_link_speed;
4799
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
4800
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
4801
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
4802
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
4803
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
4804
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
4805
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
4806
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
4807
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
4808
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
4809
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
4810
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
4811
+
u8 auto_mode;
4812
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
4813
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
4814
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
4815
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
4816
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
4817
+
#define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
4818
+
u8 auto_pause;
4819
+
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
4820
+
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
4821
+
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
4822
+
__le16 auto_link_speed;
4823
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
4824
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
4825
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
4826
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
4827
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
4828
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
4829
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
4830
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
4831
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
4832
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
4833
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
4834
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
4835
+
__le16 auto_link_speed_mask;
4836
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
4837
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
4838
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
4839
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
4840
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
4841
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
4842
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
4843
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
4844
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
4845
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
4846
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
4847
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
4848
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
4849
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
4850
+
u8 wirespeed;
4851
+
#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
4852
+
#define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
4853
+
#define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
4854
+
u8 lpbk;
4855
+
#define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
4856
+
#define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
4857
+
#define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
4858
+
#define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
4859
+
#define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
4860
+
u8 force_pause;
4861
+
#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
4862
+
#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
4863
+
u8 module_status;
4864
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
4865
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
4866
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
4867
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
4868
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
4869
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
4870
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED 0x6UL
4871
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
4872
+
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
4873
+
__le32 preemphasis;
4874
+
u8 phy_maj;
4875
+
u8 phy_min;
4876
+
u8 phy_bld;
4877
+
u8 phy_type;
4878
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
4879
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
4880
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
4881
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
4882
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
4883
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
4884
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
4885
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
4886
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
4887
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
4888
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
4889
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
4890
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
4891
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
4892
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
4893
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
4894
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
4895
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
4896
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
4897
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
4898
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
4899
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
4900
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
4901
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
4902
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
4903
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
4904
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
4905
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
4906
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
4907
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
4908
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
4909
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
4910
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL
4911
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL
4912
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL
4913
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL
4914
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL
4915
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL
4916
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL
4917
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL
4918
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL
4919
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL
4920
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL
4921
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL
4922
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL
4923
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL
4924
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL
4925
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL
4926
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL
4927
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL
4928
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL
4929
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL
4930
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL
4931
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL
4932
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL
4933
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL
4934
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8 0x38UL
4935
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8 0x39UL
4936
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8 0x3aUL
4937
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL
4938
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL
4939
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL
4940
+
#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8
4941
+
u8 media_type;
4942
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4943
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
4944
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
4945
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
4946
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL
4947
+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE
4948
+
u8 xcvr_pkg_type;
4949
+
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
4950
+
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
4951
+
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
4952
+
u8 eee_config_phy_addr;
4953
+
#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
4954
+
#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
4955
+
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
4956
+
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
4957
+
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
4958
+
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
4959
+
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
4960
+
u8 parallel_detect;
4961
+
#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
4962
+
__le16 link_partner_adv_speeds;
4963
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
4964
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
4965
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
4966
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
4967
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
4968
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
4969
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
4970
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
4971
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
4972
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
4973
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
4974
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
4975
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
4976
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
4977
+
u8 link_partner_adv_auto_mode;
4978
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
4979
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
4980
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
4981
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
4982
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
4983
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
4984
+
u8 link_partner_adv_pause;
4985
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
4986
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
4987
+
__le16 adv_eee_link_speed_mask;
4988
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4989
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4990
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4991
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
4992
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4993
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4994
+
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
4995
+
__le16 link_partner_adv_eee_link_speed_mask;
4996
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4997
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4998
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4999
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
5000
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
5001
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
5002
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
5003
+
__le32 xcvr_identifier_type_tx_lpi_timer;
5004
+
#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
5005
+
#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
5006
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
5007
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
5008
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
5009
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
5010
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
5011
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
5012
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
5013
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24)
5014
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24)
5015
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24)
5016
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24)
5017
+
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP
5018
+
__le16 fec_cfg;
5019
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
5020
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
5021
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
5022
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
5023
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
5024
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
5025
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
5026
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
5027
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
5028
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
5029
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
5030
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
5031
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
5032
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
5033
+
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
5034
+
u8 duplex_state;
5035
+
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
5036
+
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
5037
+
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
5038
+
u8 option_flags;
5039
+
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
5040
+
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL
5041
+
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL
5042
+
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_LINK_TRAINING 0x8UL
5043
+
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_PRECODING 0x10UL
5044
+
char phy_vendor_name[16];
5045
+
char phy_vendor_partnumber[16];
5046
+
__le16 support_pam4_speeds;
5047
+
#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
5048
+
#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
5049
+
#define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
5050
+
__le16 force_pam4_link_speed;
5051
+
#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
5052
+
#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
5053
+
#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
5054
+
#define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
5055
+
__le16 auto_pam4_link_speed_mask;
5056
+
#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
5057
+
#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
5058
+
#define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
5059
+
u8 link_partner_pam4_adv_speeds;
5060
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
5061
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
5062
+
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
5063
+
u8 link_down_reason;
5064
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
5065
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL
5066
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED 0x4UL
5067
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT 0x8UL
5068
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST 0x10UL
5069
+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_TX_LASER_DISABLED 0x20UL
5070
+
__le16 support_speeds2;
5071
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL
5072
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL
5073
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL
5074
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL
5075
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL
5076
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL
5077
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL
5078
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL
5079
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL
5080
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL
5081
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL
5082
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL
5083
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL
5084
+
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL
5085
+
__le16 force_link_speeds2;
5086
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL
5087
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL
5088
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL
5089
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL
5090
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
5091
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
5092
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
5093
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
5094
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
5095
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
5096
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
5097
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
5098
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
5099
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL
5100
+
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112
5101
+
__le16 auto_link_speeds2;
5102
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL
5103
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL
5104
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL
5105
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL
5106
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL
5107
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL
5108
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL
5109
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL
5110
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL
5111
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL
5112
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL
5113
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL
5114
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL
5115
+
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL
5116
+
u8 active_lanes;
5117
+
u8 valid;
5118
+
};
5119
+
5120
+
/* hwrm_port_mac_cfg_input (size:448b/56B) */
5121
+
struct hwrm_port_mac_cfg_input {
5122
+
__le16 req_type;
5123
+
__le16 cmpl_ring;
5124
+
__le16 seq_id;
5125
+
__le16 target_id;
5126
+
__le64 resp_addr;
5127
+
__le32 flags;
5128
+
#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
5129
+
#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
5130
+
#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
5131
+
#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
5132
+
#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
5133
+
#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
5134
+
#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
5135
+
#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
5136
+
#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
5137
+
#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
5138
+
#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
5139
+
#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
5140
+
#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
5141
+
#define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
5142
+
#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL
5143
+
#define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL
5144
+
__le32 enables;
5145
+
#define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
5146
+
#define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
5147
+
#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
5148
+
#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
5149
+
#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
5150
+
#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
5151
+
#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
5152
+
#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
5153
+
#define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
5154
+
#define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL
5155
+
#define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL
5156
+
__le16 port_id;
5157
+
u8 ipg;
5158
+
u8 lpbk;
5159
+
#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
5160
+
#define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
5161
+
#define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
5162
+
#define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
5163
+
u8 vlan_pri2cos_map_pri;
5164
+
u8 reserved1;
5165
+
u8 tunnel_pri2cos_map_pri;
5166
+
u8 dscp2pri_map_pri;
5167
+
__le16 rx_ts_capture_ptp_msg_type;
5168
+
__le16 tx_ts_capture_ptp_msg_type;
5169
+
u8 cos_field_cfg;
5170
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
5171
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
5172
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
5173
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
5174
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
5175
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
5176
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
5177
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
5178
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
5179
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
5180
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
5181
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
5182
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
5183
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
5184
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
5185
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
5186
+
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
5187
+
u8 unused_0[3];
5188
+
__s32 ptp_freq_adj_ppb;
5189
+
u8 unused_1[3];
5190
+
u8 ptp_load_control;
5191
+
#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL
5192
+
#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL
5193
+
#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL
5194
+
#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT
5195
+
__s64 ptp_adj_phase;
5196
+
};
5197
+
5198
+
/* hwrm_port_mac_cfg_output (size:128b/16B) */
5199
+
struct hwrm_port_mac_cfg_output {
5200
+
__le16 error_code;
5201
+
__le16 req_type;
5202
+
__le16 seq_id;
5203
+
__le16 resp_len;
5204
+
__le16 mru;
5205
+
__le16 mtu;
5206
+
u8 ipg;
5207
+
u8 lpbk;
5208
+
#define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
5209
+
#define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
5210
+
#define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
5211
+
#define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
5212
+
u8 unused_0;
5213
+
u8 valid;
5214
+
};
5215
+
5216
+
/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
5217
+
struct hwrm_port_mac_ptp_qcfg_input {
5218
+
__le16 req_type;
5219
+
__le16 cmpl_ring;
5220
+
__le16 seq_id;
5221
+
__le16 target_id;
5222
+
__le64 resp_addr;
5223
+
__le16 port_id;
5224
+
u8 unused_0[6];
5225
+
};
5226
+
5227
+
/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
5228
+
struct hwrm_port_mac_ptp_qcfg_output {
5229
+
__le16 error_code;
5230
+
__le16 req_type;
5231
+
__le16 seq_id;
5232
+
__le16 resp_len;
5233
+
u8 flags;
5234
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
5235
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
5236
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
5237
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL
5238
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL
5239
+
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL
5240
+
u8 unused_0[3];
5241
+
__le32 rx_ts_reg_off_lower;
5242
+
__le32 rx_ts_reg_off_upper;
5243
+
__le32 rx_ts_reg_off_seq_id;
5244
+
__le32 rx_ts_reg_off_src_id_0;
5245
+
__le32 rx_ts_reg_off_src_id_1;
5246
+
__le32 rx_ts_reg_off_src_id_2;
5247
+
__le32 rx_ts_reg_off_domain_id;
5248
+
__le32 rx_ts_reg_off_fifo;
5249
+
__le32 rx_ts_reg_off_fifo_adv;
5250
+
__le32 rx_ts_reg_off_granularity;
5251
+
__le32 tx_ts_reg_off_lower;
5252
+
__le32 tx_ts_reg_off_upper;
5253
+
__le32 tx_ts_reg_off_seq_id;
5254
+
__le32 tx_ts_reg_off_fifo;
5255
+
__le32 tx_ts_reg_off_granularity;
5256
+
__le32 ts_ref_clock_reg_lower;
5257
+
__le32 ts_ref_clock_reg_upper;
5258
+
u8 unused_1[7];
5259
+
u8 valid;
5260
+
};
5261
+
5262
+
/* tx_port_stats (size:3264b/408B) */
5263
+
struct tx_port_stats {
5264
+
__le64 tx_64b_frames;
5265
+
__le64 tx_65b_127b_frames;
5266
+
__le64 tx_128b_255b_frames;
5267
+
__le64 tx_256b_511b_frames;
5268
+
__le64 tx_512b_1023b_frames;
5269
+
__le64 tx_1024b_1518b_frames;
5270
+
__le64 tx_good_vlan_frames;
5271
+
__le64 tx_1519b_2047b_frames;
5272
+
__le64 tx_2048b_4095b_frames;
5273
+
__le64 tx_4096b_9216b_frames;
5274
+
__le64 tx_9217b_16383b_frames;
5275
+
__le64 tx_good_frames;
5276
+
__le64 tx_total_frames;
5277
+
__le64 tx_ucast_frames;
5278
+
__le64 tx_mcast_frames;
5279
+
__le64 tx_bcast_frames;
5280
+
__le64 tx_pause_frames;
5281
+
__le64 tx_pfc_frames;
5282
+
__le64 tx_jabber_frames;
5283
+
__le64 tx_fcs_err_frames;
5284
+
__le64 tx_control_frames;
5285
+
__le64 tx_oversz_frames;
5286
+
__le64 tx_single_dfrl_frames;
5287
+
__le64 tx_multi_dfrl_frames;
5288
+
__le64 tx_single_coll_frames;
5289
+
__le64 tx_multi_coll_frames;
5290
+
__le64 tx_late_coll_frames;
5291
+
__le64 tx_excessive_coll_frames;
5292
+
__le64 tx_frag_frames;
5293
+
__le64 tx_err;
5294
+
__le64 tx_tagged_frames;
5295
+
__le64 tx_dbl_tagged_frames;
5296
+
__le64 tx_runt_frames;
5297
+
__le64 tx_fifo_underruns;
5298
+
__le64 tx_pfc_ena_frames_pri0;
5299
+
__le64 tx_pfc_ena_frames_pri1;
5300
+
__le64 tx_pfc_ena_frames_pri2;
5301
+
__le64 tx_pfc_ena_frames_pri3;
5302
+
__le64 tx_pfc_ena_frames_pri4;
5303
+
__le64 tx_pfc_ena_frames_pri5;
5304
+
__le64 tx_pfc_ena_frames_pri6;
5305
+
__le64 tx_pfc_ena_frames_pri7;
5306
+
__le64 tx_eee_lpi_events;
5307
+
__le64 tx_eee_lpi_duration;
5308
+
__le64 tx_llfc_logical_msgs;
5309
+
__le64 tx_hcfc_msgs;
5310
+
__le64 tx_total_collisions;
5311
+
__le64 tx_bytes;
5312
+
__le64 tx_xthol_frames;
5313
+
__le64 tx_stat_discard;
5314
+
__le64 tx_stat_error;
5315
+
};
5316
+
5317
+
/* rx_port_stats (size:4224b/528B) */
5318
+
struct rx_port_stats {
5319
+
__le64 rx_64b_frames;
5320
+
__le64 rx_65b_127b_frames;
5321
+
__le64 rx_128b_255b_frames;
5322
+
__le64 rx_256b_511b_frames;
5323
+
__le64 rx_512b_1023b_frames;
5324
+
__le64 rx_1024b_1518b_frames;
5325
+
__le64 rx_good_vlan_frames;
5326
+
__le64 rx_1519b_2047b_frames;
5327
+
__le64 rx_2048b_4095b_frames;
5328
+
__le64 rx_4096b_9216b_frames;
5329
+
__le64 rx_9217b_16383b_frames;
5330
+
__le64 rx_total_frames;
5331
+
__le64 rx_ucast_frames;
5332
+
__le64 rx_mcast_frames;
5333
+
__le64 rx_bcast_frames;
5334
+
__le64 rx_fcs_err_frames;
5335
+
__le64 rx_ctrl_frames;
5336
+
__le64 rx_pause_frames;
5337
+
__le64 rx_pfc_frames;
5338
+
__le64 rx_unsupported_opcode_frames;
5339
+
__le64 rx_unsupported_da_pausepfc_frames;
5340
+
__le64 rx_wrong_sa_frames;
5341
+
__le64 rx_align_err_frames;
5342
+
__le64 rx_oor_len_frames;
5343
+
__le64 rx_code_err_frames;
5344
+
__le64 rx_false_carrier_frames;
5345
+
__le64 rx_ovrsz_frames;
5346
+
__le64 rx_jbr_frames;
5347
+
__le64 rx_mtu_err_frames;
5348
+
__le64 rx_match_crc_frames;
5349
+
__le64 rx_promiscuous_frames;
5350
+
__le64 rx_tagged_frames;
5351
+
__le64 rx_double_tagged_frames;
5352
+
__le64 rx_trunc_frames;
5353
+
__le64 rx_good_frames;
5354
+
__le64 rx_pfc_xon2xoff_frames_pri0;
5355
+
__le64 rx_pfc_xon2xoff_frames_pri1;
5356
+
__le64 rx_pfc_xon2xoff_frames_pri2;
5357
+
__le64 rx_pfc_xon2xoff_frames_pri3;
5358
+
__le64 rx_pfc_xon2xoff_frames_pri4;
5359
+
__le64 rx_pfc_xon2xoff_frames_pri5;
5360
+
__le64 rx_pfc_xon2xoff_frames_pri6;
5361
+
__le64 rx_pfc_xon2xoff_frames_pri7;
5362
+
__le64 rx_pfc_ena_frames_pri0;
5363
+
__le64 rx_pfc_ena_frames_pri1;
5364
+
__le64 rx_pfc_ena_frames_pri2;
5365
+
__le64 rx_pfc_ena_frames_pri3;
5366
+
__le64 rx_pfc_ena_frames_pri4;
5367
+
__le64 rx_pfc_ena_frames_pri5;
5368
+
__le64 rx_pfc_ena_frames_pri6;
5369
+
__le64 rx_pfc_ena_frames_pri7;
5370
+
__le64 rx_sch_crc_err_frames;
5371
+
__le64 rx_undrsz_frames;
5372
+
__le64 rx_frag_frames;
5373
+
__le64 rx_eee_lpi_events;
5374
+
__le64 rx_eee_lpi_duration;
5375
+
__le64 rx_llfc_physical_msgs;
5376
+
__le64 rx_llfc_logical_msgs;
5377
+
__le64 rx_llfc_msgs_with_crc_err;
5378
+
__le64 rx_hcfc_msgs;
5379
+
__le64 rx_hcfc_msgs_with_crc_err;
5380
+
__le64 rx_bytes;
5381
+
__le64 rx_runt_bytes;
5382
+
__le64 rx_runt_frames;
5383
+
__le64 rx_stat_discard;
5384
+
__le64 rx_stat_err;
5385
+
};
5386
+
5387
+
/* hwrm_port_qstats_input (size:320b/40B) */
5388
+
struct hwrm_port_qstats_input {
5389
+
__le16 req_type;
5390
+
__le16 cmpl_ring;
5391
+
__le16 seq_id;
5392
+
__le16 target_id;
5393
+
__le64 resp_addr;
5394
+
__le16 port_id;
5395
+
u8 flags;
5396
+
#define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
5397
+
u8 unused_0[5];
5398
+
__le64 tx_stat_host_addr;
5399
+
__le64 rx_stat_host_addr;
5400
+
};
5401
+
5402
+
/* hwrm_port_qstats_output (size:128b/16B) */
5403
+
struct hwrm_port_qstats_output {
5404
+
__le16 error_code;
5405
+
__le16 req_type;
5406
+
__le16 seq_id;
5407
+
__le16 resp_len;
5408
+
__le16 tx_stat_size;
5409
+
__le16 rx_stat_size;
5410
+
u8 flags;
5411
+
#define PORT_QSTATS_RESP_FLAGS_CLEARED 0x1UL
5412
+
u8 unused_0[2];
5413
+
u8 valid;
5414
+
};
5415
+
5416
+
/* tx_port_stats_ext (size:2048b/256B) */
5417
+
struct tx_port_stats_ext {
5418
+
__le64 tx_bytes_cos0;
5419
+
__le64 tx_bytes_cos1;
5420
+
__le64 tx_bytes_cos2;
5421
+
__le64 tx_bytes_cos3;
5422
+
__le64 tx_bytes_cos4;
5423
+
__le64 tx_bytes_cos5;
5424
+
__le64 tx_bytes_cos6;
5425
+
__le64 tx_bytes_cos7;
5426
+
__le64 tx_packets_cos0;
5427
+
__le64 tx_packets_cos1;
5428
+
__le64 tx_packets_cos2;
5429
+
__le64 tx_packets_cos3;
5430
+
__le64 tx_packets_cos4;
5431
+
__le64 tx_packets_cos5;
5432
+
__le64 tx_packets_cos6;
5433
+
__le64 tx_packets_cos7;
5434
+
__le64 pfc_pri0_tx_duration_us;
5435
+
__le64 pfc_pri0_tx_transitions;
5436
+
__le64 pfc_pri1_tx_duration_us;
5437
+
__le64 pfc_pri1_tx_transitions;
5438
+
__le64 pfc_pri2_tx_duration_us;
5439
+
__le64 pfc_pri2_tx_transitions;
5440
+
__le64 pfc_pri3_tx_duration_us;
5441
+
__le64 pfc_pri3_tx_transitions;
5442
+
__le64 pfc_pri4_tx_duration_us;
5443
+
__le64 pfc_pri4_tx_transitions;
5444
+
__le64 pfc_pri5_tx_duration_us;
5445
+
__le64 pfc_pri5_tx_transitions;
5446
+
__le64 pfc_pri6_tx_duration_us;
5447
+
__le64 pfc_pri6_tx_transitions;
5448
+
__le64 pfc_pri7_tx_duration_us;
5449
+
__le64 pfc_pri7_tx_transitions;
5450
+
};
5451
+
5452
+
/* rx_port_stats_ext (size:3904b/488B) */
5453
+
struct rx_port_stats_ext {
5454
+
__le64 link_down_events;
5455
+
__le64 continuous_pause_events;
5456
+
__le64 resume_pause_events;
5457
+
__le64 continuous_roce_pause_events;
5458
+
__le64 resume_roce_pause_events;
5459
+
__le64 rx_bytes_cos0;
5460
+
__le64 rx_bytes_cos1;
5461
+
__le64 rx_bytes_cos2;
5462
+
__le64 rx_bytes_cos3;
5463
+
__le64 rx_bytes_cos4;
5464
+
__le64 rx_bytes_cos5;
5465
+
__le64 rx_bytes_cos6;
5466
+
__le64 rx_bytes_cos7;
5467
+
__le64 rx_packets_cos0;
5468
+
__le64 rx_packets_cos1;
5469
+
__le64 rx_packets_cos2;
5470
+
__le64 rx_packets_cos3;
5471
+
__le64 rx_packets_cos4;
5472
+
__le64 rx_packets_cos5;
5473
+
__le64 rx_packets_cos6;
5474
+
__le64 rx_packets_cos7;
5475
+
__le64 pfc_pri0_rx_duration_us;
5476
+
__le64 pfc_pri0_rx_transitions;
5477
+
__le64 pfc_pri1_rx_duration_us;
5478
+
__le64 pfc_pri1_rx_transitions;
5479
+
__le64 pfc_pri2_rx_duration_us;
5480
+
__le64 pfc_pri2_rx_transitions;
5481
+
__le64 pfc_pri3_rx_duration_us;
5482
+
__le64 pfc_pri3_rx_transitions;
5483
+
__le64 pfc_pri4_rx_duration_us;
5484
+
__le64 pfc_pri4_rx_transitions;
5485
+
__le64 pfc_pri5_rx_duration_us;
5486
+
__le64 pfc_pri5_rx_transitions;
5487
+
__le64 pfc_pri6_rx_duration_us;
5488
+
__le64 pfc_pri6_rx_transitions;
5489
+
__le64 pfc_pri7_rx_duration_us;
5490
+
__le64 pfc_pri7_rx_transitions;
5491
+
__le64 rx_bits;
5492
+
__le64 rx_buffer_passed_threshold;
5493
+
__le64 rx_pcs_symbol_err;
5494
+
__le64 rx_corrected_bits;
5495
+
__le64 rx_discard_bytes_cos0;
5496
+
__le64 rx_discard_bytes_cos1;
5497
+
__le64 rx_discard_bytes_cos2;
5498
+
__le64 rx_discard_bytes_cos3;
5499
+
__le64 rx_discard_bytes_cos4;
5500
+
__le64 rx_discard_bytes_cos5;
5501
+
__le64 rx_discard_bytes_cos6;
5502
+
__le64 rx_discard_bytes_cos7;
5503
+
__le64 rx_discard_packets_cos0;
5504
+
__le64 rx_discard_packets_cos1;
5505
+
__le64 rx_discard_packets_cos2;
5506
+
__le64 rx_discard_packets_cos3;
5507
+
__le64 rx_discard_packets_cos4;
5508
+
__le64 rx_discard_packets_cos5;
5509
+
__le64 rx_discard_packets_cos6;
5510
+
__le64 rx_discard_packets_cos7;
5511
+
__le64 rx_fec_corrected_blocks;
5512
+
__le64 rx_fec_uncorrectable_blocks;
5513
+
__le64 rx_filter_miss;
5514
+
__le64 rx_fec_symbol_err;
5515
+
};
5516
+
5517
+
/* hwrm_port_qstats_ext_input (size:320b/40B) */
5518
+
struct hwrm_port_qstats_ext_input {
5519
+
__le16 req_type;
5520
+
__le16 cmpl_ring;
5521
+
__le16 seq_id;
5522
+
__le16 target_id;
5523
+
__le64 resp_addr;
5524
+
__le16 port_id;
5525
+
__le16 tx_stat_size;
5526
+
__le16 rx_stat_size;
5527
+
u8 flags;
5528
+
#define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL
5529
+
u8 unused_0;
5530
+
__le64 tx_stat_host_addr;
5531
+
__le64 rx_stat_host_addr;
5532
+
};
5533
+
5534
+
/* hwrm_port_qstats_ext_output (size:128b/16B) */
5535
+
struct hwrm_port_qstats_ext_output {
5536
+
__le16 error_code;
5537
+
__le16 req_type;
5538
+
__le16 seq_id;
5539
+
__le16 resp_len;
5540
+
__le16 tx_stat_size;
5541
+
__le16 rx_stat_size;
5542
+
__le16 total_active_cos_queues;
5543
+
u8 flags;
5544
+
#define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
5545
+
#define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED 0x2UL
5546
+
u8 valid;
5547
+
};
5548
+
5549
+
/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
5550
+
struct hwrm_port_qstats_ext_pfc_wd_input {
5551
+
__le16 req_type;
5552
+
__le16 cmpl_ring;
5553
+
__le16 seq_id;
5554
+
__le16 target_id;
5555
+
__le64 resp_addr;
5556
+
__le16 port_id;
5557
+
__le16 pfc_wd_stat_size;
5558
+
u8 unused_0[4];
5559
+
__le64 pfc_wd_stat_host_addr;
5560
+
};
5561
+
5562
+
/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
5563
+
struct hwrm_port_qstats_ext_pfc_wd_output {
5564
+
__le16 error_code;
5565
+
__le16 req_type;
5566
+
__le16 seq_id;
5567
+
__le16 resp_len;
5568
+
__le16 pfc_wd_stat_size;
5569
+
u8 unused_0[5];
5570
+
u8 valid;
5571
+
};
5572
+
5573
+
/* hwrm_port_lpbk_qstats_input (size:256b/32B) */
5574
+
struct hwrm_port_lpbk_qstats_input {
5575
+
__le16 req_type;
5576
+
__le16 cmpl_ring;
5577
+
__le16 seq_id;
5578
+
__le16 target_id;
5579
+
__le64 resp_addr;
5580
+
__le16 lpbk_stat_size;
5581
+
u8 flags;
5582
+
#define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
5583
+
u8 unused_0[5];
5584
+
__le64 lpbk_stat_host_addr;
5585
+
};
5586
+
5587
+
/* hwrm_port_lpbk_qstats_output (size:128b/16B) */
5588
+
struct hwrm_port_lpbk_qstats_output {
5589
+
__le16 error_code;
5590
+
__le16 req_type;
5591
+
__le16 seq_id;
5592
+
__le16 resp_len;
5593
+
__le16 lpbk_stat_size;
5594
+
u8 unused_0[5];
5595
+
u8 valid;
5596
+
};
5597
+
5598
+
/* port_lpbk_stats (size:640b/80B) */
5599
+
struct port_lpbk_stats {
5600
+
__le64 lpbk_ucast_frames;
5601
+
__le64 lpbk_mcast_frames;
5602
+
__le64 lpbk_bcast_frames;
5603
+
__le64 lpbk_ucast_bytes;
5604
+
__le64 lpbk_mcast_bytes;
5605
+
__le64 lpbk_bcast_bytes;
5606
+
__le64 lpbk_tx_discards;
5607
+
__le64 lpbk_tx_errors;
5608
+
__le64 lpbk_rx_discards;
5609
+
__le64 lpbk_rx_errors;
5610
+
};
5611
+
5612
+
/* hwrm_port_ecn_qstats_input (size:256b/32B) */
5613
+
struct hwrm_port_ecn_qstats_input {
5614
+
__le16 req_type;
5615
+
__le16 cmpl_ring;
5616
+
__le16 seq_id;
5617
+
__le16 target_id;
5618
+
__le64 resp_addr;
5619
+
__le16 port_id;
5620
+
__le16 ecn_stat_buf_size;
5621
+
u8 flags;
5622
+
#define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
5623
+
u8 unused_0[3];
5624
+
__le64 ecn_stat_host_addr;
5625
+
};
5626
+
5627
+
/* hwrm_port_ecn_qstats_output (size:128b/16B) */
5628
+
struct hwrm_port_ecn_qstats_output {
5629
+
__le16 error_code;
5630
+
__le16 req_type;
5631
+
__le16 seq_id;
5632
+
__le16 resp_len;
5633
+
__le16 ecn_stat_buf_size;
5634
+
u8 mark_en;
5635
+
u8 unused_0[4];
5636
+
u8 valid;
5637
+
};
5638
+
5639
+
/* port_stats_ecn (size:512b/64B) */
5640
+
struct port_stats_ecn {
5641
+
__le64 mark_cnt_cos0;
5642
+
__le64 mark_cnt_cos1;
5643
+
__le64 mark_cnt_cos2;
5644
+
__le64 mark_cnt_cos3;
5645
+
__le64 mark_cnt_cos4;
5646
+
__le64 mark_cnt_cos5;
5647
+
__le64 mark_cnt_cos6;
5648
+
__le64 mark_cnt_cos7;
5649
+
};
5650
+
5651
+
/* port_stats_ext_pfc_adv (size:1536b/192B) */
5652
+
struct port_stats_ext_pfc_adv {
5653
+
__le64 pfc_min_duration_time[8];
5654
+
__le64 pfc_max_duration_time[8];
5655
+
__le64 pfc_weighted_duration_time[8];
5656
+
};
5657
+
5658
+
/* hwrm_port_qstats_ext_pfc_adv_input (size:320b/40B) */
5659
+
struct hwrm_port_qstats_ext_pfc_adv_input {
5660
+
__le16 req_type;
5661
+
__le16 cmpl_ring;
5662
+
__le16 seq_id;
5663
+
__le16 target_id;
5664
+
__le64 resp_addr;
5665
+
__le16 port_id;
5666
+
__le16 pfc_adv_stat_size;
5667
+
u8 flags;
5668
+
#define PORT_QSTATS_EXT_PFC_ADV_REQ_FLAGS_COUNTER_MASK 0x1UL
5669
+
u8 unused_0[3];
5670
+
__le64 tx_pfc_adv_stat_host_addr;
5671
+
__le64 rx_pfc_adv_stat_host_addr;
5672
+
};
5673
+
5674
+
/* hwrm_port_qstats_ext_pfc_adv_output (size:128b/16B) */
5675
+
struct hwrm_port_qstats_ext_pfc_adv_output {
5676
+
__le16 error_code;
5677
+
__le16 req_type;
5678
+
__le16 seq_id;
5679
+
__le16 resp_len;
5680
+
__le16 pfc_adv_stat_size;
5681
+
u8 unused_0[5];
5682
+
u8 valid;
5683
+
};
5684
+
5685
+
/* hwrm_port_clr_stats_input (size:192b/24B) */
5686
+
struct hwrm_port_clr_stats_input {
5687
+
__le16 req_type;
5688
+
__le16 cmpl_ring;
5689
+
__le16 seq_id;
5690
+
__le16 target_id;
5691
+
__le64 resp_addr;
5692
+
__le16 port_id;
5693
+
u8 flags;
5694
+
#define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
5695
+
u8 unused_0[5];
5696
+
};
5697
+
5698
+
/* hwrm_port_clr_stats_output (size:128b/16B) */
5699
+
struct hwrm_port_clr_stats_output {
5700
+
__le16 error_code;
5701
+
__le16 req_type;
5702
+
__le16 seq_id;
5703
+
__le16 resp_len;
5704
+
u8 unused_0[7];
5705
+
u8 valid;
5706
+
};
5707
+
5708
+
/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */
5709
+
struct hwrm_port_lpbk_clr_stats_input {
5710
+
__le16 req_type;
5711
+
__le16 cmpl_ring;
5712
+
__le16 seq_id;
5713
+
__le16 target_id;
5714
+
__le64 resp_addr;
5715
+
__le16 port_id;
5716
+
u8 unused_0[6];
5717
+
};
5718
+
5719
+
/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
5720
+
struct hwrm_port_lpbk_clr_stats_output {
5721
+
__le16 error_code;
5722
+
__le16 req_type;
5723
+
__le16 seq_id;
5724
+
__le16 resp_len;
5725
+
u8 unused_0[7];
5726
+
u8 valid;
5727
+
};
5728
+
5729
+
/* hwrm_port_ts_query_input (size:320b/40B) */
5730
+
struct hwrm_port_ts_query_input {
5731
+
__le16 req_type;
5732
+
__le16 cmpl_ring;
5733
+
__le16 seq_id;
5734
+
__le16 target_id;
5735
+
__le64 resp_addr;
5736
+
__le32 flags;
5737
+
#define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
5738
+
#define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
5739
+
#define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
5740
+
#define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
5741
+
#define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
5742
+
__le16 port_id;
5743
+
u8 unused_0[2];
5744
+
__le16 enables;
5745
+
#define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL
5746
+
#define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL
5747
+
#define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL
5748
+
__le16 ts_req_timeout;
5749
+
__le32 ptp_seq_id;
5750
+
__le16 ptp_hdr_offset;
5751
+
u8 unused_1[6];
5752
+
};
5753
+
5754
+
/* hwrm_port_ts_query_output (size:192b/24B) */
5755
+
struct hwrm_port_ts_query_output {
5756
+
__le16 error_code;
5757
+
__le16 req_type;
5758
+
__le16 seq_id;
5759
+
__le16 resp_len;
5760
+
__le64 ptp_msg_ts;
5761
+
__le16 ptp_msg_seqid;
5762
+
u8 unused_0[5];
5763
+
u8 valid;
5764
+
};
5765
+
5766
+
/* hwrm_port_phy_qcaps_input (size:192b/24B) */
5767
+
struct hwrm_port_phy_qcaps_input {
5768
+
__le16 req_type;
5769
+
__le16 cmpl_ring;
5770
+
__le16 seq_id;
5771
+
__le16 target_id;
5772
+
__le64 resp_addr;
5773
+
__le16 port_id;
5774
+
u8 unused_0[6];
5775
+
};
5776
+
5777
+
/* hwrm_port_phy_qcaps_output (size:320b/40B) */
5778
+
struct hwrm_port_phy_qcaps_output {
5779
+
__le16 error_code;
5780
+
__le16 req_type;
5781
+
__le16 seq_id;
5782
+
__le16 resp_len;
5783
+
u8 flags;
5784
+
#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
5785
+
#define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
5786
+
#define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
5787
+
#define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
5788
+
#define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL
5789
+
#define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL
5790
+
#define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL
5791
+
#define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL
5792
+
u8 port_cnt;
5793
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
5794
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
5795
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
5796
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
5797
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
5798
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL
5799
+
#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12
5800
+
__le16 supported_speeds_force_mode;
5801
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
5802
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
5803
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
5804
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
5805
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
5806
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
5807
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
5808
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
5809
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
5810
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
5811
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
5812
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
5813
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
5814
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
5815
+
__le16 supported_speeds_auto_mode;
5816
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
5817
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
5818
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
5819
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
5820
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
5821
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
5822
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
5823
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
5824
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
5825
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
5826
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
5827
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
5828
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
5829
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
5830
+
__le16 supported_speeds_eee_mode;
5831
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
5832
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
5833
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
5834
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
5835
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
5836
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
5837
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
5838
+
__le32 tx_lpi_timer_low;
5839
+
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
5840
+
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
5841
+
#define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
5842
+
#define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
5843
+
__le32 valid_tx_lpi_timer_high;
5844
+
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
5845
+
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
5846
+
#define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL
5847
+
#define PORT_PHY_QCAPS_RESP_RSVD_SFT 24
5848
+
__le16 supported_pam4_speeds_auto_mode;
5849
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
5850
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
5851
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
5852
+
__le16 supported_pam4_speeds_force_mode;
5853
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
5854
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
5855
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
5856
+
__le16 flags2;
5857
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
5858
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
5859
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL
5860
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL
5861
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL
5862
+
#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_ADV_STATS_SUPPORTED 0x20UL
5863
+
u8 internal_port_cnt;
5864
+
u8 unused_0;
5865
+
__le16 supported_speeds2_force_mode;
5866
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL
5867
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL
5868
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL
5869
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL
5870
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL
5871
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL
5872
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL
5873
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL
5874
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL
5875
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL
5876
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL
5877
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL
5878
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL
5879
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL
5880
+
__le16 supported_speeds2_auto_mode;
5881
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL
5882
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL
5883
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL
5884
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL
5885
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL
5886
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL
5887
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL
5888
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL
5889
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL
5890
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL
5891
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL
5892
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL
5893
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL
5894
+
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL
5895
+
u8 unused_1[3];
5896
+
u8 valid;
5897
+
};
5898
+
5899
+
/* hwrm_port_phy_i2c_write_input (size:832b/104B) */
5900
+
struct hwrm_port_phy_i2c_write_input {
5901
+
__le16 req_type;
5902
+
__le16 cmpl_ring;
5903
+
__le16 seq_id;
5904
+
__le16 target_id;
5905
+
__le64 resp_addr;
5906
+
__le32 flags;
5907
+
__le32 enables;
5908
+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL
5909
+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER 0x2UL
5910
+
__le16 port_id;
5911
+
u8 i2c_slave_addr;
5912
+
u8 bank_number;
5913
+
__le16 page_number;
5914
+
__le16 page_offset;
5915
+
u8 data_length;
5916
+
u8 unused_1[7];
5917
+
__le32 data[16];
5918
+
};
5919
+
5920
+
/* hwrm_port_phy_i2c_write_output (size:128b/16B) */
5921
+
struct hwrm_port_phy_i2c_write_output {
5922
+
__le16 error_code;
5923
+
__le16 req_type;
5924
+
__le16 seq_id;
5925
+
__le16 resp_len;
5926
+
u8 unused_0[7];
5927
+
u8 valid;
5928
+
};
5929
+
5930
+
/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
5931
+
struct hwrm_port_phy_i2c_read_input {
5932
+
__le16 req_type;
5933
+
__le16 cmpl_ring;
5934
+
__le16 seq_id;
5935
+
__le16 target_id;
5936
+
__le64 resp_addr;
5937
+
__le32 flags;
5938
+
__le32 enables;
5939
+
#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
5940
+
#define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL
5941
+
__le16 port_id;
5942
+
u8 i2c_slave_addr;
5943
+
u8 bank_number;
5944
+
__le16 page_number;
5945
+
__le16 page_offset;
5946
+
u8 data_length;
5947
+
u8 unused_1[7];
5948
+
};
5949
+
5950
+
/* hwrm_port_phy_i2c_read_output (size:640b/80B) */
5951
+
struct hwrm_port_phy_i2c_read_output {
5952
+
__le16 error_code;
5953
+
__le16 req_type;
5954
+
__le16 seq_id;
5955
+
__le16 resp_len;
5956
+
__le32 data[16];
5957
+
u8 unused_0[7];
5958
+
u8 valid;
5959
+
};
5960
+
5961
+
/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
5962
+
struct hwrm_port_phy_mdio_write_input {
5963
+
__le16 req_type;
5964
+
__le16 cmpl_ring;
5965
+
__le16 seq_id;
5966
+
__le16 target_id;
5967
+
__le64 resp_addr;
5968
+
__le32 unused_0[2];
5969
+
__le16 port_id;
5970
+
u8 phy_addr;
5971
+
u8 dev_addr;
5972
+
__le16 reg_addr;
5973
+
__le16 reg_data;
5974
+
u8 cl45_mdio;
5975
+
u8 unused_1[7];
5976
+
};
5977
+
5978
+
/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
5979
+
struct hwrm_port_phy_mdio_write_output {
5980
+
__le16 error_code;
5981
+
__le16 req_type;
5982
+
__le16 seq_id;
5983
+
__le16 resp_len;
5984
+
u8 unused_0[7];
5985
+
u8 valid;
5986
+
};
5987
+
5988
+
/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
5989
+
struct hwrm_port_phy_mdio_read_input {
5990
+
__le16 req_type;
5991
+
__le16 cmpl_ring;
5992
+
__le16 seq_id;
5993
+
__le16 target_id;
5994
+
__le64 resp_addr;
5995
+
__le32 unused_0[2];
5996
+
__le16 port_id;
5997
+
u8 phy_addr;
5998
+
u8 dev_addr;
5999
+
__le16 reg_addr;
6000
+
u8 cl45_mdio;
6001
+
u8 unused_1;
6002
+
};
6003
+
6004
+
/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
6005
+
struct hwrm_port_phy_mdio_read_output {
6006
+
__le16 error_code;
6007
+
__le16 req_type;
6008
+
__le16 seq_id;
6009
+
__le16 resp_len;
6010
+
__le16 reg_data;
6011
+
u8 unused_0[5];
6012
+
u8 valid;
6013
+
};
6014
+
6015
+
/* hwrm_port_led_cfg_input (size:512b/64B) */
6016
+
struct hwrm_port_led_cfg_input {
6017
+
__le16 req_type;
6018
+
__le16 cmpl_ring;
6019
+
__le16 seq_id;
6020
+
__le16 target_id;
6021
+
__le64 resp_addr;
6022
+
__le32 enables;
6023
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
6024
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
6025
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
6026
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
6027
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
6028
+
#define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
6029
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
6030
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
6031
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
6032
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
6033
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
6034
+
#define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
6035
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
6036
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
6037
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
6038
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
6039
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
6040
+
#define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
6041
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
6042
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
6043
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
6044
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
6045
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
6046
+
#define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
6047
+
__le16 port_id;
6048
+
u8 num_leds;
6049
+
u8 rsvd;
6050
+
u8 led0_id;
6051
+
u8 led0_state;
6052
+
#define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
6053
+
#define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
6054
+
#define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
6055
+
#define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
6056
+
#define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
6057
+
#define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
6058
+
u8 led0_color;
6059
+
#define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
6060
+
#define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
6061
+
#define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
6062
+
#define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
6063
+
#define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
6064
+
u8 unused_0;
6065
+
__le16 led0_blink_on;
6066
+
__le16 led0_blink_off;
6067
+
u8 led0_group_id;
6068
+
u8 rsvd0;
6069
+
u8 led1_id;
6070
+
u8 led1_state;
6071
+
#define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
6072
+
#define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
6073
+
#define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
6074
+
#define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
6075
+
#define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
6076
+
#define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
6077
+
u8 led1_color;
6078
+
#define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
6079
+
#define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
6080
+
#define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
6081
+
#define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
6082
+
#define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
6083
+
u8 unused_1;
6084
+
__le16 led1_blink_on;
6085
+
__le16 led1_blink_off;
6086
+
u8 led1_group_id;
6087
+
u8 rsvd1;
6088
+
u8 led2_id;
6089
+
u8 led2_state;
6090
+
#define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
6091
+
#define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
6092
+
#define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
6093
+
#define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
6094
+
#define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
6095
+
#define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
6096
+
u8 led2_color;
6097
+
#define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
6098
+
#define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
6099
+
#define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
6100
+
#define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
6101
+
#define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
6102
+
u8 unused_2;
6103
+
__le16 led2_blink_on;
6104
+
__le16 led2_blink_off;
6105
+
u8 led2_group_id;
6106
+
u8 rsvd2;
6107
+
u8 led3_id;
6108
+
u8 led3_state;
6109
+
#define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
6110
+
#define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
6111
+
#define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
6112
+
#define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
6113
+
#define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
6114
+
#define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
6115
+
u8 led3_color;
6116
+
#define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
6117
+
#define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
6118
+
#define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
6119
+
#define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
6120
+
#define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
6121
+
u8 unused_3;
6122
+
__le16 led3_blink_on;
6123
+
__le16 led3_blink_off;
6124
+
u8 led3_group_id;
6125
+
u8 rsvd3;
6126
+
};
6127
+
6128
+
/* hwrm_port_led_cfg_output (size:128b/16B) */
6129
+
struct hwrm_port_led_cfg_output {
6130
+
__le16 error_code;
6131
+
__le16 req_type;
6132
+
__le16 seq_id;
6133
+
__le16 resp_len;
6134
+
u8 unused_0[7];
6135
+
u8 valid;
6136
+
};
6137
+
6138
+
/* hwrm_port_led_qcfg_input (size:192b/24B) */
6139
+
struct hwrm_port_led_qcfg_input {
6140
+
__le16 req_type;
6141
+
__le16 cmpl_ring;
6142
+
__le16 seq_id;
6143
+
__le16 target_id;
6144
+
__le64 resp_addr;
6145
+
__le16 port_id;
6146
+
u8 unused_0[6];
6147
+
};
6148
+
6149
+
/* hwrm_port_led_qcfg_output (size:448b/56B) */
6150
+
struct hwrm_port_led_qcfg_output {
6151
+
__le16 error_code;
6152
+
__le16 req_type;
6153
+
__le16 seq_id;
6154
+
__le16 resp_len;
6155
+
u8 num_leds;
6156
+
u8 led0_id;
6157
+
u8 led0_type;
6158
+
#define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
6159
+
#define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
6160
+
#define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
6161
+
#define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
6162
+
u8 led0_state;
6163
+
#define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
6164
+
#define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
6165
+
#define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
6166
+
#define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
6167
+
#define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
6168
+
#define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
6169
+
u8 led0_color;
6170
+
#define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
6171
+
#define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
6172
+
#define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
6173
+
#define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
6174
+
#define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
6175
+
u8 unused_0;
6176
+
__le16 led0_blink_on;
6177
+
__le16 led0_blink_off;
6178
+
u8 led0_group_id;
6179
+
u8 led1_id;
6180
+
u8 led1_type;
6181
+
#define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
6182
+
#define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
6183
+
#define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
6184
+
#define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
6185
+
u8 led1_state;
6186
+
#define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
6187
+
#define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
6188
+
#define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
6189
+
#define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
6190
+
#define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
6191
+
#define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
6192
+
u8 led1_color;
6193
+
#define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
6194
+
#define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
6195
+
#define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
6196
+
#define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
6197
+
#define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
6198
+
u8 unused_1;
6199
+
__le16 led1_blink_on;
6200
+
__le16 led1_blink_off;
6201
+
u8 led1_group_id;
6202
+
u8 led2_id;
6203
+
u8 led2_type;
6204
+
#define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
6205
+
#define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
6206
+
#define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
6207
+
#define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
6208
+
u8 led2_state;
6209
+
#define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
6210
+
#define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
6211
+
#define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
6212
+
#define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
6213
+
#define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
6214
+
#define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
6215
+
u8 led2_color;
6216
+
#define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
6217
+
#define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
6218
+
#define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
6219
+
#define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
6220
+
#define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
6221
+
u8 unused_2;
6222
+
__le16 led2_blink_on;
6223
+
__le16 led2_blink_off;
6224
+
u8 led2_group_id;
6225
+
u8 led3_id;
6226
+
u8 led3_type;
6227
+
#define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
6228
+
#define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
6229
+
#define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
6230
+
#define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
6231
+
u8 led3_state;
6232
+
#define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
6233
+
#define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
6234
+
#define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
6235
+
#define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
6236
+
#define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
6237
+
#define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
6238
+
u8 led3_color;
6239
+
#define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
6240
+
#define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
6241
+
#define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
6242
+
#define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
6243
+
#define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
6244
+
u8 unused_3;
6245
+
__le16 led3_blink_on;
6246
+
__le16 led3_blink_off;
6247
+
u8 led3_group_id;
6248
+
u8 unused_4[6];
6249
+
u8 valid;
6250
+
};
6251
+
6252
+
/* hwrm_port_led_qcaps_input (size:192b/24B) */
6253
+
struct hwrm_port_led_qcaps_input {
6254
+
__le16 req_type;
6255
+
__le16 cmpl_ring;
6256
+
__le16 seq_id;
6257
+
__le16 target_id;
6258
+
__le64 resp_addr;
6259
+
__le16 port_id;
6260
+
u8 unused_0[6];
6261
+
};
6262
+
6263
+
/* hwrm_port_led_qcaps_output (size:384b/48B) */
6264
+
struct hwrm_port_led_qcaps_output {
6265
+
__le16 error_code;
6266
+
__le16 req_type;
6267
+
__le16 seq_id;
6268
+
__le16 resp_len;
6269
+
u8 num_leds;
6270
+
u8 unused[3];
6271
+
u8 led0_id;
6272
+
u8 led0_type;
6273
+
#define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
6274
+
#define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
6275
+
#define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
6276
+
#define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
6277
+
u8 led0_group_id;
6278
+
u8 unused_0;
6279
+
__le16 led0_state_caps;
6280
+
#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
6281
+
#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
6282
+
#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
6283
+
#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
6284
+
#define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
6285
+
__le16 led0_color_caps;
6286
+
#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
6287
+
#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
6288
+
#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
6289
+
#define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL
6290
+
u8 led1_id;
6291
+
u8 led1_type;
6292
+
#define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
6293
+
#define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
6294
+
#define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
6295
+
#define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
6296
+
u8 led1_group_id;
6297
+
u8 unused_1;
6298
+
__le16 led1_state_caps;
6299
+
#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
6300
+
#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
6301
+
#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
6302
+
#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
6303
+
#define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
6304
+
__le16 led1_color_caps;
6305
+
#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
6306
+
#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
6307
+
#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
6308
+
#define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL
6309
+
u8 led2_id;
6310
+
u8 led2_type;
6311
+
#define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
6312
+
#define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
6313
+
#define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
6314
+
#define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
6315
+
u8 led2_group_id;
6316
+
u8 unused_2;
6317
+
__le16 led2_state_caps;
6318
+
#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
6319
+
#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
6320
+
#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
6321
+
#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
6322
+
#define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
6323
+
__le16 led2_color_caps;
6324
+
#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
6325
+
#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
6326
+
#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
6327
+
#define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL
6328
+
u8 led3_id;
6329
+
u8 led3_type;
6330
+
#define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
6331
+
#define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
6332
+
#define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
6333
+
#define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
6334
+
u8 led3_group_id;
6335
+
u8 unused_3;
6336
+
__le16 led3_state_caps;
6337
+
#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
6338
+
#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
6339
+
#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
6340
+
#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
6341
+
#define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
6342
+
__le16 led3_color_caps;
6343
+
#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
6344
+
#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
6345
+
#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
6346
+
#define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL
6347
+
u8 unused_4[3];
6348
+
u8 valid;
6349
+
};
6350
+
6351
+
/* hwrm_port_phy_fdrstat_input (size:192b/24B) */
6352
+
struct hwrm_port_phy_fdrstat_input {
6353
+
__le16 req_type;
6354
+
__le16 cmpl_ring;
6355
+
__le16 seq_id;
6356
+
__le16 target_id;
6357
+
__le64 resp_addr;
6358
+
__le16 port_id;
6359
+
__le16 rsvd[2];
6360
+
__le16 ops;
6361
+
#define PORT_PHY_FDRSTAT_REQ_OPS_START 0x0UL
6362
+
#define PORT_PHY_FDRSTAT_REQ_OPS_STOP 0x1UL
6363
+
#define PORT_PHY_FDRSTAT_REQ_OPS_CLEAR 0x2UL
6364
+
#define PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 0x3UL
6365
+
#define PORT_PHY_FDRSTAT_REQ_OPS_LAST PORT_PHY_FDRSTAT_REQ_OPS_COUNTER
6366
+
};
6367
+
6368
+
/* hwrm_port_phy_fdrstat_output (size:3072b/384B) */
6369
+
struct hwrm_port_phy_fdrstat_output {
6370
+
__le16 error_code;
6371
+
__le16 req_type;
6372
+
__le16 seq_id;
6373
+
__le16 resp_len;
6374
+
__le64 start_time;
6375
+
__le64 end_time;
6376
+
__le64 cmic_start_time;
6377
+
__le64 cmic_end_time;
6378
+
__le64 accumulated_uncorrected_codewords;
6379
+
__le64 accumulated_corrected_codewords;
6380
+
__le64 accumulated_total_codewords;
6381
+
__le64 accumulated_symbol_errors;
6382
+
__le64 accumulated_codewords_err_s0;
6383
+
__le64 accumulated_codewords_err_s1;
6384
+
__le64 accumulated_codewords_err_s2;
6385
+
__le64 accumulated_codewords_err_s3;
6386
+
__le64 accumulated_codewords_err_s4;
6387
+
__le64 accumulated_codewords_err_s5;
6388
+
__le64 accumulated_codewords_err_s6;
6389
+
__le64 accumulated_codewords_err_s7;
6390
+
__le64 accumulated_codewords_err_s8;
6391
+
__le64 accumulated_codewords_err_s9;
6392
+
__le64 accumulated_codewords_err_s10;
6393
+
__le64 accumulated_codewords_err_s11;
6394
+
__le64 accumulated_codewords_err_s12;
6395
+
__le64 accumulated_codewords_err_s13;
6396
+
__le64 accumulated_codewords_err_s14;
6397
+
__le64 accumulated_codewords_err_s15;
6398
+
__le64 accumulated_codewords_err_s16;
6399
+
__le64 uncorrected_codewords;
6400
+
__le64 corrected_codewords;
6401
+
__le64 total_codewords;
6402
+
__le64 symbol_errors;
6403
+
__le64 codewords_err_s0;
6404
+
__le64 codewords_err_s1;
6405
+
__le64 codewords_err_s2;
6406
+
__le64 codewords_err_s3;
6407
+
__le64 codewords_err_s4;
6408
+
__le64 codewords_err_s5;
6409
+
__le64 codewords_err_s6;
6410
+
__le64 codewords_err_s7;
6411
+
__le64 codewords_err_s8;
6412
+
__le64 codewords_err_s9;
6413
+
__le64 codewords_err_s10;
6414
+
__le64 codewords_err_s11;
6415
+
__le64 codewords_err_s12;
6416
+
__le64 codewords_err_s13;
6417
+
__le64 codewords_err_s14;
6418
+
__le64 codewords_err_s15;
6419
+
__le64 codewords_err_s16;
6420
+
__le32 window_size;
6421
+
__le16 unused_0[1];
6422
+
u8 unused_1;
6423
+
u8 valid;
6424
+
};
6425
+
6426
+
/* hwrm_port_phy_fdrstat_cmd_err (size:64b/8B) */
6427
+
struct hwrm_port_phy_fdrstat_cmd_err {
6428
+
u8 code;
6429
+
#define PORT_PHY_FDRSTAT_CMD_ERR_CODE_UNKNOWN 0x0UL
6430
+
#define PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 0x1UL
6431
+
#define PORT_PHY_FDRSTAT_CMD_ERR_CODE_LAST PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED
6432
+
u8 unused_0[7];
6433
+
};
6434
+
6435
+
/* hwrm_port_mac_qcaps_input (size:192b/24B) */
6436
+
struct hwrm_port_mac_qcaps_input {
6437
+
__le16 req_type;
6438
+
__le16 cmpl_ring;
6439
+
__le16 seq_id;
6440
+
__le16 target_id;
6441
+
__le64 resp_addr;
6442
+
__le16 port_id;
6443
+
u8 unused_0[6];
6444
+
};
6445
+
6446
+
/* hwrm_port_mac_qcaps_output (size:128b/16B) */
6447
+
struct hwrm_port_mac_qcaps_output {
6448
+
__le16 error_code;
6449
+
__le16 req_type;
6450
+
__le16 seq_id;
6451
+
__le16 resp_len;
6452
+
u8 flags;
6453
+
#define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL
6454
+
#define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL
6455
+
u8 unused_0[6];
6456
+
u8 valid;
6457
+
};
6458
+
6459
+
/* hwrm_queue_qportcfg_input (size:192b/24B) */
6460
+
struct hwrm_queue_qportcfg_input {
6461
+
__le16 req_type;
6462
+
__le16 cmpl_ring;
6463
+
__le16 seq_id;
6464
+
__le16 target_id;
6465
+
__le64 resp_addr;
6466
+
__le32 flags;
6467
+
#define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
6468
+
#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
6469
+
#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
6470
+
#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
6471
+
__le16 port_id;
6472
+
u8 drv_qmap_cap;
6473
+
#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
6474
+
#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
6475
+
#define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
6476
+
u8 unused_0;
6477
+
};
6478
+
6479
+
/* hwrm_queue_qportcfg_output (size:1344b/168B) */
6480
+
struct hwrm_queue_qportcfg_output {
6481
+
__le16 error_code;
6482
+
__le16 req_type;
6483
+
__le16 seq_id;
6484
+
__le16 resp_len;
6485
+
u8 max_configurable_queues;
6486
+
u8 max_configurable_lossless_queues;
6487
+
u8 queue_cfg_allowed;
6488
+
u8 queue_cfg_info;
6489
+
#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
6490
+
#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL
6491
+
u8 queue_pfcenable_cfg_allowed;
6492
+
u8 queue_pri2cos_cfg_allowed;
6493
+
u8 queue_cos2bw_cfg_allowed;
6494
+
u8 queue_id0;
6495
+
u8 queue_id0_service_profile;
6496
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
6497
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
6498
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6499
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6500
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6501
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
6502
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
6503
+
u8 queue_id1;
6504
+
u8 queue_id1_service_profile;
6505
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
6506
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
6507
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6508
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6509
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6510
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
6511
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
6512
+
u8 queue_id2;
6513
+
u8 queue_id2_service_profile;
6514
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
6515
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
6516
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6517
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6518
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6519
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
6520
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
6521
+
u8 queue_id3;
6522
+
u8 queue_id3_service_profile;
6523
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
6524
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
6525
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6526
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6527
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6528
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
6529
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
6530
+
u8 queue_id4;
6531
+
u8 queue_id4_service_profile;
6532
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
6533
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
6534
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6535
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6536
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6537
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
6538
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
6539
+
u8 queue_id5;
6540
+
u8 queue_id5_service_profile;
6541
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
6542
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
6543
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6544
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6545
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6546
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
6547
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
6548
+
u8 queue_id6;
6549
+
u8 queue_id6_service_profile;
6550
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
6551
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
6552
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6553
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6554
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6555
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
6556
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
6557
+
u8 queue_id7;
6558
+
u8 queue_id7_service_profile;
6559
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
6560
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
6561
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
6562
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
6563
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
6564
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
6565
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
6566
+
u8 queue_id0_service_profile_type;
6567
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6568
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL
6569
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL
6570
+
char qid0_name[16];
6571
+
char qid1_name[16];
6572
+
char qid2_name[16];
6573
+
char qid3_name[16];
6574
+
char qid4_name[16];
6575
+
char qid5_name[16];
6576
+
char qid6_name[16];
6577
+
char qid7_name[16];
6578
+
u8 queue_id1_service_profile_type;
6579
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6580
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL
6581
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL
6582
+
u8 queue_id2_service_profile_type;
6583
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6584
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL
6585
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL
6586
+
u8 queue_id3_service_profile_type;
6587
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6588
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL
6589
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL
6590
+
u8 queue_id4_service_profile_type;
6591
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6592
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL
6593
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL
6594
+
u8 queue_id5_service_profile_type;
6595
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6596
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL
6597
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL
6598
+
u8 queue_id6_service_profile_type;
6599
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6600
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL
6601
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL
6602
+
u8 queue_id7_service_profile_type;
6603
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL
6604
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL
6605
+
#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL
6606
+
u8 valid;
6607
+
};
6608
+
6609
+
/* hwrm_queue_qcfg_input (size:192b/24B) */
6610
+
struct hwrm_queue_qcfg_input {
6611
+
__le16 req_type;
6612
+
__le16 cmpl_ring;
6613
+
__le16 seq_id;
6614
+
__le16 target_id;
6615
+
__le64 resp_addr;
6616
+
__le32 flags;
6617
+
#define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
6618
+
#define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
6619
+
#define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
6620
+
#define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
6621
+
__le32 queue_id;
6622
+
};
6623
+
6624
+
/* hwrm_queue_qcfg_output (size:128b/16B) */
6625
+
struct hwrm_queue_qcfg_output {
6626
+
__le16 error_code;
6627
+
__le16 req_type;
6628
+
__le16 seq_id;
6629
+
__le16 resp_len;
6630
+
__le32 queue_len;
6631
+
u8 service_profile;
6632
+
#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
6633
+
#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
6634
+
#define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
6635
+
#define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
6636
+
u8 queue_cfg_info;
6637
+
#define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
6638
+
u8 unused_0;
6639
+
u8 valid;
6640
+
};
6641
+
6642
+
/* hwrm_queue_cfg_input (size:320b/40B) */
6643
+
struct hwrm_queue_cfg_input {
6644
+
__le16 req_type;
6645
+
__le16 cmpl_ring;
6646
+
__le16 seq_id;
6647
+
__le16 target_id;
6648
+
__le64 resp_addr;
6649
+
__le32 flags;
6650
+
#define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
6651
+
#define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
6652
+
#define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
6653
+
#define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
6654
+
#define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
6655
+
#define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
6656
+
__le32 enables;
6657
+
#define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
6658
+
#define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
6659
+
__le32 queue_id;
6660
+
__le32 dflt_len;
6661
+
u8 service_profile;
6662
+
#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
6663
+
#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
6664
+
#define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
6665
+
#define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
6666
+
u8 unused_0[7];
6667
+
};
6668
+
6669
+
/* hwrm_queue_cfg_output (size:128b/16B) */
6670
+
struct hwrm_queue_cfg_output {
6671
+
__le16 error_code;
6672
+
__le16 req_type;
6673
+
__le16 seq_id;
6674
+
__le16 resp_len;
6675
+
u8 unused_0[7];
6676
+
u8 valid;
6677
+
};
6678
+
6679
+
/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
6680
+
struct hwrm_queue_pfcenable_qcfg_input {
6681
+
__le16 req_type;
6682
+
__le16 cmpl_ring;
6683
+
__le16 seq_id;
6684
+
__le16 target_id;
6685
+
__le64 resp_addr;
6686
+
__le16 port_id;
6687
+
u8 unused_0[6];
6688
+
};
6689
+
6690
+
/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
6691
+
struct hwrm_queue_pfcenable_qcfg_output {
6692
+
__le16 error_code;
6693
+
__le16 req_type;
6694
+
__le16 seq_id;
6695
+
__le16 resp_len;
6696
+
__le32 flags;
6697
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
6698
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
6699
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
6700
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
6701
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
6702
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
6703
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
6704
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
6705
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
6706
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
6707
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
6708
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
6709
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
6710
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
6711
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
6712
+
#define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
6713
+
u8 unused_0[3];
6714
+
u8 valid;
6715
+
};
6716
+
6717
+
/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
6718
+
struct hwrm_queue_pfcenable_cfg_input {
6719
+
__le16 req_type;
6720
+
__le16 cmpl_ring;
6721
+
__le16 seq_id;
6722
+
__le16 target_id;
6723
+
__le64 resp_addr;
6724
+
__le32 flags;
6725
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
6726
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
6727
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
6728
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
6729
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
6730
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
6731
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
6732
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
6733
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
6734
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
6735
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
6736
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
6737
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
6738
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
6739
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
6740
+
#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
6741
+
__le16 port_id;
6742
+
u8 unused_0[2];
6743
+
};
6744
+
6745
+
/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
6746
+
struct hwrm_queue_pfcenable_cfg_output {
6747
+
__le16 error_code;
6748
+
__le16 req_type;
6749
+
__le16 seq_id;
6750
+
__le16 resp_len;
6751
+
u8 unused_0[7];
6752
+
u8 valid;
6753
+
};
6754
+
6755
+
/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
6756
+
struct hwrm_queue_pri2cos_qcfg_input {
6757
+
__le16 req_type;
6758
+
__le16 cmpl_ring;
6759
+
__le16 seq_id;
6760
+
__le16 target_id;
6761
+
__le64 resp_addr;
6762
+
__le32 flags;
6763
+
#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
6764
+
#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
6765
+
#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
6766
+
#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
6767
+
#define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
6768
+
u8 port_id;
6769
+
u8 unused_0[3];
6770
+
};
6771
+
6772
+
/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
6773
+
struct hwrm_queue_pri2cos_qcfg_output {
6774
+
__le16 error_code;
6775
+
__le16 req_type;
6776
+
__le16 seq_id;
6777
+
__le16 resp_len;
6778
+
u8 pri0_cos_queue_id;
6779
+
u8 pri1_cos_queue_id;
6780
+
u8 pri2_cos_queue_id;
6781
+
u8 pri3_cos_queue_id;
6782
+
u8 pri4_cos_queue_id;
6783
+
u8 pri5_cos_queue_id;
6784
+
u8 pri6_cos_queue_id;
6785
+
u8 pri7_cos_queue_id;
6786
+
u8 queue_cfg_info;
6787
+
#define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
6788
+
u8 unused_0[6];
6789
+
u8 valid;
6790
+
};
6791
+
6792
+
/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
6793
+
struct hwrm_queue_pri2cos_cfg_input {
6794
+
__le16 req_type;
6795
+
__le16 cmpl_ring;
6796
+
__le16 seq_id;
6797
+
__le16 target_id;
6798
+
__le64 resp_addr;
6799
+
__le32 flags;
6800
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
6801
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
6802
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
6803
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
6804
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
6805
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
6806
+
#define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
6807
+
__le32 enables;
6808
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
6809
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
6810
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
6811
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
6812
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
6813
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
6814
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
6815
+
#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
6816
+
u8 port_id;
6817
+
u8 pri0_cos_queue_id;
6818
+
u8 pri1_cos_queue_id;
6819
+
u8 pri2_cos_queue_id;
6820
+
u8 pri3_cos_queue_id;
6821
+
u8 pri4_cos_queue_id;
6822
+
u8 pri5_cos_queue_id;
6823
+
u8 pri6_cos_queue_id;
6824
+
u8 pri7_cos_queue_id;
6825
+
u8 unused_0[7];
6826
+
};
6827
+
6828
+
/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
6829
+
struct hwrm_queue_pri2cos_cfg_output {
6830
+
__le16 error_code;
6831
+
__le16 req_type;
6832
+
__le16 seq_id;
6833
+
__le16 resp_len;
6834
+
u8 unused_0[7];
6835
+
u8 valid;
6836
+
};
6837
+
6838
+
/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
6839
+
struct hwrm_queue_cos2bw_qcfg_input {
6840
+
__le16 req_type;
6841
+
__le16 cmpl_ring;
6842
+
__le16 seq_id;
6843
+
__le16 target_id;
6844
+
__le64 resp_addr;
6845
+
__le16 port_id;
6846
+
u8 unused_0[6];
6847
+
};
6848
+
6849
+
/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
6850
+
struct hwrm_queue_cos2bw_qcfg_output {
6851
+
__le16 error_code;
6852
+
__le16 req_type;
6853
+
__le16 seq_id;
6854
+
__le16 resp_len;
6855
+
u8 queue_id0;
6856
+
u8 unused_0;
6857
+
__le16 unused_1;
6858
+
__le32 queue_id0_min_bw;
6859
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
6860
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
6861
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
6862
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
6863
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
6864
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
6865
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6866
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
6867
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6868
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6869
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6870
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6871
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6872
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6873
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
6874
+
__le32 queue_id0_max_bw;
6875
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6876
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
6877
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
6878
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
6879
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
6880
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
6881
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6882
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
6883
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6884
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6885
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6886
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6887
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6888
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6889
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
6890
+
u8 queue_id0_tsa_assign;
6891
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
6892
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
6893
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
6894
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
6895
+
u8 queue_id0_pri_lvl;
6896
+
u8 queue_id0_bw_weight;
6897
+
u8 queue_id1;
6898
+
__le32 queue_id1_min_bw;
6899
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
6900
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
6901
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
6902
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
6903
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
6904
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
6905
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6906
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
6907
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6908
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6909
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6910
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6911
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6912
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6913
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
6914
+
__le32 queue_id1_max_bw;
6915
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6916
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
6917
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
6918
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
6919
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
6920
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
6921
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6922
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
6923
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6924
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6925
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6926
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6927
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6928
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6929
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
6930
+
u8 queue_id1_tsa_assign;
6931
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
6932
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
6933
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
6934
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
6935
+
u8 queue_id1_pri_lvl;
6936
+
u8 queue_id1_bw_weight;
6937
+
u8 queue_id2;
6938
+
__le32 queue_id2_min_bw;
6939
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
6940
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
6941
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
6942
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
6943
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
6944
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
6945
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6946
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
6947
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6948
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6949
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6950
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6951
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6952
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6953
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
6954
+
__le32 queue_id2_max_bw;
6955
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6956
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
6957
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
6958
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
6959
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
6960
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
6961
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6962
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
6963
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6964
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6965
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6966
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6967
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6968
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6969
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
6970
+
u8 queue_id2_tsa_assign;
6971
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
6972
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
6973
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
6974
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
6975
+
u8 queue_id2_pri_lvl;
6976
+
u8 queue_id2_bw_weight;
6977
+
u8 queue_id3;
6978
+
__le32 queue_id3_min_bw;
6979
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
6980
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
6981
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
6982
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
6983
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
6984
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
6985
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6986
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
6987
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6988
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6989
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6990
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6991
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6992
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6993
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
6994
+
__le32 queue_id3_max_bw;
6995
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6996
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
6997
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
6998
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
6999
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
7000
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
7001
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7002
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
7003
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7004
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7005
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7006
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7007
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7008
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7009
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
7010
+
u8 queue_id3_tsa_assign;
7011
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
7012
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
7013
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7014
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
7015
+
u8 queue_id3_pri_lvl;
7016
+
u8 queue_id3_bw_weight;
7017
+
u8 queue_id4;
7018
+
__le32 queue_id4_min_bw;
7019
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7020
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
7021
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
7022
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
7023
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
7024
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
7025
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7026
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
7027
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7028
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7029
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7030
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7031
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7032
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7033
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
7034
+
__le32 queue_id4_max_bw;
7035
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7036
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
7037
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
7038
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
7039
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
7040
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
7041
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7042
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
7043
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7044
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7045
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7046
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7047
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7048
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7049
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
7050
+
u8 queue_id4_tsa_assign;
7051
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
7052
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
7053
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7054
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
7055
+
u8 queue_id4_pri_lvl;
7056
+
u8 queue_id4_bw_weight;
7057
+
u8 queue_id5;
7058
+
__le32 queue_id5_min_bw;
7059
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7060
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
7061
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
7062
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
7063
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
7064
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
7065
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7066
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
7067
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7068
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7069
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7070
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7071
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7072
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7073
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
7074
+
__le32 queue_id5_max_bw;
7075
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7076
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
7077
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
7078
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
7079
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
7080
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
7081
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7082
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
7083
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7084
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7085
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7086
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7087
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7088
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7089
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
7090
+
u8 queue_id5_tsa_assign;
7091
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
7092
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
7093
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7094
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
7095
+
u8 queue_id5_pri_lvl;
7096
+
u8 queue_id5_bw_weight;
7097
+
u8 queue_id6;
7098
+
__le32 queue_id6_min_bw;
7099
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7100
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
7101
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
7102
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
7103
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
7104
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
7105
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7106
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
7107
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7108
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7109
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7110
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7111
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7112
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7113
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
7114
+
__le32 queue_id6_max_bw;
7115
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7116
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
7117
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
7118
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
7119
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
7120
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
7121
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7122
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
7123
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7124
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7125
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7126
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7127
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7128
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7129
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
7130
+
u8 queue_id6_tsa_assign;
7131
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
7132
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
7133
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7134
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
7135
+
u8 queue_id6_pri_lvl;
7136
+
u8 queue_id6_bw_weight;
7137
+
u8 queue_id7;
7138
+
__le32 queue_id7_min_bw;
7139
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7140
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
7141
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
7142
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
7143
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
7144
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
7145
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7146
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
7147
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7148
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7149
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7150
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7151
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7152
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7153
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
7154
+
__le32 queue_id7_max_bw;
7155
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7156
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
7157
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
7158
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
7159
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
7160
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
7161
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7162
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
7163
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7164
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7165
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7166
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7167
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7168
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7169
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
7170
+
u8 queue_id7_tsa_assign;
7171
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
7172
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
7173
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7174
+
#define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
7175
+
u8 queue_id7_pri_lvl;
7176
+
u8 queue_id7_bw_weight;
7177
+
u8 unused_2[4];
7178
+
u8 valid;
7179
+
};
7180
+
7181
+
/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
7182
+
struct hwrm_queue_cos2bw_cfg_input {
7183
+
__le16 req_type;
7184
+
__le16 cmpl_ring;
7185
+
__le16 seq_id;
7186
+
__le16 target_id;
7187
+
__le64 resp_addr;
7188
+
__le32 flags;
7189
+
__le32 enables;
7190
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
7191
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
7192
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
7193
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
7194
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
7195
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
7196
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
7197
+
#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
7198
+
__le16 port_id;
7199
+
u8 queue_id0;
7200
+
u8 unused_0;
7201
+
__le32 queue_id0_min_bw;
7202
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7203
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
7204
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
7205
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
7206
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
7207
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
7208
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7209
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
7210
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7211
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7212
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7213
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7214
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7215
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7216
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
7217
+
__le32 queue_id0_max_bw;
7218
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7219
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
7220
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
7221
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
7222
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
7223
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
7224
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7225
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
7226
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7227
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7228
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7229
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7230
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7231
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7232
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
7233
+
u8 queue_id0_tsa_assign;
7234
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
7235
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
7236
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7237
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
7238
+
u8 queue_id0_pri_lvl;
7239
+
u8 queue_id0_bw_weight;
7240
+
u8 queue_id1;
7241
+
__le32 queue_id1_min_bw;
7242
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7243
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
7244
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
7245
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
7246
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
7247
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
7248
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7249
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
7250
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7251
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7252
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7253
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7254
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7255
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7256
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
7257
+
__le32 queue_id1_max_bw;
7258
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7259
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
7260
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
7261
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
7262
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
7263
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
7264
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7265
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
7266
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7267
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7268
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7269
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7270
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7271
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7272
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
7273
+
u8 queue_id1_tsa_assign;
7274
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
7275
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
7276
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7277
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
7278
+
u8 queue_id1_pri_lvl;
7279
+
u8 queue_id1_bw_weight;
7280
+
u8 queue_id2;
7281
+
__le32 queue_id2_min_bw;
7282
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7283
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
7284
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
7285
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
7286
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
7287
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
7288
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7289
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
7290
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7291
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7292
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7293
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7294
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7295
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7296
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
7297
+
__le32 queue_id2_max_bw;
7298
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7299
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
7300
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
7301
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
7302
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
7303
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
7304
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7305
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
7306
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7307
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7308
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7309
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7310
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7311
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7312
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
7313
+
u8 queue_id2_tsa_assign;
7314
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
7315
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
7316
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7317
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
7318
+
u8 queue_id2_pri_lvl;
7319
+
u8 queue_id2_bw_weight;
7320
+
u8 queue_id3;
7321
+
__le32 queue_id3_min_bw;
7322
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7323
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
7324
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
7325
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
7326
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
7327
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
7328
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7329
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
7330
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7331
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7332
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7333
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7334
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7335
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7336
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
7337
+
__le32 queue_id3_max_bw;
7338
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7339
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
7340
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
7341
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
7342
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
7343
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
7344
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7345
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
7346
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7347
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7348
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7349
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7350
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7351
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7352
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
7353
+
u8 queue_id3_tsa_assign;
7354
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
7355
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
7356
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7357
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
7358
+
u8 queue_id3_pri_lvl;
7359
+
u8 queue_id3_bw_weight;
7360
+
u8 queue_id4;
7361
+
__le32 queue_id4_min_bw;
7362
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7363
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
7364
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
7365
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
7366
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
7367
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
7368
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7369
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
7370
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7371
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7372
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7373
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7374
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7375
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7376
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
7377
+
__le32 queue_id4_max_bw;
7378
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7379
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
7380
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
7381
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
7382
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
7383
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
7384
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7385
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
7386
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7387
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7388
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7389
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7390
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7391
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7392
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
7393
+
u8 queue_id4_tsa_assign;
7394
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
7395
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
7396
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7397
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
7398
+
u8 queue_id4_pri_lvl;
7399
+
u8 queue_id4_bw_weight;
7400
+
u8 queue_id5;
7401
+
__le32 queue_id5_min_bw;
7402
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7403
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
7404
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
7405
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
7406
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
7407
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
7408
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7409
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
7410
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7411
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7412
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7413
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7414
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7415
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7416
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
7417
+
__le32 queue_id5_max_bw;
7418
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7419
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
7420
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
7421
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
7422
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
7423
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
7424
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7425
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
7426
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7427
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7428
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7429
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7430
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7431
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7432
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
7433
+
u8 queue_id5_tsa_assign;
7434
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
7435
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
7436
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7437
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
7438
+
u8 queue_id5_pri_lvl;
7439
+
u8 queue_id5_bw_weight;
7440
+
u8 queue_id6;
7441
+
__le32 queue_id6_min_bw;
7442
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7443
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
7444
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
7445
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
7446
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
7447
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
7448
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7449
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
7450
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7451
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7452
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7453
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7454
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7455
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7456
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
7457
+
__le32 queue_id6_max_bw;
7458
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7459
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
7460
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
7461
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
7462
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
7463
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
7464
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7465
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
7466
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7467
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7468
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7469
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7470
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7471
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7472
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
7473
+
u8 queue_id6_tsa_assign;
7474
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
7475
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
7476
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7477
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
7478
+
u8 queue_id6_pri_lvl;
7479
+
u8 queue_id6_bw_weight;
7480
+
u8 queue_id7;
7481
+
__le32 queue_id7_min_bw;
7482
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
7483
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
7484
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
7485
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
7486
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
7487
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
7488
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7489
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
7490
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7491
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7492
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7493
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7494
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7495
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7496
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
7497
+
__le32 queue_id7_max_bw;
7498
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
7499
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
7500
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
7501
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
7502
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
7503
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
7504
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
7505
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
7506
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7507
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
7508
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
7509
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7510
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7511
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7512
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
7513
+
u8 queue_id7_tsa_assign;
7514
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
7515
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
7516
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
7517
+
#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
7518
+
u8 queue_id7_pri_lvl;
7519
+
u8 queue_id7_bw_weight;
7520
+
u8 unused_1[5];
7521
+
};
7522
+
7523
+
/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
7524
+
struct hwrm_queue_cos2bw_cfg_output {
7525
+
__le16 error_code;
7526
+
__le16 req_type;
7527
+
__le16 seq_id;
7528
+
__le16 resp_len;
7529
+
u8 unused_0[7];
7530
+
u8 valid;
7531
+
};
7532
+
7533
+
/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
7534
+
struct hwrm_queue_dscp_qcaps_input {
7535
+
__le16 req_type;
7536
+
__le16 cmpl_ring;
7537
+
__le16 seq_id;
7538
+
__le16 target_id;
7539
+
__le64 resp_addr;
7540
+
u8 port_id;
7541
+
u8 unused_0[7];
7542
+
};
7543
+
7544
+
/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
7545
+
struct hwrm_queue_dscp_qcaps_output {
7546
+
__le16 error_code;
7547
+
__le16 req_type;
7548
+
__le16 seq_id;
7549
+
__le16 resp_len;
7550
+
u8 num_dscp_bits;
7551
+
u8 unused_0;
7552
+
__le16 max_entries;
7553
+
u8 unused_1[3];
7554
+
u8 valid;
7555
+
};
7556
+
7557
+
/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
7558
+
struct hwrm_queue_dscp2pri_qcfg_input {
7559
+
__le16 req_type;
7560
+
__le16 cmpl_ring;
7561
+
__le16 seq_id;
7562
+
__le16 target_id;
7563
+
__le64 resp_addr;
7564
+
__le64 dest_data_addr;
7565
+
u8 port_id;
7566
+
u8 unused_0;
7567
+
__le16 dest_data_buffer_size;
7568
+
u8 unused_1[4];
7569
+
};
7570
+
7571
+
/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
7572
+
struct hwrm_queue_dscp2pri_qcfg_output {
7573
+
__le16 error_code;
7574
+
__le16 req_type;
7575
+
__le16 seq_id;
7576
+
__le16 resp_len;
7577
+
__le16 entry_cnt;
7578
+
u8 default_pri;
7579
+
u8 unused_0[4];
7580
+
u8 valid;
7581
+
};
7582
+
7583
+
/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
7584
+
struct hwrm_queue_dscp2pri_cfg_input {
7585
+
__le16 req_type;
7586
+
__le16 cmpl_ring;
7587
+
__le16 seq_id;
7588
+
__le16 target_id;
7589
+
__le64 resp_addr;
7590
+
__le64 src_data_addr;
7591
+
__le32 flags;
7592
+
#define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
7593
+
__le32 enables;
7594
+
#define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
7595
+
u8 port_id;
7596
+
u8 default_pri;
7597
+
__le16 entry_cnt;
7598
+
u8 unused_0[4];
7599
+
};
7600
+
7601
+
/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
7602
+
struct hwrm_queue_dscp2pri_cfg_output {
7603
+
__le16 error_code;
7604
+
__le16 req_type;
7605
+
__le16 seq_id;
7606
+
__le16 resp_len;
7607
+
u8 unused_0[7];
7608
+
u8 valid;
7609
+
};
7610
+
7611
+
/* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */
7612
+
struct hwrm_queue_pfcwd_timeout_cfg_input {
7613
+
__le16 req_type;
7614
+
__le16 cmpl_ring;
7615
+
__le16 seq_id;
7616
+
__le16 target_id;
7617
+
__le64 resp_addr;
7618
+
__le16 pfcwd_timeout_value;
7619
+
u8 unused_0[6];
7620
+
};
7621
+
7622
+
/* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */
7623
+
struct hwrm_queue_pfcwd_timeout_cfg_output {
7624
+
__le16 error_code;
7625
+
__le16 req_type;
7626
+
__le16 seq_id;
7627
+
__le16 resp_len;
7628
+
u8 unused_0[7];
7629
+
u8 valid;
7630
+
};
7631
+
7632
+
/* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */
7633
+
struct hwrm_queue_pfcwd_timeout_qcfg_input {
7634
+
__le16 req_type;
7635
+
__le16 cmpl_ring;
7636
+
__le16 seq_id;
7637
+
__le16 target_id;
7638
+
__le64 resp_addr;
7639
+
};
7640
+
7641
+
/* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */
7642
+
struct hwrm_queue_pfcwd_timeout_qcfg_output {
7643
+
__le16 error_code;
7644
+
__le16 req_type;
7645
+
__le16 seq_id;
7646
+
__le16 resp_len;
7647
+
__le16 pfcwd_timeout_value;
7648
+
u8 unused_0[5];
7649
+
u8 valid;
7650
+
};
7651
+
7652
+
/* hwrm_vnic_alloc_input (size:192b/24B) */
7653
+
struct hwrm_vnic_alloc_input {
7654
+
__le16 req_type;
7655
+
__le16 cmpl_ring;
7656
+
__le16 seq_id;
7657
+
__le16 target_id;
7658
+
__le64 resp_addr;
7659
+
__le32 flags;
7660
+
#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
7661
+
#define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL
7662
+
#define VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID 0x4UL
7663
+
__le16 virtio_net_fid;
7664
+
__le16 vnic_id;
7665
+
};
7666
+
7667
+
/* hwrm_vnic_alloc_output (size:128b/16B) */
7668
+
struct hwrm_vnic_alloc_output {
7669
+
__le16 error_code;
7670
+
__le16 req_type;
7671
+
__le16 seq_id;
7672
+
__le16 resp_len;
7673
+
__le32 vnic_id;
7674
+
u8 unused_0[3];
7675
+
u8 valid;
7676
+
};
7677
+
7678
+
/* hwrm_vnic_update_input (size:256b/32B) */
7679
+
struct hwrm_vnic_update_input {
7680
+
__le16 req_type;
7681
+
__le16 cmpl_ring;
7682
+
__le16 seq_id;
7683
+
__le16 target_id;
7684
+
__le64 resp_addr;
7685
+
__le32 vnic_id;
7686
+
__le32 enables;
7687
+
#define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID 0x1UL
7688
+
#define VNIC_UPDATE_REQ_ENABLES_MRU_VALID 0x2UL
7689
+
#define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID 0x4UL
7690
+
u8 vnic_state;
7691
+
#define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL
7692
+
#define VNIC_UPDATE_REQ_VNIC_STATE_DROP 0x1UL
7693
+
#define VNIC_UPDATE_REQ_VNIC_STATE_LAST VNIC_UPDATE_REQ_VNIC_STATE_DROP
7694
+
u8 metadata_format_type;
7695
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL
7696
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL
7697
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL
7698
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL
7699
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL
7700
+
#define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4
7701
+
__le16 mru;
7702
+
u8 unused_1[4];
7703
+
};
7704
+
7705
+
/* hwrm_vnic_update_output (size:128b/16B) */
7706
+
struct hwrm_vnic_update_output {
7707
+
__le16 error_code;
7708
+
__le16 req_type;
7709
+
__le16 seq_id;
7710
+
__le16 resp_len;
7711
+
u8 unused_0[7];
7712
+
u8 valid;
7713
+
};
7714
+
7715
+
/* hwrm_vnic_free_input (size:192b/24B) */
7716
+
struct hwrm_vnic_free_input {
7717
+
__le16 req_type;
7718
+
__le16 cmpl_ring;
7719
+
__le16 seq_id;
7720
+
__le16 target_id;
7721
+
__le64 resp_addr;
7722
+
__le32 vnic_id;
7723
+
u8 unused_0[4];
7724
+
};
7725
+
7726
+
/* hwrm_vnic_free_output (size:128b/16B) */
7727
+
struct hwrm_vnic_free_output {
7728
+
__le16 error_code;
7729
+
__le16 req_type;
7730
+
__le16 seq_id;
7731
+
__le16 resp_len;
7732
+
u8 unused_0[7];
7733
+
u8 valid;
7734
+
};
7735
+
7736
+
/* hwrm_vnic_cfg_input (size:384b/48B) */
7737
+
struct hwrm_vnic_cfg_input {
7738
+
__le16 req_type;
7739
+
__le16 cmpl_ring;
7740
+
__le16 seq_id;
7741
+
__le16 target_id;
7742
+
__le64 resp_addr;
7743
+
__le32 flags;
7744
+
#define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
7745
+
#define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
7746
+
#define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
7747
+
#define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
7748
+
#define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
7749
+
#define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
7750
+
#define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
7751
+
#define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL
7752
+
__le32 enables;
7753
+
#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
7754
+
#define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
7755
+
#define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
7756
+
#define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
7757
+
#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
7758
+
#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
7759
+
#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
7760
+
#define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
7761
+
#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
7762
+
#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL
7763
+
#define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL
7764
+
__le16 vnic_id;
7765
+
__le16 dflt_ring_grp;
7766
+
__le16 rss_rule;
7767
+
__le16 cos_rule;
7768
+
__le16 lb_rule;
7769
+
__le16 mru;
7770
+
__le16 default_rx_ring_id;
7771
+
__le16 default_cmpl_ring_id;
7772
+
__le16 queue_id;
7773
+
u8 rx_csum_v2_mode;
7774
+
#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
7775
+
#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL
7776
+
#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL
7777
+
#define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
7778
+
u8 l2_cqe_mode;
7779
+
#define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL
7780
+
#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
7781
+
#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL
7782
+
#define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED
7783
+
__le32 raw_qp_id;
7784
+
};
7785
+
7786
+
/* hwrm_vnic_cfg_output (size:128b/16B) */
7787
+
struct hwrm_vnic_cfg_output {
7788
+
__le16 error_code;
7789
+
__le16 req_type;
7790
+
__le16 seq_id;
7791
+
__le16 resp_len;
7792
+
u8 unused_0[7];
7793
+
u8 valid;
7794
+
};
7795
+
7796
+
/* hwrm_vnic_qcaps_input (size:192b/24B) */
7797
+
struct hwrm_vnic_qcaps_input {
7798
+
__le16 req_type;
7799
+
__le16 cmpl_ring;
7800
+
__le16 seq_id;
7801
+
__le16 target_id;
7802
+
__le64 resp_addr;
7803
+
__le32 enables;
7804
+
u8 unused_0[4];
7805
+
};
7806
+
7807
+
/* hwrm_vnic_qcaps_output (size:192b/24B) */
7808
+
struct hwrm_vnic_qcaps_output {
7809
+
__le16 error_code;
7810
+
__le16 req_type;
7811
+
__le16 seq_id;
7812
+
__le16 resp_len;
7813
+
__le16 mru;
7814
+
u8 unused_0[2];
7815
+
__le32 flags;
7816
+
#define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
7817
+
#define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
7818
+
#define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
7819
+
#define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
7820
+
#define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
7821
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
7822
+
#define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
7823
+
#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
7824
+
#define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
7825
+
#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL
7826
+
#define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL
7827
+
#define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL
7828
+
#define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL
7829
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL
7830
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL
7831
+
#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL
7832
+
#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL
7833
+
#define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL
7834
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL
7835
+
#define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL
7836
+
#define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL
7837
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL
7838
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL
7839
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL
7840
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL
7841
+
#define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL
7842
+
#define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL
7843
+
#define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL
7844
+
#define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL
7845
+
#define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL
7846
+
#define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP 0x40000000UL
7847
+
__le16 max_aggs_supported;
7848
+
u8 unused_1[5];
7849
+
u8 valid;
7850
+
};
7851
+
7852
+
/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */
7853
+
struct hwrm_vnic_tpa_cfg_input {
7854
+
__le16 req_type;
7855
+
__le16 cmpl_ring;
7856
+
__le16 seq_id;
7857
+
__le16 target_id;
7858
+
__le64 resp_addr;
7859
+
__le32 flags;
7860
+
#define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
7861
+
#define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
7862
+
#define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
7863
+
#define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
7864
+
#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
7865
+
#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
7866
+
#define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
7867
+
#define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
7868
+
#define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
7869
+
__le32 enables;
7870
+
#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
7871
+
#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
7872
+
#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
7873
+
#define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
7874
+
#define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL
7875
+
__le16 vnic_id;
7876
+
__le16 max_agg_segs;
7877
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
7878
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
7879
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
7880
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
7881
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
7882
+
#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
7883
+
__le16 max_aggs;
7884
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
7885
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
7886
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
7887
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
7888
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
7889
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
7890
+
#define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
7891
+
u8 unused_0[2];
7892
+
__le32 max_agg_timer;
7893
+
__le32 min_agg_len;
7894
+
__le32 tnl_tpa_en_bitmap;
7895
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL
7896
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL
7897
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL
7898
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL
7899
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL
7900
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL
7901
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL
7902
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL
7903
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL
7904
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL
7905
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL
7906
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL
7907
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL
7908
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL
7909
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL
7910
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL
7911
+
#define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL
7912
+
u8 unused_1[4];
7913
+
};
7914
+
7915
+
/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
7916
+
struct hwrm_vnic_tpa_cfg_output {
7917
+
__le16 error_code;
7918
+
__le16 req_type;
7919
+
__le16 seq_id;
7920
+
__le16 resp_len;
7921
+
u8 unused_0[7];
7922
+
u8 valid;
7923
+
};
7924
+
7925
+
/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
7926
+
struct hwrm_vnic_tpa_qcfg_input {
7927
+
__le16 req_type;
7928
+
__le16 cmpl_ring;
7929
+
__le16 seq_id;
7930
+
__le16 target_id;
7931
+
__le64 resp_addr;
7932
+
__le16 vnic_id;
7933
+
u8 unused_0[6];
7934
+
};
7935
+
7936
+
/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
7937
+
struct hwrm_vnic_tpa_qcfg_output {
7938
+
__le16 error_code;
7939
+
__le16 req_type;
7940
+
__le16 seq_id;
7941
+
__le16 resp_len;
7942
+
__le32 flags;
7943
+
#define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
7944
+
#define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
7945
+
#define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
7946
+
#define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
7947
+
#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
7948
+
#define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
7949
+
#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
7950
+
#define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
7951
+
__le16 max_agg_segs;
7952
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
7953
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
7954
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
7955
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
7956
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
7957
+
#define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
7958
+
__le16 max_aggs;
7959
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
7960
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
7961
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
7962
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
7963
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
7964
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
7965
+
#define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
7966
+
__le32 max_agg_timer;
7967
+
__le32 min_agg_len;
7968
+
__le32 tnl_tpa_en_bitmap;
7969
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL
7970
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL
7971
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL
7972
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL
7973
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL
7974
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL
7975
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL
7976
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL
7977
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL
7978
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL
7979
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL
7980
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL
7981
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL
7982
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL
7983
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL
7984
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL
7985
+
#define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL
7986
+
u8 unused_0[3];
7987
+
u8 valid;
7988
+
};
7989
+
7990
+
/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
7991
+
struct hwrm_vnic_rss_cfg_input {
7992
+
__le16 req_type;
7993
+
__le16 cmpl_ring;
7994
+
__le16 seq_id;
7995
+
__le16 target_id;
7996
+
__le64 resp_addr;
7997
+
__le32 hash_type;
7998
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
7999
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
8000
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
8001
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
8002
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
8003
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
8004
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
8005
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL
8006
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL
8007
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL
8008
+
#define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL
8009
+
__le16 vnic_id;
8010
+
u8 ring_table_pair_index;
8011
+
u8 hash_mode_flags;
8012
+
#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
8013
+
#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
8014
+
#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
8015
+
#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
8016
+
#define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
8017
+
__le64 ring_grp_tbl_addr;
8018
+
__le64 hash_key_tbl_addr;
8019
+
__le16 rss_ctx_idx;
8020
+
u8 flags;
8021
+
#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL
8022
+
#define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL
8023
+
#define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL
8024
+
u8 ring_select_mode;
8025
+
#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL
8026
+
#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL
8027
+
#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
8028
+
#define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
8029
+
u8 unused_1[4];
8030
+
};
8031
+
8032
+
/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
8033
+
struct hwrm_vnic_rss_cfg_output {
8034
+
__le16 error_code;
8035
+
__le16 req_type;
8036
+
__le16 seq_id;
8037
+
__le16 resp_len;
8038
+
u8 unused_0[7];
8039
+
u8 valid;
8040
+
};
8041
+
8042
+
/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
8043
+
struct hwrm_vnic_rss_cfg_cmd_err {
8044
+
u8 code;
8045
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
8046
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
8047
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_UNABLE_TO_GET_RSS_CFG 0x2UL
8048
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_UNSUPPORTED 0x3UL
8049
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_ERR 0x4UL
8050
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_MODE_FAIL 0x5UL
8051
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_RING_GRP_TABLE_ALLOC_ERR 0x6UL
8052
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_KEY_ALLOC_ERR 0x7UL
8053
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_DMA_FAILED 0x8UL
8054
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_RX_RING_ALLOC_ERR 0x9UL
8055
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_CMPL_RING_ALLOC_ERR 0xaUL
8056
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_HW_SET_RSS_FAILED 0xbUL
8057
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_CTX_INVALID 0xcUL
8058
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_INVALID 0xdUL
8059
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 0xeUL
8060
+
#define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID
8061
+
u8 unused_0[7];
8062
+
};
8063
+
8064
+
/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
8065
+
struct hwrm_vnic_rss_qcfg_input {
8066
+
__le16 req_type;
8067
+
__le16 cmpl_ring;
8068
+
__le16 seq_id;
8069
+
__le16 target_id;
8070
+
__le64 resp_addr;
8071
+
__le16 rss_ctx_idx;
8072
+
__le16 vnic_id;
8073
+
u8 unused_0[4];
8074
+
};
8075
+
8076
+
/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
8077
+
struct hwrm_vnic_rss_qcfg_output {
8078
+
__le16 error_code;
8079
+
__le16 req_type;
8080
+
__le16 seq_id;
8081
+
__le16 resp_len;
8082
+
__le32 hash_type;
8083
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL
8084
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL
8085
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL
8086
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL
8087
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL
8088
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL
8089
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
8090
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL
8091
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL
8092
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL
8093
+
#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL
8094
+
u8 unused_0[4];
8095
+
__le32 hash_key[10];
8096
+
u8 hash_mode_flags;
8097
+
#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL
8098
+
#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
8099
+
#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
8100
+
#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
8101
+
#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
8102
+
u8 ring_select_mode;
8103
+
#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL
8104
+
#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL
8105
+
#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
8106
+
#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
8107
+
u8 unused_1[5];
8108
+
u8 valid;
8109
+
};
8110
+
8111
+
/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
8112
+
struct hwrm_vnic_plcmodes_cfg_input {
8113
+
__le16 req_type;
8114
+
__le16 cmpl_ring;
8115
+
__le16 seq_id;
8116
+
__le16 target_id;
8117
+
__le64 resp_addr;
8118
+
__le32 flags;
8119
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
8120
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
8121
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
8122
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
8123
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
8124
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
8125
+
#define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL
8126
+
__le32 enables;
8127
+
#define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
8128
+
#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
8129
+
#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
8130
+
#define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL
8131
+
__le32 vnic_id;
8132
+
__le16 jumbo_thresh;
8133
+
__le16 hds_offset;
8134
+
__le16 hds_threshold;
8135
+
__le16 max_bds;
8136
+
u8 unused_0[4];
8137
+
};
8138
+
8139
+
/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
8140
+
struct hwrm_vnic_plcmodes_cfg_output {
8141
+
__le16 error_code;
8142
+
__le16 req_type;
8143
+
__le16 seq_id;
8144
+
__le16 resp_len;
8145
+
u8 unused_0[7];
8146
+
u8 valid;
8147
+
};
8148
+
8149
+
/* hwrm_vnic_plcmodes_cfg_cmd_err (size:64b/8B) */
8150
+
struct hwrm_vnic_plcmodes_cfg_cmd_err {
8151
+
u8 code;
8152
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
8153
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 0x1UL
8154
+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_LAST VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD
8155
+
u8 unused_0[7];
8156
+
};
8157
+
8158
+
/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
8159
+
struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
8160
+
__le16 req_type;
8161
+
__le16 cmpl_ring;
8162
+
__le16 seq_id;
8163
+
__le16 target_id;
8164
+
__le64 resp_addr;
8165
+
};
8166
+
8167
+
/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
8168
+
struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
8169
+
__le16 error_code;
8170
+
__le16 req_type;
8171
+
__le16 seq_id;
8172
+
__le16 resp_len;
8173
+
__le16 rss_cos_lb_ctx_id;
8174
+
u8 unused_0[5];
8175
+
u8 valid;
8176
+
};
8177
+
8178
+
/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
8179
+
struct hwrm_vnic_rss_cos_lb_ctx_free_input {
8180
+
__le16 req_type;
8181
+
__le16 cmpl_ring;
8182
+
__le16 seq_id;
8183
+
__le16 target_id;
8184
+
__le64 resp_addr;
8185
+
__le16 rss_cos_lb_ctx_id;
8186
+
u8 unused_0[6];
8187
+
};
8188
+
8189
+
/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
8190
+
struct hwrm_vnic_rss_cos_lb_ctx_free_output {
8191
+
__le16 error_code;
8192
+
__le16 req_type;
8193
+
__le16 seq_id;
8194
+
__le16 resp_len;
8195
+
u8 unused_0[7];
8196
+
u8 valid;
8197
+
};
8198
+
8199
+
/* hwrm_ring_alloc_input (size:768b/96B) */
8200
+
struct hwrm_ring_alloc_input {
8201
+
__le16 req_type;
8202
+
__le16 cmpl_ring;
8203
+
__le16 seq_id;
8204
+
__le16 target_id;
8205
+
__le64 resp_addr;
8206
+
__le32 enables;
8207
+
#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
8208
+
#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
8209
+
#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
8210
+
#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
8211
+
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
8212
+
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
8213
+
#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
8214
+
#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
8215
+
#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
8216
+
#define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL
8217
+
#define RING_ALLOC_REQ_ENABLES_DPI_VALID 0x2000UL
8218
+
u8 ring_type;
8219
+
#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
8220
+
#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
8221
+
#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
8222
+
#define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
8223
+
#define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
8224
+
#define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
8225
+
#define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
8226
+
u8 cmpl_coal_cnt;
8227
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL
8228
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL
8229
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL
8230
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL
8231
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL
8232
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL
8233
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL
8234
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL
8235
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL
8236
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL
8237
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL
8238
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL
8239
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL
8240
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL
8241
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL
8242
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL
8243
+
#define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX
8244
+
__le16 flags;
8245
+
#define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
8246
+
#define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL
8247
+
#define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL
8248
+
#define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL
8249
+
__le64 page_tbl_addr;
8250
+
__le32 fbo;
8251
+
u8 page_size;
8252
+
u8 page_tbl_depth;
8253
+
__le16 schq_id;
8254
+
__le32 length;
8255
+
__le16 logical_id;
8256
+
__le16 cmpl_ring_id;
8257
+
__le16 queue_id;
8258
+
__le16 rx_buf_size;
8259
+
__le16 rx_ring_id;
8260
+
__le16 nq_ring_id;
8261
+
__le16 ring_arb_cfg;
8262
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
8263
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
8264
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
8265
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
8266
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
8267
+
#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
8268
+
#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
8269
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
8270
+
#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
8271
+
__le16 steering_tag;
8272
+
__le32 reserved3;
8273
+
__le32 stat_ctx_id;
8274
+
__le32 reserved4;
8275
+
__le32 max_bw;
8276
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
8277
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
8278
+
#define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
8279
+
#define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
8280
+
#define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
8281
+
#define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
8282
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
8283
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
8284
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
8285
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
8286
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
8287
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
8288
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
8289
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
8290
+
#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
8291
+
u8 int_mode;
8292
+
#define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
8293
+
#define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
8294
+
#define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
8295
+
#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
8296
+
#define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
8297
+
u8 mpc_chnls_type;
8298
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL
8299
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL
8300
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL
8301
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
8302
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
8303
+
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
8304
+
u8 rx_rate_profile_sel;
8305
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_DEFAULT 0x0UL
8306
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 0x1UL
8307
+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE
8308
+
u8 unused_4;
8309
+
__le64 cq_handle;
8310
+
__le16 dpi;
8311
+
__le16 unused_5[3];
8312
+
};
8313
+
8314
+
/* hwrm_ring_alloc_output (size:128b/16B) */
8315
+
struct hwrm_ring_alloc_output {
8316
+
__le16 error_code;
8317
+
__le16 req_type;
8318
+
__le16 seq_id;
8319
+
__le16 resp_len;
8320
+
__le16 ring_id;
8321
+
__le16 logical_ring_id;
8322
+
u8 push_buffer_index;
8323
+
#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
8324
+
#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
8325
+
#define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
8326
+
u8 unused_0[2];
8327
+
u8 valid;
8328
+
};
8329
+
8330
+
/* hwrm_ring_free_input (size:256b/32B) */
8331
+
struct hwrm_ring_free_input {
8332
+
__le16 req_type;
8333
+
__le16 cmpl_ring;
8334
+
__le16 seq_id;
8335
+
__le16 target_id;
8336
+
__le64 resp_addr;
8337
+
u8 ring_type;
8338
+
#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
8339
+
#define RING_FREE_REQ_RING_TYPE_TX 0x1UL
8340
+
#define RING_FREE_REQ_RING_TYPE_RX 0x2UL
8341
+
#define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
8342
+
#define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
8343
+
#define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
8344
+
#define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
8345
+
u8 flags;
8346
+
#define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL
8347
+
#define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID
8348
+
__le16 ring_id;
8349
+
__le32 prod_idx;
8350
+
__le32 opaque;
8351
+
__le32 unused_1;
8352
+
};
8353
+
8354
+
/* hwrm_ring_free_output (size:128b/16B) */
8355
+
struct hwrm_ring_free_output {
8356
+
__le16 error_code;
8357
+
__le16 req_type;
8358
+
__le16 seq_id;
8359
+
__le16 resp_len;
8360
+
u8 unused_0[7];
8361
+
u8 valid;
8362
+
};
8363
+
8364
+
/* hwrm_ring_reset_input (size:192b/24B) */
8365
+
struct hwrm_ring_reset_input {
8366
+
__le16 req_type;
8367
+
__le16 cmpl_ring;
8368
+
__le16 seq_id;
8369
+
__le16 target_id;
8370
+
__le64 resp_addr;
8371
+
u8 ring_type;
8372
+
#define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
8373
+
#define RING_RESET_REQ_RING_TYPE_TX 0x1UL
8374
+
#define RING_RESET_REQ_RING_TYPE_RX 0x2UL
8375
+
#define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
8376
+
#define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
8377
+
#define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP
8378
+
u8 unused_0;
8379
+
__le16 ring_id;
8380
+
u8 unused_1[4];
8381
+
};
8382
+
8383
+
/* hwrm_ring_reset_output (size:128b/16B) */
8384
+
struct hwrm_ring_reset_output {
8385
+
__le16 error_code;
8386
+
__le16 req_type;
8387
+
__le16 seq_id;
8388
+
__le16 resp_len;
8389
+
u8 push_buffer_index;
8390
+
#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
8391
+
#define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
8392
+
#define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
8393
+
u8 unused_0[3];
8394
+
u8 consumer_idx[3];
8395
+
u8 valid;
8396
+
};
8397
+
8398
+
/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
8399
+
struct hwrm_ring_aggint_qcaps_input {
8400
+
__le16 req_type;
8401
+
__le16 cmpl_ring;
8402
+
__le16 seq_id;
8403
+
__le16 target_id;
8404
+
__le64 resp_addr;
8405
+
};
8406
+
8407
+
/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
8408
+
struct hwrm_ring_aggint_qcaps_output {
8409
+
__le16 error_code;
8410
+
__le16 req_type;
8411
+
__le16 seq_id;
8412
+
__le16 resp_len;
8413
+
__le32 cmpl_params;
8414
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
8415
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
8416
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
8417
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
8418
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
8419
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
8420
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
8421
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
8422
+
#define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
8423
+
__le32 nq_params;
8424
+
#define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
8425
+
__le16 num_cmpl_dma_aggr_min;
8426
+
__le16 num_cmpl_dma_aggr_max;
8427
+
__le16 num_cmpl_dma_aggr_during_int_min;
8428
+
__le16 num_cmpl_dma_aggr_during_int_max;
8429
+
__le16 cmpl_aggr_dma_tmr_min;
8430
+
__le16 cmpl_aggr_dma_tmr_max;
8431
+
__le16 cmpl_aggr_dma_tmr_during_int_min;
8432
+
__le16 cmpl_aggr_dma_tmr_during_int_max;
8433
+
__le16 int_lat_tmr_min_min;
8434
+
__le16 int_lat_tmr_min_max;
8435
+
__le16 int_lat_tmr_max_min;
8436
+
__le16 int_lat_tmr_max_max;
8437
+
__le16 num_cmpl_aggr_int_min;
8438
+
__le16 num_cmpl_aggr_int_max;
8439
+
__le16 timer_units;
8440
+
u8 unused_0[1];
8441
+
u8 valid;
8442
+
};
8443
+
8444
+
/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
8445
+
struct hwrm_ring_cmpl_ring_qaggint_params_input {
8446
+
__le16 req_type;
8447
+
__le16 cmpl_ring;
8448
+
__le16 seq_id;
8449
+
__le16 target_id;
8450
+
__le64 resp_addr;
8451
+
__le16 ring_id;
8452
+
__le16 flags;
8453
+
#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
8454
+
#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
8455
+
#define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
8456
+
u8 unused_0[4];
8457
+
};
8458
+
8459
+
/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
8460
+
struct hwrm_ring_cmpl_ring_qaggint_params_output {
8461
+
__le16 error_code;
8462
+
__le16 req_type;
8463
+
__le16 seq_id;
8464
+
__le16 resp_len;
8465
+
__le16 flags;
8466
+
#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
8467
+
#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
8468
+
__le16 num_cmpl_dma_aggr;
8469
+
__le16 num_cmpl_dma_aggr_during_int;
8470
+
__le16 cmpl_aggr_dma_tmr;
8471
+
__le16 cmpl_aggr_dma_tmr_during_int;
8472
+
__le16 int_lat_tmr_min;
8473
+
__le16 int_lat_tmr_max;
8474
+
__le16 num_cmpl_aggr_int;
8475
+
u8 unused_0[7];
8476
+
u8 valid;
8477
+
};
8478
+
8479
+
/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
8480
+
struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
8481
+
__le16 req_type;
8482
+
__le16 cmpl_ring;
8483
+
__le16 seq_id;
8484
+
__le16 target_id;
8485
+
__le64 resp_addr;
8486
+
__le16 ring_id;
8487
+
__le16 flags;
8488
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
8489
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
8490
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
8491
+
__le16 num_cmpl_dma_aggr;
8492
+
__le16 num_cmpl_dma_aggr_during_int;
8493
+
__le16 cmpl_aggr_dma_tmr;
8494
+
__le16 cmpl_aggr_dma_tmr_during_int;
8495
+
__le16 int_lat_tmr_min;
8496
+
__le16 int_lat_tmr_max;
8497
+
__le16 num_cmpl_aggr_int;
8498
+
__le16 enables;
8499
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
8500
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
8501
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
8502
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
8503
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
8504
+
#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
8505
+
u8 unused_0[4];
8506
+
};
8507
+
8508
+
/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
8509
+
struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
8510
+
__le16 error_code;
8511
+
__le16 req_type;
8512
+
__le16 seq_id;
8513
+
__le16 resp_len;
8514
+
u8 unused_0[7];
8515
+
u8 valid;
8516
+
};
8517
+
8518
+
/* hwrm_ring_grp_alloc_input (size:192b/24B) */
8519
+
struct hwrm_ring_grp_alloc_input {
8520
+
__le16 req_type;
8521
+
__le16 cmpl_ring;
8522
+
__le16 seq_id;
8523
+
__le16 target_id;
8524
+
__le64 resp_addr;
8525
+
__le16 cr;
8526
+
__le16 rr;
8527
+
__le16 ar;
8528
+
__le16 sc;
8529
+
};
8530
+
8531
+
/* hwrm_ring_grp_alloc_output (size:128b/16B) */
8532
+
struct hwrm_ring_grp_alloc_output {
8533
+
__le16 error_code;
8534
+
__le16 req_type;
8535
+
__le16 seq_id;
8536
+
__le16 resp_len;
8537
+
__le32 ring_group_id;
8538
+
u8 unused_0[3];
8539
+
u8 valid;
8540
+
};
8541
+
8542
+
/* hwrm_ring_grp_free_input (size:192b/24B) */
8543
+
struct hwrm_ring_grp_free_input {
8544
+
__le16 req_type;
8545
+
__le16 cmpl_ring;
8546
+
__le16 seq_id;
8547
+
__le16 target_id;
8548
+
__le64 resp_addr;
8549
+
__le32 ring_group_id;
8550
+
u8 unused_0[4];
8551
+
};
8552
+
8553
+
/* hwrm_ring_grp_free_output (size:128b/16B) */
8554
+
struct hwrm_ring_grp_free_output {
8555
+
__le16 error_code;
8556
+
__le16 req_type;
8557
+
__le16 seq_id;
8558
+
__le16 resp_len;
8559
+
u8 unused_0[7];
8560
+
u8 valid;
8561
+
};
8562
+
8563
+
#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
8564
+
#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
8565
+
#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
8566
+
#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
8567
+
8568
+
/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
8569
+
struct hwrm_cfa_l2_filter_alloc_input {
8570
+
__le16 req_type;
8571
+
__le16 cmpl_ring;
8572
+
__le16 seq_id;
8573
+
__le16 target_id;
8574
+
__le64 resp_addr;
8575
+
__le32 flags;
8576
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
8577
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
8578
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
8579
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
8580
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
8581
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
8582
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
8583
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
8584
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
8585
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
8586
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
8587
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
8588
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
8589
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
8590
+
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
8591
+
__le32 enables;
8592
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
8593
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
8594
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
8595
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
8596
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
8597
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
8598
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
8599
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
8600
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
8601
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
8602
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
8603
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
8604
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
8605
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
8606
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
8607
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
8608
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
8609
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
8610
+
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
8611
+
u8 l2_addr[6];
8612
+
u8 num_vlans;
8613
+
u8 t_num_vlans;
8614
+
u8 l2_addr_mask[6];
8615
+
__le16 l2_ovlan;
8616
+
__le16 l2_ovlan_mask;
8617
+
__le16 l2_ivlan;
8618
+
__le16 l2_ivlan_mask;
8619
+
u8 unused_1[2];
8620
+
u8 t_l2_addr[6];
8621
+
u8 unused_2[2];
8622
+
u8 t_l2_addr_mask[6];
8623
+
__le16 t_l2_ovlan;
8624
+
__le16 t_l2_ovlan_mask;
8625
+
__le16 t_l2_ivlan;
8626
+
__le16 t_l2_ivlan_mask;
8627
+
u8 src_type;
8628
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
8629
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
8630
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
8631
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
8632
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
8633
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
8634
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
8635
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
8636
+
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
8637
+
u8 unused_3;
8638
+
__le32 src_id;
8639
+
u8 tunnel_type;
8640
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
8641
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8642
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
8643
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
8644
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
8645
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8646
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
8647
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
8648
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
8649
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8650
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8651
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8652
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8653
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
8654
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
8655
+
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
8656
+
u8 unused_4;
8657
+
__le16 dst_id;
8658
+
__le16 mirror_vnic_id;
8659
+
u8 pri_hint;
8660
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
8661
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
8662
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
8663
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
8664
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
8665
+
#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
8666
+
u8 unused_5;
8667
+
__le32 unused_6;
8668
+
__le64 l2_filter_id_hint;
8669
+
};
8670
+
8671
+
/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
8672
+
struct hwrm_cfa_l2_filter_alloc_output {
8673
+
__le16 error_code;
8674
+
__le16 req_type;
8675
+
__le16 seq_id;
8676
+
__le16 resp_len;
8677
+
__le64 l2_filter_id;
8678
+
__le32 flow_id;
8679
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
8680
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
8681
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
8682
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
8683
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
8684
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
8685
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
8686
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
8687
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
8688
+
#define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
8689
+
u8 unused_0[3];
8690
+
u8 valid;
8691
+
};
8692
+
8693
+
/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
8694
+
struct hwrm_cfa_l2_filter_free_input {
8695
+
__le16 req_type;
8696
+
__le16 cmpl_ring;
8697
+
__le16 seq_id;
8698
+
__le16 target_id;
8699
+
__le64 resp_addr;
8700
+
__le64 l2_filter_id;
8701
+
};
8702
+
8703
+
/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
8704
+
struct hwrm_cfa_l2_filter_free_output {
8705
+
__le16 error_code;
8706
+
__le16 req_type;
8707
+
__le16 seq_id;
8708
+
__le16 resp_len;
8709
+
u8 unused_0[7];
8710
+
u8 valid;
8711
+
};
8712
+
8713
+
/* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */
8714
+
struct hwrm_cfa_l2_filter_cfg_input {
8715
+
__le16 req_type;
8716
+
__le16 cmpl_ring;
8717
+
__le16 seq_id;
8718
+
__le16 target_id;
8719
+
__le64 resp_addr;
8720
+
__le32 flags;
8721
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
8722
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
8723
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
8724
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
8725
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
8726
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
8727
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
8728
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
8729
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
8730
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
8731
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
8732
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL
8733
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4
8734
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4)
8735
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4)
8736
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4)
8737
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP (0x3UL << 4)
8738
+
#define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP
8739
+
__le32 enables;
8740
+
#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
8741
+
#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
8742
+
#define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL
8743
+
#define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL
8744
+
__le64 l2_filter_id;
8745
+
__le32 dst_id;
8746
+
__le32 new_mirror_vnic_id;
8747
+
__le32 prof_func;
8748
+
__le32 l2_context_id;
8749
+
};
8750
+
8751
+
/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
8752
+
struct hwrm_cfa_l2_filter_cfg_output {
8753
+
__le16 error_code;
8754
+
__le16 req_type;
8755
+
__le16 seq_id;
8756
+
__le16 resp_len;
8757
+
u8 unused_0[7];
8758
+
u8 valid;
8759
+
};
8760
+
8761
+
/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
8762
+
struct hwrm_cfa_l2_set_rx_mask_input {
8763
+
__le16 req_type;
8764
+
__le16 cmpl_ring;
8765
+
__le16 seq_id;
8766
+
__le16 target_id;
8767
+
__le64 resp_addr;
8768
+
__le32 vnic_id;
8769
+
__le32 mask;
8770
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
8771
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
8772
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
8773
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
8774
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
8775
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
8776
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
8777
+
#define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
8778
+
__le64 mc_tbl_addr;
8779
+
__le32 num_mc_entries;
8780
+
u8 unused_0[4];
8781
+
__le64 vlan_tag_tbl_addr;
8782
+
__le32 num_vlan_tags;
8783
+
u8 unused_1[4];
8784
+
};
8785
+
8786
+
/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
8787
+
struct hwrm_cfa_l2_set_rx_mask_output {
8788
+
__le16 error_code;
8789
+
__le16 req_type;
8790
+
__le16 seq_id;
8791
+
__le16 resp_len;
8792
+
u8 unused_0[7];
8793
+
u8 valid;
8794
+
};
8795
+
8796
+
/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
8797
+
struct hwrm_cfa_l2_set_rx_mask_cmd_err {
8798
+
u8 code;
8799
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
8800
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
8801
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_MAX_VLAN_TAGS 0x2UL
8802
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_VNIC_ID 0x3UL
8803
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 0x4UL
8804
+
#define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION
8805
+
u8 unused_0[7];
8806
+
};
8807
+
8808
+
/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
8809
+
struct hwrm_cfa_tunnel_filter_alloc_input {
8810
+
__le16 req_type;
8811
+
__le16 cmpl_ring;
8812
+
__le16 seq_id;
8813
+
__le16 target_id;
8814
+
__le64 resp_addr;
8815
+
__le32 flags;
8816
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
8817
+
__le32 enables;
8818
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
8819
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
8820
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
8821
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
8822
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
8823
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
8824
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
8825
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
8826
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
8827
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
8828
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
8829
+
__le64 l2_filter_id;
8830
+
u8 l2_addr[6];
8831
+
__le16 l2_ivlan;
8832
+
__le32 l3_addr[4];
8833
+
__le32 t_l3_addr[4];
8834
+
u8 l3_addr_type;
8835
+
u8 t_l3_addr_type;
8836
+
u8 tunnel_type;
8837
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
8838
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8839
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
8840
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
8841
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
8842
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8843
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
8844
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
8845
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
8846
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8847
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8848
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8849
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8850
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
8851
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
8852
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
8853
+
u8 tunnel_flags;
8854
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
8855
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
8856
+
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
8857
+
__le32 vni;
8858
+
__le32 dst_vnic_id;
8859
+
__le32 mirror_vnic_id;
8860
+
};
8861
+
8862
+
/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
8863
+
struct hwrm_cfa_tunnel_filter_alloc_output {
8864
+
__le16 error_code;
8865
+
__le16 req_type;
8866
+
__le16 seq_id;
8867
+
__le16 resp_len;
8868
+
__le64 tunnel_filter_id;
8869
+
__le32 flow_id;
8870
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
8871
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
8872
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
8873
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
8874
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
8875
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
8876
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
8877
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
8878
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
8879
+
#define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
8880
+
u8 unused_0[3];
8881
+
u8 valid;
8882
+
};
8883
+
8884
+
/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
8885
+
struct hwrm_cfa_tunnel_filter_free_input {
8886
+
__le16 req_type;
8887
+
__le16 cmpl_ring;
8888
+
__le16 seq_id;
8889
+
__le16 target_id;
8890
+
__le64 resp_addr;
8891
+
__le64 tunnel_filter_id;
8892
+
};
8893
+
8894
+
/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
8895
+
struct hwrm_cfa_tunnel_filter_free_output {
8896
+
__le16 error_code;
8897
+
__le16 req_type;
8898
+
__le16 seq_id;
8899
+
__le16 resp_len;
8900
+
u8 unused_0[7];
8901
+
u8 valid;
8902
+
};
8903
+
8904
+
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
8905
+
struct hwrm_cfa_ntuple_filter_alloc_output {
8906
+
__le16 error_code;
8907
+
__le16 req_type;
8908
+
__le16 seq_id;
8909
+
__le16 resp_len;
8910
+
__le64 ntuple_filter_id;
8911
+
__le32 flow_id;
8912
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
8913
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
8914
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
8915
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
8916
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
8917
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
8918
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
8919
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
8920
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
8921
+
#define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
8922
+
u8 unused_0[3];
8923
+
u8 valid;
8924
+
};
8925
+
8926
+
/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
8927
+
struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
8928
+
u8 code;
8929
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
8930
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_MAC 0x65UL
8931
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_BC_MC_MAC 0x66UL
8932
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_VNIC 0x67UL
8933
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_PF_FID 0x68UL
8934
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L2_CTXT_ID 0x69UL
8935
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_CTXT_CFG 0x6aUL
8936
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_DATA_FLD 0x6bUL
8937
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_CFA_LAYOUT 0x6cUL
8938
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_CTXT_ALLOC_FAIL 0x6dUL
8939
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ROCE_FLOW_ERR 0x6eUL
8940
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_OWNER_FID 0x6fUL
8941
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_REF_CNT 0x70UL
8942
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_FLOW_TYPE 0x71UL
8943
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_IVLAN 0x72UL
8944
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_MAX_VLAN_ID 0x73UL
8945
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_TNL_REQ 0x74UL
8946
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_ADDR 0x75UL
8947
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_IVLAN 0x76UL
8948
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR 0x77UL
8949
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR_TYPE 0x78UL
8950
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_T_L3_ADDR_TYPE 0x79UL
8951
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DST_VNIC_ID 0x7aUL
8952
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VNI 0x7bUL
8953
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_DST_ID 0x7cUL
8954
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_FAIL_ROCE_L2_FLOW 0x7dUL
8955
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_NPAR_VLAN 0x7eUL
8956
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ATSP_ADD 0x7fUL
8957
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DFLT_VLAN_FAIL 0x80UL
8958
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L3_TYPE 0x81UL
8959
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 0x82UL
8960
+
#define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW
8961
+
u8 unused_0[7];
8962
+
};
8963
+
8964
+
/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
8965
+
struct hwrm_cfa_ntuple_filter_free_input {
8966
+
__le16 req_type;
8967
+
__le16 cmpl_ring;
8968
+
__le16 seq_id;
8969
+
__le16 target_id;
8970
+
__le64 resp_addr;
8971
+
__le64 ntuple_filter_id;
8972
+
};
8973
+
8974
+
/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
8975
+
struct hwrm_cfa_ntuple_filter_free_output {
8976
+
__le16 error_code;
8977
+
__le16 req_type;
8978
+
__le16 seq_id;
8979
+
__le16 resp_len;
8980
+
u8 unused_0[7];
8981
+
u8 valid;
8982
+
};
8983
+
8984
+
/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
8985
+
struct hwrm_cfa_ntuple_filter_cfg_input {
8986
+
__le16 req_type;
8987
+
__le16 cmpl_ring;
8988
+
__le16 seq_id;
8989
+
__le16 target_id;
8990
+
__le64 resp_addr;
8991
+
__le32 enables;
8992
+
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
8993
+
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
8994
+
#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
8995
+
__le32 flags;
8996
+
#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
8997
+
#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
8998
+
#define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL
8999
+
__le64 ntuple_filter_id;
9000
+
__le32 new_dst_id;
9001
+
__le32 new_mirror_vnic_id;
9002
+
__le16 new_meter_instance_id;
9003
+
#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
9004
+
#define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
9005
+
u8 unused_1[6];
9006
+
};
9007
+
9008
+
/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
9009
+
struct hwrm_cfa_ntuple_filter_cfg_output {
9010
+
__le16 error_code;
9011
+
__le16 req_type;
9012
+
__le16 seq_id;
9013
+
__le16 resp_len;
9014
+
u8 unused_0[7];
9015
+
u8 valid;
9016
+
};
9017
+
9018
+
/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
9019
+
struct hwrm_tunnel_dst_port_alloc_input {
9020
+
__le16 req_type;
9021
+
__le16 cmpl_ring;
9022
+
__le16 seq_id;
9023
+
__le16 target_id;
9024
+
__le64 resp_addr;
9025
+
u8 tunnel_type;
9026
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
9027
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
9028
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
9029
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
9030
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
9031
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
9032
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
9033
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL
9034
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL
9035
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
9036
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL
9037
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL
9038
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL
9039
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL
9040
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL
9041
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL
9042
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL
9043
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL
9044
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL
9045
+
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07
9046
+
u8 tunnel_next_proto;
9047
+
__be16 tunnel_dst_port_val;
9048
+
u8 unused_0[4];
9049
+
};
9050
+
9051
+
/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
9052
+
struct hwrm_tunnel_dst_port_alloc_output {
9053
+
__le16 error_code;
9054
+
__le16 req_type;
9055
+
__le16 seq_id;
9056
+
__le16 resp_len;
9057
+
__le16 tunnel_dst_port_id;
9058
+
u8 error_info;
9059
+
#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL
9060
+
#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL
9061
+
#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL
9062
+
#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL
9063
+
#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED
9064
+
u8 upar_in_use;
9065
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL
9066
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL
9067
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL
9068
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL
9069
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL
9070
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL
9071
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL
9072
+
#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL
9073
+
u8 unused_0[3];
9074
+
u8 valid;
9075
+
};
9076
+
9077
+
/* hwrm_tunnel_dst_port_alloc_cmd_err (size:64b/8B) */
9078
+
struct hwrm_tunnel_dst_port_alloc_cmd_err {
9079
+
u8 code;
9080
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_UNKNOWN 0x0UL
9081
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_TUNNEL_ALLOC_ERR 0x1UL
9082
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_ACCESS_DENIED 0x2UL
9083
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_GET_PORT_FAILED 0x3UL
9084
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_PORT_NUM_ERR 0x4UL
9085
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_CUSTOM_TNL_PORT_ERR 0x5UL
9086
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_TUNNEL_QUERY_ERR 0x6UL
9087
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_GRE_MODE_UNSUPPORTED 0x7UL
9088
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_GRE_ALREADY_ALLOC 0x8UL
9089
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_TUNNEL_TYPE_INVALID 0x9UL
9090
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_UPAR_ERR 0xaUL
9091
+
#define TUNNEL_DST_PORT_ALLOC_CMD_ERR_LAST TUNNEL_DST_PORT_ALLOC_CMD_ERR_UPAR_ERR
9092
+
u8 unused_0[7];
9093
+
};
9094
+
9095
+
/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
9096
+
struct hwrm_tunnel_dst_port_free_input {
9097
+
__le16 req_type;
9098
+
__le16 cmpl_ring;
9099
+
__le16 seq_id;
9100
+
__le16 target_id;
9101
+
__le64 resp_addr;
9102
+
u8 tunnel_type;
9103
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
9104
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
9105
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
9106
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
9107
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
9108
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
9109
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
9110
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL
9111
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL
9112
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL
9113
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL
9114
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL
9115
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL
9116
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL
9117
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL
9118
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL
9119
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL
9120
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL
9121
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL
9122
+
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07
9123
+
u8 tunnel_next_proto;
9124
+
__le16 tunnel_dst_port_id;
9125
+
u8 unused_0[4];
9126
+
};
9127
+
9128
+
/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
9129
+
struct hwrm_tunnel_dst_port_free_output {
9130
+
__le16 error_code;
9131
+
__le16 req_type;
9132
+
__le16 seq_id;
9133
+
__le16 resp_len;
9134
+
u8 error_info;
9135
+
#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL
9136
+
#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL
9137
+
#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL
9138
+
#define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED
9139
+
u8 unused_1[6];
9140
+
u8 valid;
9141
+
};
9142
+
9143
+
/* ctx_hw_stats (size:1280b/160B) */
9144
+
struct ctx_hw_stats {
9145
+
__le64 rx_ucast_pkts;
9146
+
__le64 rx_mcast_pkts;
9147
+
__le64 rx_bcast_pkts;
9148
+
__le64 rx_discard_pkts;
9149
+
__le64 rx_error_pkts;
9150
+
__le64 rx_ucast_bytes;
9151
+
__le64 rx_mcast_bytes;
9152
+
__le64 rx_bcast_bytes;
9153
+
__le64 tx_ucast_pkts;
9154
+
__le64 tx_mcast_pkts;
9155
+
__le64 tx_bcast_pkts;
9156
+
__le64 tx_error_pkts;
9157
+
__le64 tx_discard_pkts;
9158
+
__le64 tx_ucast_bytes;
9159
+
__le64 tx_mcast_bytes;
9160
+
__le64 tx_bcast_bytes;
9161
+
__le64 tpa_pkts;
9162
+
__le64 tpa_bytes;
9163
+
__le64 tpa_events;
9164
+
__le64 tpa_aborts;
9165
+
};
9166
+
9167
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_UNKNOWN 0x0UL
9168
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_INVALID_FID 0x65UL
9169
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_INVALID_CTX_ID 0x66UL
9170
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_INVALID_PAYLOAD 0x67UL
9171
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_CTX_STAT_RETRIEVAL_FAIL 0x68UL
9172
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_RES_NOT_ALLOCATED 0x69UL
9173
+
#define HWRM_STAT_COMMON_CMD_ERR_CODE_LAST HWRM_STAT_COMMON_CMD_ERR_CODE_RES_NOT_ALLOCATED
9174
+
9175
+
/* ctx_hw_stats_ext (size:1408b/176B) */
9176
+
struct ctx_hw_stats_ext {
9177
+
__le64 rx_ucast_pkts;
9178
+
__le64 rx_mcast_pkts;
9179
+
__le64 rx_bcast_pkts;
9180
+
__le64 rx_discard_pkts;
9181
+
__le64 rx_error_pkts;
9182
+
__le64 rx_ucast_bytes;
9183
+
__le64 rx_mcast_bytes;
9184
+
__le64 rx_bcast_bytes;
9185
+
__le64 tx_ucast_pkts;
9186
+
__le64 tx_mcast_pkts;
9187
+
__le64 tx_bcast_pkts;
9188
+
__le64 tx_error_pkts;
9189
+
__le64 tx_discard_pkts;
9190
+
__le64 tx_ucast_bytes;
9191
+
__le64 tx_mcast_bytes;
9192
+
__le64 tx_bcast_bytes;
9193
+
__le64 rx_tpa_eligible_pkt;
9194
+
__le64 rx_tpa_eligible_bytes;
9195
+
__le64 rx_tpa_pkt;
9196
+
__le64 rx_tpa_bytes;
9197
+
__le64 rx_tpa_errors;
9198
+
__le64 rx_tpa_events;
9199
+
};
9200
+
9201
+
/* ctx_eng_stats (size:512b/64B) */
9202
+
struct ctx_eng_stats {
9203
+
__le64 eng_bytes_in;
9204
+
__le64 eng_bytes_out;
9205
+
__le64 aux_bytes_in;
9206
+
__le64 aux_bytes_out;
9207
+
__le64 commands;
9208
+
__le64 error_commands;
9209
+
__le64 cce_engine_usage;
9210
+
__le64 cdd_engine_usage;
9211
+
};
9212
+
9213
+
/* hwrm_stat_ctx_alloc_input (size:384b/48B) */
9214
+
struct hwrm_stat_ctx_alloc_input {
9215
+
__le16 req_type;
9216
+
__le16 cmpl_ring;
9217
+
__le16 seq_id;
9218
+
__le16 target_id;
9219
+
__le64 resp_addr;
9220
+
__le64 stats_dma_addr;
9221
+
__le32 update_period_ms;
9222
+
u8 stat_ctx_flags;
9223
+
#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
9224
+
#define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF 0x2UL
9225
+
u8 unused_0;
9226
+
__le16 stats_dma_length;
9227
+
__le16 flags;
9228
+
#define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL
9229
+
__le16 steering_tag;
9230
+
__le32 stat_ctx_id;
9231
+
__le16 alloc_seq_id;
9232
+
u8 unused_1[6];
9233
+
};
9234
+
9235
+
/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
9236
+
struct hwrm_stat_ctx_alloc_output {
9237
+
__le16 error_code;
9238
+
__le16 req_type;
9239
+
__le16 seq_id;
9240
+
__le16 resp_len;
9241
+
__le32 stat_ctx_id;
9242
+
u8 unused_0[3];
9243
+
u8 valid;
9244
+
};
9245
+
9246
+
/* hwrm_stat_ctx_alloc_cmd_err (size:64b/8B) */
9247
+
struct hwrm_stat_ctx_alloc_cmd_err {
9248
+
u8 code;
9249
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
9250
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_INVALID_FID 0x1UL
9251
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_INVALID_FLAG 0x2UL
9252
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_INVALID_DMA_ADDR 0x3UL
9253
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_RES_NOT_AVAIL 0x4UL
9254
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_RES_POOL_EXHAUSTED 0x5UL
9255
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_CTX_ALLOC_FAIL 0x6UL
9256
+
#define STAT_CTX_ALLOC_CMD_ERR_CODE_LAST STAT_CTX_ALLOC_CMD_ERR_CODE_CTX_ALLOC_FAIL
9257
+
u8 unused_0[7];
9258
+
};
9259
+
9260
+
/* hwrm_stat_ctx_free_input (size:192b/24B) */
9261
+
struct hwrm_stat_ctx_free_input {
9262
+
__le16 req_type;
9263
+
__le16 cmpl_ring;
9264
+
__le16 seq_id;
9265
+
__le16 target_id;
9266
+
__le64 resp_addr;
9267
+
__le32 stat_ctx_id;
9268
+
u8 unused_0[4];
9269
+
};
9270
+
9271
+
/* hwrm_stat_ctx_free_output (size:128b/16B) */
9272
+
struct hwrm_stat_ctx_free_output {
9273
+
__le16 error_code;
9274
+
__le16 req_type;
9275
+
__le16 seq_id;
9276
+
__le16 resp_len;
9277
+
__le32 stat_ctx_id;
9278
+
u8 unused_0[3];
9279
+
u8 valid;
9280
+
};
9281
+
9282
+
/* hwrm_stat_ctx_free_cmd_err (size:64b/8B) */
9283
+
struct hwrm_stat_ctx_free_cmd_err {
9284
+
u8 code;
9285
+
#define STAT_CTX_FREE_CMD_ERR_CODE_UNKNOWN 0x0UL
9286
+
#define STAT_CTX_FREE_CMD_ERR_CODE_INVALID_CTX_ID 0x1UL
9287
+
#define STAT_CTX_FREE_CMD_ERR_CODE_RES_DEALLOC_FAIL 0x2UL
9288
+
#define STAT_CTX_FREE_CMD_ERR_CODE_CTX_FREE_FAIL 0x3UL
9289
+
#define STAT_CTX_FREE_CMD_ERR_CODE_LAST STAT_CTX_FREE_CMD_ERR_CODE_CTX_FREE_FAIL
9290
+
u8 unused_0[7];
9291
+
};
9292
+
9293
+
/* hwrm_stat_ctx_query_input (size:192b/24B) */
9294
+
struct hwrm_stat_ctx_query_input {
9295
+
__le16 req_type;
9296
+
__le16 cmpl_ring;
9297
+
__le16 seq_id;
9298
+
__le16 target_id;
9299
+
__le64 resp_addr;
9300
+
__le32 stat_ctx_id;
9301
+
u8 flags;
9302
+
#define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
9303
+
u8 unused_0[3];
9304
+
};
9305
+
9306
+
/* hwrm_stat_ctx_query_output (size:1408b/176B) */
9307
+
struct hwrm_stat_ctx_query_output {
9308
+
__le16 error_code;
9309
+
__le16 req_type;
9310
+
__le16 seq_id;
9311
+
__le16 resp_len;
9312
+
__le64 tx_ucast_pkts;
9313
+
__le64 tx_mcast_pkts;
9314
+
__le64 tx_bcast_pkts;
9315
+
__le64 tx_discard_pkts;
9316
+
__le64 tx_error_pkts;
9317
+
__le64 tx_ucast_bytes;
9318
+
__le64 tx_mcast_bytes;
9319
+
__le64 tx_bcast_bytes;
9320
+
__le64 rx_ucast_pkts;
9321
+
__le64 rx_mcast_pkts;
9322
+
__le64 rx_bcast_pkts;
9323
+
__le64 rx_discard_pkts;
9324
+
__le64 rx_error_pkts;
9325
+
__le64 rx_ucast_bytes;
9326
+
__le64 rx_mcast_bytes;
9327
+
__le64 rx_bcast_bytes;
9328
+
__le64 rx_agg_pkts;
9329
+
__le64 rx_agg_bytes;
9330
+
__le64 rx_agg_events;
9331
+
__le64 rx_agg_aborts;
9332
+
u8 unused_0[7];
9333
+
u8 valid;
9334
+
};
9335
+
9336
+
/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
9337
+
struct hwrm_stat_ext_ctx_query_input {
9338
+
__le16 req_type;
9339
+
__le16 cmpl_ring;
9340
+
__le16 seq_id;
9341
+
__le16 target_id;
9342
+
__le64 resp_addr;
9343
+
__le32 stat_ctx_id;
9344
+
u8 flags;
9345
+
#define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
9346
+
u8 unused_0[3];
9347
+
};
9348
+
9349
+
/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
9350
+
struct hwrm_stat_ext_ctx_query_output {
9351
+
__le16 error_code;
9352
+
__le16 req_type;
9353
+
__le16 seq_id;
9354
+
__le16 resp_len;
9355
+
__le64 rx_ucast_pkts;
9356
+
__le64 rx_mcast_pkts;
9357
+
__le64 rx_bcast_pkts;
9358
+
__le64 rx_discard_pkts;
9359
+
__le64 rx_error_pkts;
9360
+
__le64 rx_ucast_bytes;
9361
+
__le64 rx_mcast_bytes;
9362
+
__le64 rx_bcast_bytes;
9363
+
__le64 tx_ucast_pkts;
9364
+
__le64 tx_mcast_pkts;
9365
+
__le64 tx_bcast_pkts;
9366
+
__le64 tx_error_pkts;
9367
+
__le64 tx_discard_pkts;
9368
+
__le64 tx_ucast_bytes;
9369
+
__le64 tx_mcast_bytes;
9370
+
__le64 tx_bcast_bytes;
9371
+
__le64 rx_tpa_eligible_pkt;
9372
+
__le64 rx_tpa_eligible_bytes;
9373
+
__le64 rx_tpa_pkt;
9374
+
__le64 rx_tpa_bytes;
9375
+
__le64 rx_tpa_errors;
9376
+
__le64 rx_tpa_events;
9377
+
u8 unused_0[7];
9378
+
u8 valid;
9379
+
};
9380
+
9381
+
/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
9382
+
struct hwrm_stat_ctx_eng_query_input {
9383
+
__le16 req_type;
9384
+
__le16 cmpl_ring;
9385
+
__le16 seq_id;
9386
+
__le16 target_id;
9387
+
__le64 resp_addr;
9388
+
__le32 stat_ctx_id;
9389
+
u8 unused_0[4];
9390
+
};
9391
+
9392
+
/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
9393
+
struct hwrm_stat_ctx_eng_query_output {
9394
+
__le16 error_code;
9395
+
__le16 req_type;
9396
+
__le16 seq_id;
9397
+
__le16 resp_len;
9398
+
__le64 eng_bytes_in;
9399
+
__le64 eng_bytes_out;
9400
+
__le64 aux_bytes_in;
9401
+
__le64 aux_bytes_out;
9402
+
__le64 commands;
9403
+
__le64 error_commands;
9404
+
__le64 cce_engine_usage;
9405
+
__le64 cdd_engine_usage;
9406
+
u8 unused_0[7];
9407
+
u8 valid;
9408
+
};
9409
+
9410
+
/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
9411
+
struct hwrm_stat_ctx_clr_stats_input {
9412
+
__le16 req_type;
9413
+
__le16 cmpl_ring;
9414
+
__le16 seq_id;
9415
+
__le16 target_id;
9416
+
__le64 resp_addr;
9417
+
__le32 stat_ctx_id;
9418
+
u8 unused_0[4];
9419
+
};
9420
+
9421
+
/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
9422
+
struct hwrm_stat_ctx_clr_stats_output {
9423
+
__le16 error_code;
9424
+
__le16 req_type;
9425
+
__le16 seq_id;
9426
+
__le16 resp_len;
9427
+
u8 unused_0[7];
9428
+
u8 valid;
9429
+
};
9430
+
9431
+
/* hwrm_pcie_qstats_input (size:256b/32B) */
9432
+
struct hwrm_pcie_qstats_input {
9433
+
__le16 req_type;
9434
+
__le16 cmpl_ring;
9435
+
__le16 seq_id;
9436
+
__le16 target_id;
9437
+
__le64 resp_addr;
9438
+
__le16 pcie_stat_size;
9439
+
u8 unused_0[6];
9440
+
__le64 pcie_stat_host_addr;
9441
+
};
9442
+
9443
+
/* hwrm_pcie_qstats_output (size:128b/16B) */
9444
+
struct hwrm_pcie_qstats_output {
9445
+
__le16 error_code;
9446
+
__le16 req_type;
9447
+
__le16 seq_id;
9448
+
__le16 resp_len;
9449
+
__le16 pcie_stat_size;
9450
+
u8 unused_0[5];
9451
+
u8 valid;
9452
+
};
9453
+
9454
+
/* hwrm_pcie_qstats_cmd_err (size:64b/8B) */
9455
+
struct hwrm_pcie_qstats_cmd_err {
9456
+
u8 code;
9457
+
#define PCIE_QSTATS_CMD_ERR_CODE_UNKNOWN 0x0UL
9458
+
#define PCIE_QSTATS_CMD_ERR_CODE_LEGACY_INVALID_PF_ID 0x1UL
9459
+
#define PCIE_QSTATS_CMD_ERR_CODE_GENERIC_INVALID_EP_IDX 0x2UL
9460
+
#define PCIE_QSTATS_CMD_ERR_CODE_GENERIC_MEM_ALLOC_FAIL 0x3UL
9461
+
#define PCIE_QSTATS_CMD_ERR_CODE_LAST PCIE_QSTATS_CMD_ERR_CODE_GENERIC_MEM_ALLOC_FAIL
9462
+
u8 unused_0[7];
9463
+
};
9464
+
9465
+
/* pcie_ctx_hw_stats (size:768b/96B) */
9466
+
struct pcie_ctx_hw_stats {
9467
+
__le64 pcie_pl_signal_integrity;
9468
+
__le64 pcie_dl_signal_integrity;
9469
+
__le64 pcie_tl_signal_integrity;
9470
+
__le64 pcie_link_integrity;
9471
+
__le64 pcie_tx_traffic_rate;
9472
+
__le64 pcie_rx_traffic_rate;
9473
+
__le64 pcie_tx_dllp_statistics;
9474
+
__le64 pcie_rx_dllp_statistics;
9475
+
__le64 pcie_equalization_time;
9476
+
__le32 pcie_ltssm_histogram[4];
9477
+
__le64 pcie_recovery_histogram;
9478
+
};
9479
+
9480
+
/* pcie_ctx_hw_stats_v2 (size:4544b/568B) */
9481
+
struct pcie_ctx_hw_stats_v2 {
9482
+
__le64 pcie_pl_signal_integrity;
9483
+
__le64 pcie_dl_signal_integrity;
9484
+
__le64 pcie_tl_signal_integrity;
9485
+
__le64 pcie_link_integrity;
9486
+
__le64 pcie_tx_traffic_rate;
9487
+
__le64 pcie_rx_traffic_rate;
9488
+
__le64 pcie_tx_dllp_statistics;
9489
+
__le64 pcie_rx_dllp_statistics;
9490
+
__le64 pcie_equalization_time;
9491
+
__le32 pcie_ltssm_histogram[4];
9492
+
__le64 pcie_recovery_histogram;
9493
+
__le32 pcie_tl_credit_nph_histogram[8];
9494
+
__le32 pcie_tl_credit_ph_histogram[8];
9495
+
__le32 pcie_tl_credit_pd_histogram[8];
9496
+
__le32 pcie_cmpl_latest_times[4];
9497
+
__le32 pcie_cmpl_longest_time;
9498
+
__le32 pcie_cmpl_shortest_time;
9499
+
__le32 unused_0[2];
9500
+
__le32 pcie_cmpl_latest_headers[4][4];
9501
+
__le32 pcie_cmpl_longest_headers[4][4];
9502
+
__le32 pcie_cmpl_shortest_headers[4][4];
9503
+
__le32 pcie_wr_latency_histogram[12];
9504
+
__le32 pcie_wr_latency_all_normal_count;
9505
+
__le32 unused_1;
9506
+
__le64 pcie_posted_packet_count;
9507
+
__le64 pcie_non_posted_packet_count;
9508
+
__le64 pcie_other_packet_count;
9509
+
__le64 pcie_blocked_packet_count;
9510
+
__le64 pcie_cmpl_packet_count;
9511
+
__le32 pcie_rd_latency_histogram[12];
9512
+
__le32 pcie_rd_latency_all_normal_count;
9513
+
__le32 unused_2;
9514
+
};
9515
+
9516
+
/* hwrm_stat_generic_qstats_input (size:256b/32B) */
9517
+
struct hwrm_stat_generic_qstats_input {
9518
+
__le16 req_type;
9519
+
__le16 cmpl_ring;
9520
+
__le16 seq_id;
9521
+
__le16 target_id;
9522
+
__le64 resp_addr;
9523
+
__le16 generic_stat_size;
9524
+
u8 flags;
9525
+
#define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
9526
+
u8 unused_0[5];
9527
+
__le64 generic_stat_host_addr;
9528
+
};
9529
+
9530
+
/* hwrm_stat_generic_qstats_output (size:128b/16B) */
9531
+
struct hwrm_stat_generic_qstats_output {
9532
+
__le16 error_code;
9533
+
__le16 req_type;
9534
+
__le16 seq_id;
9535
+
__le16 resp_len;
9536
+
__le16 generic_stat_size;
9537
+
u8 unused_0[5];
9538
+
u8 valid;
9539
+
};
9540
+
9541
+
/* hwrm_stat_generic_qstats_cmd_err (size:64b/8B) */
9542
+
struct hwrm_stat_generic_qstats_cmd_err {
9543
+
u8 code;
9544
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_UNKNOWN 0x0UL
9545
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_INVALID_EP_ID 0x1UL
9546
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_INVALID_STAT_SIZE 0x2UL
9547
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_INVALID_DMA_ADDR 0x3UL
9548
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_HOST_NOT_ACTIVE 0x4UL
9549
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_MEM_ALLOC_FAIL 0x5UL
9550
+
#define STAT_GENERIC_QSTATS_CMD_ERR_CODE_LAST STAT_GENERIC_QSTATS_CMD_ERR_CODE_MEM_ALLOC_FAIL
9551
+
u8 unused_0[7];
9552
+
};
9553
+
9554
+
/* generic_sw_hw_stats (size:1472b/184B) */
9555
+
struct generic_sw_hw_stats {
9556
+
__le64 pcie_statistics_tx_tlp;
9557
+
__le64 pcie_statistics_rx_tlp;
9558
+
__le64 pcie_credit_fc_hdr_posted;
9559
+
__le64 pcie_credit_fc_hdr_nonposted;
9560
+
__le64 pcie_credit_fc_hdr_cmpl;
9561
+
__le64 pcie_credit_fc_data_posted;
9562
+
__le64 pcie_credit_fc_data_nonposted;
9563
+
__le64 pcie_credit_fc_data_cmpl;
9564
+
__le64 pcie_credit_fc_tgt_nonposted;
9565
+
__le64 pcie_credit_fc_tgt_data_posted;
9566
+
__le64 pcie_credit_fc_tgt_hdr_posted;
9567
+
__le64 pcie_credit_fc_cmpl_hdr_posted;
9568
+
__le64 pcie_credit_fc_cmpl_data_posted;
9569
+
__le64 pcie_cmpl_longest;
9570
+
__le64 pcie_cmpl_shortest;
9571
+
__le64 cache_miss_count_cfcq;
9572
+
__le64 cache_miss_count_cfcs;
9573
+
__le64 cache_miss_count_cfcc;
9574
+
__le64 cache_miss_count_cfcm;
9575
+
__le64 hw_db_recov_dbs_dropped;
9576
+
__le64 hw_db_recov_drops_serviced;
9577
+
__le64 hw_db_recov_dbs_recovered;
9578
+
__le64 hw_db_recov_oo_drop_count;
9579
+
};
9580
+
9581
+
/* hwrm_stat_db_error_qstats_input (size:128b/16B) */
9582
+
struct hwrm_stat_db_error_qstats_input {
9583
+
__le16 req_type;
9584
+
__le16 cmpl_ring;
9585
+
__le16 seq_id;
9586
+
__le16 target_id;
9587
+
__le64 resp_addr;
9588
+
};
9589
+
9590
+
/* hwrm_stat_db_error_qstats_output (size:320b/40B) */
9591
+
struct hwrm_stat_db_error_qstats_output {
9592
+
__le16 error_code;
9593
+
__le16 req_type;
9594
+
__le16 seq_id;
9595
+
__le16 resp_len;
9596
+
__le32 tx_db_drop_invalid_qp_state;
9597
+
__le32 rx_db_drop_invalid_rq_state;
9598
+
__le32 tx_db_drop_format_error;
9599
+
__le32 express_db_dropped_misc_error;
9600
+
__le32 express_db_dropped_sq_overflow;
9601
+
__le32 express_db_dropped_rq_overflow;
9602
+
u8 unused_0[7];
9603
+
u8 valid;
9604
+
};
9605
+
9606
+
/* hwrm_stat_query_roce_stats_input (size:256b/32B) */
9607
+
struct hwrm_stat_query_roce_stats_input {
9608
+
__le16 req_type;
9609
+
__le16 cmpl_ring;
9610
+
__le16 seq_id;
9611
+
__le16 target_id;
9612
+
__le64 resp_addr;
9613
+
__le16 roce_stat_size;
9614
+
u8 unused_0[6];
9615
+
__le64 roce_stat_host_addr;
9616
+
};
9617
+
9618
+
/* hwrm_stat_query_roce_stats_output (size:128b/16B) */
9619
+
struct hwrm_stat_query_roce_stats_output {
9620
+
__le16 error_code;
9621
+
__le16 req_type;
9622
+
__le16 seq_id;
9623
+
__le16 resp_len;
9624
+
__le16 roce_stat_size;
9625
+
u8 unused_0[5];
9626
+
u8 valid;
9627
+
};
9628
+
9629
+
/* stat_query_roce_stats_data (size:2944b/368B) */
9630
+
struct stat_query_roce_stats_data {
9631
+
__le64 to_retransmits;
9632
+
__le64 seq_err_naks_rcvd;
9633
+
__le64 max_retry_exceeded;
9634
+
__le64 rnr_naks_rcvd;
9635
+
__le64 missing_resp;
9636
+
__le64 unrecoverable_err;
9637
+
__le64 bad_resp_err;
9638
+
__le64 local_qp_op_err;
9639
+
__le64 local_protection_err;
9640
+
__le64 mem_mgmt_op_err;
9641
+
__le64 remote_invalid_req_err;
9642
+
__le64 remote_access_err;
9643
+
__le64 remote_op_err;
9644
+
__le64 dup_req;
9645
+
__le64 res_exceed_max;
9646
+
__le64 res_length_mismatch;
9647
+
__le64 res_exceeds_wqe;
9648
+
__le64 res_opcode_err;
9649
+
__le64 res_rx_invalid_rkey;
9650
+
__le64 res_rx_domain_err;
9651
+
__le64 res_rx_no_perm;
9652
+
__le64 res_rx_range_err;
9653
+
__le64 res_tx_invalid_rkey;
9654
+
__le64 res_tx_domain_err;
9655
+
__le64 res_tx_no_perm;
9656
+
__le64 res_tx_range_err;
9657
+
__le64 res_irrq_oflow;
9658
+
__le64 res_unsup_opcode;
9659
+
__le64 res_unaligned_atomic;
9660
+
__le64 res_rem_inv_err;
9661
+
__le64 res_mem_error;
9662
+
__le64 res_srq_err;
9663
+
__le64 res_cmp_err;
9664
+
__le64 res_invalid_dup_rkey;
9665
+
__le64 res_wqe_format_err;
9666
+
__le64 res_cq_load_err;
9667
+
__le64 res_srq_load_err;
9668
+
__le64 res_tx_pci_err;
9669
+
__le64 res_rx_pci_err;
9670
+
__le64 res_oos_drop_count;
9671
+
__le64 active_qp_count_p0;
9672
+
__le64 active_qp_count_p1;
9673
+
__le64 active_qp_count_p2;
9674
+
__le64 active_qp_count_p3;
9675
+
__le64 xp_sq_overflow_err;
9676
+
__le64 xp_rq_overflow_error;
9677
+
};
9678
+
9679
+
/* hwrm_stat_query_roce_stats_ext_input (size:256b/32B) */
9680
+
struct hwrm_stat_query_roce_stats_ext_input {
9681
+
__le16 req_type;
9682
+
__le16 cmpl_ring;
9683
+
__le16 seq_id;
9684
+
__le16 target_id;
9685
+
__le64 resp_addr;
9686
+
__le16 roce_stat_size;
9687
+
u8 unused_0[6];
9688
+
__le64 roce_stat_host_addr;
9689
+
};
9690
+
9691
+
/* hwrm_stat_query_roce_stats_ext_output (size:128b/16B) */
9692
+
struct hwrm_stat_query_roce_stats_ext_output {
9693
+
__le16 error_code;
9694
+
__le16 req_type;
9695
+
__le16 seq_id;
9696
+
__le16 resp_len;
9697
+
__le16 roce_stat_size;
9698
+
u8 unused_0[5];
9699
+
u8 valid;
9700
+
};
9701
+
9702
+
/* stat_query_roce_stats_ext_data (size:2240b/280B) */
9703
+
struct stat_query_roce_stats_ext_data {
9704
+
__le64 tx_atomic_req_pkts;
9705
+
__le64 tx_read_req_pkts;
9706
+
__le64 tx_read_res_pkts;
9707
+
__le64 tx_write_req_pkts;
9708
+
__le64 tx_send_req_pkts;
9709
+
__le64 tx_roce_pkts;
9710
+
__le64 tx_roce_bytes;
9711
+
__le64 rx_atomic_req_pkts;
9712
+
__le64 rx_read_req_pkts;
9713
+
__le64 rx_read_res_pkts;
9714
+
__le64 rx_write_req_pkts;
9715
+
__le64 rx_send_req_pkts;
9716
+
__le64 rx_roce_pkts;
9717
+
__le64 rx_roce_bytes;
9718
+
__le64 rx_roce_good_pkts;
9719
+
__le64 rx_roce_good_bytes;
9720
+
__le64 rx_out_of_buffer_pkts;
9721
+
__le64 rx_out_of_sequence_pkts;
9722
+
__le64 tx_cnp_pkts;
9723
+
__le64 rx_cnp_pkts;
9724
+
__le64 rx_ecn_marked_pkts;
9725
+
__le64 tx_cnp_bytes;
9726
+
__le64 rx_cnp_bytes;
9727
+
__le64 seq_err_naks_rcvd;
9728
+
__le64 rnr_naks_rcvd;
9729
+
__le64 missing_resp;
9730
+
__le64 to_retransmit;
9731
+
__le64 dup_req;
9732
+
__le64 rx_dcn_payload_cut;
9733
+
__le64 te_bypassed;
9734
+
__le64 tx_dcn_cnp;
9735
+
__le64 rx_dcn_cnp;
9736
+
__le64 rx_payload_cut;
9737
+
__le64 rx_payload_cut_ignored;
9738
+
__le64 rx_dcn_cnp_ignored;
9739
+
};
9740
+
9741
+
/* hwrm_fw_reset_input (size:192b/24B) */
9742
+
struct hwrm_fw_reset_input {
9743
+
__le16 req_type;
9744
+
__le16 cmpl_ring;
9745
+
__le16 seq_id;
9746
+
__le16 target_id;
9747
+
__le64 resp_addr;
9748
+
u8 embedded_proc_type;
9749
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
9750
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
9751
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
9752
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
9753
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
9754
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
9755
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
9756
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
9757
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
9758
+
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
9759
+
u8 selfrst_status;
9760
+
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
9761
+
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
9762
+
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
9763
+
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
9764
+
#define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
9765
+
u8 host_idx;
9766
+
u8 flags;
9767
+
#define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
9768
+
#define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL
9769
+
u8 unused_0[4];
9770
+
};
9771
+
9772
+
/* hwrm_fw_reset_output (size:128b/16B) */
9773
+
struct hwrm_fw_reset_output {
9774
+
__le16 error_code;
9775
+
__le16 req_type;
9776
+
__le16 seq_id;
9777
+
__le16 resp_len;
9778
+
u8 selfrst_status;
9779
+
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
9780
+
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
9781
+
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
9782
+
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
9783
+
#define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
9784
+
u8 unused_0[6];
9785
+
u8 valid;
9786
+
};
9787
+
9788
+
/* hwrm_fw_qstatus_input (size:192b/24B) */
9789
+
struct hwrm_fw_qstatus_input {
9790
+
__le16 req_type;
9791
+
__le16 cmpl_ring;
9792
+
__le16 seq_id;
9793
+
__le16 target_id;
9794
+
__le64 resp_addr;
9795
+
u8 embedded_proc_type;
9796
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
9797
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
9798
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
9799
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
9800
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
9801
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
9802
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
9803
+
#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
9804
+
u8 unused_0[7];
9805
+
};
9806
+
9807
+
/* hwrm_fw_qstatus_output (size:128b/16B) */
9808
+
struct hwrm_fw_qstatus_output {
9809
+
__le16 error_code;
9810
+
__le16 req_type;
9811
+
__le16 seq_id;
9812
+
__le16 resp_len;
9813
+
u8 selfrst_status;
9814
+
#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
9815
+
#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
9816
+
#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
9817
+
#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
9818
+
#define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
9819
+
u8 nvm_option_action_status;
9820
+
#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL
9821
+
#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL
9822
+
#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL
9823
+
#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL
9824
+
#define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT
9825
+
u8 unused_0[5];
9826
+
u8 valid;
9827
+
};
9828
+
9829
+
/* hwrm_fw_set_time_input (size:256b/32B) */
9830
+
struct hwrm_fw_set_time_input {
9831
+
__le16 req_type;
9832
+
__le16 cmpl_ring;
9833
+
__le16 seq_id;
9834
+
__le16 target_id;
9835
+
__le64 resp_addr;
9836
+
__le16 year;
9837
+
#define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
9838
+
#define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
9839
+
u8 month;
9840
+
u8 day;
9841
+
u8 hour;
9842
+
u8 minute;
9843
+
u8 second;
9844
+
u8 unused_0;
9845
+
__le16 millisecond;
9846
+
__le16 zone;
9847
+
#define FW_SET_TIME_REQ_ZONE_UTC 0
9848
+
#define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
9849
+
#define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
9850
+
u8 unused_1[4];
9851
+
};
9852
+
9853
+
/* hwrm_fw_set_time_output (size:128b/16B) */
9854
+
struct hwrm_fw_set_time_output {
9855
+
__le16 error_code;
9856
+
__le16 req_type;
9857
+
__le16 seq_id;
9858
+
__le16 resp_len;
9859
+
u8 unused_0[7];
9860
+
u8 valid;
9861
+
};
9862
+
9863
+
/* hwrm_fw_get_time_input (size:128b/16B) */
9864
+
struct hwrm_fw_get_time_input {
9865
+
__le16 req_type;
9866
+
__le16 cmpl_ring;
9867
+
__le16 seq_id;
9868
+
__le16 target_id;
9869
+
__le64 resp_addr;
9870
+
};
9871
+
9872
+
/* hwrm_fw_get_time_output (size:192b/24B) */
9873
+
struct hwrm_fw_get_time_output {
9874
+
__le16 error_code;
9875
+
__le16 req_type;
9876
+
__le16 seq_id;
9877
+
__le16 resp_len;
9878
+
__le16 year;
9879
+
#define FW_GET_TIME_RESP_YEAR_UNKNOWN 0x0UL
9880
+
#define FW_GET_TIME_RESP_YEAR_LAST FW_GET_TIME_RESP_YEAR_UNKNOWN
9881
+
u8 month;
9882
+
u8 day;
9883
+
u8 hour;
9884
+
u8 minute;
9885
+
u8 second;
9886
+
u8 unused_0;
9887
+
__le16 millisecond;
9888
+
__le16 zone;
9889
+
#define FW_GET_TIME_RESP_ZONE_UTC 0
9890
+
#define FW_GET_TIME_RESP_ZONE_UNKNOWN 65535
9891
+
#define FW_GET_TIME_RESP_ZONE_LAST FW_GET_TIME_RESP_ZONE_UNKNOWN
9892
+
u8 unused_1[3];
9893
+
u8 valid;
9894
+
};
9895
+
9896
+
/* hwrm_struct_hdr (size:128b/16B) */
9897
+
struct hwrm_struct_hdr {
9898
+
__le16 struct_id;
9899
+
#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
9900
+
#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
9901
+
#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
9902
+
#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
9903
+
#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
9904
+
#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
9905
+
#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
9906
+
#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
9907
+
#define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL
9908
+
#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
9909
+
#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
9910
+
#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
9911
+
#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
9912
+
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL
9913
+
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL
9914
+
#define STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 0x190UL
9915
+
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS
9916
+
__le16 len;
9917
+
u8 version;
9918
+
#define STRUCT_HDR_VERSION_0 0x0UL
9919
+
#define STRUCT_HDR_VERSION_1 0x1UL
9920
+
#define STRUCT_HDR_VERSION_LAST STRUCT_HDR_VERSION_1
9921
+
u8 count;
9922
+
__le16 subtype;
9923
+
__le16 next_offset;
9924
+
#define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
9925
+
u8 unused_0[6];
9926
+
};
9927
+
9928
+
/* hwrm_struct_data_dcbx_ets (size:256b/32B) */
9929
+
struct hwrm_struct_data_dcbx_ets {
9930
+
u8 destination;
9931
+
#define STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION 0x1UL
9932
+
#define STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION 0x2UL
9933
+
#define STRUCT_DATA_DCBX_ETS_DESTINATION_LAST STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION
9934
+
u8 max_tcs;
9935
+
__le16 unused1;
9936
+
u8 pri0_to_tc_map;
9937
+
u8 pri1_to_tc_map;
9938
+
u8 pri2_to_tc_map;
9939
+
u8 pri3_to_tc_map;
9940
+
u8 pri4_to_tc_map;
9941
+
u8 pri5_to_tc_map;
9942
+
u8 pri6_to_tc_map;
9943
+
u8 pri7_to_tc_map;
9944
+
u8 tc0_to_bw_map;
9945
+
u8 tc1_to_bw_map;
9946
+
u8 tc2_to_bw_map;
9947
+
u8 tc3_to_bw_map;
9948
+
u8 tc4_to_bw_map;
9949
+
u8 tc5_to_bw_map;
9950
+
u8 tc6_to_bw_map;
9951
+
u8 tc7_to_bw_map;
9952
+
u8 tc0_to_tsa_map;
9953
+
#define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP 0x0UL
9954
+
#define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS 0x1UL
9955
+
#define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS 0x2UL
9956
+
#define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC 0xffUL
9957
+
#define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC
9958
+
u8 tc1_to_tsa_map;
9959
+
u8 tc2_to_tsa_map;
9960
+
u8 tc3_to_tsa_map;
9961
+
u8 tc4_to_tsa_map;
9962
+
u8 tc5_to_tsa_map;
9963
+
u8 tc6_to_tsa_map;
9964
+
u8 tc7_to_tsa_map;
9965
+
u8 unused_0[4];
9966
+
};
9967
+
9968
+
/* hwrm_struct_data_dcbx_pfc (size:64b/8B) */
9969
+
struct hwrm_struct_data_dcbx_pfc {
9970
+
u8 pfc_priority_bitmap;
9971
+
u8 max_pfc_tcs;
9972
+
u8 mbc;
9973
+
u8 unused_0[5];
9974
+
};
9975
+
9976
+
/* hwrm_struct_data_dcbx_app (size:64b/8B) */
9977
+
struct hwrm_struct_data_dcbx_app {
9978
+
__be16 protocol_id;
9979
+
u8 protocol_selector;
9980
+
#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
9981
+
#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
9982
+
#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
9983
+
#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
9984
+
#define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
9985
+
u8 priority;
9986
+
u8 valid;
9987
+
u8 unused_0[3];
9988
+
};
9989
+
9990
+
/* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */
9991
+
struct hwrm_struct_data_dcbx_feature_state {
9992
+
u8 dcbx_mode;
9993
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED 0x0UL
9994
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE 0x1UL
9995
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE 0x2UL
9996
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE
9997
+
u8 ets_state;
9998
+
u8 pfc_state;
9999
+
u8 app_state;
10000
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS 0x7UL
10001
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS 0x6UL
10002
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS 0x5UL
10003
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS
10004
+
u8 unused[3];
10005
+
u8 resets;
10006
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS 0x1UL
10007
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC 0x2UL
10008
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP 0x4UL
10009
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE 0x8UL
10010
+
#define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE
10011
+
};
10012
+
10013
+
/* hwrm_struct_data_lldp (size:64b/8B) */
10014
+
struct hwrm_struct_data_lldp {
10015
+
u8 admin_state;
10016
+
#define STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE 0x0UL
10017
+
#define STRUCT_DATA_LLDP_ADMIN_STATE_TX 0x1UL
10018
+
#define STRUCT_DATA_LLDP_ADMIN_STATE_RX 0x2UL
10019
+
#define STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE 0x3UL
10020
+
#define STRUCT_DATA_LLDP_ADMIN_STATE_LAST STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE
10021
+
u8 port_description_state;
10022
+
#define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE 0x0UL
10023
+
#define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE 0x1UL
10024
+
#define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE
10025
+
u8 system_name_state;
10026
+
#define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE 0x0UL
10027
+
#define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE 0x1UL
10028
+
#define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE
10029
+
u8 system_desc_state;
10030
+
#define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE 0x0UL
10031
+
#define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE 0x1UL
10032
+
#define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE
10033
+
u8 system_cap_state;
10034
+
#define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE 0x0UL
10035
+
#define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE 0x1UL
10036
+
#define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE
10037
+
u8 mgmt_addr_state;
10038
+
#define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE 0x0UL
10039
+
#define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE 0x1UL
10040
+
#define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE
10041
+
u8 async_event_notification_state;
10042
+
#define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE 0x0UL
10043
+
#define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE 0x1UL
10044
+
#define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE
10045
+
u8 unused_0;
10046
+
};
10047
+
10048
+
/* hwrm_struct_data_lldp_generic (size:2112b/264B) */
10049
+
struct hwrm_struct_data_lldp_generic {
10050
+
u8 tlv_type;
10051
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS 0x1UL
10052
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT 0x2UL
10053
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME 0x3UL
10054
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION 0x4UL
10055
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME 0x5UL
10056
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION 0x6UL
10057
+
#define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION
10058
+
u8 subtype;
10059
+
u8 length;
10060
+
u8 unused1[5];
10061
+
__le32 tlv_value[64];
10062
+
};
10063
+
10064
+
/* hwrm_struct_data_lldp_device (size:1472b/184B) */
10065
+
struct hwrm_struct_data_lldp_device {
10066
+
__le16 ttl;
10067
+
u8 mgmt_addr_len;
10068
+
u8 mgmt_addr_type;
10069
+
u8 unused_3[4];
10070
+
__le32 mgmt_addr[8];
10071
+
__le32 system_caps;
10072
+
u8 intf_num_type;
10073
+
u8 mgmt_addr_oid_length;
10074
+
u8 unused_4[2];
10075
+
__le32 intf_num;
10076
+
u8 unused_5[4];
10077
+
__le32 mgmt_addr_oid[32];
10078
+
};
10079
+
10080
+
/* hwrm_struct_data_port_description (size:64b/8B) */
10081
+
struct hwrm_struct_data_port_description {
10082
+
u8 port_id;
10083
+
u8 unused_0[7];
10084
+
};
10085
+
10086
+
/* hwrm_struct_data_rss_v2 (size:128b/16B) */
10087
+
struct hwrm_struct_data_rss_v2 {
10088
+
__le16 flags;
10089
+
#define STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID 0x1UL
10090
+
__le16 rss_ctx_id;
10091
+
__le16 num_ring_groups;
10092
+
__le16 hash_type;
10093
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 0x1UL
10094
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 0x2UL
10095
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 0x4UL
10096
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 0x8UL
10097
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 0x10UL
10098
+
#define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 0x20UL
10099
+
__le64 hash_key_ring_group_ids;
10100
+
};
10101
+
10102
+
/* hwrm_struct_data_power_information (size:192b/24B) */
10103
+
struct hwrm_struct_data_power_information {
10104
+
__le32 bkup_power_info_ver;
10105
+
__le32 platform_bkup_power_count;
10106
+
__le32 load_milli_watt;
10107
+
__le32 bkup_time_milli_seconds;
10108
+
__le32 bkup_power_status;
10109
+
__le32 bkup_power_charge_time;
10110
+
};
10111
+
10112
+
/* hwrm_struct_data_peer_mmap (size:1600b/200B) */
10113
+
struct hwrm_struct_data_peer_mmap {
10114
+
__le16 fid;
10115
+
__le16 count;
10116
+
__le32 unused_0;
10117
+
__le64 hpa_0;
10118
+
__le64 gpa_0;
10119
+
__le64 size_0;
10120
+
__le64 hpa_1;
10121
+
__le64 gpa_1;
10122
+
__le64 size_1;
10123
+
__le64 hpa_2;
10124
+
__le64 gpa_2;
10125
+
__le64 size_2;
10126
+
__le64 hpa_3;
10127
+
__le64 gpa_3;
10128
+
__le64 size_3;
10129
+
__le64 hpa_4;
10130
+
__le64 gpa_4;
10131
+
__le64 size_4;
10132
+
__le64 hpa_5;
10133
+
__le64 gpa_5;
10134
+
__le64 size_5;
10135
+
__le64 hpa_6;
10136
+
__le64 gpa_6;
10137
+
__le64 size_6;
10138
+
__le64 hpa_7;
10139
+
__le64 gpa_7;
10140
+
__le64 size_7;
10141
+
};
10142
+
10143
+
/* hwrm_struct_data_peer_mmap_v2 (size:1792b/224B) */
10144
+
struct hwrm_struct_data_peer_mmap_v2 {
10145
+
__le16 fid;
10146
+
__le16 count;
10147
+
__le32 unused_0;
10148
+
__le64 hpa_0;
10149
+
__le64 gpa_0;
10150
+
__le64 size_0;
10151
+
__le64 hpa_1;
10152
+
__le64 gpa_1;
10153
+
__le64 size_1;
10154
+
__le64 hpa_2;
10155
+
__le64 gpa_2;
10156
+
__le64 size_2;
10157
+
__le64 hpa_3;
10158
+
__le64 gpa_3;
10159
+
__le64 size_3;
10160
+
__le64 hpa_4;
10161
+
__le64 gpa_4;
10162
+
__le64 size_4;
10163
+
__le64 hpa_5;
10164
+
__le64 gpa_5;
10165
+
__le64 size_5;
10166
+
__le64 hpa_6;
10167
+
__le64 gpa_6;
10168
+
__le64 size_6;
10169
+
__le64 hpa_7;
10170
+
__le64 gpa_7;
10171
+
__le64 size_7;
10172
+
__le16 ds_port;
10173
+
__le16 auth_status;
10174
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_SUCCESS 0x0UL
10175
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_NONCE_MIS 0xdUL
10176
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_SIG_INVALID 0xeUL
10177
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_AUTH_FAILED 0xfUL
10178
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_CERT_N_VAL 0x10UL
10179
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_INVA_CMD_CODE 0x11UL
10180
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_INVALID_HDR 0x12UL
10181
+
#define STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_LAST STRUCT_DATA_PEER_MMAP_V2_AUTH_STATUS_INVALID_HDR
10182
+
__le32 unused_2;
10183
+
__le16 status[8];
10184
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_SUCCESS 0x0UL
10185
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_HDR_VER_MISMATCH 0x1UL
10186
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_PKT_SOM_MISSING 0x2UL
10187
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_OUT_OF_ORDER_PKTS 0x3UL
10188
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_ALREADY_ADDED 0x4UL
10189
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_ALREADY_DELETED 0x5UL
10190
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_NOT_ADDED 0x6UL
10191
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_NOT_DELETED 0x7UL
10192
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_NO_EP_CNTX 0x8UL
10193
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_INVALID_BUF_SZ 0xaUL
10194
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_ALLOC_MEM_FAILED 0xbUL
10195
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_ENTRY_CNT_ERR 0xcUL
10196
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_NO_RESPONSE 0x13UL
10197
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_IPC_ERROR 0x14UL
10198
+
#define STRUCT_DATA_PEER_MMAP_V2_STATUS_LAST STRUCT_DATA_PEER_MMAP_V2_STATUS_IPC_ERROR
10199
+
};
10200
+
10201
+
/* hwrm_struct_data_msix_per_vf (size:320b/40B) */
10202
+
struct hwrm_struct_data_msix_per_vf {
10203
+
__le16 pf_id;
10204
+
__le16 count;
10205
+
__le32 unused_0;
10206
+
__le16 start_vf_0;
10207
+
__le16 msix_0;
10208
+
__le16 start_vf_1;
10209
+
__le16 msix_1;
10210
+
__le16 start_vf_2;
10211
+
__le16 msix_2;
10212
+
__le16 start_vf_3;
10213
+
__le16 msix_3;
10214
+
__le16 start_vf_4;
10215
+
__le16 msix_4;
10216
+
__le16 start_vf_5;
10217
+
__le16 msix_5;
10218
+
__le16 start_vf_6;
10219
+
__le16 msix_6;
10220
+
__le16 start_vf_7;
10221
+
__le16 msix_7;
10222
+
};
10223
+
10224
+
/* hwrm_struct_data_dbg_token_claims (size:128b/16B) */
10225
+
struct hwrm_struct_data_dbg_token_claims {
10226
+
__s32 claim_number;
10227
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_EXP 4
10228
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_CTI 7
10229
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_AUTH_ID -67000
10230
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_PERSIST -67001
10231
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_SDB_EN -68000
10232
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_DIAGRW_EN -68003
10233
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_FW_CLI -68100
10234
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_LAST STRUCT_DATA_DBG_TOKEN_CLAIMS_CLAIM_NUMBER_FW_CLI
10235
+
__le16 data_type;
10236
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_UINT_1_BYTE 0x1UL
10237
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_UINT_2_BYTES 0x2UL
10238
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_UINT_4_BYTES 0x3UL
10239
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_UINT_8_BYTES 0x4UL
10240
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_BOOLEAN 0x5UL
10241
+
#define STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_LAST STRUCT_DATA_DBG_TOKEN_CLAIMS_DATA_TYPE_BOOLEAN
10242
+
__le16 unused_0;
10243
+
u8 claim_data[8];
10244
+
};
10245
+
10246
+
/* hwrm_fw_set_structured_data_input (size:256b/32B) */
10247
+
struct hwrm_fw_set_structured_data_input {
10248
+
__le16 req_type;
10249
+
__le16 cmpl_ring;
10250
+
__le16 seq_id;
10251
+
__le16 target_id;
10252
+
__le64 resp_addr;
10253
+
__le64 src_data_addr;
10254
+
__le16 data_len;
10255
+
u8 hdr_cnt;
10256
+
u8 unused_0[5];
10257
+
};
10258
+
10259
+
/* hwrm_fw_set_structured_data_output (size:128b/16B) */
10260
+
struct hwrm_fw_set_structured_data_output {
10261
+
__le16 error_code;
10262
+
__le16 req_type;
10263
+
__le16 seq_id;
10264
+
__le16 resp_len;
10265
+
u8 unused_0[7];
10266
+
u8 valid;
10267
+
};
10268
+
10269
+
/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
10270
+
struct hwrm_fw_set_structured_data_cmd_err {
10271
+
u8 code;
10272
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
10273
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
10274
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
10275
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
10276
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_ALREADY_ADDED 0x4UL
10277
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 0x5UL
10278
+
#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG
10279
+
u8 unused_0[7];
10280
+
};
10281
+
10282
+
/* hwrm_fw_get_structured_data_input (size:256b/32B) */
10283
+
struct hwrm_fw_get_structured_data_input {
10284
+
__le16 req_type;
10285
+
__le16 cmpl_ring;
10286
+
__le16 seq_id;
10287
+
__le16 target_id;
10288
+
__le64 resp_addr;
10289
+
__le64 dest_data_addr;
10290
+
__le16 data_len;
10291
+
__le16 structure_id;
10292
+
__le16 subtype;
10293
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
10294
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
10295
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
10296
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
10297
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
10298
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
10299
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
10300
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
10301
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
10302
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_SUPPORTED 0x320UL
10303
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 0x321UL
10304
+
#define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE
10305
+
u8 count;
10306
+
u8 unused_0;
10307
+
};
10308
+
10309
+
/* hwrm_fw_get_structured_data_output (size:128b/16B) */
10310
+
struct hwrm_fw_get_structured_data_output {
10311
+
__le16 error_code;
10312
+
__le16 req_type;
10313
+
__le16 seq_id;
10314
+
__le16 resp_len;
10315
+
u8 hdr_cnt;
10316
+
u8 unused_0[6];
10317
+
u8 valid;
10318
+
};
10319
+
10320
+
/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
10321
+
struct hwrm_fw_get_structured_data_cmd_err {
10322
+
u8 code;
10323
+
#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
10324
+
#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
10325
+
#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
10326
+
u8 unused_0[7];
10327
+
};
10328
+
10329
+
/* hwrm_fw_ipc_msg_input (size:320b/40B) */
10330
+
struct hwrm_fw_ipc_msg_input {
10331
+
__le16 req_type;
10332
+
__le16 cmpl_ring;
10333
+
__le16 seq_id;
10334
+
__le16 target_id;
10335
+
__le64 resp_addr;
10336
+
__le32 enables;
10337
+
#define FW_IPC_MSG_REQ_ENABLES_COMMAND_ID 0x1UL
10338
+
#define FW_IPC_MSG_REQ_ENABLES_SRC_PROCESSOR 0x2UL
10339
+
#define FW_IPC_MSG_REQ_ENABLES_DATA_OFFSET 0x4UL
10340
+
#define FW_IPC_MSG_REQ_ENABLES_LENGTH 0x8UL
10341
+
__le16 command_id;
10342
+
#define FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG 0x1UL
10343
+
#define FW_IPC_MSG_REQ_COMMAND_ID_MHB_HOST 0x2UL
10344
+
#define FW_IPC_MSG_REQ_COMMAND_ID_ROCE_DRVR_VERSION 0x3UL
10345
+
#define FW_IPC_MSG_REQ_COMMAND_ID_LOG2H 0x4UL
10346
+
#define FW_IPC_MSG_REQ_COMMAND_ID_LAST FW_IPC_MSG_REQ_COMMAND_ID_LOG2H
10347
+
u8 src_processor;
10348
+
#define FW_IPC_MSG_REQ_SRC_PROCESSOR_CFW 0x1UL
10349
+
#define FW_IPC_MSG_REQ_SRC_PROCESSOR_BONO 0x2UL
10350
+
#define FW_IPC_MSG_REQ_SRC_PROCESSOR_APE 0x3UL
10351
+
#define FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG 0x4UL
10352
+
#define FW_IPC_MSG_REQ_SRC_PROCESSOR_LAST FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG
10353
+
u8 unused_0;
10354
+
__le32 data_offset;
10355
+
__le16 length;
10356
+
u8 unused_1[2];
10357
+
__le64 opaque;
10358
+
};
10359
+
10360
+
/* hwrm_fw_ipc_msg_output (size:256b/32B) */
10361
+
struct hwrm_fw_ipc_msg_output {
10362
+
__le16 error_code;
10363
+
__le16 req_type;
10364
+
__le16 seq_id;
10365
+
__le16 resp_len;
10366
+
__le32 msg_data_1;
10367
+
__le32 msg_data_2;
10368
+
__le64 reserved64;
10369
+
u8 reserved48[7];
10370
+
u8 valid;
10371
+
};
10372
+
10373
+
/* hwrm_fw_ipc_mailbox_input (size:256b/32B) */
10374
+
struct hwrm_fw_ipc_mailbox_input {
10375
+
__le16 req_type;
10376
+
__le16 cmpl_ring;
10377
+
__le16 seq_id;
10378
+
__le16 target_id;
10379
+
__le64 resp_addr;
10380
+
u8 flags;
10381
+
u8 unused;
10382
+
u8 event_id;
10383
+
u8 port_id;
10384
+
__le32 event_data1;
10385
+
__le32 event_data2;
10386
+
u8 unused_0[4];
10387
+
};
10388
+
10389
+
/* hwrm_fw_ipc_mailbox_output (size:128b/16B) */
10390
+
struct hwrm_fw_ipc_mailbox_output {
10391
+
__le16 error_code;
10392
+
__le16 req_type;
10393
+
__le16 seq_id;
10394
+
__le16 resp_len;
10395
+
u8 unused_0[7];
10396
+
u8 valid;
10397
+
};
10398
+
10399
+
/* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */
10400
+
struct hwrm_fw_ipc_mailbox_cmd_err {
10401
+
u8 code;
10402
+
#define FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN 0x0UL
10403
+
#define FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID 0x3UL
10404
+
#define FW_IPC_MAILBOX_CMD_ERR_CODE_LAST FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID
10405
+
u8 unused_0[7];
10406
+
};
10407
+
10408
+
/* hwrm_fw_ecn_cfg_input (size:192b/24B) */
10409
+
struct hwrm_fw_ecn_cfg_input {
10410
+
__le16 req_type;
10411
+
__le16 cmpl_ring;
10412
+
__le16 seq_id;
10413
+
__le16 target_id;
10414
+
__le64 resp_addr;
10415
+
__le16 flags;
10416
+
#define FW_ECN_CFG_REQ_FLAGS_ENABLE_ECN 0x1UL
10417
+
u8 unused_0[6];
10418
+
};
10419
+
10420
+
/* hwrm_fw_ecn_cfg_output (size:128b/16B) */
10421
+
struct hwrm_fw_ecn_cfg_output {
10422
+
__le16 error_code;
10423
+
__le16 req_type;
10424
+
__le16 seq_id;
10425
+
__le16 resp_len;
10426
+
u8 unused_0[7];
10427
+
u8 valid;
10428
+
};
10429
+
10430
+
/* hwrm_fw_ecn_qcfg_input (size:128b/16B) */
10431
+
struct hwrm_fw_ecn_qcfg_input {
10432
+
__le16 req_type;
10433
+
__le16 cmpl_ring;
10434
+
__le16 seq_id;
10435
+
__le16 target_id;
10436
+
__le64 resp_addr;
10437
+
};
10438
+
10439
+
/* hwrm_fw_ecn_qcfg_output (size:128b/16B) */
10440
+
struct hwrm_fw_ecn_qcfg_output {
10441
+
__le16 error_code;
10442
+
__le16 req_type;
10443
+
__le16 seq_id;
10444
+
__le16 resp_len;
10445
+
__le16 flags;
10446
+
#define FW_ECN_QCFG_RESP_FLAGS_ENABLE_ECN 0x1UL
10447
+
u8 unused_0[5];
10448
+
u8 valid;
10449
+
};
10450
+
10451
+
/* hwrm_fw_health_check_input (size:128b/16B) */
10452
+
struct hwrm_fw_health_check_input {
10453
+
__le16 req_type;
10454
+
__le16 cmpl_ring;
10455
+
__le16 seq_id;
10456
+
__le16 target_id;
10457
+
__le64 resp_addr;
10458
+
};
10459
+
10460
+
/* hwrm_fw_health_check_output (size:128b/16B) */
10461
+
struct hwrm_fw_health_check_output {
10462
+
__le16 error_code;
10463
+
__le16 req_type;
10464
+
__le16 seq_id;
10465
+
__le16 resp_len;
10466
+
__le32 fw_status;
10467
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_BOOTED 0x1UL
10468
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_MISMATCH 0x2UL
10469
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_BOOTED 0x4UL
10470
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_MISMATCH 0x8UL
10471
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_BOOTED 0x10UL
10472
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_MISMATCH 0x20UL
10473
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SECOND_RT 0x40UL
10474
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_FASTBOOTED 0x80UL
10475
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_DIR_HDR_BOOTED 0x100UL
10476
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_DIR_HDR_MISMATCH 0x200UL
10477
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_MBR_CORRUPT 0x400UL
10478
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_CFG_MISMATCH 0x800UL
10479
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_FRU_MISMATCH 0x1000UL
10480
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT2_BOOTED 0x2000UL
10481
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT2_MISMATCH 0x4000UL
10482
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_GXRT_BOOTED 0x8000UL
10483
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_GXRT_MISMATCH 0x10000UL
10484
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT2_BOOTED 0x20000UL
10485
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT2_MISMATCH 0x40000UL
10486
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_ART_MISMATCH 0x80000UL
10487
+
#define FW_HEALTH_CHECK_RESP_FW_STATUS_ART_BOOTED 0x100000UL
10488
+
u8 unused_0[3];
10489
+
u8 valid;
10490
+
};
10491
+
10492
+
/* hwrm_fw_livepatch_query_input (size:192b/24B) */
10493
+
struct hwrm_fw_livepatch_query_input {
10494
+
__le16 req_type;
10495
+
__le16 cmpl_ring;
10496
+
__le16 seq_id;
10497
+
__le16 target_id;
10498
+
__le64 resp_addr;
10499
+
u8 fw_target;
10500
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL
10501
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL
10502
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_MPRT_FW 0x3UL
10503
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_RERT_FW 0x4UL
10504
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_AUXRT_FW 0x5UL
10505
+
#define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_AUXRT_FW
10506
+
u8 unused_0[7];
10507
+
};
10508
+
10509
+
/* hwrm_fw_livepatch_query_output (size:640b/80B) */
10510
+
struct hwrm_fw_livepatch_query_output {
10511
+
__le16 error_code;
10512
+
__le16 req_type;
10513
+
__le16 seq_id;
10514
+
__le16 resp_len;
10515
+
char install_ver[32];
10516
+
char active_ver[32];
10517
+
__le16 status_flags;
10518
+
#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL
10519
+
#define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL
10520
+
u8 unused_0[5];
10521
+
u8 valid;
10522
+
};
10523
+
10524
+
/* hwrm_fw_livepatch_input (size:256b/32B) */
10525
+
struct hwrm_fw_livepatch_input {
10526
+
__le16 req_type;
10527
+
__le16 cmpl_ring;
10528
+
__le16 seq_id;
10529
+
__le16 target_id;
10530
+
__le64 resp_addr;
10531
+
u8 opcode;
10532
+
#define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL
10533
+
#define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL
10534
+
#define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE
10535
+
u8 fw_target;
10536
+
#define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL
10537
+
#define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL
10538
+
#define FW_LIVEPATCH_REQ_FW_TARGET_MPRT_FW 0x3UL
10539
+
#define FW_LIVEPATCH_REQ_FW_TARGET_RERT_FW 0x4UL
10540
+
#define FW_LIVEPATCH_REQ_FW_TARGET_AUXRT_FW 0x5UL
10541
+
#define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_AUXRT_FW
10542
+
u8 loadtype;
10543
+
#define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL
10544
+
#define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL
10545
+
#define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT
10546
+
u8 flags;
10547
+
__le32 patch_len;
10548
+
__le64 host_addr;
10549
+
};
10550
+
10551
+
/* hwrm_fw_livepatch_output (size:128b/16B) */
10552
+
struct hwrm_fw_livepatch_output {
10553
+
__le16 error_code;
10554
+
__le16 req_type;
10555
+
__le16 seq_id;
10556
+
__le16 resp_len;
10557
+
u8 unused_0[7];
10558
+
u8 valid;
10559
+
};
10560
+
10561
+
/* hwrm_fw_sync_input (size:192b/24B) */
10562
+
struct hwrm_fw_sync_input {
10563
+
__le16 req_type;
10564
+
__le16 cmpl_ring;
10565
+
__le16 seq_id;
10566
+
__le16 target_id;
10567
+
__le64 resp_addr;
10568
+
__le32 sync_action;
10569
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_SBI 0x1UL
10570
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_SRT 0x2UL
10571
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_CRT 0x4UL
10572
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_DIR_HDR 0x8UL
10573
+
#define FW_SYNC_REQ_SYNC_ACTION_WRITE_MBR 0x10UL
10574
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_CFG 0x20UL
10575
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_FRU 0x40UL
10576
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_CRT2 0x80UL
10577
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_GXRT 0x100UL
10578
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_SRT2 0x200UL
10579
+
#define FW_SYNC_REQ_SYNC_ACTION_SYNC_ART 0x400UL
10580
+
#define FW_SYNC_REQ_SYNC_ACTION_ACTION 0x80000000UL
10581
+
u8 unused_0[4];
10582
+
};
10583
+
10584
+
/* hwrm_fw_sync_output (size:128b/16B) */
10585
+
struct hwrm_fw_sync_output {
10586
+
__le16 error_code;
10587
+
__le16 req_type;
10588
+
__le16 seq_id;
10589
+
__le16 resp_len;
10590
+
__le32 sync_status;
10591
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_MASK 0xffUL
10592
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SFT 0
10593
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SUCCESS 0x0UL
10594
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_IN_PROGRESS 0x1UL
10595
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_TIMEOUT 0x2UL
10596
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL 0x3UL
10597
+
#define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_LAST FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL
10598
+
#define FW_SYNC_RESP_SYNC_STATUS_SYNC_ERR 0x40000000UL
10599
+
#define FW_SYNC_RESP_SYNC_STATUS_SYNC_COMPLETE 0x80000000UL
10600
+
u8 unused_0[3];
10601
+
u8 valid;
10602
+
};
10603
+
10604
+
/* hwrm_fw_sync_cmd_err (size:64b/8B) */
10605
+
struct hwrm_fw_sync_cmd_err {
10606
+
u8 code;
10607
+
#define FW_SYNC_CMD_ERR_CODE_UNKNOWN 0x0UL
10608
+
#define FW_SYNC_CMD_ERR_CODE_INVALID_LEN 0x1UL
10609
+
#define FW_SYNC_CMD_ERR_CODE_INVALID_CRID 0x2UL
10610
+
#define FW_SYNC_CMD_ERR_CODE_NO_WORKSPACE_MEM 0x2UL
10611
+
#define FW_SYNC_CMD_ERR_CODE_SYNC_FAILED 0x3UL
10612
+
#define FW_SYNC_CMD_ERR_CODE_LAST FW_SYNC_CMD_ERR_CODE_SYNC_FAILED
10613
+
u8 unused_0[7];
10614
+
};
10615
+
10616
+
/* hwrm_fw_state_qcaps_input (size:128b/16B) */
10617
+
struct hwrm_fw_state_qcaps_input {
10618
+
__le16 req_type;
10619
+
__le16 cmpl_ring;
10620
+
__le16 seq_id;
10621
+
__le16 target_id;
10622
+
__le64 resp_addr;
10623
+
};
10624
+
10625
+
/* hwrm_fw_state_qcaps_output (size:256b/32B) */
10626
+
struct hwrm_fw_state_qcaps_output {
10627
+
__le16 error_code;
10628
+
__le16 req_type;
10629
+
__le16 seq_id;
10630
+
__le16 resp_len;
10631
+
__le32 backup_memory;
10632
+
__le32 quiesce_timeout;
10633
+
__le32 fw_status_blackout;
10634
+
__le32 fw_status_max_wait;
10635
+
u8 unused_0[4];
10636
+
u8 unused_1[3];
10637
+
u8 valid;
10638
+
};
10639
+
10640
+
/* hwrm_fw_state_quiesce_input (size:192b/24B) */
10641
+
struct hwrm_fw_state_quiesce_input {
10642
+
__le16 req_type;
10643
+
__le16 cmpl_ring;
10644
+
__le16 seq_id;
10645
+
__le16 target_id;
10646
+
__le64 resp_addr;
10647
+
u8 flags;
10648
+
#define FW_STATE_QUIESCE_REQ_FLAGS_ERROR_RECOVERY 0x1UL
10649
+
u8 unused_0[7];
10650
+
};
10651
+
10652
+
/* hwrm_fw_state_quiesce_output (size:192b/24B) */
10653
+
struct hwrm_fw_state_quiesce_output {
10654
+
__le16 error_code;
10655
+
__le16 req_type;
10656
+
__le16 seq_id;
10657
+
__le16 resp_len;
10658
+
__le32 quiesce_status;
10659
+
#define FW_STATE_QUIESCE_RESP_QUIESCE_STATUS_INITIATED 0x80000000UL
10660
+
u8 unused_0[4];
10661
+
u8 unused_1[7];
10662
+
u8 valid;
10663
+
};
10664
+
10665
+
/* hwrm_fw_state_unquiesce_input (size:128b/16B) */
10666
+
struct hwrm_fw_state_unquiesce_input {
10667
+
__le16 req_type;
10668
+
__le16 cmpl_ring;
10669
+
__le16 seq_id;
10670
+
__le16 target_id;
10671
+
__le64 resp_addr;
10672
+
};
10673
+
10674
+
/* hwrm_fw_state_unquiesce_output (size:192b/24B) */
10675
+
struct hwrm_fw_state_unquiesce_output {
10676
+
__le16 error_code;
10677
+
__le16 req_type;
10678
+
__le16 seq_id;
10679
+
__le16 resp_len;
10680
+
__le32 unquiesce_status;
10681
+
#define FW_STATE_UNQUIESCE_RESP_UNQUIESCE_STATUS_COMPLETE 0x80000000UL
10682
+
u8 unused_0[4];
10683
+
u8 unused_1[7];
10684
+
u8 valid;
10685
+
};
10686
+
10687
+
/* hwrm_fw_state_backup_input (size:256b/32B) */
10688
+
struct hwrm_fw_state_backup_input {
10689
+
__le16 req_type;
10690
+
__le16 cmpl_ring;
10691
+
__le16 seq_id;
10692
+
__le16 target_id;
10693
+
__le64 resp_addr;
10694
+
u8 backup_pg_size_backup_lvl;
10695
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_MASK 0xfUL
10696
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_SFT 0
10697
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_LVL_0 0x0UL
10698
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_LVL_1 0x1UL
10699
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_LVL_2 0x2UL
10700
+
#define FW_STATE_BACKUP_REQ_BACKUP_LVL_LAST FW_STATE_BACKUP_REQ_BACKUP_LVL_LVL_2
10701
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_MASK 0xf0UL
10702
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_SFT 4
10703
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_4K (0x0UL << 4)
10704
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_8K (0x1UL << 4)
10705
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_64K (0x2UL << 4)
10706
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_2M (0x3UL << 4)
10707
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_8M (0x4UL << 4)
10708
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_1G (0x5UL << 4)
10709
+
#define FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_LAST FW_STATE_BACKUP_REQ_BACKUP_PG_SIZE_PG_1G
10710
+
u8 unused_0[7];
10711
+
__le64 backup_page_dir;
10712
+
};
10713
+
10714
+
/* hwrm_fw_state_backup_output (size:192b/24B) */
10715
+
struct hwrm_fw_state_backup_output {
10716
+
__le16 error_code;
10717
+
__le16 req_type;
10718
+
__le16 seq_id;
10719
+
__le16 resp_len;
10720
+
__le32 backup_status;
10721
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_MASK 0xffUL
10722
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_SFT 0
10723
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_SUCCESS 0x0UL
10724
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR 0x1UL
10725
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_GENERAL 0x3UL
10726
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_LAST FW_STATE_BACKUP_RESP_BACKUP_STATUS_ERR_CODE_GENERAL
10727
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_RESET_REQUIRED 0x40000000UL
10728
+
#define FW_STATE_BACKUP_RESP_BACKUP_STATUS_COMPLETE 0x80000000UL
10729
+
u8 unused_0[4];
10730
+
u8 unused_1[7];
10731
+
u8 valid;
10732
+
};
10733
+
10734
+
/* hwrm_fw_state_restore_input (size:256b/32B) */
10735
+
struct hwrm_fw_state_restore_input {
10736
+
__le16 req_type;
10737
+
__le16 cmpl_ring;
10738
+
__le16 seq_id;
10739
+
__le16 target_id;
10740
+
__le64 resp_addr;
10741
+
u8 restore_pg_size_restore_lvl;
10742
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_MASK 0xfUL
10743
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_SFT 0
10744
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_LVL_0 0x0UL
10745
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_LVL_1 0x1UL
10746
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_LVL_2 0x2UL
10747
+
#define FW_STATE_RESTORE_REQ_RESTORE_LVL_LAST FW_STATE_RESTORE_REQ_RESTORE_LVL_LVL_2
10748
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_MASK 0xf0UL
10749
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_SFT 4
10750
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_4K (0x0UL << 4)
10751
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_8K (0x1UL << 4)
10752
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_64K (0x2UL << 4)
10753
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_2M (0x3UL << 4)
10754
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_8M (0x4UL << 4)
10755
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_1G (0x5UL << 4)
10756
+
#define FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_LAST FW_STATE_RESTORE_REQ_RESTORE_PG_SIZE_PG_1G
10757
+
u8 unused_0[7];
10758
+
__le64 restore_page_dir;
10759
+
};
10760
+
10761
+
/* hwrm_fw_state_restore_output (size:128b/16B) */
10762
+
struct hwrm_fw_state_restore_output {
10763
+
__le16 error_code;
10764
+
__le16 req_type;
10765
+
__le16 seq_id;
10766
+
__le16 resp_len;
10767
+
__le32 restore_status;
10768
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_MASK 0xffUL
10769
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_SFT 0
10770
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_SUCCESS 0x0UL
10771
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_GENERAL 0x1UL
10772
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE 0x2UL
10773
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK 0x3UL
10774
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_LAST FW_STATE_RESTORE_RESP_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK
10775
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED 0x40000000UL
10776
+
#define FW_STATE_RESTORE_RESP_RESTORE_STATUS_COMPLETE 0x80000000UL
10777
+
u8 unused_0[3];
10778
+
u8 valid;
10779
+
};
10780
+
10781
+
/* hwrm_fw_secure_cfg_input (size:256b/32B) */
10782
+
struct hwrm_fw_secure_cfg_input {
10783
+
__le16 req_type;
10784
+
__le16 cmpl_ring;
10785
+
__le16 seq_id;
10786
+
__le16 target_id;
10787
+
__le64 resp_addr;
10788
+
u8 enable;
10789
+
#define FW_SECURE_CFG_REQ_ENABLE_NVRAM 0x1UL
10790
+
#define FW_SECURE_CFG_REQ_ENABLE_GRC 0x2UL
10791
+
#define FW_SECURE_CFG_REQ_ENABLE_UART 0x3UL
10792
+
#define FW_SECURE_CFG_REQ_ENABLE_LAST FW_SECURE_CFG_REQ_ENABLE_UART
10793
+
u8 config_mode;
10794
+
#define FW_SECURE_CFG_REQ_CONFIG_MODE_PERSISTENT 0x1UL
10795
+
#define FW_SECURE_CFG_REQ_CONFIG_MODE_RUNTIME 0x2UL
10796
+
u8 nvm_lock_mode;
10797
+
#define FW_SECURE_CFG_REQ_NVM_LOCK_MODE_NONE 0x0UL
10798
+
#define FW_SECURE_CFG_REQ_NVM_LOCK_MODE_PARTIAL 0x1UL
10799
+
#define FW_SECURE_CFG_REQ_NVM_LOCK_MODE_FULL 0x2UL
10800
+
#define FW_SECURE_CFG_REQ_NVM_LOCK_MODE_CHIP 0x3UL
10801
+
#define FW_SECURE_CFG_REQ_NVM_LOCK_MODE_LAST FW_SECURE_CFG_REQ_NVM_LOCK_MODE_CHIP
10802
+
u8 nvm_partial_lock_mask;
10803
+
#define FW_SECURE_CFG_REQ_NVM_PARTIAL_LOCK_MASK_EXE 0x1UL
10804
+
#define FW_SECURE_CFG_REQ_NVM_PARTIAL_LOCK_MASK_CFG 0x2UL
10805
+
u8 grc_ctrl;
10806
+
#define FW_SECURE_CFG_REQ_GRC_CTRL_RO 0x0UL
10807
+
#define FW_SECURE_CFG_REQ_GRC_CTRL_RW 0x1UL
10808
+
#define FW_SECURE_CFG_REQ_GRC_CTRL_LAST FW_SECURE_CFG_REQ_GRC_CTRL_RW
10809
+
u8 uart_ctrl;
10810
+
#define FW_SECURE_CFG_REQ_UART_CTRL_DISABLE 0x0UL
10811
+
#define FW_SECURE_CFG_REQ_UART_CTRL_ENABLE 0x1UL
10812
+
#define FW_SECURE_CFG_REQ_UART_CTRL_LAST FW_SECURE_CFG_REQ_UART_CTRL_ENABLE
10813
+
u8 unused_0[2];
10814
+
__le32 unused_1[2];
10815
+
};
10816
+
10817
+
/* hwrm_fw_secure_cfg_output (size:128b/16B) */
10818
+
struct hwrm_fw_secure_cfg_output {
10819
+
__le16 error_code;
10820
+
__le16 req_type;
10821
+
__le16 seq_id;
10822
+
__le16 resp_len;
10823
+
u8 unused_0[7];
10824
+
u8 valid;
10825
+
};
10826
+
10827
+
/* hwrm_exec_fwd_resp_input (size:1024b/128B) */
10828
+
struct hwrm_exec_fwd_resp_input {
10829
+
__le16 req_type;
10830
+
__le16 cmpl_ring;
10831
+
__le16 seq_id;
10832
+
__le16 target_id;
10833
+
__le64 resp_addr;
10834
+
__le32 encap_request[26];
10835
+
__le16 encap_resp_target_id;
10836
+
u8 unused_0[6];
10837
+
};
10838
+
10839
+
/* hwrm_exec_fwd_resp_output (size:128b/16B) */
10840
+
struct hwrm_exec_fwd_resp_output {
10841
+
__le16 error_code;
10842
+
__le16 req_type;
10843
+
__le16 seq_id;
10844
+
__le16 resp_len;
10845
+
u8 unused_0[7];
10846
+
u8 valid;
10847
+
};
10848
+
10849
+
/* hwrm_reject_fwd_resp_input (size:1024b/128B) */
10850
+
struct hwrm_reject_fwd_resp_input {
10851
+
__le16 req_type;
10852
+
__le16 cmpl_ring;
10853
+
__le16 seq_id;
10854
+
__le16 target_id;
10855
+
__le64 resp_addr;
10856
+
__le32 encap_request[26];
10857
+
__le16 encap_resp_target_id;
10858
+
u8 unused_0[6];
10859
+
};
10860
+
10861
+
/* hwrm_reject_fwd_resp_output (size:128b/16B) */
10862
+
struct hwrm_reject_fwd_resp_output {
10863
+
__le16 error_code;
10864
+
__le16 req_type;
10865
+
__le16 seq_id;
10866
+
__le16 resp_len;
10867
+
u8 unused_0[7];
10868
+
u8 valid;
10869
+
};
10870
+
10871
+
/* hwrm_fwd_resp_input (size:1792b/224B) */
10872
+
struct hwrm_fwd_resp_input {
10873
+
__le16 req_type;
10874
+
__le16 cmpl_ring;
10875
+
__le16 seq_id;
10876
+
__le16 target_id;
10877
+
__le64 resp_addr;
10878
+
__le16 encap_resp_target_id;
10879
+
__le16 encap_resp_cmpl_ring;
10880
+
__le16 encap_resp_len;
10881
+
u8 unused_0;
10882
+
u8 unused_1;
10883
+
__le64 encap_resp_addr;
10884
+
__le32 encap_resp[48];
10885
+
};
10886
+
10887
+
/* hwrm_fwd_resp_output (size:128b/16B) */
10888
+
struct hwrm_fwd_resp_output {
10889
+
__le16 error_code;
10890
+
__le16 req_type;
10891
+
__le16 seq_id;
10892
+
__le16 resp_len;
10893
+
u8 unused_0[7];
10894
+
u8 valid;
10895
+
};
10896
+
10897
+
/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
10898
+
struct hwrm_fwd_async_event_cmpl_input {
10899
+
__le16 req_type;
10900
+
__le16 cmpl_ring;
10901
+
__le16 seq_id;
10902
+
__le16 target_id;
10903
+
__le64 resp_addr;
10904
+
__le16 encap_async_event_target_id;
10905
+
u8 unused_0[6];
10906
+
__le32 encap_async_event_cmpl[4];
10907
+
};
10908
+
10909
+
/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
10910
+
struct hwrm_fwd_async_event_cmpl_output {
10911
+
__le16 error_code;
10912
+
__le16 req_type;
10913
+
__le16 seq_id;
10914
+
__le16 resp_len;
10915
+
u8 unused_0[7];
10916
+
u8 valid;
10917
+
};
10918
+
10919
+
/* hwrm_temp_monitor_query_input (size:128b/16B) */
10920
+
struct hwrm_temp_monitor_query_input {
10921
+
__le16 req_type;
10922
+
__le16 cmpl_ring;
10923
+
__le16 seq_id;
10924
+
__le16 target_id;
10925
+
__le64 resp_addr;
10926
+
};
10927
+
10928
+
/* hwrm_temp_monitor_query_output (size:192b/24B) */
10929
+
struct hwrm_temp_monitor_query_output {
10930
+
__le16 error_code;
10931
+
__le16 req_type;
10932
+
__le16 seq_id;
10933
+
__le16 resp_len;
10934
+
u8 temp;
10935
+
u8 phy_temp;
10936
+
u8 om_temp;
10937
+
u8 flags;
10938
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
10939
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
10940
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
10941
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
10942
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL
10943
+
#define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL
10944
+
u8 temp2;
10945
+
u8 phy_temp2;
10946
+
u8 om_temp2;
10947
+
u8 warn_threshold;
10948
+
u8 critical_threshold;
10949
+
u8 fatal_threshold;
10950
+
u8 shutdown_threshold;
10951
+
u8 unused_0[4];
10952
+
u8 valid;
10953
+
};
10954
+
10955
+
/* hwrm_reg_power_query_input (size:128b/16B) */
10956
+
struct hwrm_reg_power_query_input {
10957
+
__le16 req_type;
10958
+
__le16 cmpl_ring;
10959
+
__le16 seq_id;
10960
+
__le16 target_id;
10961
+
__le64 resp_addr;
10962
+
};
10963
+
10964
+
/* hwrm_reg_power_query_output (size:192b/24B) */
10965
+
struct hwrm_reg_power_query_output {
10966
+
__le16 error_code;
10967
+
__le16 req_type;
10968
+
__le16 seq_id;
10969
+
__le16 resp_len;
10970
+
__le32 flags;
10971
+
#define REG_POWER_QUERY_RESP_FLAGS_IN_POWER_AVAILABLE 0x1UL
10972
+
#define REG_POWER_QUERY_RESP_FLAGS_OUT_POWER_AVAILABLE 0x2UL
10973
+
__le32 in_power_mw;
10974
+
__le32 out_power_mw;
10975
+
u8 unused_0[3];
10976
+
u8 valid;
10977
+
};
10978
+
10979
+
/* hwrm_core_frequency_query_input (size:128b/16B) */
10980
+
struct hwrm_core_frequency_query_input {
10981
+
__le16 req_type;
10982
+
__le16 cmpl_ring;
10983
+
__le16 seq_id;
10984
+
__le16 target_id;
10985
+
__le64 resp_addr;
10986
+
};
10987
+
10988
+
/* hwrm_core_frequency_query_output (size:128b/16B) */
10989
+
struct hwrm_core_frequency_query_output {
10990
+
__le16 error_code;
10991
+
__le16 req_type;
10992
+
__le16 seq_id;
10993
+
__le16 resp_len;
10994
+
__le32 core_frequency_hz;
10995
+
u8 unused_0[3];
10996
+
u8 valid;
10997
+
};
10998
+
10999
+
/* hwrm_reg_power_histogram_input (size:192b/24B) */
11000
+
struct hwrm_reg_power_histogram_input {
11001
+
__le16 req_type;
11002
+
__le16 cmpl_ring;
11003
+
__le16 seq_id;
11004
+
__le16 target_id;
11005
+
__le64 resp_addr;
11006
+
__le32 flags;
11007
+
#define REG_POWER_HISTOGRAM_REQ_FLAGS_CLEAR_HISTOGRAM 0x1UL
11008
+
__le32 unused_0;
11009
+
};
11010
+
11011
+
/* hwrm_reg_power_histogram_output (size:1088b/136B) */
11012
+
struct hwrm_reg_power_histogram_output {
11013
+
__le16 error_code;
11014
+
__le16 req_type;
11015
+
__le16 seq_id;
11016
+
__le16 resp_len;
11017
+
__le16 flags;
11018
+
#define REG_POWER_HISTOGRAM_RESP_FLAGS_POWER_IN_OUT 0x1UL
11019
+
#define REG_POWER_HISTOGRAM_RESP_FLAGS_POWER_IN_OUT_INPUT 0x0UL
11020
+
#define REG_POWER_HISTOGRAM_RESP_FLAGS_POWER_IN_OUT_OUTPUT 0x1UL
11021
+
#define REG_POWER_HISTOGRAM_RESP_FLAGS_POWER_IN_OUT_LAST REG_POWER_HISTOGRAM_RESP_FLAGS_POWER_IN_OUT_OUTPUT
11022
+
u8 unused_0[2];
11023
+
__le32 sampling_period;
11024
+
__le64 sample_count;
11025
+
__le32 power_hist[26];
11026
+
u8 unused_1[7];
11027
+
u8 valid;
11028
+
};
11029
+
11030
+
#define BUCKET_NO_DATA_FOR_SAMPLE 0x0UL
11031
+
#define BUCKET_RANGE_8W_OR_LESS 0x1UL
11032
+
#define BUCKET_RANGE_8W_TO_9W 0x2UL
11033
+
#define BUCKET_RANGE_9W_TO_10W 0x3UL
11034
+
#define BUCKET_RANGE_10W_TO_11W 0x4UL
11035
+
#define BUCKET_RANGE_11W_TO_12W 0x5UL
11036
+
#define BUCKET_RANGE_12W_TO_13W 0x6UL
11037
+
#define BUCKET_RANGE_13W_TO_14W 0x7UL
11038
+
#define BUCKET_RANGE_14W_TO_15W 0x8UL
11039
+
#define BUCKET_RANGE_15W_TO_16W 0x9UL
11040
+
#define BUCKET_RANGE_16W_TO_18W 0xaUL
11041
+
#define BUCKET_RANGE_18W_TO_20W 0xbUL
11042
+
#define BUCKET_RANGE_20W_TO_22W 0xcUL
11043
+
#define BUCKET_RANGE_22W_TO_24W 0xdUL
11044
+
#define BUCKET_RANGE_24W_TO_26W 0xeUL
11045
+
#define BUCKET_RANGE_26W_TO_28W 0xfUL
11046
+
#define BUCKET_RANGE_28W_TO_30W 0x10UL
11047
+
#define BUCKET_RANGE_30W_TO_32W 0x11UL
11048
+
#define BUCKET_RANGE_32W_TO_34W 0x12UL
11049
+
#define BUCKET_RANGE_34W_TO_36W 0x13UL
11050
+
#define BUCKET_RANGE_36W_TO_38W 0x14UL
11051
+
#define BUCKET_RANGE_38W_TO_40W 0x15UL
11052
+
#define BUCKET_RANGE_40W_TO_42W 0x16UL
11053
+
#define BUCKET_RANGE_42W_TO_44W 0x17UL
11054
+
#define BUCKET_RANGE_44W_TO_50W 0x18UL
11055
+
#define BUCKET_RANGE_OVER_50W 0x19UL
11056
+
#define BUCKET_LAST BUCKET_RANGE_OVER_50W
11057
+
11058
+
/* hwrm_monitor_pax_histogram_start_input (size:448b/56B) */
11059
+
struct hwrm_monitor_pax_histogram_start_input {
11060
+
__le16 req_type;
11061
+
__le16 cmpl_ring;
11062
+
__le16 seq_id;
11063
+
__le16 target_id;
11064
+
__le64 resp_addr;
11065
+
__le32 flags;
11066
+
#define MONITOR_PAX_HISTOGRAM_START_REQ_FLAGS_PROFILE 0x1UL
11067
+
#define MONITOR_PAX_HISTOGRAM_START_REQ_FLAGS_PROFILE_READ 0x1UL
11068
+
#define MONITOR_PAX_HISTOGRAM_START_REQ_FLAGS_PROFILE_WRITE 0x0UL
11069
+
#define MONITOR_PAX_HISTOGRAM_START_REQ_FLAGS_PROFILE_LAST MONITOR_PAX_HISTOGRAM_START_REQ_FLAGS_PROFILE_WRITE
11070
+
u8 unused_0[4];
11071
+
__le64 start_addr;
11072
+
__le64 end_addr;
11073
+
__le32 axuser_value;
11074
+
__le32 axuser_mask;
11075
+
u8 lsb_sel;
11076
+
u8 unused_1[7];
11077
+
};
11078
+
11079
+
/* hwrm_monitor_pax_histogram_start_output (size:192b/24B) */
11080
+
struct hwrm_monitor_pax_histogram_start_output {
11081
+
__le16 error_code;
11082
+
__le16 req_type;
11083
+
__le16 seq_id;
11084
+
__le16 resp_len;
11085
+
__le64 timestamp;
11086
+
u8 unused_0[7];
11087
+
u8 valid;
11088
+
};
11089
+
11090
+
#define PAX_HISTOGRAM_BUCKET0 0x0UL
11091
+
#define PAX_HISTOGRAM_BUCKET1 0x1UL
11092
+
#define PAX_HISTOGRAM_BUCKET2 0x2UL
11093
+
#define PAX_HISTOGRAM_BUCKET3 0x3UL
11094
+
#define PAX_HISTOGRAM_BUCKET4 0x4UL
11095
+
#define PAX_HISTOGRAM_BUCKET5 0x5UL
11096
+
#define PAX_HISTOGRAM_BUCKET6 0x6UL
11097
+
#define PAX_HISTOGRAM_BUCKET7 0x7UL
11098
+
#define PAX_HISTOGRAM_BUCKET8 0x8UL
11099
+
#define PAX_HISTOGRAM_BUCKET9 0x9UL
11100
+
#define PAX_HISTOGRAM_BUCKET10 0xaUL
11101
+
#define PAX_HISTOGRAM_BUCKET11 0xbUL
11102
+
#define PAX_HISTOGRAM_BUCKET12 0xcUL
11103
+
#define PAX_HISTOGRAM_BUCKET13 0xdUL
11104
+
#define PAX_HISTOGRAM_BUCKET14 0xeUL
11105
+
#define PAX_HISTOGRAM_BUCKET15 0xfUL
11106
+
#define PAX_HISTOGRAM_MIN_LATENCY 0x10UL
11107
+
#define PAX_HISTOGRAM_MAX_LATENCY 0x11UL
11108
+
#define PAX_HISTOGRAM_EVENT_COUNTER 0x12UL
11109
+
#define PAX_HISTOGRAM_ACCUMULATOR 0x13UL
11110
+
#define PAX_HISTOGRAM_LAST PAX_HISTOGRAM_ACCUMULATOR
11111
+
11112
+
/* hwrm_monitor_pax_histogram_collect_input (size:192b/24B) */
11113
+
struct hwrm_monitor_pax_histogram_collect_input {
11114
+
__le16 req_type;
11115
+
__le16 cmpl_ring;
11116
+
__le16 seq_id;
11117
+
__le16 target_id;
11118
+
__le64 resp_addr;
11119
+
__le32 flags;
11120
+
#define MONITOR_PAX_HISTOGRAM_COLLECT_REQ_FLAGS_PROFILE 0x1UL
11121
+
#define MONITOR_PAX_HISTOGRAM_COLLECT_REQ_FLAGS_PROFILE_READ 0x1UL
11122
+
#define MONITOR_PAX_HISTOGRAM_COLLECT_REQ_FLAGS_PROFILE_WRITE 0x0UL
11123
+
#define MONITOR_PAX_HISTOGRAM_COLLECT_REQ_FLAGS_PROFILE_LAST MONITOR_PAX_HISTOGRAM_COLLECT_REQ_FLAGS_PROFILE_WRITE
11124
+
u8 unused_0[4];
11125
+
};
11126
+
11127
+
/* hwrm_monitor_pax_histogram_collect_output (size:2752b/344B) */
11128
+
struct hwrm_monitor_pax_histogram_collect_output {
11129
+
__le16 error_code;
11130
+
__le16 req_type;
11131
+
__le16 seq_id;
11132
+
__le16 resp_len;
11133
+
__le64 timestamp;
11134
+
__le64 histogram_data_mst0[20];
11135
+
__le64 histogram_data_mst1[20];
11136
+
u8 unused_0[7];
11137
+
u8 valid;
11138
+
};
11139
+
11140
+
/* hwrm_wol_filter_alloc_input (size:512b/64B) */
11141
+
struct hwrm_wol_filter_alloc_input {
11142
+
__le16 req_type;
11143
+
__le16 cmpl_ring;
11144
+
__le16 seq_id;
11145
+
__le16 target_id;
11146
+
__le64 resp_addr;
11147
+
__le32 flags;
11148
+
__le32 enables;
11149
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
11150
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
11151
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
11152
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
11153
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
11154
+
#define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
11155
+
__le16 port_id;
11156
+
u8 wol_type;
11157
+
#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
11158
+
#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
11159
+
#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
11160
+
#define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
11161
+
u8 unused_0[5];
11162
+
u8 mac_address[6];
11163
+
__le16 pattern_offset;
11164
+
__le16 pattern_buf_size;
11165
+
__le16 pattern_mask_size;
11166
+
u8 unused_1[4];
11167
+
__le64 pattern_buf_addr;
11168
+
__le64 pattern_mask_addr;
11169
+
};
11170
+
11171
+
/* hwrm_wol_filter_alloc_output (size:128b/16B) */
11172
+
struct hwrm_wol_filter_alloc_output {
11173
+
__le16 error_code;
11174
+
__le16 req_type;
11175
+
__le16 seq_id;
11176
+
__le16 resp_len;
11177
+
u8 wol_filter_id;
11178
+
u8 unused_0[6];
11179
+
u8 valid;
11180
+
};
11181
+
11182
+
/* hwrm_wol_filter_free_input (size:256b/32B) */
11183
+
struct hwrm_wol_filter_free_input {
11184
+
__le16 req_type;
11185
+
__le16 cmpl_ring;
11186
+
__le16 seq_id;
11187
+
__le16 target_id;
11188
+
__le64 resp_addr;
11189
+
__le32 flags;
11190
+
#define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
11191
+
__le32 enables;
11192
+
#define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
11193
+
__le16 port_id;
11194
+
u8 wol_filter_id;
11195
+
u8 unused_0[5];
11196
+
};
11197
+
11198
+
/* hwrm_wol_filter_free_output (size:128b/16B) */
11199
+
struct hwrm_wol_filter_free_output {
11200
+
__le16 error_code;
11201
+
__le16 req_type;
11202
+
__le16 seq_id;
11203
+
__le16 resp_len;
11204
+
u8 unused_0[7];
11205
+
u8 valid;
11206
+
};
11207
+
11208
+
/* hwrm_wol_filter_qcfg_input (size:448b/56B) */
11209
+
struct hwrm_wol_filter_qcfg_input {
11210
+
__le16 req_type;
11211
+
__le16 cmpl_ring;
11212
+
__le16 seq_id;
11213
+
__le16 target_id;
11214
+
__le64 resp_addr;
11215
+
__le16 port_id;
11216
+
__le16 handle;
11217
+
u8 unused_0[4];
11218
+
__le64 pattern_buf_addr;
11219
+
__le16 pattern_buf_size;
11220
+
u8 unused_1[6];
11221
+
__le64 pattern_mask_addr;
11222
+
__le16 pattern_mask_size;
11223
+
u8 unused_2[6];
11224
+
};
11225
+
11226
+
/* hwrm_wol_filter_qcfg_output (size:256b/32B) */
11227
+
struct hwrm_wol_filter_qcfg_output {
11228
+
__le16 error_code;
11229
+
__le16 req_type;
11230
+
__le16 seq_id;
11231
+
__le16 resp_len;
11232
+
__le16 next_handle;
11233
+
u8 wol_filter_id;
11234
+
u8 wol_type;
11235
+
#define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
11236
+
#define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
11237
+
#define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
11238
+
#define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
11239
+
__le32 unused_0;
11240
+
u8 mac_address[6];
11241
+
__le16 pattern_offset;
11242
+
__le16 pattern_size;
11243
+
__le16 pattern_mask_size;
11244
+
u8 unused_1[3];
11245
+
u8 valid;
11246
+
};
11247
+
11248
+
/* hwrm_wol_reason_qcfg_input (size:320b/40B) */
11249
+
struct hwrm_wol_reason_qcfg_input {
11250
+
__le16 req_type;
11251
+
__le16 cmpl_ring;
11252
+
__le16 seq_id;
11253
+
__le16 target_id;
11254
+
__le64 resp_addr;
11255
+
__le16 port_id;
11256
+
u8 unused_0[6];
11257
+
__le64 wol_pkt_buf_addr;
11258
+
__le16 wol_pkt_buf_size;
11259
+
u8 unused_1[6];
11260
+
};
11261
+
11262
+
/* hwrm_wol_reason_qcfg_output (size:128b/16B) */
11263
+
struct hwrm_wol_reason_qcfg_output {
11264
+
__le16 error_code;
11265
+
__le16 req_type;
11266
+
__le16 seq_id;
11267
+
__le16 resp_len;
11268
+
u8 wol_filter_id;
11269
+
u8 wol_reason;
11270
+
#define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
11271
+
#define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
11272
+
#define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
11273
+
#define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
11274
+
u8 wol_pkt_len;
11275
+
u8 unused_0[4];
11276
+
u8 valid;
11277
+
};
11278
+
11279
+
/* hwrm_dbg_qcaps_input (size:192b/24B) */
11280
+
struct hwrm_dbg_qcaps_input {
11281
+
__le16 req_type;
11282
+
__le16 cmpl_ring;
11283
+
__le16 seq_id;
11284
+
__le16 target_id;
11285
+
__le64 resp_addr;
11286
+
__le16 fid;
11287
+
u8 unused_0[6];
11288
+
};
11289
+
11290
+
/* hwrm_dbg_qcaps_output (size:192b/24B) */
11291
+
struct hwrm_dbg_qcaps_output {
11292
+
__le16 error_code;
11293
+
__le16 req_type;
11294
+
__le16 seq_id;
11295
+
__le16 resp_len;
11296
+
__le16 fid;
11297
+
u8 unused_0[2];
11298
+
__le32 coredump_component_disable_caps;
11299
+
#define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL
11300
+
__le32 flags;
11301
+
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
11302
+
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
11303
+
#define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
11304
+
#define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL
11305
+
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL
11306
+
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL
11307
+
#define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL
11308
+
#define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL
11309
+
u8 unused_1[3];
11310
+
u8 valid;
11311
+
};
11312
+
11313
+
/* hwrm_dbg_qcfg_input (size:192b/24B) */
11314
+
struct hwrm_dbg_qcfg_input {
11315
+
__le16 req_type;
11316
+
__le16 cmpl_ring;
11317
+
__le16 seq_id;
11318
+
__le16 target_id;
11319
+
__le64 resp_addr;
11320
+
__le16 fid;
11321
+
__le16 flags;
11322
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL
11323
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
11324
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL
11325
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL
11326
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL
11327
+
#define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
11328
+
__le32 coredump_component_disable_flags;
11329
+
#define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL
11330
+
};
11331
+
11332
+
/* hwrm_dbg_qcfg_output (size:256b/32B) */
11333
+
struct hwrm_dbg_qcfg_output {
11334
+
__le16 error_code;
11335
+
__le16 req_type;
11336
+
__le16 seq_id;
11337
+
__le16 resp_len;
11338
+
__le16 fid;
11339
+
u8 unused_0[2];
11340
+
__le32 coredump_size;
11341
+
__le32 flags;
11342
+
#define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL
11343
+
#define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL
11344
+
#define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL
11345
+
#define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL
11346
+
#define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL
11347
+
#define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL
11348
+
__le16 async_cmpl_ring;
11349
+
u8 unused_2[2];
11350
+
__le32 crashdump_size;
11351
+
u8 unused_3[3];
11352
+
u8 valid;
11353
+
};
11354
+
11355
+
/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */
11356
+
struct hwrm_dbg_crashdump_medium_cfg_input {
11357
+
__le16 req_type;
11358
+
__le16 cmpl_ring;
11359
+
__le16 seq_id;
11360
+
__le16 target_id;
11361
+
__le64 resp_addr;
11362
+
__le16 output_dest_flags;
11363
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL
11364
+
__le16 pg_size_lvl;
11365
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL
11366
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0
11367
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL
11368
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL
11369
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL
11370
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2
11371
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL
11372
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2
11373
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2)
11374
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2)
11375
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2)
11376
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2)
11377
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2)
11378
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2)
11379
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G
11380
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL
11381
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5
11382
+
__le32 size;
11383
+
__le32 coredump_component_disable_flags;
11384
+
#define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL
11385
+
__le32 unused_0;
11386
+
__le64 pbl;
11387
+
};
11388
+
11389
+
/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */
11390
+
struct hwrm_dbg_crashdump_medium_cfg_output {
11391
+
__le16 error_code;
11392
+
__le16 req_type;
11393
+
__le16 seq_id;
11394
+
__le16 resp_len;
11395
+
u8 unused_1[7];
11396
+
u8 valid;
11397
+
};
11398
+
11399
+
/* coredump_segment_record (size:128b/16B) */
11400
+
struct coredump_segment_record {
11401
+
__le16 component_id;
11402
+
__le16 segment_id;
11403
+
__le16 max_instances;
11404
+
u8 version_hi;
11405
+
u8 version_low;
11406
+
u8 seg_flags;
11407
+
u8 compress_flags;
11408
+
#define SFLAG_COMPRESSED_ZLIB 0x1UL
11409
+
u8 unused_0[2];
11410
+
__le32 segment_len;
11411
+
};
11412
+
11413
+
/* hwrm_dbg_coredump_list_input (size:256b/32B) */
11414
+
struct hwrm_dbg_coredump_list_input {
11415
+
__le16 req_type;
11416
+
__le16 cmpl_ring;
11417
+
__le16 seq_id;
11418
+
__le16 target_id;
11419
+
__le64 resp_addr;
11420
+
__le64 host_dest_addr;
11421
+
__le32 host_buf_len;
11422
+
__le16 seq_no;
11423
+
u8 flags;
11424
+
#define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
11425
+
u8 unused_0;
11426
+
};
11427
+
11428
+
/* hwrm_dbg_coredump_list_output (size:128b/16B) */
11429
+
struct hwrm_dbg_coredump_list_output {
11430
+
__le16 error_code;
11431
+
__le16 req_type;
11432
+
__le16 seq_id;
11433
+
__le16 resp_len;
11434
+
u8 flags;
11435
+
#define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
11436
+
u8 unused_0;
11437
+
__le16 total_segments;
11438
+
__le16 data_len;
11439
+
u8 unused_1;
11440
+
u8 valid;
11441
+
};
11442
+
11443
+
/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
11444
+
struct hwrm_dbg_coredump_initiate_input {
11445
+
__le16 req_type;
11446
+
__le16 cmpl_ring;
11447
+
__le16 seq_id;
11448
+
__le16 target_id;
11449
+
__le64 resp_addr;
11450
+
__le16 component_id;
11451
+
__le16 segment_id;
11452
+
__le16 instance;
11453
+
__le16 unused_0;
11454
+
u8 seg_flags;
11455
+
#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA 0x1UL
11456
+
#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA 0x2UL
11457
+
#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE 0x4UL
11458
+
u8 unused_1[7];
11459
+
};
11460
+
11461
+
/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
11462
+
struct hwrm_dbg_coredump_initiate_output {
11463
+
__le16 error_code;
11464
+
__le16 req_type;
11465
+
__le16 seq_id;
11466
+
__le16 resp_len;
11467
+
u8 unused_0[7];
11468
+
u8 valid;
11469
+
};
11470
+
11471
+
/* coredump_data_hdr (size:128b/16B) */
11472
+
struct coredump_data_hdr {
11473
+
__le32 address;
11474
+
__le32 flags_length;
11475
+
#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL
11476
+
#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0
11477
+
#define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL
11478
+
__le32 instance;
11479
+
__le32 next_offset;
11480
+
};
11481
+
11482
+
/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
11483
+
struct hwrm_dbg_coredump_retrieve_input {
11484
+
__le16 req_type;
11485
+
__le16 cmpl_ring;
11486
+
__le16 seq_id;
11487
+
__le16 target_id;
11488
+
__le64 resp_addr;
11489
+
__le64 host_dest_addr;
11490
+
__le32 host_buf_len;
11491
+
__le32 unused_0;
11492
+
__le16 component_id;
11493
+
__le16 segment_id;
11494
+
__le16 instance;
11495
+
__le16 unused_1;
11496
+
u8 seg_flags;
11497
+
u8 unused_2;
11498
+
__le16 unused_3;
11499
+
__le32 unused_4;
11500
+
__le32 seq_no;
11501
+
__le32 unused_5;
11502
+
};
11503
+
11504
+
/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
11505
+
struct hwrm_dbg_coredump_retrieve_output {
11506
+
__le16 error_code;
11507
+
__le16 req_type;
11508
+
__le16 seq_id;
11509
+
__le16 resp_len;
11510
+
u8 flags;
11511
+
#define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
11512
+
u8 unused_0;
11513
+
__le16 data_len;
11514
+
u8 unused_1[3];
11515
+
u8 valid;
11516
+
};
11517
+
11518
+
#define HWRM_NVM_COMMON_CMD_ERR_UNKNOWN 0x0UL
11519
+
#define HWRM_NVM_COMMON_CMD_ERR_ACCESS_DENIED 0x65UL
11520
+
#define HWRM_NVM_COMMON_CMD_ERR_FW_BUSY 0x66UL
11521
+
#define HWRM_NVM_COMMON_CMD_ERR_FW_ABORT 0x67UL
11522
+
#define HWRM_NVM_COMMON_CMD_ERR_FW_UPGRD_IN_PROG 0x68UL
11523
+
#define HWRM_NVM_COMMON_CMD_ERR_NO_WORKSPACE_MEM 0x69UL
11524
+
#define HWRM_NVM_COMMON_CMD_ERR_RESOURCE_LOCKED 0x6aUL
11525
+
#define HWRM_NVM_COMMON_CMD_ERR_FILE_OPEN_FAILED 0x6bUL
11526
+
#define HWRM_NVM_COMMON_CMD_ERR_DMA_FAILED 0x6cUL
11527
+
#define HWRM_NVM_COMMON_CMD_ERR_LAST HWRM_NVM_COMMON_CMD_ERR_DMA_FAILED
11528
+
11529
+
/* hwrm_nvm_raw_write_blk_input (size:320b/40B) */
11530
+
struct hwrm_nvm_raw_write_blk_input {
11531
+
__le16 req_type;
11532
+
__le16 cmpl_ring;
11533
+
__le16 seq_id;
11534
+
__le16 target_id;
11535
+
__le64 resp_addr;
11536
+
__le64 host_src_addr;
11537
+
__le32 dest_addr;
11538
+
__le32 len;
11539
+
u8 flags;
11540
+
#define NVM_RAW_WRITE_BLK_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL
11541
+
u8 unused_0[7];
11542
+
};
11543
+
11544
+
/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
11545
+
struct hwrm_nvm_raw_write_blk_output {
11546
+
__le16 error_code;
11547
+
__le16 req_type;
11548
+
__le16 seq_id;
11549
+
__le16 resp_len;
11550
+
u8 unused_0[7];
11551
+
u8 valid;
11552
+
};
11553
+
11554
+
/* hwrm_nvm_raw_write_blk_cmd_err (size:64b/8B) */
11555
+
struct hwrm_nvm_raw_write_blk_cmd_err {
11556
+
u8 code;
11557
+
#define NVM_RAW_WRITE_BLK_CMD_ERR_CODE_UNKNOWN 0x0UL
11558
+
#define NVM_RAW_WRITE_BLK_CMD_ERR_CODE_INVALID_LEN 0x1UL
11559
+
#define NVM_RAW_WRITE_BLK_CMD_ERR_CODE_INVALID_ADDR 0x2UL
11560
+
#define NVM_RAW_WRITE_BLK_CMD_ERR_CODE_WRITE_FAILED 0x3UL
11561
+
#define NVM_RAW_WRITE_BLK_CMD_ERR_CODE_LAST NVM_RAW_WRITE_BLK_CMD_ERR_CODE_WRITE_FAILED
11562
+
u8 unused_0[7];
11563
+
};
11564
+
11565
+
/* hwrm_nvm_read_input (size:320b/40B) */
11566
+
struct hwrm_nvm_read_input {
11567
+
__le16 req_type;
11568
+
__le16 cmpl_ring;
11569
+
__le16 seq_id;
11570
+
__le16 target_id;
11571
+
__le64 resp_addr;
11572
+
__le64 host_dest_addr;
11573
+
__le16 dir_idx;
11574
+
u8 unused_0[2];
11575
+
__le32 offset;
11576
+
__le32 len;
11577
+
u8 unused_1[4];
11578
+
};
11579
+
11580
+
/* hwrm_nvm_read_output (size:128b/16B) */
11581
+
struct hwrm_nvm_read_output {
11582
+
__le16 error_code;
11583
+
__le16 req_type;
11584
+
__le16 seq_id;
11585
+
__le16 resp_len;
11586
+
u8 unused_0[7];
11587
+
u8 valid;
11588
+
};
11589
+
11590
+
/* hwrm_nvm_read_cmd_err (size:64b/8B) */
11591
+
struct hwrm_nvm_read_cmd_err {
11592
+
u8 code;
11593
+
#define NVM_READ_CMD_ERR_CODE_UNKNOWN 0x0UL
11594
+
#define NVM_READ_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x1UL
11595
+
#define NVM_READ_CMD_ERR_CODE_INVALID_LEN 0x2UL
11596
+
#define NVM_READ_CMD_ERR_CODE_READ_FAILED 0x3UL
11597
+
#define NVM_READ_CMD_ERR_CODE_FRU_CRC_CHECK_FAILED 0x4UL
11598
+
#define NVM_READ_CMD_ERR_CODE_LAST NVM_READ_CMD_ERR_CODE_FRU_CRC_CHECK_FAILED
11599
+
u8 unused_0[7];
11600
+
};
11601
+
11602
+
/* hwrm_nvm_raw_dump_input (size:320b/40B) */
11603
+
struct hwrm_nvm_raw_dump_input {
11604
+
__le16 req_type;
11605
+
__le16 cmpl_ring;
11606
+
__le16 seq_id;
11607
+
__le16 target_id;
11608
+
__le64 resp_addr;
11609
+
__le64 host_dest_addr;
11610
+
__le32 offset;
11611
+
__le32 len;
11612
+
u8 flags;
11613
+
#define NVM_RAW_DUMP_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL
11614
+
u8 unused_0[7];
11615
+
};
11616
+
11617
+
/* hwrm_nvm_raw_dump_output (size:128b/16B) */
11618
+
struct hwrm_nvm_raw_dump_output {
11619
+
__le16 error_code;
11620
+
__le16 req_type;
11621
+
__le16 seq_id;
11622
+
__le16 resp_len;
11623
+
u8 unused_0[7];
11624
+
u8 valid;
11625
+
};
11626
+
11627
+
/* hwrm_nvm_raw_dump_cmd_err (size:64b/8B) */
11628
+
struct hwrm_nvm_raw_dump_cmd_err {
11629
+
u8 code;
11630
+
#define NVM_RAW_DUMP_CMD_ERR_CODE_UNKNOWN 0x0UL
11631
+
#define NVM_RAW_DUMP_CMD_ERR_CODE_INVALID_LEN 0x1UL
11632
+
#define NVM_RAW_DUMP_CMD_ERR_CODE_INVALID_OFFSET 0x2UL
11633
+
#define NVM_RAW_DUMP_CMD_ERR_CODE_VALIDATE_FAILED 0x3UL
11634
+
#define NVM_RAW_DUMP_CMD_ERR_CODE_LAST NVM_RAW_DUMP_CMD_ERR_CODE_VALIDATE_FAILED
11635
+
u8 unused_0[7];
11636
+
};
11637
+
11638
+
/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
11639
+
struct hwrm_nvm_get_dir_entries_input {
11640
+
__le16 req_type;
11641
+
__le16 cmpl_ring;
11642
+
__le16 seq_id;
11643
+
__le16 target_id;
11644
+
__le64 resp_addr;
11645
+
__le64 host_dest_addr;
11646
+
};
11647
+
11648
+
/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
11649
+
struct hwrm_nvm_get_dir_entries_output {
11650
+
__le16 error_code;
11651
+
__le16 req_type;
11652
+
__le16 seq_id;
11653
+
__le16 resp_len;
11654
+
u8 unused_0[7];
11655
+
u8 valid;
11656
+
};
11657
+
11658
+
/* hwrm_nvm_get_dir_entries_cmd_err (size:64b/8B) */
11659
+
struct hwrm_nvm_get_dir_entries_cmd_err {
11660
+
u8 code;
11661
+
#define NVM_GET_DIR_ENTRIES_CMD_ERR_CODE_UNKNOWN 0x0UL
11662
+
#define NVM_GET_DIR_ENTRIES_CMD_ERR_CODE_GET_DIR_LIST_FAILED 0x1UL
11663
+
#define NVM_GET_DIR_ENTRIES_CMD_ERR_CODE_LAST NVM_GET_DIR_ENTRIES_CMD_ERR_CODE_GET_DIR_LIST_FAILED
11664
+
u8 unused_0[7];
11665
+
};
11666
+
11667
+
/* hwrm_nvm_get_dir_info_input (size:128b/16B) */
11668
+
struct hwrm_nvm_get_dir_info_input {
11669
+
__le16 req_type;
11670
+
__le16 cmpl_ring;
11671
+
__le16 seq_id;
11672
+
__le16 target_id;
11673
+
__le64 resp_addr;
11674
+
};
11675
+
11676
+
/* hwrm_nvm_get_dir_info_output (size:192b/24B) */
11677
+
struct hwrm_nvm_get_dir_info_output {
11678
+
__le16 error_code;
11679
+
__le16 req_type;
11680
+
__le16 seq_id;
11681
+
__le16 resp_len;
11682
+
__le32 entries;
11683
+
__le32 entry_length;
11684
+
u8 unused_0[7];
11685
+
u8 valid;
11686
+
};
11687
+
11688
+
/* hwrm_nvm_write_input (size:448b/56B) */
11689
+
struct hwrm_nvm_write_input {
11690
+
__le16 req_type;
11691
+
__le16 cmpl_ring;
11692
+
__le16 seq_id;
11693
+
__le16 target_id;
11694
+
__le64 resp_addr;
11695
+
__le64 host_src_addr;
11696
+
__le16 dir_type;
11697
+
__le16 dir_ordinal;
11698
+
__le16 dir_ext;
11699
+
__le16 dir_attr;
11700
+
__le32 dir_data_length;
11701
+
__le16 option;
11702
+
__le16 flags;
11703
+
#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
11704
+
#define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL
11705
+
#define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL
11706
+
#define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL
11707
+
__le32 dir_item_length;
11708
+
__le32 offset;
11709
+
__le32 len;
11710
+
__le32 unused_0;
11711
+
};
11712
+
11713
+
/* hwrm_nvm_write_output (size:128b/16B) */
11714
+
struct hwrm_nvm_write_output {
11715
+
__le16 error_code;
11716
+
__le16 req_type;
11717
+
__le16 seq_id;
11718
+
__le16 resp_len;
11719
+
__le32 dir_item_length;
11720
+
__le16 dir_idx;
11721
+
u8 unused_0;
11722
+
u8 valid;
11723
+
};
11724
+
11725
+
/* hwrm_nvm_write_cmd_err (size:64b/8B) */
11726
+
struct hwrm_nvm_write_cmd_err {
11727
+
u8 code;
11728
+
#define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
11729
+
#define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
11730
+
#define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
11731
+
#define NVM_WRITE_CMD_ERR_CODE_WRITE_FAILED 0x3UL
11732
+
#define NVM_WRITE_CMD_ERR_CODE_REQD_ERASE_FAILED 0x4UL
11733
+
#define NVM_WRITE_CMD_ERR_CODE_VERIFY_FAILED 0x5UL
11734
+
#define NVM_WRITE_CMD_ERR_CODE_INVALID_HEADER 0x6UL
11735
+
#define NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 0x7UL
11736
+
#define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED
11737
+
u8 unused_0[7];
11738
+
};
11739
+
11740
+
/* hwrm_nvm_modify_input (size:320b/40B) */
11741
+
struct hwrm_nvm_modify_input {
11742
+
__le16 req_type;
11743
+
__le16 cmpl_ring;
11744
+
__le16 seq_id;
11745
+
__le16 target_id;
11746
+
__le64 resp_addr;
11747
+
__le64 host_src_addr;
11748
+
__le16 dir_idx;
11749
+
__le16 flags;
11750
+
#define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL
11751
+
#define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL
11752
+
__le32 offset;
11753
+
__le32 len;
11754
+
u8 unused_1[4];
11755
+
};
11756
+
11757
+
/* hwrm_nvm_modify_output (size:128b/16B) */
11758
+
struct hwrm_nvm_modify_output {
11759
+
__le16 error_code;
11760
+
__le16 req_type;
11761
+
__le16 seq_id;
11762
+
__le16 resp_len;
11763
+
u8 unused_0[7];
11764
+
u8 valid;
11765
+
};
11766
+
11767
+
/* hwrm_nvm_modify_cmd_err (size:64b/8B) */
11768
+
struct hwrm_nvm_modify_cmd_err {
11769
+
u8 code;
11770
+
#define NVM_MODIFY_CMD_ERR_CODE_UNKNOWN 0x0UL
11771
+
#define NVM_MODIFY_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x1UL
11772
+
#define NVM_MODIFY_CMD_ERR_CODE_INVALID_OFFSET 0x2UL
11773
+
#define NVM_MODIFY_CMD_ERR_CODE_ITEM_TOO_BIG_ERR 0x3UL
11774
+
#define NVM_MODIFY_CMD_ERR_CODE_BLK_BOUNDARY_ERR 0x4UL
11775
+
#define NVM_MODIFY_CMD_ERR_CODE_SECURITY_VIOLATION 0x5UL
11776
+
#define NVM_MODIFY_CMD_ERR_CODE_WRITE_FAILED 0x6UL
11777
+
#define NVM_MODIFY_CMD_ERR_CODE_ERASE_SECTORS_FAILED 0x7UL
11778
+
#define NVM_MODIFY_CMD_ERR_CODE_COMPUTE_CRC_FAILED 0x8UL
11779
+
#define NVM_MODIFY_CMD_ERR_CODE_LAST NVM_MODIFY_CMD_ERR_CODE_COMPUTE_CRC_FAILED
11780
+
u8 unused_0[7];
11781
+
};
11782
+
11783
+
/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
11784
+
struct hwrm_nvm_find_dir_entry_input {
11785
+
__le16 req_type;
11786
+
__le16 cmpl_ring;
11787
+
__le16 seq_id;
11788
+
__le16 target_id;
11789
+
__le64 resp_addr;
11790
+
__le32 enables;
11791
+
#define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
11792
+
__le16 dir_idx;
11793
+
__le16 dir_type;
11794
+
__le16 dir_ordinal;
11795
+
__le16 dir_ext;
11796
+
u8 opt_ordinal;
11797
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
11798
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
11799
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
11800
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
11801
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
11802
+
#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
11803
+
u8 unused_0[3];
11804
+
};
11805
+
11806
+
/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
11807
+
struct hwrm_nvm_find_dir_entry_output {
11808
+
__le16 error_code;
11809
+
__le16 req_type;
11810
+
__le16 seq_id;
11811
+
__le16 resp_len;
11812
+
__le32 dir_item_length;
11813
+
__le32 dir_data_length;
11814
+
__le32 fw_ver;
11815
+
__le16 dir_ordinal;
11816
+
__le16 dir_idx;
11817
+
u8 unused_0[7];
11818
+
u8 valid;
11819
+
};
11820
+
11821
+
/* hwrm_nvm_find_dir_entry_cmd_err (size:64b/8B) */
11822
+
struct hwrm_nvm_find_dir_entry_cmd_err {
11823
+
u8 code;
11824
+
#define NVM_FIND_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN 0x0UL
11825
+
#define NVM_FIND_DIR_ENTRY_CMD_ERR_CODE_MGMT_FW_DISABLED 0x1UL
11826
+
#define NVM_FIND_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x2UL
11827
+
#define NVM_FIND_DIR_ENTRY_CMD_ERR_CODE_LAST NVM_FIND_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN_DIR_ERR
11828
+
u8 unused_0[7];
11829
+
};
11830
+
11831
+
/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
11832
+
struct hwrm_nvm_erase_dir_entry_input {
11833
+
__le16 req_type;
11834
+
__le16 cmpl_ring;
11835
+
__le16 seq_id;
11836
+
__le16 target_id;
11837
+
__le64 resp_addr;
11838
+
__le16 dir_idx;
11839
+
u8 unused_0[6];
11840
+
};
11841
+
11842
+
/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
11843
+
struct hwrm_nvm_erase_dir_entry_output {
11844
+
__le16 error_code;
11845
+
__le16 req_type;
11846
+
__le16 seq_id;
11847
+
__le16 resp_len;
11848
+
u8 unused_0[7];
11849
+
u8 valid;
11850
+
};
11851
+
11852
+
/* hwrm_nvm_erase_dir_entry_cmd_err (size:64b/8B) */
11853
+
struct hwrm_nvm_erase_dir_entry_cmd_err {
11854
+
u8 code;
11855
+
#define NVM_ERASE_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN 0x0UL
11856
+
#define NVM_ERASE_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x1UL
11857
+
#define NVM_ERASE_DIR_ENTRY_CMD_ERR_CODE_SECURITY_VIOLATION 0x5UL
11858
+
#define NVM_ERASE_DIR_ENTRY_CMD_ERR_CODE_LAST NVM_ERASE_DIR_ENTRY_CMD_ERR_CODE_SECURITY_VIOLATION
11859
+
u8 unused_0[7];
11860
+
};
11861
+
11862
+
/* hwrm_nvm_get_dev_info_input (size:192b/24B) */
11863
+
struct hwrm_nvm_get_dev_info_input {
11864
+
__le16 req_type;
11865
+
__le16 cmpl_ring;
11866
+
__le16 seq_id;
11867
+
__le16 target_id;
11868
+
__le64 resp_addr;
11869
+
u8 flags;
11870
+
#define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL
11871
+
u8 unused_0[7];
11872
+
};
11873
+
11874
+
/* hwrm_nvm_get_dev_info_output (size:832b/104B) */
11875
+
struct hwrm_nvm_get_dev_info_output {
11876
+
__le16 error_code;
11877
+
__le16 req_type;
11878
+
__le16 seq_id;
11879
+
__le16 resp_len;
11880
+
__le16 manufacturer_id;
11881
+
__le16 device_id;
11882
+
__le32 sector_size;
11883
+
__le32 nvram_size;
11884
+
__le32 reserved_size;
11885
+
__le32 available_size;
11886
+
u8 nvm_cfg_ver_maj;
11887
+
u8 nvm_cfg_ver_min;
11888
+
u8 nvm_cfg_ver_upd;
11889
+
u8 flags;
11890
+
#define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL
11891
+
char pkg_name[16];
11892
+
__le16 hwrm_fw_major;
11893
+
__le16 hwrm_fw_minor;
11894
+
__le16 hwrm_fw_build;
11895
+
__le16 hwrm_fw_patch;
11896
+
__le16 mgmt_fw_major;
11897
+
__le16 mgmt_fw_minor;
11898
+
__le16 mgmt_fw_build;
11899
+
__le16 mgmt_fw_patch;
11900
+
__le16 roce_fw_major;
11901
+
__le16 roce_fw_minor;
11902
+
__le16 roce_fw_build;
11903
+
__le16 roce_fw_patch;
11904
+
__le16 netctrl_fw_major;
11905
+
__le16 netctrl_fw_minor;
11906
+
__le16 netctrl_fw_build;
11907
+
__le16 netctrl_fw_patch;
11908
+
__le16 srt2_fw_major;
11909
+
__le16 srt2_fw_minor;
11910
+
__le16 srt2_fw_build;
11911
+
__le16 srt2_fw_patch;
11912
+
__le16 art_fw_major;
11913
+
__le16 art_fw_minor;
11914
+
__le16 art_fw_build;
11915
+
__le16 art_fw_patch;
11916
+
u8 security_soc_fw_major;
11917
+
u8 security_soc_fw_minor;
11918
+
u8 security_soc_fw_build;
11919
+
u8 security_soc_fw_patch;
11920
+
u8 unused_0[3];
11921
+
u8 valid;
11922
+
};
11923
+
11924
+
/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
11925
+
struct hwrm_nvm_mod_dir_entry_input {
11926
+
__le16 req_type;
11927
+
__le16 cmpl_ring;
11928
+
__le16 seq_id;
11929
+
__le16 target_id;
11930
+
__le64 resp_addr;
11931
+
__le32 enables;
11932
+
#define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
11933
+
__le16 dir_idx;
11934
+
__le16 dir_ordinal;
11935
+
__le16 dir_ext;
11936
+
__le16 dir_attr;
11937
+
__le32 checksum;
11938
+
};
11939
+
11940
+
/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
11941
+
struct hwrm_nvm_mod_dir_entry_output {
11942
+
__le16 error_code;
11943
+
__le16 req_type;
11944
+
__le16 seq_id;
11945
+
__le16 resp_len;
11946
+
u8 unused_0[7];
11947
+
u8 valid;
11948
+
};
11949
+
11950
+
/* hwrm_nvm_mod_dir_entry_cmd_err (size:64b/8B) */
11951
+
struct hwrm_nvm_mod_dir_entry_cmd_err {
11952
+
u8 code;
11953
+
#define NVM_MOD_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN 0x0UL
11954
+
#define NVM_MOD_DIR_ENTRY_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x1UL
11955
+
#define NVM_MOD_DIR_ENTRY_CMD_ERR_CODE_SECURITY_VIOLATION 0x5UL
11956
+
#define NVM_MOD_DIR_ENTRY_CMD_ERR_CODE_LAST NVM_MOD_DIR_ENTRY_CMD_ERR_CODE_SECURITY_VIOLATION
11957
+
u8 unused_0[7];
11958
+
};
11959
+
11960
+
/* hwrm_nvm_verify_update_input (size:192b/24B) */
11961
+
struct hwrm_nvm_verify_update_input {
11962
+
__le16 req_type;
11963
+
__le16 cmpl_ring;
11964
+
__le16 seq_id;
11965
+
__le16 target_id;
11966
+
__le64 resp_addr;
11967
+
__le16 dir_type;
11968
+
__le16 dir_ordinal;
11969
+
__le16 dir_ext;
11970
+
u8 unused_0[2];
11971
+
};
11972
+
11973
+
/* hwrm_nvm_verify_update_output (size:128b/16B) */
11974
+
struct hwrm_nvm_verify_update_output {
11975
+
__le16 error_code;
11976
+
__le16 req_type;
11977
+
__le16 seq_id;
11978
+
__le16 resp_len;
11979
+
u8 unused_0[7];
11980
+
u8 valid;
11981
+
};
11982
+
11983
+
/* hwrm_nvm_install_update_input (size:192b/24B) */
11984
+
struct hwrm_nvm_install_update_input {
11985
+
__le16 req_type;
11986
+
__le16 cmpl_ring;
11987
+
__le16 seq_id;
11988
+
__le16 target_id;
11989
+
__le64 resp_addr;
11990
+
__le32 install_type;
11991
+
#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
11992
+
#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
11993
+
#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
11994
+
__le16 flags;
11995
+
#define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
11996
+
#define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
11997
+
#define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
11998
+
#define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL
11999
+
u8 unused_0[2];
12000
+
};
12001
+
12002
+
/* hwrm_nvm_install_update_output (size:192b/24B) */
12003
+
struct hwrm_nvm_install_update_output {
12004
+
__le16 error_code;
12005
+
__le16 req_type;
12006
+
__le16 seq_id;
12007
+
__le16 resp_len;
12008
+
__le64 installed_items;
12009
+
u8 result;
12010
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
12011
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL
12012
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL
12013
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL
12014
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL
12015
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL
12016
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL
12017
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL
12018
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL
12019
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL
12020
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL
12021
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL
12022
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL
12023
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL
12024
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL
12025
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL
12026
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL
12027
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL
12028
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL
12029
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL
12030
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL
12031
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL
12032
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL
12033
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL
12034
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL
12035
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL
12036
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL
12037
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL
12038
+
#define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED
12039
+
u8 problem_item;
12040
+
#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
12041
+
#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
12042
+
#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
12043
+
u8 reset_required;
12044
+
#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
12045
+
#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
12046
+
#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
12047
+
#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
12048
+
u8 unused_0[4];
12049
+
u8 valid;
12050
+
};
12051
+
12052
+
/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
12053
+
struct hwrm_nvm_install_update_cmd_err {
12054
+
u8 code;
12055
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
12056
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
12057
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
12058
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL
12059
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL
12060
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_DEFRAG_FAILED 0x5UL
12061
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x6UL
12062
+
#define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR
12063
+
u8 unused_0[7];
12064
+
};
12065
+
12066
+
/* hwrm_nvm_flush_input (size:128b/16B) */
12067
+
struct hwrm_nvm_flush_input {
12068
+
__le16 req_type;
12069
+
__le16 cmpl_ring;
12070
+
__le16 seq_id;
12071
+
__le16 target_id;
12072
+
__le64 resp_addr;
12073
+
};
12074
+
12075
+
/* hwrm_nvm_flush_output (size:128b/16B) */
12076
+
struct hwrm_nvm_flush_output {
12077
+
__le16 error_code;
12078
+
__le16 req_type;
12079
+
__le16 seq_id;
12080
+
__le16 resp_len;
12081
+
u8 unused_0[7];
12082
+
u8 valid;
12083
+
};
12084
+
12085
+
/* hwrm_nvm_flush_cmd_err (size:64b/8B) */
12086
+
struct hwrm_nvm_flush_cmd_err {
12087
+
u8 code;
12088
+
#define NVM_FLUSH_CMD_ERR_CODE_UNKNOWN 0x0UL
12089
+
#define NVM_FLUSH_CMD_ERR_CODE_FAIL 0x1UL
12090
+
#define NVM_FLUSH_CMD_ERR_CODE_LAST NVM_FLUSH_CMD_ERR_CODE_FAIL
12091
+
u8 unused_0[7];
12092
+
};
12093
+
12094
+
/* hwrm_nvm_get_variable_input (size:320b/40B) */
12095
+
struct hwrm_nvm_get_variable_input {
12096
+
__le16 req_type;
12097
+
__le16 cmpl_ring;
12098
+
__le16 seq_id;
12099
+
__le16 target_id;
12100
+
__le64 resp_addr;
12101
+
__le64 dest_data_addr;
12102
+
__le16 data_len;
12103
+
__le16 option_num;
12104
+
#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
12105
+
#define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
12106
+
#define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
12107
+
__le16 dimensions;
12108
+
__le16 index_0;
12109
+
__le16 index_1;
12110
+
__le16 index_2;
12111
+
__le16 index_3;
12112
+
u8 flags;
12113
+
#define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
12114
+
#define NVM_GET_VARIABLE_REQ_FLAGS_VALIDATE_OPT_VALUE 0x2UL
12115
+
u8 unused_0;
12116
+
};
12117
+
12118
+
/* hwrm_nvm_get_variable_output (size:128b/16B) */
12119
+
struct hwrm_nvm_get_variable_output {
12120
+
__le16 error_code;
12121
+
__le16 req_type;
12122
+
__le16 seq_id;
12123
+
__le16 resp_len;
12124
+
__le16 data_len;
12125
+
__le16 option_num;
12126
+
#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
12127
+
#define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
12128
+
#define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
12129
+
u8 flags;
12130
+
#define NVM_GET_VARIABLE_RESP_FLAGS_VALIDATE_OPT_VALUE 0x1UL
12131
+
u8 unused_0[2];
12132
+
u8 valid;
12133
+
};
12134
+
12135
+
/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
12136
+
struct hwrm_nvm_get_variable_cmd_err {
12137
+
u8 code;
12138
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
12139
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
12140
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
12141
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
12142
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x4UL
12143
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x5UL
12144
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x6UL
12145
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x7UL
12146
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x8UL
12147
+
#define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM
12148
+
u8 unused_0[7];
12149
+
};
12150
+
12151
+
/* hwrm_nvm_set_variable_input (size:320b/40B) */
12152
+
struct hwrm_nvm_set_variable_input {
12153
+
__le16 req_type;
12154
+
__le16 cmpl_ring;
12155
+
__le16 seq_id;
12156
+
__le16 target_id;
12157
+
__le64 resp_addr;
12158
+
__le64 src_data_addr;
12159
+
__le16 data_len;
12160
+
__le16 option_num;
12161
+
#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
12162
+
#define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
12163
+
#define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
12164
+
__le16 dimensions;
12165
+
__le16 index_0;
12166
+
__le16 index_1;
12167
+
__le16 index_2;
12168
+
__le16 index_3;
12169
+
u8 flags;
12170
+
#define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
12171
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
12172
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
12173
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
12174
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
12175
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
12176
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
12177
+
#define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
12178
+
#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
12179
+
#define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
12180
+
#define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
12181
+
u8 unused_0;
12182
+
};
12183
+
12184
+
/* hwrm_nvm_set_variable_output (size:128b/16B) */
12185
+
struct hwrm_nvm_set_variable_output {
12186
+
__le16 error_code;
12187
+
__le16 req_type;
12188
+
__le16 seq_id;
12189
+
__le16 resp_len;
12190
+
u8 unused_0[7];
12191
+
u8 valid;
12192
+
};
12193
+
12194
+
/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
12195
+
struct hwrm_nvm_set_variable_cmd_err {
12196
+
u8 code;
12197
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
12198
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
12199
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
12200
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
12201
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_ACTION_NOT_SUPPORTED 0x4UL
12202
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x5UL
12203
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x6UL
12204
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x7UL
12205
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL
12206
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL
12207
+
#define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM
12208
+
u8 unused_0[7];
12209
+
};
12210
+
12211
+
/* hwrm_nvm_defrag_input (size:192b/24B) */
12212
+
struct hwrm_nvm_defrag_input {
12213
+
__le16 req_type;
12214
+
__le16 cmpl_ring;
12215
+
__le16 seq_id;
12216
+
__le16 target_id;
12217
+
__le64 resp_addr;
12218
+
__le32 flags;
12219
+
#define NVM_DEFRAG_REQ_FLAGS_DEFRAG 0x1UL
12220
+
u8 unused_0[4];
12221
+
};
12222
+
12223
+
/* hwrm_nvm_defrag_output (size:128b/16B) */
12224
+
struct hwrm_nvm_defrag_output {
12225
+
__le16 error_code;
12226
+
__le16 req_type;
12227
+
__le16 seq_id;
12228
+
__le16 resp_len;
12229
+
u8 unused_0[7];
12230
+
u8 valid;
12231
+
};
12232
+
12233
+
/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */
12234
+
struct hwrm_nvm_defrag_cmd_err {
12235
+
u8 code;
12236
+
#define NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN 0x0UL
12237
+
#define NVM_DEFRAG_CMD_ERR_CODE_FAIL 0x1UL
12238
+
#define NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 0x2UL
12239
+
#define NVM_DEFRAG_CMD_ERR_CODE_LAST NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL
12240
+
u8 unused_0[7];
12241
+
};
12242
+
12243
+
/* hwrm_nvm_get_vpd_field_info_input (size:192b/24B) */
12244
+
struct hwrm_nvm_get_vpd_field_info_input {
12245
+
__le16 req_type;
12246
+
__le16 cmpl_ring;
12247
+
__le16 seq_id;
12248
+
__le16 target_id;
12249
+
__le64 resp_addr;
12250
+
u8 tag_id[2];
12251
+
u8 unused_0[6];
12252
+
};
12253
+
12254
+
/* hwrm_nvm_get_vpd_field_info_output (size:2176b/272B) */
12255
+
struct hwrm_nvm_get_vpd_field_info_output {
12256
+
__le16 error_code;
12257
+
__le16 req_type;
12258
+
__le16 seq_id;
12259
+
__le16 resp_len;
12260
+
u8 data[256];
12261
+
__le16 data_len;
12262
+
u8 unused_0[5];
12263
+
u8 valid;
12264
+
};
12265
+
12266
+
/* hwrm_nvm_get_vpd_field_info_cmd_err (size:64b/8B) */
12267
+
struct hwrm_nvm_get_vpd_field_info_cmd_err {
12268
+
u8 code;
12269
+
#define NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_UNKNOWN 0x0UL
12270
+
#define NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_NOT_CACHED 0x1UL
12271
+
#define NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_VPD_PARSE_FAILED 0x2UL
12272
+
#define NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_INVALID_TAG_ID 0x3UL
12273
+
#define NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_LAST NVM_GET_VPD_FIELD_INFO_CMD_ERR_CODE_INVALID_TAG_ID
12274
+
u8 unused_0[7];
12275
+
};
12276
+
12277
+
/* hwrm_nvm_set_vpd_field_info_input (size:256b/32B) */
12278
+
struct hwrm_nvm_set_vpd_field_info_input {
12279
+
__le16 req_type;
12280
+
__le16 cmpl_ring;
12281
+
__le16 seq_id;
12282
+
__le16 target_id;
12283
+
__le64 resp_addr;
12284
+
__le64 host_src_addr;
12285
+
u8 tag_id[2];
12286
+
__le16 data_len;
12287
+
u8 unused_0[4];
12288
+
};
12289
+
12290
+
/* hwrm_nvm_set_vpd_field_info_output (size:128b/16B) */
12291
+
struct hwrm_nvm_set_vpd_field_info_output {
12292
+
__le16 error_code;
12293
+
__le16 req_type;
12294
+
__le16 seq_id;
12295
+
__le16 resp_len;
12296
+
u8 unused_0[7];
12297
+
u8 valid;
12298
+
};
12299
+
12300
+
/* hwrm_nvm_set_profile_input (size:256b/32B) */
12301
+
struct hwrm_nvm_set_profile_input {
12302
+
__le16 req_type;
12303
+
__le16 cmpl_ring;
12304
+
__le16 seq_id;
12305
+
__le16 target_id;
12306
+
__le64 resp_addr;
12307
+
__le64 src_data_addr;
12308
+
__le16 data_len;
12309
+
u8 option_count;
12310
+
u8 flags;
12311
+
#define NVM_SET_PROFILE_REQ_FLAGS_FORCE_FLUSH 0x1UL
12312
+
#define NVM_SET_PROFILE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x3eUL
12313
+
#define NVM_SET_PROFILE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 1
12314
+
#define NVM_SET_PROFILE_REQ_FLAGS_VALIDATE_ONLY 0x40UL
12315
+
#define NVM_SET_PROFILE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
12316
+
u8 profile_type;
12317
+
#define NVM_SET_PROFILE_REQ_PROFILE_TYPE_NONE 0x0UL
12318
+
#define NVM_SET_PROFILE_REQ_PROFILE_TYPE_EROCE 0x1UL
12319
+
#define NVM_SET_PROFILE_REQ_PROFILE_TYPE_LAST NVM_SET_PROFILE_REQ_PROFILE_TYPE_EROCE
12320
+
u8 unused_2[3];
12321
+
};
12322
+
12323
+
/* hwrm_nvm_set_profile_output (size:128b/16B) */
12324
+
struct hwrm_nvm_set_profile_output {
12325
+
__le16 error_code;
12326
+
__le16 req_type;
12327
+
__le16 seq_id;
12328
+
__le16 resp_len;
12329
+
u8 unused_0[7];
12330
+
u8 valid;
12331
+
};
12332
+
12333
+
/* hwrm_nvm_set_profile_cmd_err (size:64b/8B) */
12334
+
struct hwrm_nvm_set_profile_cmd_err {
12335
+
u8 code;
12336
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_UNKNOWN 0x0UL
12337
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
12338
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
12339
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
12340
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_ACTION_NOT_SUPPORTED 0x4UL
12341
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_INDEX_INVALID 0x5UL
12342
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_ACCESS_DENIED 0x6UL
12343
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_CB_FAILED 0x7UL
12344
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL
12345
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_NO_MEM 0x9UL
12346
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_PROVISION_ERROR 0xaUL
12347
+
#define NVM_SET_PROFILE_CMD_ERR_CODE_LAST NVM_SET_PROFILE_CMD_ERR_CODE_PROVISION_ERROR
12348
+
u8 err_index;
12349
+
u8 unused_0[6];
12350
+
};
12351
+
12352
+
/* hwrm_nvm_set_profile_sb (size:128b/16B) */
12353
+
struct hwrm_nvm_set_profile_sb {
12354
+
__le16 data_len;
12355
+
__le16 option_num;
12356
+
#define NVM_SET_PROFILE_SB_OPTION_NUM_RSVD_0 0x0UL
12357
+
#define NVM_SET_PROFILE_SB_OPTION_NUM_RSVD_FFFF 0xffffUL
12358
+
#define NVM_SET_PROFILE_SB_OPTION_NUM_LAST NVM_SET_PROFILE_SB_OPTION_NUM_RSVD_FFFF
12359
+
__le16 dimensions;
12360
+
__le16 index_0;
12361
+
__le16 index_1;
12362
+
__le16 index_2;
12363
+
__le16 index_3;
12364
+
u8 flags;
12365
+
#define NVM_SET_PROFILE_SB_FLAGS_FLAGS_UNUSED_0_MASK 0xffUL
12366
+
#define NVM_SET_PROFILE_SB_FLAGS_FLAGS_UNUSED_0_SFT 0
12367
+
u8 unused_0;
12368
+
};
12369
+
12370
+
/* hwrm_selftest_qlist_input (size:128b/16B) */
12371
+
struct hwrm_selftest_qlist_input {
12372
+
__le16 req_type;
12373
+
__le16 cmpl_ring;
12374
+
__le16 seq_id;
12375
+
__le16 target_id;
12376
+
__le64 resp_addr;
12377
+
};
12378
+
12379
+
/* hwrm_selftest_qlist_output (size:2240b/280B) */
12380
+
struct hwrm_selftest_qlist_output {
12381
+
__le16 error_code;
12382
+
__le16 req_type;
12383
+
__le16 seq_id;
12384
+
__le16 resp_len;
12385
+
u8 num_tests;
12386
+
u8 available_tests;
12387
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
12388
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
12389
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
12390
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
12391
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
12392
+
#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
12393
+
u8 offline_tests;
12394
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
12395
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
12396
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
12397
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
12398
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
12399
+
#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
12400
+
u8 unused_0;
12401
+
__le16 test_timeout;
12402
+
u8 unused_1[2];
12403
+
char test_name[8][32];
12404
+
u8 eyescope_target_BER_support;
12405
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL
12406
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL
12407
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
12408
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
12409
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
12410
+
#define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
12411
+
u8 unused_2[6];
12412
+
u8 valid;
12413
+
};
12414
+
12415
+
/* hwrm_selftest_exec_input (size:192b/24B) */
12416
+
struct hwrm_selftest_exec_input {
12417
+
__le16 req_type;
12418
+
__le16 cmpl_ring;
12419
+
__le16 seq_id;
12420
+
__le16 target_id;
12421
+
__le64 resp_addr;
12422
+
u8 flags;
12423
+
#define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
12424
+
#define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
12425
+
#define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
12426
+
#define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
12427
+
#define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
12428
+
#define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
12429
+
u8 unused_0[7];
12430
+
};
12431
+
12432
+
/* hwrm_selftest_exec_output (size:128b/16B) */
12433
+
struct hwrm_selftest_exec_output {
12434
+
__le16 error_code;
12435
+
__le16 req_type;
12436
+
__le16 seq_id;
12437
+
__le16 resp_len;
12438
+
u8 requested_tests;
12439
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
12440
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
12441
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
12442
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
12443
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
12444
+
#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
12445
+
u8 test_success;
12446
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
12447
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
12448
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
12449
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
12450
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
12451
+
#define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
12452
+
u8 unused_0[5];
12453
+
u8 valid;
12454
+
};
12455
+
12456
+
/* hwrm_selftest_irq_input (size:128b/16B) */
12457
+
struct hwrm_selftest_irq_input {
12458
+
__le16 req_type;
12459
+
__le16 cmpl_ring;
12460
+
__le16 seq_id;
12461
+
__le16 target_id;
12462
+
__le64 resp_addr;
12463
+
};
12464
+
12465
+
/* hwrm_selftest_irq_output (size:128b/16B) */
12466
+
struct hwrm_selftest_irq_output {
12467
+
__le16 error_code;
12468
+
__le16 req_type;
12469
+
__le16 seq_id;
12470
+
__le16 resp_len;
12471
+
u8 unused_0[7];
12472
+
u8 valid;
12473
+
};
12474
+
12475
+
/* dbc_dbc (size:64b/8B) */
12476
+
struct dbc_dbc {
12477
+
__le32 index;
12478
+
#define DBC_DBC_INDEX_MASK 0xffffffUL
12479
+
#define DBC_DBC_INDEX_SFT 0
12480
+
#define DBC_DBC_EPOCH 0x1000000UL
12481
+
#define DBC_DBC_TOGGLE_MASK 0x6000000UL
12482
+
#define DBC_DBC_TOGGLE_SFT 25
12483
+
__le32 type_path_xid;
12484
+
#define DBC_DBC_XID_MASK 0xfffffUL
12485
+
#define DBC_DBC_XID_SFT 0
12486
+
#define DBC_DBC_PATH_MASK 0x3000000UL
12487
+
#define DBC_DBC_PATH_SFT 24
12488
+
#define DBC_DBC_PATH_ROCE (0x0UL << 24)
12489
+
#define DBC_DBC_PATH_L2 (0x1UL << 24)
12490
+
#define DBC_DBC_PATH_ENGINE (0x2UL << 24)
12491
+
#define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
12492
+
#define DBC_DBC_VALID 0x4000000UL
12493
+
#define DBC_DBC_DEBUG_TRACE 0x8000000UL
12494
+
#define DBC_DBC_TYPE_MASK 0xf0000000UL
12495
+
#define DBC_DBC_TYPE_SFT 28
12496
+
#define DBC_DBC_TYPE_SQ (0x0UL << 28)
12497
+
#define DBC_DBC_TYPE_RQ (0x1UL << 28)
12498
+
#define DBC_DBC_TYPE_SRQ (0x2UL << 28)
12499
+
#define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28)
12500
+
#define DBC_DBC_TYPE_CQ (0x4UL << 28)
12501
+
#define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28)
12502
+
#define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28)
12503
+
#define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28)
12504
+
#define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28)
12505
+
#define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
12506
+
#define DBC_DBC_TYPE_NQ (0xaUL << 28)
12507
+
#define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28)
12508
+
#define DBC_DBC_TYPE_CQ_REASSIGN (0xcUL << 28)
12509
+
#define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28)
12510
+
#define DBC_DBC_TYPE_NULL (0xfUL << 28)
12511
+
#define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
12512
+
};
12513
+
12514
+
/* db_push_start (size:64b/8B) */
12515
+
struct db_push_start {
12516
+
u64 db;
12517
+
#define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL
12518
+
#define DB_PUSH_START_DB_INDEX_SFT 0
12519
+
#define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL
12520
+
#define DB_PUSH_START_DB_PI_LO_SFT 24
12521
+
#define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL
12522
+
#define DB_PUSH_START_DB_XID_SFT 32
12523
+
#define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL
12524
+
#define DB_PUSH_START_DB_PI_HI_SFT 52
12525
+
#define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL
12526
+
#define DB_PUSH_START_DB_TYPE_SFT 60
12527
+
#define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60)
12528
+
#define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60)
12529
+
#define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END
12530
+
};
12531
+
12532
+
/* db_push_end (size:64b/8B) */
12533
+
struct db_push_end {
12534
+
u64 db;
12535
+
#define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL
12536
+
#define DB_PUSH_END_DB_INDEX_SFT 0
12537
+
#define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL
12538
+
#define DB_PUSH_END_DB_PI_LO_SFT 24
12539
+
#define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL
12540
+
#define DB_PUSH_END_DB_XID_SFT 32
12541
+
#define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL
12542
+
#define DB_PUSH_END_DB_PI_HI_SFT 52
12543
+
#define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL
12544
+
#define DB_PUSH_END_DB_PATH_SFT 56
12545
+
#define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56)
12546
+
#define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56)
12547
+
#define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56)
12548
+
#define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE
12549
+
#define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL
12550
+
#define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL
12551
+
#define DB_PUSH_END_DB_TYPE_SFT 60
12552
+
#define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60)
12553
+
#define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60)
12554
+
#define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END
12555
+
};
12556
+
12557
+
/* db_push_info (size:64b/8B) */
12558
+
struct db_push_info {
12559
+
u32 push_size_push_index;
12560
+
#define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
12561
+
#define DB_PUSH_INFO_PUSH_INDEX_SFT 0
12562
+
#define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
12563
+
#define DB_PUSH_INFO_PUSH_SIZE_SFT 24
12564
+
u32 reserved32;
12565
+
};
12566
+
12567
+
/* fw_status_reg (size:32b/4B) */
12568
+
struct fw_status_reg {
12569
+
u32 fw_status;
12570
+
#define FW_STATUS_REG_CODE_MASK 0xffffUL
12571
+
#define FW_STATUS_REG_CODE_SFT 0
12572
+
#define FW_STATUS_REG_CODE_READY 0x8000UL
12573
+
#define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY
12574
+
#define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL
12575
+
#define FW_STATUS_REG_RECOVERABLE 0x20000UL
12576
+
#define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL
12577
+
#define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
12578
+
#define FW_STATUS_REG_SHUTDOWN 0x100000UL
12579
+
#define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
12580
+
#define FW_STATUS_REG_RECOVERING 0x400000UL
12581
+
#define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL
12582
+
};
12583
+
12584
+
/* hcomm_status (size:64b/8B) */
12585
+
struct hcomm_status {
12586
+
u32 sig_ver;
12587
+
#define HCOMM_STATUS_VER_MASK 0xffUL
12588
+
#define HCOMM_STATUS_VER_SFT 0
12589
+
#define HCOMM_STATUS_VER_LATEST 0x1UL
12590
+
#define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
12591
+
#define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
12592
+
#define HCOMM_STATUS_SIGNATURE_SFT 8
12593
+
#define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8)
12594
+
#define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
12595
+
u32 fw_status_loc;
12596
+
#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL
12597
+
#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
12598
+
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL
12599
+
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL
12600
+
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL
12601
+
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL
12602
+
#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
12603
+
#define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL
12604
+
#define HCOMM_STATUS_TRUE_OFFSET_SFT 2
12605
+
};
12606
+
12607
+
#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
12608
+
12609
+
#endif /* _BNGE_HSI_H_ */