Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
serial: sh-sci: Add support for RZ/G3E RSCI
Add support for RZ/G3E RSCI. RSCI IP found on the RZ/G3E SoC is similar
to RZ/T2H, but it has a 32-stage FIFO. It has 6 clocks(5 module clocks
+ 1 external clock) instead of 3 clocks(2 module clocks + 1 external
clock) on T2H, has 6 irqs compared to 4 on RZ/T2H and has multiple resets.
Add support for the hardware flow control.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20251129164325.209213-18-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Biju Das
and committed by
Greg Kroah-Hartman
42eeed6d
068b862f
+257
-9
+251
-9
drivers/tty/serial/rsci.c
+251
-9
drivers/tty/serial/rsci.c
···
11
11
#include <linux/serial_core.h>
12
12
#include <linux/serial_sci.h>
13
13
#include <linux/tty_flip.h>
14
+
15
+
#include "serial_mctrl_gpio.h"
14
16
#include "rsci.h"
15
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16
18
MODULE_IMPORT_NS("SH_SCI");
···
60
58
#define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */
61
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#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */
62
60
#define CCR1_CTSE BIT(0) /* CTS Enable */
61
+
62
+
/* CCR2 (Common Control Register 2) */
63
+
#define CCR2_INIT 0xFF000004
64
+
#define CCR2_CKS_TCLK (0) /* TCLK clock */
65
+
#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */
66
+
#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */
67
+
#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */
68
+
#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */
69
+
#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */
70
+
#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */
71
+
#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */
72
+
73
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/* CCR3 (Common Control Register 3) */
74
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#define CCR3_INIT 0x1203
75
+
#define CCR3_BLK BIT(29) /* Block Transfer Mode */
76
+
#define CCR3_GM BIT(28) /* GSM Mode */
77
+
#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */
78
+
#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */
79
+
#define CCR3_DEN BIT(21) /* Driver Enabled */
80
+
#define CCR3_FM BIT(20) /* FIFO Mode Select */
81
+
#define CCR3_MP BIT(19) /* Multi-Processor Mode */
82
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#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */
83
+
#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */
84
+
#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */
85
+
#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */
86
+
#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */
87
+
#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */
88
+
#define CCR3_STP BIT(14) /* Stop bit Length */
89
+
#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */
90
+
#define CCR3_LSBF BIT(12) /* LSB First select */
91
+
#define CCR3_CHR1 BIT(9) /* Character Length */
92
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#define CCR3_CHR0 BIT(8) /* Character Length */
93
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#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */
94
+
#define CCR3_CPOL BIT(1) /* Clock Polarity Select */
95
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#define CCR3_CPHA BIT(0) /* Clock Phase Select */
63
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64
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/* FCR (FIFO Control Register) */
65
98
#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */
···
175
138
rsci_serial_out(port, CCR0, ctrl);
176
139
}
177
140
141
+
static void rsci_enable_ms(struct uart_port *port)
142
+
{
143
+
mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
144
+
}
145
+
146
+
static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
147
+
{
148
+
struct sci_port *s = to_sci_port(port);
149
+
150
+
/* Use port-specific handler if provided */
151
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if (s->cfg->ops && s->cfg->ops->init_pins) {
152
+
s->cfg->ops->init_pins(port, cflag);
153
+
return;
154
+
}
155
+
156
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if (!s->has_rtscts)
157
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return;
158
+
159
+
if (s->autorts)
160
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rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
161
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CCR1_CTSE | CCR1_CTSPEN);
162
+
}
163
+
178
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static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
179
165
{
180
166
u32 fcr = rsci_serial_in(port, FCR);
···
217
157
static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
218
158
const struct ktermios *old)
219
159
{
160
+
unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
161
+
unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
162
+
unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
220
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struct sci_port *s = to_sci_port(port);
164
+
unsigned int brr = 255, cks = 0;
165
+
int min_err = INT_MAX, err;
166
+
unsigned long max_freq = 0;
167
+
unsigned int baud, i;
221
168
unsigned long flags;
169
+
unsigned int ctrl;
170
+
int best_clk = -1;
171
+
172
+
if ((termios->c_cflag & CSIZE) == CS7) {
173
+
ccr3_val |= CCR3_CHR0;
174
+
} else {
175
+
termios->c_cflag &= ~CSIZE;
176
+
termios->c_cflag |= CS8;
177
+
}
178
+
179
+
if (termios->c_cflag & PARENB)
180
+
ccr1_val |= CCR1_PE;
181
+
182
+
if (termios->c_cflag & PARODD)
183
+
ccr1_val |= (CCR1_PE | CCR1_PM);
184
+
185
+
if (termios->c_cflag & CSTOPB)
186
+
ccr3_val |= CCR3_STP;
187
+
188
+
/* Enable noise filter function */
189
+
ccr1_val |= CCR1_NFEN;
190
+
191
+
/*
192
+
* earlyprintk comes here early on with port->uartclk set to zero.
193
+
* the clock framework is not up and running at this point so here
194
+
* we assume that 115200 is the maximum baud rate. please note that
195
+
* the baud rate is not programmed during earlyprintk - it is assumed
196
+
* that the previous boot loader has enabled required clocks and
197
+
* setup the baud rate generator hardware for us already.
198
+
*/
199
+
if (!port->uartclk) {
200
+
max_freq = 115200;
201
+
} else {
202
+
for (i = 0; i < SCI_NUM_CLKS; i++)
203
+
max_freq = max(max_freq, s->clk_rates[i]);
204
+
205
+
max_freq /= min_sr(s);
206
+
}
207
+
208
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baud = uart_get_baud_rate(port, termios, old, 0, max_freq);
209
+
if (!baud)
210
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goto done;
211
+
212
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/* Divided Functional Clock using standard Bit Rate Register */
213
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err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
214
+
if (abs(err) < abs(min_err)) {
215
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best_clk = SCI_FCK;
216
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ccr0_val = 0;
217
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min_err = err;
218
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brr = brr1;
219
+
cks = cks1;
220
+
}
221
+
222
+
done:
223
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if (best_clk >= 0)
224
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dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
225
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s->clks[best_clk], baud, min_err);
222
226
223
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sci_port_enable(s);
224
228
uart_port_lock_irqsave(port, &flags);
225
229
226
-
/* For now, only RX enabling is supported */
227
-
if (termios->c_cflag & CREAD)
230
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uart_update_timeout(port, termios->c_cflag, baud);
231
+
232
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rsci_serial_out(port, CCR0, ccr0_val);
233
+
234
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ccr3_val |= CCR3_FM;
235
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rsci_serial_out(port, CCR3, ccr3_val);
236
+
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ccr2_val |= (cks << 20) | (brr << 8);
238
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rsci_serial_out(port, CCR2, ccr2_val);
239
+
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rsci_serial_out(port, CCR1, ccr1_val);
241
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rsci_serial_out(port, CCR4, ccr4_val);
242
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ctrl = rsci_serial_in(port, FCR);
244
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ctrl |= (FCR_RFRST | FCR_TFRST);
245
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rsci_serial_out(port, FCR, ctrl);
246
+
247
+
if (s->rx_trigger > 1)
248
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rsci_scif_set_rtrg(port, s->rx_trigger);
249
+
250
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port->status &= ~UPSTAT_AUTOCTS;
251
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s->autorts = false;
252
+
253
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if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
254
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port->status |= UPSTAT_AUTOCTS;
255
+
s->autorts = true;
256
+
}
257
+
258
+
rsci_init_pins(port, termios->c_cflag);
259
+
rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
260
+
rsci_serial_out(port, FFCLR, FFCLR_DRC);
261
+
262
+
ccr0_val |= CCR0_RE;
263
+
rsci_serial_out(port, CCR0, ccr0_val);
264
+
265
+
if ((termios->c_cflag & CREAD) != 0)
228
266
rsci_start_rx(port);
229
267
230
268
uart_port_unlock_irqrestore(port, flags);
231
269
sci_port_disable(s);
270
+
271
+
if (UART_ENABLE_MS(port, termios->c_cflag))
272
+
rsci_enable_ms(port);
232
273
}
233
274
234
275
static int rsci_txfill(struct uart_port *port)
···
354
193
355
194
static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
356
195
{
357
-
/* Not supported yet */
196
+
if (mctrl & TIOCM_LOOP) {
197
+
/* Standard loopback mode */
198
+
rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
199
+
}
358
200
}
359
201
360
202
static unsigned int rsci_get_mctrl(struct uart_port *port)
361
203
{
362
-
/* Not supported yet */
363
-
return 0;
204
+
struct sci_port *s = to_sci_port(port);
205
+
struct mctrl_gpios *gpios = s->gpios;
206
+
unsigned int mctrl = 0;
207
+
208
+
mctrl_gpio_get(gpios, &mctrl);
209
+
210
+
/*
211
+
* CTS/RTS is handled in hardware when supported, while nothing
212
+
* else is wired up.
213
+
*/
214
+
if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
215
+
mctrl |= TIOCM_CTS;
216
+
217
+
if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
218
+
mctrl |= TIOCM_DSR;
219
+
220
+
if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
221
+
mctrl |= TIOCM_CAR;
222
+
223
+
return mctrl;
364
224
}
365
225
366
226
static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
···
511
329
continue;
512
330
}
513
331
514
-
/* Store data and status.
332
+
/*
333
+
* Store data and status.
515
334
* Non FIFO mode is not supported
516
335
*/
517
336
if (rdat & RDR_FFER) {
···
546
363
}
547
364
}
548
365
366
+
static void rsci_break_ctl(struct uart_port *port, int break_state)
367
+
{
368
+
unsigned short ccr0_val, ccr1_val;
369
+
unsigned long flags;
370
+
371
+
uart_port_lock_irqsave(port, &flags);
372
+
ccr1_val = rsci_serial_in(port, CCR1);
373
+
ccr0_val = rsci_serial_in(port, CCR0);
374
+
375
+
if (break_state == -1) {
376
+
ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
377
+
ccr0_val &= ~CCR0_TE;
378
+
} else {
379
+
ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
380
+
ccr0_val |= CCR0_TE;
381
+
}
382
+
383
+
rsci_serial_out(port, CCR1, ccr1_val);
384
+
rsci_serial_out(port, CCR0, ccr0_val);
385
+
uart_port_unlock_irqrestore(port, flags);
386
+
}
387
+
549
388
static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
550
389
{
551
390
u32 status;
···
589
384
static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
590
385
{
591
386
struct sci_port *s = to_sci_port(port);
592
-
u32 ctrl_temp =
593
-
s->params->param_bits->rxtx_enable | CCR0_TIE |
594
-
s->hscif_tot;
387
+
u32 ctrl_temp = s->params->param_bits->rxtx_enable;
388
+
389
+
if (s->type == RSCI_PORT_SCIF16)
390
+
ctrl_temp |= CCR0_TIE | s->hscif_tot;
391
+
595
392
rsci_serial_out(port, CCR0, ctrl_temp);
393
+
}
394
+
395
+
static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
396
+
{
397
+
/* First set TE = 0 and then restore the CCR0 value */
398
+
rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
399
+
rsci_serial_out(port, CCR0, ctrl);
596
400
}
597
401
598
402
static const char *rsci_type(struct uart_port *port)
···
633
419
.poll_sent_bits = CSR_TDRE | CSR_TEND,
634
420
};
635
421
422
+
static const struct sci_port_params rsci_rzg3e_port_params = {
423
+
.fifosize = 32,
424
+
.overrun_reg = CSR,
425
+
.overrun_mask = CSR_ORER,
426
+
.sampling_rate_mask = SCI_SR(32),
427
+
.error_mask = RSCI_DEFAULT_ERROR_MASK,
428
+
.error_clear = RSCI_ERROR_CLEAR,
429
+
.param_bits = &rsci_port_param_bits,
430
+
.common_regs = &rsci_common_regs,
431
+
};
432
+
636
433
static const struct sci_port_params rsci_rzt2h_port_params = {
637
434
.fifosize = 16,
638
435
.overrun_reg = CSR,
···
662
437
.start_tx = rsci_start_tx,
663
438
.stop_tx = rsci_stop_tx,
664
439
.stop_rx = rsci_stop_rx,
440
+
.enable_ms = rsci_enable_ms,
441
+
.break_ctl = rsci_break_ctl,
665
442
.startup = sci_startup,
666
443
.shutdown = sci_shutdown,
667
444
.set_termios = rsci_set_termios,
···
683
456
.receive_chars = rsci_receive_chars,
684
457
.poll_put_char = rsci_poll_put_char,
685
458
.prepare_console_write = rsci_prepare_console_write,
459
+
.finish_console_write = rsci_finish_console_write,
686
460
.suspend_regs_size = rsci_suspend_regs_size,
687
461
.set_rtrg = rsci_scif_set_rtrg,
688
462
.shutdown_complete = rsci_shutdown_complete,
463
+
};
464
+
465
+
struct sci_of_data of_rsci_rzg3e_data = {
466
+
.type = RSCI_PORT_SCIF32,
467
+
.ops = &rsci_port_ops,
468
+
.uart_ops = &rsci_uart_ops,
469
+
.params = &rsci_rzg3e_port_params,
689
470
};
690
471
691
472
struct sci_of_data of_rsci_rzt2h_data = {
···
705
470
706
471
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
707
472
473
+
static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device,
474
+
const char *opt)
475
+
{
476
+
return scix_early_console_setup(device, &of_rsci_rzg3e_data);
477
+
}
478
+
708
479
static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device,
709
480
const char *opt)
710
481
{
711
482
return scix_early_console_setup(device, &of_rsci_rzt2h_data);
712
483
}
713
484
485
+
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup);
714
486
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup);
715
487
716
488
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
+1
drivers/tty/serial/rsci.h
+1
drivers/tty/serial/rsci.h
+5
drivers/tty/serial/sh-sci.c
+5
drivers/tty/serial/sh-sci.c
···
3329
3329
sci_port->rx_trigger = 64;
3330
3330
break;
3331
3331
case PORT_SCIFA:
3332
+
case RSCI_PORT_SCIF32:
3332
3333
sci_port->rx_trigger = 32;
3333
3334
break;
3334
3335
case PORT_SCIF:
···
3663
3662
.data = &of_sci_scif_rzv2h,
3664
3663
},
3665
3664
#ifdef CONFIG_SERIAL_RSCI
3665
+
{
3666
+
.compatible = "renesas,r9a09g047-rsci",
3667
+
.data = &of_rsci_rzg3e_data,
3668
+
},
3666
3669
{
3667
3670
.compatible = "renesas,r9a09g077-rsci",
3668
3671
.data = &of_rsci_rzt2h_data,