+4

arch/arm/boot/dts/nxp/imx/Makefile

reviewed

··· 73 73 imx6dl-cubox-i-emmc-som-v15.dtb \ 74 74 imx6dl-cubox-i-som-v15.dtb \ 75 75 imx6dl-dfi-fs700-m60.dtb \ 76 76 + imx6dl-dhcom-pdk2.dtb \ 76 77 imx6dl-dhcom-picoitx.dtb \ 77 78 imx6dl-eckelmann-ci4x10.dtb \ 78 79 imx6dl-emcon-avari.dtb \ ··· 212 211 imx6q-kontron-samx6i-ads2.dtb \ 213 212 imx6q-kp-tpc.dtb \ 214 213 imx6q-logicpd.dtb \ 214 214 + imx6q-lxr.dtb \ 215 215 imx6q-marsboard.dtb \ 216 216 imx6q-mba6a.dtb \ 217 217 imx6q-mba6b.dtb \ ··· 292 290 dtb-$(CONFIG_SOC_IMX6SLL) += \ 293 291 imx6sll-evk.dtb \ 294 292 imx6sll-kobo-clarahd.dtb \ 293 293 + imx6sll-kobo-clara2e-a.dtb \ 294 294 + imx6sll-kobo-clara2e-b.dtb \ 295 295 imx6sll-kobo-librah2o.dtb 296 296 dtb-$(CONFIG_SOC_IMX6SX) += \ 297 297 imx6sx-nitrogen6sx.dtb \

+30 -32

arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi

reviewed

··· 44 44 }; 45 45 46 46 &iomuxc { 47 47 - imx35-eukrea { 48 48 - pinctrl_fec: fecgrp { 49 49 - fsl,pins = < 50 50 - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 51 51 - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 52 52 - MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 53 53 - MX35_PAD_FEC_COL__FEC_COL 0x80000000 54 54 - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 55 55 - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 56 56 - MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 57 57 - MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 58 58 - MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 59 59 - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 60 60 - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 61 61 - MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 62 62 - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 63 63 - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 64 64 - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 65 65 - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 66 66 - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 67 67 - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 68 68 - >; 69 69 - }; 47 47 + pinctrl_fec: fecgrp { 48 48 + fsl,pins = < 49 49 + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 50 50 + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 51 51 + MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 52 52 + MX35_PAD_FEC_COL__FEC_COL 0x80000000 53 53 + MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 54 54 + MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 55 55 + MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 56 56 + MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 57 57 + MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 58 58 + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 59 59 + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 60 60 + MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 61 61 + MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 62 62 + MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 63 63 + MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 64 64 + MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 65 65 + MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 66 66 + MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 67 67 + >; 68 68 + }; 70 69 71 71 - pinctrl_i2c1: i2c1grp { 72 72 - fsl,pins = < 73 73 - MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 74 74 - MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 75 75 - >; 76 76 - }; 70 70 + pinctrl_i2c1: i2c1grp { 71 71 + fsl,pins = < 72 72 + MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 73 73 + MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 74 74 + >; 75 75 + }; 77 76 78 78 - pinctrl_tsc2007_1: tsc2007grp-1 { 79 79 - fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; 80 80 - }; 77 77 + pinctrl_tsc2007_1: tsc2007-1-grp { 78 78 + fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; 81 79 }; 82 80 }; 83 81

+43 -45

arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts

reviewed

··· 69 69 }; 70 70 71 71 &iomuxc { 72 72 - imx35-eukrea { 73 73 - pinctrl_audmux: audmuxgrp { 74 74 - fsl,pins = < 75 75 - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 76 76 - MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 77 77 - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 78 78 - MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 79 79 - >; 80 80 - }; 72 72 + pinctrl_audmux: audmuxgrp { 73 73 + fsl,pins = < 74 74 + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 75 75 + MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 76 76 + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 77 77 + MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 78 78 + >; 79 79 + }; 81 80 82 82 - pinctrl_bp1: bp1grp { 83 83 - fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>; 84 84 - }; 81 81 + pinctrl_bp1: bp1grp { 82 82 + fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>; 83 83 + }; 85 84 86 86 - pinctrl_esdhc1: esdhc1grp { 87 87 - fsl,pins = < 88 88 - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 89 89 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 90 90 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 91 91 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 92 92 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 93 93 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 94 94 - MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ 95 95 - >; 96 96 - }; 85 85 + pinctrl_esdhc1: esdhc1grp { 86 86 + fsl,pins = < 87 87 + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 88 88 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 89 89 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 90 90 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 91 91 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 92 92 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 93 93 + MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ 94 94 + >; 95 95 + }; 97 96 98 98 - pinctrl_led1: led1grp { 99 99 - fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>; 100 100 - }; 97 97 + pinctrl_led1: led1grp { 98 98 + fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>; 99 99 + }; 101 100 102 102 - pinctrl_reg_lcd_3v3: reg-lcd-3v3 { 103 103 - fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>; 104 104 - }; 101 101 + pinctrl_reg_lcd_3v3: reg-lcd-3v3grp { 102 102 + fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>; 103 103 + }; 105 104 106 106 - pinctrl_uart1: uart1grp { 107 107 - fsl,pins = < 108 108 - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 109 109 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 110 110 - MX35_PAD_CTS1__UART1_CTS 0x1c5 111 111 - MX35_PAD_RTS1__UART1_RTS 0x1c5 112 112 - >; 113 113 - }; 105 105 + pinctrl_uart1: uart1grp { 106 106 + fsl,pins = < 107 107 + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 108 108 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 109 109 + MX35_PAD_CTS1__UART1_CTS 0x1c5 110 110 + MX35_PAD_RTS1__UART1_RTS 0x1c5 111 111 + >; 112 112 + }; 114 113 115 115 - pinctrl_uart2: uart2grp { 116 116 - fsl,pins = < 117 117 - MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 118 118 - MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 119 119 - MX35_PAD_RTS2__UART2_RTS 0x1c5 120 120 - MX35_PAD_CTS2__UART2_CTS 0x1c5 121 121 - >; 122 122 - }; 114 114 + pinctrl_uart2: uart2grp { 115 115 + fsl,pins = < 116 116 + MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 117 117 + MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 118 118 + MX35_PAD_RTS2__UART2_RTS 0x1c5 119 119 + MX35_PAD_CTS2__UART2_CTS 0x1c5 120 120 + >; 123 121 }; 124 122 }; 125 123

+17 -19

arch/arm/boot/dts/nxp/imx/imx35-pdk.dts

reviewed

··· 24 24 }; 25 25 26 26 &iomuxc { 27 27 - imx35-pdk { 28 28 - pinctrl_esdhc1: esdhc1grp { 29 29 - fsl,pins = < 30 30 - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 31 31 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 32 32 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 33 33 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 34 34 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 35 35 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 36 36 - >; 37 37 - }; 27 27 + pinctrl_esdhc1: esdhc1grp { 28 28 + fsl,pins = < 29 29 + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 30 30 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 31 31 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 32 32 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 33 33 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 34 34 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 35 35 + >; 36 36 + }; 38 37 39 39 - pinctrl_uart1: uart1grp { 40 40 - fsl,pins = < 41 41 - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 42 42 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 43 43 - MX35_PAD_CTS1__UART1_CTS 0x1c5 44 44 - MX35_PAD_RTS1__UART1_RTS 0x1c5 45 45 - >; 46 46 - }; 38 38 + pinctrl_uart1: uart1grp { 39 39 + fsl,pins = < 40 40 + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 41 41 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 42 42 + MX35_PAD_CTS1__UART1_CTS 0x1c5 43 43 + MX35_PAD_RTS1__UART1_RTS 0x1c5 44 44 + >; 47 45 }; 48 46 }; 49 47

+1 -1

arch/arm/boot/dts/nxp/imx/imx35.dtsi

reviewed

··· 156 156 status = "disabled"; 157 157 }; 158 158 159 159 - iomuxc: iomuxc@43fac000 { 159 159 + iomuxc: pinctrl@43fac000 { 160 160 compatible = "fsl,imx35-iomuxc"; 161 161 reg = <0x43fac000 0x4000>; 162 162 };

+30 -32

arch/arm/boot/dts/nxp/imx/imx50-evk.dts

reviewed

··· 52 52 }; 53 53 54 54 &iomuxc { 55 55 - imx50-evk { 56 56 - pinctrl_cspi: cspigrp { 57 57 - fsl,pins = < 58 58 - MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 59 59 - MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 60 60 - MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 61 61 - MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 62 62 - MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 63 63 - >; 64 64 - }; 55 55 + pinctrl_cspi: cspigrp { 56 56 + fsl,pins = < 57 57 + MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 58 58 + MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 59 59 + MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 60 60 + MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 61 61 + MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 62 62 + >; 63 63 + }; 65 64 66 66 - pinctrl_fec: fecgrp { 67 67 - fsl,pins = < 68 68 - MX50_PAD_SSI_RXFS__FEC_MDC 0x80 69 69 - MX50_PAD_SSI_RXC__FEC_MDIO 0x80 70 70 - MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 71 71 - MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 72 72 - MX50_PAD_DISP_D2__FEC_RX_DV 0x80 73 73 - MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 74 74 - MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 75 75 - MX50_PAD_DISP_D5__FEC_TX_EN 0x80 76 76 - MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 77 77 - MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 78 78 - >; 79 79 - }; 65 65 + pinctrl_fec: fecgrp { 66 66 + fsl,pins = < 67 67 + MX50_PAD_SSI_RXFS__FEC_MDC 0x80 68 68 + MX50_PAD_SSI_RXC__FEC_MDIO 0x80 69 69 + MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 70 70 + MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 71 71 + MX50_PAD_DISP_D2__FEC_RX_DV 0x80 72 72 + MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 73 73 + MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 74 74 + MX50_PAD_DISP_D5__FEC_TX_EN 0x80 75 75 + MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 76 76 + MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 77 77 + >; 78 78 + }; 80 79 81 81 - pinctrl_uart1: uart1grp { 82 82 - fsl,pins = < 83 83 - MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 84 84 - MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 85 85 - MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 86 86 - MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 87 87 - >; 88 88 - }; 80 80 + pinctrl_uart1: uart1grp { 81 81 + fsl,pins = < 82 82 + MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 83 83 + MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 84 84 + MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 85 85 + MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 86 86 + >; 89 87 }; 90 88 }; 91 89

+1 -1

arch/arm/boot/dts/nxp/imx/imx50.dtsi

reviewed

··· 283 283 clock-names = "ipg", "per"; 284 284 }; 285 285 286 286 - iomuxc: iomuxc@53fa8000 { 286 286 + iomuxc: pinctrl@53fa8000 { 287 287 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; 288 288 reg = <0x53fa8000 0x4000>; 289 289 };

+27 -29

arch/arm/boot/dts/nxp/imx/imx51-apf51.dts

reviewed

··· 37 37 }; 38 38 39 39 &iomuxc { 40 40 - imx51-apf51 { 41 41 - pinctrl_fec: fecgrp { 42 42 - fsl,pins = < 43 43 - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 44 44 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 45 45 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 46 46 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 47 47 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 48 48 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 49 49 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 50 50 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 51 51 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 52 52 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 53 53 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 54 54 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 55 55 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 56 56 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 57 57 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 58 58 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 59 59 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 60 60 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 61 61 - >; 62 62 - }; 40 40 + pinctrl_fec: fecgrp { 41 41 + fsl,pins = < 42 42 + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 43 43 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 44 44 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 45 45 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 46 46 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 47 47 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 48 48 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 49 49 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 50 50 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 51 51 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 52 52 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 53 53 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 54 54 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 55 55 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 56 56 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 57 57 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 58 58 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 59 59 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 60 60 + >; 61 61 + }; 63 62 64 64 - pinctrl_uart3: uart3grp { 65 65 - fsl,pins = < 66 66 - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 67 67 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 68 68 - >; 69 69 - }; 63 63 + pinctrl_uart3: uart3grp { 64 64 + fsl,pins = < 65 65 + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 66 66 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 67 67 + >; 70 68 }; 71 69 }; 72 70

+87 -89

arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts

reviewed

··· 113 113 pinctrl-names = "default"; 114 114 pinctrl-0 = <&pinctrl_hog>; 115 115 116 116 - imx51-apf51dev { 117 117 - pinctrl_backlight: backlightgrp { 118 118 - fsl,pins = < 119 119 - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 120 120 - >; 121 121 - }; 116 116 + pinctrl_backlight: backlightgrp { 117 117 + fsl,pins = < 118 118 + MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 119 119 + >; 120 120 + }; 122 121 123 123 - pinctrl_hog: hoggrp { 124 124 - fsl,pins = < 125 125 - MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 126 126 - MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 127 127 - MX51_PAD_EIM_CS4__GPIO2_29 0x100 128 128 - MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 129 129 - MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 130 130 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 131 131 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 132 132 - MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 133 133 - MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 134 134 - >; 135 135 - }; 122 122 + pinctrl_hog: hoggrp { 123 123 + fsl,pins = < 124 124 + MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 125 125 + MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 126 126 + MX51_PAD_EIM_CS4__GPIO2_29 0x100 127 127 + MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 128 128 + MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 129 129 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 130 130 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 131 131 + MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 132 132 + MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 133 133 + >; 134 134 + }; 136 135 137 137 - pinctrl_ecspi1: ecspi1grp { 138 138 - fsl,pins = < 139 139 - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 140 140 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 141 141 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 142 142 - >; 143 143 - }; 136 136 + pinctrl_ecspi1: ecspi1grp { 137 137 + fsl,pins = < 138 138 + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 139 139 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 140 140 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 141 141 + >; 142 142 + }; 144 143 145 145 - pinctrl_ecspi2: ecspi2grp { 146 146 - fsl,pins = < 147 147 - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 148 148 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 149 149 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 150 150 - >; 151 151 - }; 144 144 + pinctrl_ecspi2: ecspi2grp { 145 145 + fsl,pins = < 146 146 + MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 147 147 + MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 148 148 + MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 149 149 + >; 150 150 + }; 152 151 153 153 - pinctrl_esdhc1: esdhc1grp { 154 154 - fsl,pins = < 155 155 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 156 156 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 157 157 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 158 158 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 159 159 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 160 160 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 161 161 - >; 162 162 - }; 152 152 + pinctrl_esdhc1: esdhc1grp { 153 153 + fsl,pins = < 154 154 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 155 155 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 156 156 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 157 157 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 158 158 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 159 159 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 160 160 + >; 161 161 + }; 163 162 164 164 - pinctrl_esdhc2: esdhc2grp { 165 165 - fsl,pins = < 166 166 - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 167 167 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 168 168 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 169 169 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 170 170 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 171 171 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 172 172 - >; 173 173 - }; 163 163 + pinctrl_esdhc2: esdhc2grp { 164 164 + fsl,pins = < 165 165 + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 166 166 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 167 167 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 168 168 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 169 169 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 170 170 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 171 171 + >; 172 172 + }; 174 173 175 175 - pinctrl_i2c2: i2c2grp { 176 176 - fsl,pins = < 177 177 - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed 178 178 - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed 179 179 - >; 180 180 - }; 174 174 + pinctrl_i2c2: i2c2grp { 175 175 + fsl,pins = < 176 176 + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed 177 177 + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed 178 178 + >; 179 179 + }; 181 180 182 182 - pinctrl_ipu_disp1: ipudisp1grp { 183 183 - fsl,pins = < 184 184 - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 185 185 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 186 186 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 187 187 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 188 188 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 189 189 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 190 190 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 191 191 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 192 192 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 193 193 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 194 194 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 195 195 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 196 196 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 197 197 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 198 198 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 199 199 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 200 200 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 201 201 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 202 202 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 203 203 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 204 204 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 205 205 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 206 206 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 207 207 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 208 208 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 209 209 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 210 210 - >; 211 211 - }; 181 181 + pinctrl_ipu_disp1: ipudisp1grp { 182 182 + fsl,pins = < 183 183 + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 184 184 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 185 185 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 186 186 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 187 187 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 188 188 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 189 189 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 190 190 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 191 191 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 192 192 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 193 193 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 194 194 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 195 195 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 196 196 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 197 197 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 198 198 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 199 199 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 200 200 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 201 201 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 202 202 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 203 203 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 204 204 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 205 205 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 206 206 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 207 207 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 208 208 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 209 209 + >; 212 210 }; 213 211 }; 214 212

+218 -220

arch/arm/boot/dts/nxp/imx/imx51-babbage.dts

reviewed

··· 474 474 }; 475 475 476 476 &iomuxc { 477 477 - imx51-babbage { 478 478 - pinctrl_audmux: audmuxgrp { 479 479 - fsl,pins = < 480 480 - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 481 481 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 482 482 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 483 483 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 484 484 - >; 485 485 - }; 477 477 + pinctrl_audmux: audmuxgrp { 478 478 + fsl,pins = < 479 479 + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 480 480 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 481 481 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 482 482 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 483 483 + >; 484 484 + }; 486 485 487 487 - pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { 488 488 - fsl,pins = < 489 489 - MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 490 490 - >; 491 491 - }; 486 486 + pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { 487 487 + fsl,pins = < 488 488 + MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 489 489 + >; 490 490 + }; 492 491 493 493 - pinctrl_clk26mhz_osc: clk26mhzoscgrp { 494 494 - fsl,pins = < 495 495 - MX51_PAD_DI1_PIN12__GPIO3_1 0x85 496 496 - >; 497 497 - }; 492 492 + pinctrl_clk26mhz_osc: clk26mhzoscgrp { 493 493 + fsl,pins = < 494 494 + MX51_PAD_DI1_PIN12__GPIO3_1 0x85 495 495 + >; 496 496 + }; 498 497 499 499 - pinctrl_clk26mhz_usb: clk26mhzusbgrp { 500 500 - fsl,pins = < 501 501 - MX51_PAD_EIM_D17__GPIO2_1 0x85 502 502 - >; 503 503 - }; 498 498 + pinctrl_clk26mhz_usb: clk26mhzusbgrp { 499 499 + fsl,pins = < 500 500 + MX51_PAD_EIM_D17__GPIO2_1 0x85 501 501 + >; 502 502 + }; 504 503 505 505 - pinctrl_ecspi1: ecspi1grp { 506 506 - fsl,pins = < 507 507 - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 508 508 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 509 509 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 510 510 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 511 511 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ 512 512 - >; 513 513 - }; 504 504 + pinctrl_ecspi1: ecspi1grp { 505 505 + fsl,pins = < 506 506 + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 507 507 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 508 508 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 509 509 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 510 510 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ 511 511 + >; 512 512 + }; 514 513 515 515 - pinctrl_esdhc1: esdhc1grp { 516 516 - fsl,pins = < 517 517 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 518 518 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 519 519 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 520 520 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 521 521 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 522 522 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 523 523 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 524 524 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 525 525 - >; 526 526 - }; 514 514 + pinctrl_esdhc1: esdhc1grp { 515 515 + fsl,pins = < 516 516 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 517 517 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 518 518 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 519 519 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 520 520 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 521 521 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 522 522 + MX51_PAD_GPIO1_0__GPIO1_0 0x100 523 523 + MX51_PAD_GPIO1_1__GPIO1_1 0x100 524 524 + >; 525 525 + }; 527 526 528 528 - pinctrl_esdhc2: esdhc2grp { 529 529 - fsl,pins = < 530 530 - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 531 531 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 532 532 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 533 533 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 534 534 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 535 535 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 536 536 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ 537 537 - MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ 538 538 - >; 539 539 - }; 527 527 + pinctrl_esdhc2: esdhc2grp { 528 528 + fsl,pins = < 529 529 + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 530 530 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 531 531 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 532 532 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 533 533 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 534 534 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 535 535 + MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ 536 536 + MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ 537 537 + >; 538 538 + }; 540 539 541 541 - pinctrl_fec: fecgrp { 542 542 - fsl,pins = < 543 543 - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 544 544 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 545 545 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 546 546 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 547 547 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 548 548 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 549 549 - MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 550 550 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 551 551 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 552 552 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 553 553 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 554 554 - MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 555 555 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 556 556 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 557 557 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 558 558 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 559 559 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 560 560 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 561 561 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ 562 562 - >; 563 563 - }; 540 540 + pinctrl_fec: fecgrp { 541 541 + fsl,pins = < 542 542 + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 543 543 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 544 544 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 545 545 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 546 546 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 547 547 + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 548 548 + MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 549 549 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 550 550 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 551 551 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 552 552 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 553 553 + MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 554 554 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 555 555 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 556 556 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 557 557 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 558 558 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 559 559 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 560 560 + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ 561 561 + >; 562 562 + }; 564 563 565 565 - pinctrl_gpio_keys: gpiokeysgrp { 566 566 - fsl,pins = < 567 567 - MX51_PAD_EIM_A27__GPIO2_21 0x5 568 568 - >; 569 569 - }; 564 564 + pinctrl_gpio_keys: gpiokeysgrp { 565 565 + fsl,pins = < 566 566 + MX51_PAD_EIM_A27__GPIO2_21 0x5 567 567 + >; 568 568 + }; 570 569 571 571 - pinctrl_gpio_leds: gpioledsgrp { 572 572 - fsl,pins = < 573 573 - MX51_PAD_EIM_D22__GPIO2_6 0x80000000 574 574 - >; 575 575 - }; 570 570 + pinctrl_gpio_leds: gpioledsgrp { 571 571 + fsl,pins = < 572 572 + MX51_PAD_EIM_D22__GPIO2_6 0x80000000 573 573 + >; 574 574 + }; 576 575 577 577 - pinctrl_i2c1: i2c1grp { 578 578 - fsl,pins = < 579 579 - MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed 580 580 - MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed 581 581 - >; 582 582 - }; 576 576 + pinctrl_i2c1: i2c1grp { 577 577 + fsl,pins = < 578 578 + MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed 579 579 + MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed 580 580 + >; 581 581 + }; 583 582 584 584 - pinctrl_i2c2: i2c2grp { 585 585 - fsl,pins = < 586 586 - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 587 587 - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 588 588 - >; 589 589 - }; 583 583 + pinctrl_i2c2: i2c2grp { 584 584 + fsl,pins = < 585 585 + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 586 586 + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 587 587 + >; 588 588 + }; 590 589 591 591 - pinctrl_ipu_disp1: ipudisp1grp { 592 592 - fsl,pins = < 593 593 - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 594 594 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 595 595 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 596 596 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 597 597 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 598 598 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 599 599 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 600 600 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 601 601 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 602 602 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 603 603 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 604 604 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 605 605 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 606 606 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 607 607 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 608 608 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 609 609 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 610 610 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 611 611 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 612 612 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 613 613 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 614 614 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 615 615 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 616 616 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 617 617 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 618 618 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 619 619 - >; 620 620 - }; 590 590 + pinctrl_ipu_disp1: ipudisp1grp { 591 591 + fsl,pins = < 592 592 + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 593 593 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 594 594 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 595 595 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 596 596 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 597 597 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 598 598 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 599 599 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 600 600 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 601 601 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 602 602 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 603 603 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 604 604 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 605 605 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 606 606 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 607 607 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 608 608 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 609 609 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 610 610 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 611 611 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 612 612 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 613 613 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 614 614 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 615 615 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 616 616 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 617 617 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 618 618 + >; 619 619 + }; 621 620 622 622 - pinctrl_ipu_disp2: ipudisp2grp { 623 623 - fsl,pins = < 624 624 - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 625 625 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 626 626 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 627 627 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 628 628 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 629 629 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 630 630 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 631 631 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 632 632 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 633 633 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 634 634 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 635 635 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 636 636 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 637 637 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 638 638 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 639 639 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 640 640 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 641 641 - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 642 642 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 643 643 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 644 644 - >; 645 645 - }; 621 621 + pinctrl_ipu_disp2: ipudisp2grp { 622 622 + fsl,pins = < 623 623 + MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 624 624 + MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 625 625 + MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 626 626 + MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 627 627 + MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 628 628 + MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 629 629 + MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 630 630 + MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 631 631 + MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 632 632 + MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 633 633 + MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 634 634 + MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 635 635 + MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 636 636 + MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 637 637 + MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 638 638 + MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 639 639 + MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 640 640 + MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 641 641 + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 642 642 + MX51_PAD_DI_GP4__DI2_PIN15 0x5 643 643 + >; 644 644 + }; 646 645 647 647 - pinctrl_kpp: kppgrp { 648 648 - fsl,pins = < 649 649 - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 650 650 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 651 651 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 652 652 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 653 653 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 654 654 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 655 655 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 656 656 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 657 657 - >; 658 658 - }; 646 646 + pinctrl_kpp: kppgrp { 647 647 + fsl,pins = < 648 648 + MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 649 649 + MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 650 650 + MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 651 651 + MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 652 652 + MX51_PAD_KEY_COL0__KEY_COL0 0xe8 653 653 + MX51_PAD_KEY_COL1__KEY_COL1 0xe8 654 654 + MX51_PAD_KEY_COL2__KEY_COL2 0xe8 655 655 + MX51_PAD_KEY_COL3__KEY_COL3 0xe8 656 656 + >; 657 657 + }; 659 658 660 660 - pinctrl_pmic: pmicgrp { 661 661 - fsl,pins = < 662 662 - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ 663 663 - >; 664 664 - }; 659 659 + pinctrl_pmic: pmicgrp { 660 660 + fsl,pins = < 661 661 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ 662 662 + >; 663 663 + }; 665 664 666 666 - pinctrl_uart1: uart1grp { 667 667 - fsl,pins = < 668 668 - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 669 669 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 670 670 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 671 671 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 672 672 - >; 673 673 - }; 665 665 + pinctrl_uart1: uart1grp { 666 666 + fsl,pins = < 667 667 + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 668 668 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 669 669 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 670 670 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 671 671 + >; 672 672 + }; 674 673 675 675 - pinctrl_uart2: uart2grp { 676 676 - fsl,pins = < 677 677 - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 678 678 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 679 679 - >; 680 680 - }; 674 674 + pinctrl_uart2: uart2grp { 675 675 + fsl,pins = < 676 676 + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 677 677 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 678 678 + >; 679 679 + }; 681 680 682 682 - pinctrl_uart3: uart3grp { 683 683 - fsl,pins = < 684 684 - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 685 685 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 686 686 - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 687 687 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 688 688 - >; 689 689 - }; 681 681 + pinctrl_uart3: uart3grp { 682 682 + fsl,pins = < 683 683 + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 684 684 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 685 685 + MX51_PAD_EIM_D27__UART3_RTS 0x1c5 686 686 + MX51_PAD_EIM_D24__UART3_CTS 0x1c5 687 687 + >; 688 688 + }; 690 689 691 691 - pinctrl_usbh1: usbh1grp { 692 692 - fsl,pins = < 693 693 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 694 694 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 695 695 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 696 696 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 697 697 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 698 698 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 699 699 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 700 700 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 701 701 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 702 702 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 703 703 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 704 704 - >; 705 705 - }; 690 690 + pinctrl_usbh1: usbh1grp { 691 691 + fsl,pins = < 692 692 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 693 693 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 694 694 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 695 695 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 696 696 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 697 697 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 698 698 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 699 699 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 700 700 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 701 701 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 702 702 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 703 703 + >; 704 704 + }; 706 705 707 707 - pinctrl_usbh1reg: usbh1reggrp { 708 708 - fsl,pins = < 709 709 - MX51_PAD_EIM_D21__GPIO2_5 0x85 710 710 - >; 711 711 - }; 706 706 + pinctrl_usbh1reg: usbh1reggrp { 707 707 + fsl,pins = < 708 708 + MX51_PAD_EIM_D21__GPIO2_5 0x85 709 709 + >; 710 710 + }; 712 711 713 713 - pinctrl_usbotgreg: usbotgreggrp { 714 714 - fsl,pins = < 715 715 - MX51_PAD_GPIO1_7__GPIO1_7 0x85 716 716 - >; 717 717 - }; 712 712 + pinctrl_usbotgreg: usbotgreggrp { 713 713 + fsl,pins = < 714 714 + MX51_PAD_GPIO1_7__GPIO1_7 0x85 715 715 + >; 718 716 }; 719 717 };

+38 -40

arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts

reviewed

··· 78 78 }; 79 79 80 80 &iomuxc { 81 81 - imx51-digi-connectcore-jsk { 82 82 - pinctrl_owire: owiregrp { 83 83 - fsl,pins = < 84 84 - MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 85 85 - >; 86 86 - }; 81 81 + pinctrl_owire: owiregrp { 82 82 + fsl,pins = < 83 83 + MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 84 84 + >; 85 85 + }; 87 86 88 88 - pinctrl_uart1: uart1grp { 89 89 - fsl,pins = < 90 90 - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 91 91 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 92 92 - >; 93 93 - }; 87 87 + pinctrl_uart1: uart1grp { 88 88 + fsl,pins = < 89 89 + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 90 90 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 91 91 + >; 92 92 + }; 94 93 95 95 - pinctrl_uart2: uart2grp { 96 96 - fsl,pins = < 97 97 - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 98 98 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 99 99 - >; 100 100 - }; 94 94 + pinctrl_uart2: uart2grp { 95 95 + fsl,pins = < 96 96 + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 97 97 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 98 98 + >; 99 99 + }; 101 100 102 102 - pinctrl_uart3: uart3grp { 103 103 - fsl,pins = < 104 104 - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 105 105 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 106 106 - >; 107 107 - }; 101 101 + pinctrl_uart3: uart3grp { 102 102 + fsl,pins = < 103 103 + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 104 104 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 105 105 + >; 106 106 + }; 108 107 109 109 - pinctrl_usbh1: usbh1grp { 110 110 - fsl,pins = < 111 111 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 112 112 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 113 113 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 114 114 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 115 115 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 116 116 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 117 117 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 118 118 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 119 119 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 120 120 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 121 121 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 122 122 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 123 123 - >; 124 124 - }; 108 108 + pinctrl_usbh1: usbh1grp { 109 109 + fsl,pins = < 110 110 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 111 111 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 112 112 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 113 113 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 114 114 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 115 115 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 116 116 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 117 117 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 118 118 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 119 119 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 120 120 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 121 121 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 122 122 + >; 125 123 }; 126 124 };

+145 -147

arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi

reviewed

··· 215 215 }; 216 216 217 217 &iomuxc { 218 218 - imx51-digi-connectcore-som { 219 219 - pinctrl_ecspi1: ecspi1grp { 220 220 - fsl,pins = < 221 221 - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 222 222 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 223 223 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 224 224 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 225 225 - >; 226 226 - }; 218 218 + pinctrl_ecspi1: ecspi1grp { 219 219 + fsl,pins = < 220 220 + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 221 221 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 222 222 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 223 223 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 224 224 + >; 225 225 + }; 227 226 228 228 - pinctrl_esdhc1: esdhc1grp { 229 229 - fsl,pins = < 230 230 - MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 231 231 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 232 232 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 233 233 - >; 234 234 - }; 227 227 + pinctrl_esdhc1: esdhc1grp { 228 228 + fsl,pins = < 229 229 + MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 230 230 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 231 231 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 232 232 + >; 233 233 + }; 235 234 236 236 - pinctrl_esdhc2: esdhc2grp { 237 237 - fsl,pins = < 238 238 - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 239 239 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 240 240 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 241 241 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 242 242 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 243 243 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 244 244 - >; 245 245 - }; 235 235 + pinctrl_esdhc2: esdhc2grp { 236 236 + fsl,pins = < 237 237 + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 238 238 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 239 239 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 240 240 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 241 241 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 242 242 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 243 243 + >; 244 244 + }; 246 245 247 247 - pinctrl_fec: fecgrp { 248 248 - fsl,pins = < 249 249 - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 250 250 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 251 251 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 252 252 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 253 253 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 254 254 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 255 255 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 256 256 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 257 257 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 258 258 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 259 259 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 260 260 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 261 261 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 262 262 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 263 263 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 264 264 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 265 265 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 266 266 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 267 267 - >; 268 268 - }; 246 246 + pinctrl_fec: fecgrp { 247 247 + fsl,pins = < 248 248 + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 249 249 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 250 250 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 251 251 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 252 252 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 253 253 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 254 254 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 255 255 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 256 256 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 257 257 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 258 258 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 259 259 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 260 260 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 261 261 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 262 262 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 263 263 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 264 264 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 265 265 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 266 266 + >; 267 267 + }; 269 268 270 270 - pinctrl_i2c2: i2c2grp { 271 271 - fsl,pins = < 272 272 - MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed 273 273 - MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed 274 274 - >; 275 275 - }; 269 269 + pinctrl_i2c2: i2c2grp { 270 270 + fsl,pins = < 271 271 + MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed 272 272 + MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed 273 273 + >; 274 274 + }; 276 275 277 277 - pinctrl_i2c2_gpio: i2c2gpiogrp { 278 278 - fsl,pins = < 279 279 - MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed 280 280 - MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed 281 281 - >; 282 282 - }; 276 276 + pinctrl_i2c2_gpio: i2c2gpiogrp { 277 277 + fsl,pins = < 278 278 + MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed 279 279 + MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed 280 280 + >; 281 281 + }; 283 282 284 284 - pinctrl_nfc: nfcgrp { 285 285 - fsl,pins = < 286 286 - MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 287 287 - MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 288 288 - MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 289 289 - MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 290 290 - MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 291 291 - MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 292 292 - MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 293 293 - MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 294 294 - MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 295 295 - MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 296 296 - MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 297 297 - MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 298 298 - MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 299 299 - MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 300 300 - MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 301 301 - >; 302 302 - }; 283 283 + pinctrl_nfc: nfcgrp { 284 284 + fsl,pins = < 285 285 + MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 286 286 + MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 287 287 + MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 288 288 + MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 289 289 + MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 290 290 + MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 291 291 + MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 292 292 + MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 293 293 + MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 294 294 + MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 295 295 + MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 296 296 + MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 297 297 + MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 298 298 + MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 299 299 + MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 300 300 + >; 301 301 + }; 303 302 304 304 - pinctrl_lan9221: lan9221grp { 305 305 - fsl,pins = < 306 306 - MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ 307 307 - >; 308 308 - }; 303 303 + pinctrl_lan9221: lan9221grp { 304 304 + fsl,pins = < 305 305 + MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ 306 306 + >; 307 307 + }; 309 308 310 310 - pinctrl_mc13892: mc13892grp { 311 311 - fsl,pins = < 312 312 - MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ 313 313 - >; 314 314 - }; 309 309 + pinctrl_mc13892: mc13892grp { 310 310 + fsl,pins = < 311 311 + MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ 312 312 + >; 313 313 + }; 315 314 316 316 - pinctrl_mma7455l: mma7455lgrp { 317 317 - fsl,pins = < 318 318 - MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ 319 319 - MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ 320 320 - >; 321 321 - }; 315 315 + pinctrl_mma7455l: mma7455lgrp { 316 316 + fsl,pins = < 317 317 + MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ 318 318 + MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ 319 319 + >; 320 320 + }; 322 321 323 323 - pinctrl_weim: weimgrp { 324 324 - fsl,pins = < 325 325 - MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 326 326 - MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 327 327 - MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 328 328 - MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 329 329 - MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 330 330 - MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 331 331 - MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 332 332 - MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 333 333 - MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 334 334 - MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 335 335 - MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 336 336 - MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 337 337 - MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 338 338 - MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 339 339 - MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 340 340 - MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 341 341 - MX51_PAD_EIM_A16__EIM_A16 0x80000000 342 342 - MX51_PAD_EIM_A17__EIM_A17 0x80000000 343 343 - MX51_PAD_EIM_A18__EIM_A18 0x80000000 344 344 - MX51_PAD_EIM_A19__EIM_A19 0x80000000 345 345 - MX51_PAD_EIM_A20__EIM_A20 0x80000000 346 346 - MX51_PAD_EIM_A21__EIM_A21 0x80000000 347 347 - MX51_PAD_EIM_A22__EIM_A22 0x80000000 348 348 - MX51_PAD_EIM_A23__EIM_A23 0x80000000 349 349 - MX51_PAD_EIM_A24__EIM_A24 0x80000000 350 350 - MX51_PAD_EIM_A25__EIM_A25 0x80000000 351 351 - MX51_PAD_EIM_A26__EIM_A26 0x80000000 352 352 - MX51_PAD_EIM_A27__EIM_A27 0x80000000 353 353 - MX51_PAD_EIM_D16__EIM_D16 0x80000000 354 354 - MX51_PAD_EIM_D17__EIM_D17 0x80000000 355 355 - MX51_PAD_EIM_D18__EIM_D18 0x80000000 356 356 - MX51_PAD_EIM_D19__EIM_D19 0x80000000 357 357 - MX51_PAD_EIM_D20__EIM_D20 0x80000000 358 358 - MX51_PAD_EIM_D21__EIM_D21 0x80000000 359 359 - MX51_PAD_EIM_D22__EIM_D22 0x80000000 360 360 - MX51_PAD_EIM_D23__EIM_D23 0x80000000 361 361 - MX51_PAD_EIM_D24__EIM_D24 0x80000000 362 362 - MX51_PAD_EIM_D25__EIM_D25 0x80000000 363 363 - MX51_PAD_EIM_D26__EIM_D26 0x80000000 364 364 - MX51_PAD_EIM_D27__EIM_D27 0x80000000 365 365 - MX51_PAD_EIM_D28__EIM_D28 0x80000000 366 366 - MX51_PAD_EIM_D29__EIM_D29 0x80000000 367 367 - MX51_PAD_EIM_D30__EIM_D30 0x80000000 368 368 - MX51_PAD_EIM_D31__EIM_D31 0x80000000 369 369 - MX51_PAD_EIM_OE__EIM_OE 0x80000000 370 370 - MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 371 371 - MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 372 372 - MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ 373 373 - >; 374 374 - }; 322 322 + pinctrl_weim: weimgrp { 323 323 + fsl,pins = < 324 324 + MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 325 325 + MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 326 326 + MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 327 327 + MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 328 328 + MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 329 329 + MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 330 330 + MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 331 331 + MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 332 332 + MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 333 333 + MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 334 334 + MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 335 335 + MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 336 336 + MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 337 337 + MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 338 338 + MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 339 339 + MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 340 340 + MX51_PAD_EIM_A16__EIM_A16 0x80000000 341 341 + MX51_PAD_EIM_A17__EIM_A17 0x80000000 342 342 + MX51_PAD_EIM_A18__EIM_A18 0x80000000 343 343 + MX51_PAD_EIM_A19__EIM_A19 0x80000000 344 344 + MX51_PAD_EIM_A20__EIM_A20 0x80000000 345 345 + MX51_PAD_EIM_A21__EIM_A21 0x80000000 346 346 + MX51_PAD_EIM_A22__EIM_A22 0x80000000 347 347 + MX51_PAD_EIM_A23__EIM_A23 0x80000000 348 348 + MX51_PAD_EIM_A24__EIM_A24 0x80000000 349 349 + MX51_PAD_EIM_A25__EIM_A25 0x80000000 350 350 + MX51_PAD_EIM_A26__EIM_A26 0x80000000 351 351 + MX51_PAD_EIM_A27__EIM_A27 0x80000000 352 352 + MX51_PAD_EIM_D16__EIM_D16 0x80000000 353 353 + MX51_PAD_EIM_D17__EIM_D17 0x80000000 354 354 + MX51_PAD_EIM_D18__EIM_D18 0x80000000 355 355 + MX51_PAD_EIM_D19__EIM_D19 0x80000000 356 356 + MX51_PAD_EIM_D20__EIM_D20 0x80000000 357 357 + MX51_PAD_EIM_D21__EIM_D21 0x80000000 358 358 + MX51_PAD_EIM_D22__EIM_D22 0x80000000 359 359 + MX51_PAD_EIM_D23__EIM_D23 0x80000000 360 360 + MX51_PAD_EIM_D24__EIM_D24 0x80000000 361 361 + MX51_PAD_EIM_D25__EIM_D25 0x80000000 362 362 + MX51_PAD_EIM_D26__EIM_D26 0x80000000 363 363 + MX51_PAD_EIM_D27__EIM_D27 0x80000000 364 364 + MX51_PAD_EIM_D28__EIM_D28 0x80000000 365 365 + MX51_PAD_EIM_D29__EIM_D29 0x80000000 366 366 + MX51_PAD_EIM_D30__EIM_D30 0x80000000 367 367 + MX51_PAD_EIM_D31__EIM_D31 0x80000000 368 368 + MX51_PAD_EIM_OE__EIM_OE 0x80000000 369 369 + MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 370 370 + MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 371 371 + MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ 372 372 + >; 375 373 }; 376 374 };

+33 -35

arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi

reviewed

··· 44 44 }; 45 45 46 46 &iomuxc { 47 47 - imx51-eukrea { 48 48 - pinctrl_tsc2007_1: tsc2007grp-1 { 49 49 - fsl,pins = < 50 50 - MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 51 51 - MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 52 52 - >; 53 53 - }; 47 47 + pinctrl_tsc2007_1: tsc2007-1-grp { 48 48 + fsl,pins = < 49 49 + MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 50 50 + MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 51 51 + >; 52 52 + }; 54 53 55 55 - pinctrl_fec: fecgrp { 56 56 - fsl,pins = < 57 57 - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 58 58 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 59 59 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 60 60 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 61 61 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 62 62 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 63 63 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 64 64 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 65 65 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 66 66 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 67 67 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 68 68 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 69 69 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 70 70 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 71 71 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 72 72 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 73 73 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 74 74 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 75 75 - >; 76 76 - }; 54 54 + pinctrl_fec: fecgrp { 55 55 + fsl,pins = < 56 56 + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 57 57 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 58 58 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 59 59 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 60 60 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 61 61 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 62 62 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 63 63 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 64 64 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 65 65 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 66 66 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 67 67 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 68 68 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 69 69 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 70 70 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 71 71 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 72 72 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 73 73 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 74 74 + >; 75 75 + }; 77 76 78 78 - pinctrl_i2c1: i2c1grp { 79 79 - fsl,pins = < 80 80 - MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed 81 81 - MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed 82 82 - >; 83 83 - }; 77 77 + pinctrl_i2c1: i2c1grp { 78 78 + fsl,pins = < 79 79 + MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed 80 80 + MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed 81 81 + >; 84 82 }; 85 83 }; 86 84

+95 -97

arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts

reviewed

··· 112 112 }; 113 113 114 114 &iomuxc { 115 115 - imx51-eukrea { 116 116 - pinctrl_audmux: audmuxgrp { 117 117 - fsl,pins = < 118 118 - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 119 119 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 120 120 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 121 121 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 122 122 - >; 123 123 - }; 115 115 + pinctrl_audmux: audmuxgrp { 116 116 + fsl,pins = < 117 117 + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 118 118 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 119 119 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 120 120 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 121 121 + >; 122 122 + }; 124 123 125 124 126 126 - pinctrl_can: cangrp { 127 127 - fsl,pins = < 128 128 - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ 129 129 - MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ 130 130 - >; 131 131 - }; 125 125 + pinctrl_can: cangrp { 126 126 + fsl,pins = < 127 127 + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ 128 128 + MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ 129 129 + >; 130 130 + }; 132 131 133 133 - pinctrl_ecspi1: ecspi1grp { 134 134 - fsl,pins = < 135 135 - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 136 136 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 137 137 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 138 138 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ 139 139 - >; 140 140 - }; 132 132 + pinctrl_ecspi1: ecspi1grp { 133 133 + fsl,pins = < 134 134 + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 135 135 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 136 136 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 137 137 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ 138 138 + >; 139 139 + }; 141 140 142 142 - pinctrl_esdhc1: esdhc1grp { 143 143 - fsl,pins = < 144 144 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 145 145 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 146 146 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 147 147 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 148 148 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 149 149 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 150 150 - >; 151 151 - }; 141 141 + pinctrl_esdhc1: esdhc1grp { 142 142 + fsl,pins = < 143 143 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 144 144 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 145 145 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 146 146 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 147 147 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 148 148 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 149 149 + >; 150 150 + }; 152 151 153 153 - pinctrl_uart1: uart1grp { 154 154 - fsl,pins = < 155 155 - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 156 156 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 157 157 - >; 158 158 - }; 152 152 + pinctrl_uart1: uart1grp { 153 153 + fsl,pins = < 154 154 + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 155 155 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 156 156 + >; 157 157 + }; 159 158 160 160 - pinctrl_uart3: uart3grp { 161 161 - fsl,pins = < 162 162 - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 163 163 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 164 164 - >; 165 165 - }; 159 159 + pinctrl_uart3: uart3grp { 160 160 + fsl,pins = < 161 161 + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 162 162 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 163 163 + >; 164 164 + }; 166 165 167 167 - pinctrl_uart3_rtscts: uart3rtsctsgrp { 168 168 - fsl,pins = < 169 169 - MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 170 170 - MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 171 171 - >; 172 172 - }; 166 166 + pinctrl_uart3_rtscts: uart3rtsctsgrp { 167 167 + fsl,pins = < 168 168 + MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 169 169 + MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 170 170 + >; 171 171 + }; 173 172 174 174 - pinctrl_backlight_1: backlightgrp-1 { 175 175 - fsl,pins = < 176 176 - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 177 177 - >; 178 178 - }; 173 173 + pinctrl_backlight_1: backlight1grp { 174 174 + fsl,pins = < 175 175 + MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 176 176 + >; 177 177 + }; 179 178 180 180 - pinctrl_esdhc1_cd: esdhc1_cd { 181 181 - fsl,pins = < 182 182 - MX51_PAD_GPIO1_0__GPIO1_0 0xd5 183 183 - >; 184 184 - }; 179 179 + pinctrl_esdhc1_cd: esdhc1_cdgrp { 180 180 + fsl,pins = < 181 181 + MX51_PAD_GPIO1_0__GPIO1_0 0xd5 182 182 + >; 183 183 + }; 185 184 186 186 - pinctrl_gpiokeys_1: gpiokeysgrp-1 { 187 187 - fsl,pins = < 188 188 - MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 189 189 - >; 190 190 - }; 185 185 + pinctrl_gpiokeys_1: gpiokeys1grp { 186 186 + fsl,pins = < 187 187 + MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 188 188 + >; 189 189 + }; 191 190 192 192 - pinctrl_gpioled: gpioledgrp-1 { 193 193 - fsl,pins = < 194 194 - MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 195 195 - >; 196 196 - }; 191 191 + pinctrl_gpioled: gpioled1grp { 192 192 + fsl,pins = < 193 193 + MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 194 194 + >; 195 195 + }; 197 196 198 198 - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { 199 199 - fsl,pins = < 200 200 - MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 201 201 - >; 202 202 - }; 197 197 + pinctrl_reg_lcd_3v3: reg_lcd_3v3grp { 198 198 + fsl,pins = < 199 199 + MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 200 200 + >; 201 201 + }; 203 202 204 204 - pinctrl_usbh1: usbh1grp { 205 205 - fsl,pins = < 206 206 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 207 207 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 208 208 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 209 209 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 210 210 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 211 211 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 212 212 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 213 213 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 214 214 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 215 215 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 216 216 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 217 217 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 218 218 - >; 219 219 - }; 203 203 + pinctrl_usbh1: usbh1grp { 204 204 + fsl,pins = < 205 205 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 206 206 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 207 207 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 208 208 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 209 209 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 210 210 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 211 211 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 212 212 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 213 213 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 214 214 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 215 215 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 216 216 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 217 217 + >; 218 218 + }; 220 219 221 221 - pinctrl_usbh1_vbus: usbh1-vbusgrp { 222 222 - fsl,pins = < 223 223 - MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 224 224 - >; 225 225 - }; 220 220 + pinctrl_usbh1_vbus: usbh1-vbusgrp { 221 221 + fsl,pins = < 222 222 + MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 223 223 + >; 226 224 }; 227 225 }; 228 226

+1 -1

arch/arm/boot/dts/nxp/imx/imx51.dtsi

reviewed

··· 399 399 clock-names = "ipg", "per"; 400 400 }; 401 401 402 402 - iomuxc: iomuxc@73fa8000 { 402 402 + iomuxc: pinctrl@73fa8000 { 403 403 compatible = "fsl,imx51-iomuxc"; 404 404 reg = <0x73fa8000 0x4000>; 405 405 };

+57 -59

arch/arm/boot/dts/nxp/imx/imx53-ard.dts

reviewed

··· 101 101 pinctrl-names = "default"; 102 102 pinctrl-0 = <&pinctrl_hog>; 103 103 104 104 - imx53-ard { 105 105 - pinctrl_hog: hoggrp { 106 106 - fsl,pins = < 107 107 - MX53_PAD_GPIO_1__GPIO1_1 0x80000000 108 108 - MX53_PAD_GPIO_9__GPIO1_9 0x80000000 109 109 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 110 110 - MX53_PAD_GPIO_10__GPIO4_0 0x80000000 111 111 - MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 112 112 - MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 113 113 - MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 114 114 - MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 115 115 - MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 116 116 - MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 117 117 - MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 118 118 - MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 119 119 - MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 120 120 - MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 121 121 - MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 122 122 - MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 123 123 - MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 124 124 - MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 125 125 - MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 126 126 - MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 127 127 - MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 128 128 - MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 129 129 - MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 130 130 - MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 131 131 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 132 132 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 133 133 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 134 134 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 135 135 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 136 136 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 137 137 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 138 138 - MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 139 139 - MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 140 140 - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 141 141 - >; 142 142 - }; 104 104 + pinctrl_hog: hoggrp { 105 105 + fsl,pins = < 106 106 + MX53_PAD_GPIO_1__GPIO1_1 0x80000000 107 107 + MX53_PAD_GPIO_9__GPIO1_9 0x80000000 108 108 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 109 109 + MX53_PAD_GPIO_10__GPIO4_0 0x80000000 110 110 + MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 111 111 + MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 112 112 + MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 113 113 + MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 114 114 + MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 115 115 + MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 116 116 + MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 117 117 + MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 118 118 + MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 119 119 + MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 120 120 + MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 121 121 + MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 122 122 + MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 123 123 + MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 124 124 + MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 125 125 + MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 126 126 + MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 127 127 + MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 128 128 + MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 129 129 + MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 130 130 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 131 131 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 132 132 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 133 133 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 134 134 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 135 135 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 136 136 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 137 137 + MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 138 138 + MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 139 139 + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 140 140 + >; 141 141 + }; 143 142 144 144 - pinctrl_esdhc1: esdhc1grp { 145 145 - fsl,pins = < 146 146 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 147 147 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 148 148 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 149 149 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 150 150 - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 151 151 - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 152 152 - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 153 153 - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 154 154 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 155 155 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 156 156 - >; 157 157 - }; 143 143 + pinctrl_esdhc1: esdhc1grp { 144 144 + fsl,pins = < 145 145 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 146 146 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 147 147 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 148 148 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 149 149 + MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 150 150 + MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 151 151 + MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 152 152 + MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 153 153 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 154 154 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 155 155 + >; 156 156 + }; 158 157 159 159 - pinctrl_uart1: uart1grp { 160 160 - fsl,pins = < 161 161 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 162 162 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 163 163 - >; 164 164 - }; 158 158 + pinctrl_uart1: uart1grp { 159 159 + fsl,pins = < 160 160 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 161 161 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 162 162 + >; 165 163 }; 166 164 }; 167 165

+30 -32

arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts

reviewed

··· 102 102 }; 103 103 104 104 &iomuxc { 105 105 - imx53-kp-ddc { 106 106 - pinctrl_disp: dispgrp { 107 107 - fsl,pins = < 108 108 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 109 109 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 110 110 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 111 111 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 112 112 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 113 113 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 114 114 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 115 115 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 116 116 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 117 117 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 118 118 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 119 119 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 120 120 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 121 121 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 122 122 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 123 123 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 124 124 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 125 125 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 126 126 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 127 127 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 128 128 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 129 129 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 130 130 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 131 131 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 132 132 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 133 133 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 134 134 - MX53_PAD_GPIO_1__PWM2_PWMO 0x4 135 135 - >; 136 136 - }; 105 105 + pinctrl_disp: dispgrp { 106 106 + fsl,pins = < 107 107 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 108 108 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 109 109 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 110 110 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 111 111 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 112 112 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 113 113 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 114 114 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 115 115 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 116 116 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 117 117 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 118 118 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 119 119 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 120 120 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 121 121 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 122 122 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 123 123 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 124 124 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 125 125 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 126 126 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 127 127 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 128 128 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 129 129 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 130 130 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 131 131 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 132 132 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 133 133 + MX53_PAD_GPIO_1__PWM2_PWMO 0x4 134 134 + >; 137 135 }; 138 136 }; 139 137

+44 -46

arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi

reviewed

··· 98 98 pinctrl-names = "default"; 99 99 pinctrl-0 = <&pinctrl_kp_common>; 100 100 101 101 - imx53-kp-common { 102 102 - pinctrl_buzzer: buzzergrp { 103 103 - fsl,pins = < 104 104 - MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 105 105 - >; 106 106 - }; 101 101 + pinctrl_buzzer: buzzergrp { 102 102 + fsl,pins = < 103 103 + MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 104 104 + >; 105 105 + }; 107 106 108 108 - pinctrl_gpiobuttons: gpiobuttonsgrp { 109 109 - fsl,pins = < 110 110 - MX53_PAD_EIM_RW__GPIO2_26 0x1e4 111 111 - MX53_PAD_EIM_D22__GPIO3_22 0x1e4 112 112 - >; 113 113 - }; 107 107 + pinctrl_gpiobuttons: gpiobuttonsgrp { 108 108 + fsl,pins = < 109 109 + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 110 110 + MX53_PAD_EIM_D22__GPIO3_22 0x1e4 111 111 + >; 112 112 + }; 114 113 115 115 - pinctrl_kp_common: kpcommongrp { 116 116 - fsl,pins = < 117 117 - MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 118 118 - MX53_PAD_GPIO_19__GPIO4_5 0x1e4 119 119 - MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 120 120 - MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 121 121 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 122 122 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 123 123 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 124 124 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 125 125 - MX53_PAD_EIM_D18__GPIO3_18 0x1e4 126 126 - MX53_PAD_EIM_D21__GPIO3_21 0x1e4 127 127 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 128 128 - MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 129 129 - MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 130 130 - MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 131 131 - MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 132 132 - MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 133 133 - MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 134 134 - >; 135 135 - }; 114 114 + pinctrl_kp_common: kpcommongrp { 115 115 + fsl,pins = < 116 116 + MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 117 117 + MX53_PAD_GPIO_19__GPIO4_5 0x1e4 118 118 + MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 119 119 + MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 120 120 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 121 121 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 122 122 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 123 123 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 124 124 + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 125 125 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 126 126 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 127 127 + MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 128 128 + MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 129 129 + MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 130 130 + MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 131 131 + MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 132 132 + MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 133 133 + >; 134 134 + }; 136 135 137 137 - pinctrl_leds: ledgrp { 138 138 - fsl,pins = < 139 139 - MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 140 140 - MX53_PAD_EIM_D28__GPIO3_28 0x1d4 141 141 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 142 142 - >; 143 143 - }; 136 136 + pinctrl_leds: ledgrp { 137 137 + fsl,pins = < 138 138 + MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 139 139 + MX53_PAD_EIM_D28__GPIO3_28 0x1d4 140 140 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 141 141 + >; 142 142 + }; 144 143 145 145 - pinctrl_uart4: uart4grp { 146 146 - fsl,pins = < 147 147 - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 148 148 - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 149 149 - >; 150 150 - }; 144 144 + pinctrl_uart4: uart4grp { 145 145 + fsl,pins = < 146 146 + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 147 147 + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 148 148 + >; 151 149 }; 152 150 }; 153 151

+31 -33

arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi

reviewed

··· 77 77 pinctrl-names = "default"; 78 78 pinctrl-0 = <&pinctrl_hog>; 79 79 80 80 - imx53-m53evk { 81 81 - pinctrl_hog: hoggrp { 82 82 - fsl,pins = < 83 83 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 84 84 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 85 85 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 86 86 - >; 87 87 - }; 80 80 + pinctrl_hog: hoggrp { 81 81 + fsl,pins = < 82 82 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 83 83 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 84 84 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 85 85 + >; 86 86 + }; 88 87 89 89 - pinctrl_i2c2: i2c2grp { 90 90 - fsl,pins = < 91 91 - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 92 92 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 93 93 - >; 94 94 - }; 88 88 + pinctrl_i2c2: i2c2grp { 89 89 + fsl,pins = < 90 90 + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 91 91 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 92 92 + >; 93 93 + }; 95 94 96 96 - pinctrl_nand: nandgrp { 97 97 - fsl,pins = < 98 98 - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 99 99 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 100 100 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 101 101 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 102 102 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 103 103 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 104 104 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 105 105 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 106 106 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 107 107 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 108 108 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 109 109 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 110 110 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 111 111 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 112 112 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 113 113 - >; 114 114 - }; 95 95 + pinctrl_nand: nandgrp { 96 96 + fsl,pins = < 97 97 + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 98 98 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 99 99 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 100 100 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 101 101 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 102 102 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 103 103 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 104 104 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 105 105 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 106 106 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 107 107 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 108 108 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 109 109 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 110 110 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 111 111 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 112 112 + >; 115 113 }; 116 114 }; 117 115

+133 -135

arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts

reviewed

··· 156 156 pinctrl-names = "default"; 157 157 pinctrl-0 = <&pinctrl_hog>; 158 158 159 159 - imx53-m53evk { 160 160 - pinctrl_usb: usbgrp { 161 161 - fsl,pins = < 162 162 - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 163 163 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 164 164 - >; 165 165 - }; 159 159 + pinctrl_usb: usbgrp { 160 160 + fsl,pins = < 161 161 + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 162 162 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 163 163 + >; 164 164 + }; 166 165 167 167 - pinctrl_usbotg: usbotggrp { 168 168 - fsl,pins = < 169 169 - MX53_PAD_GPIO_4__GPIO1_4 0x000b0 170 170 - >; 171 171 - }; 166 166 + pinctrl_usbotg: usbotggrp { 167 167 + fsl,pins = < 168 168 + MX53_PAD_GPIO_4__GPIO1_4 0x000b0 169 169 + >; 170 170 + }; 172 171 173 173 - led_pin_gpio: led_gpio { 174 174 - fsl,pins = < 175 175 - MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 176 176 - MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 177 177 - >; 178 178 - }; 172 172 + led_pin_gpio: ledgpiogrp { 173 173 + fsl,pins = < 174 174 + MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 175 175 + MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 176 176 + >; 177 177 + }; 179 178 180 180 - pinctrl_audmux: audmuxgrp { 181 181 - fsl,pins = < 182 182 - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 183 183 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 184 184 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 185 185 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 186 186 - >; 187 187 - }; 179 179 + pinctrl_audmux: audmuxgrp { 180 180 + fsl,pins = < 181 181 + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 182 182 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 183 183 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 184 184 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 185 185 + >; 186 186 + }; 188 187 189 189 - pinctrl_can1: can1grp { 190 190 - fsl,pins = < 191 191 - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 192 192 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 193 193 - >; 194 194 - }; 188 188 + pinctrl_can1: can1grp { 189 189 + fsl,pins = < 190 190 + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 191 191 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 192 192 + >; 193 193 + }; 195 194 196 196 - pinctrl_can2: can2grp { 197 197 - fsl,pins = < 198 198 - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 199 199 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 200 200 - >; 201 201 - }; 195 195 + pinctrl_can2: can2grp { 196 196 + fsl,pins = < 197 197 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 198 198 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 199 199 + >; 200 200 + }; 202 201 203 203 - pinctrl_esdhc1: esdhc1grp { 204 204 - fsl,pins = < 205 205 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 206 206 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 207 207 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 208 208 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 209 209 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 210 210 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 211 211 - >; 212 212 - }; 202 202 + pinctrl_esdhc1: esdhc1grp { 203 203 + fsl,pins = < 204 204 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 205 205 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 206 206 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 207 207 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 208 208 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 209 209 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 210 210 + >; 211 211 + }; 213 212 214 214 - pinctrl_fec: fecgrp { 215 215 - fsl,pins = < 216 216 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 217 217 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 218 218 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 219 219 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 220 220 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 221 221 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 222 222 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 223 223 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 224 224 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 225 225 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 226 226 - >; 227 227 - }; 213 213 + pinctrl_fec: fecgrp { 214 214 + fsl,pins = < 215 215 + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 216 216 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 217 217 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 218 218 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 219 219 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 220 220 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 221 221 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 222 222 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 223 223 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 224 224 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 225 225 + >; 226 226 + }; 228 227 229 229 - pinctrl_i2c1: i2c1grp { 230 230 - fsl,pins = < 231 231 - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 232 232 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 233 233 - >; 234 234 - }; 228 228 + pinctrl_i2c1: i2c1grp { 229 229 + fsl,pins = < 230 230 + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 231 231 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 232 232 + >; 233 233 + }; 235 234 236 236 - pinctrl_i2c3: i2c3grp { 237 237 - fsl,pins = < 238 238 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 239 239 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 240 240 - >; 241 241 - }; 235 235 + pinctrl_i2c3: i2c3grp { 236 236 + fsl,pins = < 237 237 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 238 238 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 239 239 + >; 240 240 + }; 242 241 243 243 - pinctrl_ipu_disp1: ipudisp1grp { 244 244 - fsl,pins = < 245 245 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 246 246 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 247 247 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 248 248 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 249 249 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 250 250 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 251 251 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 252 252 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 253 253 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 254 254 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 255 255 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 256 256 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 257 257 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 258 258 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 259 259 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 260 260 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 261 261 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 262 262 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 263 263 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 264 264 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 265 265 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 266 266 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 267 267 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 268 268 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 269 269 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 270 270 - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 271 271 - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 272 272 - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 273 273 - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 274 274 - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 275 275 - MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 276 276 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 277 277 - >; 278 278 - }; 242 242 + pinctrl_ipu_disp1: ipudisp1grp { 243 243 + fsl,pins = < 244 244 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 245 245 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 246 246 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 247 247 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 248 248 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 249 249 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 250 250 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 251 251 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 252 252 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 253 253 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 254 254 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 255 255 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 256 256 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 257 257 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 258 258 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 259 259 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 260 260 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 261 261 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 262 262 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 263 263 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 264 264 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 265 265 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 266 266 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 267 267 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 268 268 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 269 269 + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 270 270 + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 271 271 + MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 272 272 + MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 273 273 + MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 274 274 + MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 275 275 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 276 276 + >; 277 277 + }; 279 278 280 280 - pinctrl_pwm1: pwm1grp { 281 281 - fsl,pins = < 282 282 - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 283 283 - >; 284 284 - }; 279 279 + pinctrl_pwm1: pwm1grp { 280 280 + fsl,pins = < 281 281 + MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 282 282 + >; 283 283 + }; 285 284 286 286 - pinctrl_uart1: uart1grp { 287 287 - fsl,pins = < 288 288 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 289 289 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 290 290 - >; 291 291 - }; 285 285 + pinctrl_uart1: uart1grp { 286 286 + fsl,pins = < 287 287 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 288 288 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 289 289 + >; 290 290 + }; 292 291 293 293 - pinctrl_uart2: uart2grp { 294 294 - fsl,pins = < 295 295 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 296 296 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 297 297 - >; 298 298 - }; 292 292 + pinctrl_uart2: uart2grp { 293 293 + fsl,pins = < 294 294 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 295 295 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 296 296 + >; 297 297 + }; 299 298 300 300 - pinctrl_uart3: uart3grp { 301 301 - fsl,pins = < 302 302 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 303 303 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 304 304 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 305 305 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 306 306 - >; 307 307 - }; 299 299 + pinctrl_uart3: uart3grp { 300 300 + fsl,pins = < 301 301 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 302 302 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 303 303 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 304 304 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 305 305 + >; 308 306 }; 309 307 }; 310 308

+159 -161

arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts

reviewed

··· 278 278 pinctrl-names = "default"; 279 279 pinctrl-0 = <&pinctrl_hog>; 280 280 281 281 - imx53-m53evk { 282 282 - hoggrp { 283 283 - fsl,pins = < 284 284 - MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 285 285 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 286 286 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 287 287 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 288 288 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 289 289 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 290 290 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 291 291 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 292 292 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 293 293 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 294 294 - MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 295 295 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 296 296 - MX53_PAD_EIM_D25__GPIO3_25 0x1e4 297 297 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 298 298 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 299 299 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 300 300 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 301 301 - MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 302 302 - >; 303 303 - }; 281 281 + hoggrp { 282 282 + fsl,pins = < 283 283 + MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 284 284 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 285 285 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 286 286 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 287 287 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 288 288 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 289 289 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 290 290 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 291 291 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 292 292 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 293 293 + MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 294 294 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 295 295 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 296 296 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 297 297 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 298 298 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 299 299 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 300 300 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 301 301 + >; 302 302 + }; 304 303 305 305 - pinctrl_led: ledgrp { 306 306 - fsl,pins = < 307 307 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 308 308 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 309 309 - >; 310 310 - }; 304 304 + pinctrl_led: ledgrp { 305 305 + fsl,pins = < 306 306 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 307 307 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 308 308 + >; 309 309 + }; 311 310 312 312 - pinctrl_beeper: beepergrp { 313 313 - fsl,pins = < 314 314 - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 315 315 - >; 316 316 - }; 311 311 + pinctrl_beeper: beepergrp { 312 312 + fsl,pins = < 313 313 + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 314 314 + >; 315 315 + }; 317 316 318 318 - pinctrl_can1: can1grp { 319 319 - fsl,pins = < 320 320 - MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 321 321 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 322 322 - >; 323 323 - }; 317 317 + pinctrl_can1: can1grp { 318 318 + fsl,pins = < 319 319 + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 320 320 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 321 321 + >; 322 322 + }; 324 323 325 325 - pinctrl_can2: can2grp { 326 326 - fsl,pins = < 327 327 - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 328 328 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 329 329 - >; 330 330 - }; 324 324 + pinctrl_can2: can2grp { 325 325 + fsl,pins = < 326 326 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 327 327 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 328 328 + >; 329 329 + }; 331 330 332 332 - pinctrl_display_gpio: display-gpiogrp { 333 333 - fsl,pins = < 334 334 - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ 335 335 - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ 336 336 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ 331 331 + pinctrl_display_gpio: display-gpiogrp { 332 332 + fsl,pins = < 333 333 + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ 334 334 + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ 335 335 + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ 337 336 338 338 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ 339 339 - >; 340 340 - }; 337 337 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ 338 338 + >; 339 339 + }; 341 340 342 342 - pinctrl_edt_ft5x06: edt-ft5x06grp { 343 343 - fsl,pins = < 344 344 - MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ 345 345 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ 346 346 - MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ 347 347 - >; 348 348 - }; 341 341 + pinctrl_edt_ft5x06: edt-ft5x06grp { 342 342 + fsl,pins = < 343 343 + MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ 344 344 + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ 345 345 + MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ 346 346 + >; 347 347 + }; 349 348 350 350 - pinctrl_ecspi2: ecspi2grp { 351 351 - fsl,pins = < 352 352 - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 353 353 - MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 354 354 - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 355 355 - MX53_PAD_EIM_RW__GPIO2_26 0xe4 356 356 - MX53_PAD_EIM_LBA__GPIO2_27 0xe4 357 357 - >; 358 358 - }; 349 349 + pinctrl_ecspi2: ecspi2grp { 350 350 + fsl,pins = < 351 351 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 352 352 + MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 353 353 + MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 354 354 + MX53_PAD_EIM_RW__GPIO2_26 0xe4 355 355 + MX53_PAD_EIM_LBA__GPIO2_27 0xe4 356 356 + >; 357 357 + }; 359 358 360 360 - pinctrl_esdhc1: esdhc1grp { 361 361 - fsl,pins = < 362 362 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 363 363 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 364 364 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 365 365 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 366 366 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 367 367 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 368 368 - MX53_PAD_GPIO_1__GPIO1_1 0x1c4 369 369 - MX53_PAD_GPIO_9__GPIO1_9 0x1e4 370 370 - >; 371 371 - }; 359 359 + pinctrl_esdhc1: esdhc1grp { 360 360 + fsl,pins = < 361 361 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 362 362 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 363 363 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 364 364 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 365 365 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 366 366 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 367 367 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 368 368 + MX53_PAD_GPIO_9__GPIO1_9 0x1e4 369 369 + >; 370 370 + }; 372 371 373 373 - pinctrl_fec: fecgrp { 374 374 - fsl,pins = < 375 375 - MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 376 376 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 377 377 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 378 378 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 379 379 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 380 380 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 381 381 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 382 382 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 383 383 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 384 384 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 385 385 - MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 386 386 - MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 387 387 - >; 388 388 - }; 372 372 + pinctrl_fec: fecgrp { 373 373 + fsl,pins = < 374 374 + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 375 375 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 376 376 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 377 377 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 378 378 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 379 379 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 380 380 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 381 381 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 382 382 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 383 383 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 384 384 + MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 385 385 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 386 386 + >; 387 387 + }; 389 388 390 390 - pinctrl_i2c1: i2c1grp { 391 391 - fsl,pins = < 392 392 - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 393 393 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 394 394 - >; 395 395 - }; 389 389 + pinctrl_i2c1: i2c1grp { 390 390 + fsl,pins = < 391 391 + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 392 392 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 393 393 + >; 394 394 + }; 396 395 397 397 - pinctrl_i2c3: i2c3grp { 398 398 - fsl,pins = < 399 399 - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 400 400 - MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 401 401 - >; 402 402 - }; 396 396 + pinctrl_i2c3: i2c3grp { 397 397 + fsl,pins = < 398 398 + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 399 399 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 400 400 + >; 401 401 + }; 403 402 404 404 - pinctrl_lvds0: lvds0grp { 405 405 - /* LVDS pins only have pin mux configuration */ 406 406 - fsl,pins = < 407 407 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 408 408 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 409 409 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 410 410 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 411 411 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 412 412 - >; 413 413 - }; 403 403 + pinctrl_lvds0: lvds0grp { 404 404 + /* LVDS pins only have pin mux configuration */ 405 405 + fsl,pins = < 406 406 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 407 407 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 408 408 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 409 409 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 410 410 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 411 411 + >; 412 412 + }; 414 413 415 415 - pinctrl_power_button: powerbutgrp { 416 416 - fsl,pins = < 417 417 - MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 418 418 - >; 419 419 - }; 414 414 + pinctrl_power_button: powerbutgrp { 415 415 + fsl,pins = < 416 416 + MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 417 417 + >; 418 418 + }; 420 419 421 421 - pinctrl_power_out: poweroutgrp { 422 422 - fsl,pins = < 423 423 - MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 424 424 - >; 425 425 - }; 420 420 + pinctrl_power_out: poweroutgrp { 421 421 + fsl,pins = < 422 422 + MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 423 423 + >; 424 424 + }; 426 425 427 427 - pinctrl_uart1: uart1grp { 428 428 - fsl,pins = < 429 429 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 430 430 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 431 431 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 432 432 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 433 433 - >; 434 434 - }; 426 426 + pinctrl_uart1: uart1grp { 427 427 + fsl,pins = < 428 428 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 429 429 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 430 430 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 431 431 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 432 432 + >; 433 433 + }; 435 434 436 436 - pinctrl_uart2: uart2grp { 437 437 - fsl,pins = < 438 438 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 439 439 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 440 440 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 441 441 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 442 442 - >; 443 443 - }; 435 435 + pinctrl_uart2: uart2grp { 436 436 + fsl,pins = < 437 437 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 438 438 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 439 439 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 440 440 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 441 441 + >; 442 442 + }; 444 443 445 445 - pinctrl_uart3: uart3grp { 446 446 - fsl,pins = < 447 447 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 448 448 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 449 449 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 450 450 - >; 451 451 - }; 444 444 + pinctrl_uart3: uart3grp { 445 445 + fsl,pins = < 446 446 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 447 447 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 448 448 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 449 449 + >; 450 450 + }; 452 451 453 453 - pinctrl_usb: usbgrp { 454 454 - fsl,pins = < 455 455 - MX53_PAD_GPIO_2__GPIO1_2 0x1c4 456 456 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 457 457 - MX53_PAD_GPIO_4__GPIO1_4 0x1c4 458 458 - MX53_PAD_GPIO_18__GPIO7_13 0x1c4 459 459 - >; 460 460 - }; 452 452 + pinctrl_usb: usbgrp { 453 453 + fsl,pins = < 454 454 + MX53_PAD_GPIO_2__GPIO1_2 0x1c4 455 455 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 456 456 + MX53_PAD_GPIO_4__GPIO1_4 0x1c4 457 457 + MX53_PAD_GPIO_18__GPIO7_13 0x1c4 458 458 + >; 461 459 }; 462 460 }; 463 461

+55 -61

arch/arm/boot/dts/nxp/imx/imx53-mba53.dts

reviewed

··· 75 75 }; 76 76 77 77 &iomuxc { 78 78 - lvds1 { 79 79 - pinctrl_lvds1_1: lvds1-grp1 { 80 80 - fsl,pins = < 81 81 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 82 82 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 83 83 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 84 84 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 85 85 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 86 86 - >; 87 87 - }; 88 88 - 89 89 - pinctrl_lvds1_2: lvds1-grp2 { 90 90 - fsl,pins = < 91 91 - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 92 92 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 93 93 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 94 94 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 95 95 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 96 96 - >; 97 97 - }; 78 78 + pinctrl_lvds1_1: lvds1-1-grp { 79 79 + fsl,pins = < 80 80 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 81 81 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 82 82 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 83 83 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 84 84 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 85 85 + >; 98 86 }; 99 87 100 100 - disp1 { 101 101 - pinctrl_disp1_1: disp1-grp1 { 102 102 - fsl,pins = < 103 103 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ 104 104 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ 105 105 - MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ 106 106 - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ 107 107 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 108 108 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 109 109 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 110 110 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 111 111 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 112 112 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 113 113 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 114 114 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 115 115 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 116 116 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 117 117 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 118 118 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 119 119 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 120 120 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 121 121 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 122 122 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 123 123 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 124 124 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 125 125 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 126 126 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 127 127 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 128 128 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 129 129 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 130 130 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 131 131 - >; 132 132 - }; 88 88 + pinctrl_lvds1_2: lvds1-2-grp { 89 89 + fsl,pins = < 90 90 + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 91 91 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 92 92 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 93 93 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 94 94 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 95 95 + >; 133 96 }; 134 97 135 135 - tve { 136 136 - pinctrl_vga_sync_1: vgasync-grp1 { 137 137 - fsl,pins = < 138 138 - /* VGA_VSYNC, HSYNC with max drive strength */ 139 139 - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 140 140 - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 141 141 - >; 142 142 - }; 98 98 + pinctrl_disp1_1: disp1-1-grp { 99 99 + fsl,pins = < 100 100 + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ 101 101 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ 102 102 + MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ 103 103 + MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ 104 104 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 105 105 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 106 106 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 107 107 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 108 108 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 109 109 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 110 110 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 111 111 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 112 112 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 113 113 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 114 114 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 115 115 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 116 116 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 117 117 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 118 118 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 119 119 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 120 120 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 121 121 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 122 122 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 123 123 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 124 124 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 125 125 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 126 126 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 127 127 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 128 128 + >; 129 129 + }; 130 130 + 131 131 + pinctrl_vga_sync_1: vgasync-1-grp { 132 132 + fsl,pins = < 133 133 + /* VGA_VSYNC, HSYNC with max drive strength */ 134 134 + MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 135 135 + MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 136 136 + >; 143 137 }; 144 138 }; 145 139

+136 -138

arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi

reviewed

··· 170 170 pinctrl-names = "default"; 171 171 pinctrl-0 = <&pinctrl_hog>; 172 172 173 173 - imx53-qsb { 174 174 - pinctrl_hog: hoggrp { 175 175 - fsl,pins = < 176 176 - MX53_PAD_GPIO_8__GPIO1_8 0x80000000 177 177 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 178 178 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 179 179 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 180 180 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 181 181 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 182 182 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 183 183 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 184 184 - >; 185 185 - }; 173 173 + pinctrl_hog: hoggrp { 174 174 + fsl,pins = < 175 175 + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 176 176 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 177 177 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 178 178 + MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 179 179 + MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 180 180 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 181 181 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 182 182 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 183 183 + >; 184 184 + }; 186 185 187 187 - led_pin_gpio7_7: led_gpio7_7 { 188 188 - fsl,pins = < 189 189 - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 190 190 - >; 191 191 - }; 186 186 + led_pin_gpio7_7: led_gpio7-7-grp { 187 187 + fsl,pins = < 188 188 + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 189 189 + >; 190 190 + }; 192 191 193 193 - pinctrl_audmux: audmuxgrp { 194 194 - fsl,pins = < 195 195 - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 196 196 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 197 197 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 198 198 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 199 199 - >; 200 200 - }; 192 192 + pinctrl_audmux: audmuxgrp { 193 193 + fsl,pins = < 194 194 + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 195 195 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 196 196 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 197 197 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 198 198 + >; 199 199 + }; 201 200 202 202 - pinctrl_codec: codecgrp { 203 203 - fsl,pins = < 204 204 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 205 205 - >; 206 206 - }; 201 201 + pinctrl_codec: codecgrp { 202 202 + fsl,pins = < 203 203 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 204 204 + >; 205 205 + }; 207 206 208 208 - pinctrl_display_power: displaypowergrp { 209 209 - fsl,pins = < 210 210 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 211 211 - >; 212 212 - }; 207 207 + pinctrl_display_power: displaypowergrp { 208 208 + fsl,pins = < 209 209 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 210 210 + >; 211 211 + }; 213 212 214 214 - pinctrl_esdhc1: esdhc1grp { 215 215 - fsl,pins = < 216 216 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 217 217 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 218 218 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 219 219 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 220 220 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 221 221 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 222 222 - MX53_PAD_EIM_DA13__GPIO3_13 0xe4 223 223 - >; 224 224 - }; 213 213 + pinctrl_esdhc1: esdhc1grp { 214 214 + fsl,pins = < 215 215 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 216 216 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 217 217 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 218 218 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 219 219 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 220 220 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 221 221 + MX53_PAD_EIM_DA13__GPIO3_13 0xe4 222 222 + >; 223 223 + }; 225 224 226 226 - pinctrl_esdhc3: esdhc3grp { 227 227 - fsl,pins = < 228 228 - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 229 229 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 230 230 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 231 231 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 232 232 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 233 233 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 234 234 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 235 235 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 236 236 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 237 237 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 238 238 - >; 239 239 - }; 225 225 + pinctrl_esdhc3: esdhc3grp { 226 226 + fsl,pins = < 227 227 + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 228 228 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 229 229 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 230 230 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 231 231 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 232 232 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 233 233 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 234 234 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 235 235 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 236 236 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 237 237 + >; 238 238 + }; 240 239 241 241 - pinctrl_fec: fecgrp { 242 242 - fsl,pins = < 243 243 - MX53_PAD_FEC_MDC__FEC_MDC 0x4 244 244 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 245 245 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 246 246 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 247 247 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 248 248 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 249 249 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 250 250 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 251 251 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 252 252 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 253 253 - >; 254 254 - }; 240 240 + pinctrl_fec: fecgrp { 241 241 + fsl,pins = < 242 242 + MX53_PAD_FEC_MDC__FEC_MDC 0x4 243 243 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 244 244 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 245 245 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 246 246 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 247 247 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 248 248 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 249 249 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 250 250 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 251 251 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 252 252 + >; 253 253 + }; 255 254 256 256 - /* open drain */ 257 257 - pinctrl_i2c1: i2c1grp { 258 258 - fsl,pins = < 259 259 - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec 260 260 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 261 261 - >; 262 262 - }; 255 255 + /* open drain */ 256 256 + pinctrl_i2c1: i2c1grp { 257 257 + fsl,pins = < 258 258 + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec 259 259 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 260 260 + >; 261 261 + }; 263 262 264 264 - pinctrl_i2c2: i2c2grp { 265 265 - fsl,pins = < 266 266 - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 267 267 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 268 268 - >; 269 269 - }; 263 263 + pinctrl_i2c2: i2c2grp { 264 264 + fsl,pins = < 265 265 + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 266 266 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 267 267 + >; 268 268 + }; 270 269 271 271 - pinctrl_ipu_disp0: ipudisp0grp { 272 272 - fsl,pins = < 273 273 - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 274 274 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 275 275 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 276 276 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 277 277 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 278 278 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 279 279 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 280 280 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 281 281 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 282 282 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 283 283 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 284 284 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 285 285 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 286 286 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 287 287 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 288 288 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 289 289 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 290 290 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 291 291 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 292 292 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 293 293 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 294 294 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 295 295 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 296 296 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 297 297 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 298 298 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 299 299 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 300 300 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 301 301 - >; 302 302 - }; 270 270 + pinctrl_ipu_disp0: ipudisp0grp { 271 271 + fsl,pins = < 272 272 + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 273 273 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 274 274 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 275 275 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 276 276 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 277 277 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 278 278 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 279 279 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 280 280 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 281 281 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 282 282 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 283 283 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 284 284 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 285 285 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 286 286 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 287 287 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 288 288 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 289 289 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 290 290 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 291 291 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 292 292 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 293 293 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 294 294 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 295 295 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 296 296 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 297 297 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 298 298 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 299 299 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 300 300 + >; 301 301 + }; 303 302 304 304 - pinctrl_pwm2: pwm2grp { 305 305 - fsl,pins = < 306 306 - MX53_PAD_GPIO_1__PWM2_PWMO 0x5 307 307 - >; 308 308 - }; 303 303 + pinctrl_pwm2: pwm2grp { 304 304 + fsl,pins = < 305 305 + MX53_PAD_GPIO_1__PWM2_PWMO 0x5 306 306 + >; 307 307 + }; 309 308 310 310 - pinctrl_vga_sync: vgasync-grp { 311 311 - fsl,pins = < 312 312 - /* VGA_HSYNC, VSYNC with max drive strength */ 313 313 - MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 314 314 - MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 315 315 - >; 316 316 - }; 309 309 + pinctrl_vga_sync: vgasync-grp { 310 310 + fsl,pins = < 311 311 + /* VGA_HSYNC, VSYNC with max drive strength */ 312 312 + MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 313 313 + MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 314 314 + >; 315 315 + }; 317 316 318 318 - pinctrl_uart1: uart1grp { 319 319 - fsl,pins = < 320 320 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 321 321 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 322 322 - >; 323 323 - }; 317 317 + pinctrl_uart1: uart1grp { 318 318 + fsl,pins = < 319 319 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 320 320 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 321 321 + >; 324 322 }; 325 323 }; 326 324

+4 -6

arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts

reviewed

··· 13 13 }; 14 14 15 15 &iomuxc { 16 16 - imx53-qsrb { 17 17 - pinctrl_pmic: pmicgrp { 18 18 - fsl,pins = < 19 19 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ 20 20 - >; 21 21 - }; 16 16 + pinctrl_pmic: pmicgrp { 17 17 + fsl,pins = < 18 18 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ 19 19 + >; 22 20 }; 23 21 }; 24 22

+120 -122

arch/arm/boot/dts/nxp/imx/imx53-smd.dts

reviewed

··· 98 98 pinctrl-names = "default"; 99 99 pinctrl-0 = <&pinctrl_hog>; 100 100 101 101 - imx53-smd { 102 102 - pinctrl_hog: hoggrp { 103 103 - fsl,pins = < 104 104 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 105 105 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 106 106 - MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 107 107 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 108 108 - MX53_PAD_EIM_D19__GPIO3_19 0x80000000 109 109 - MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 110 110 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 111 111 - >; 112 112 - }; 101 101 + pinctrl_hog: hoggrp { 102 102 + fsl,pins = < 103 103 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 104 104 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 105 105 + MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 106 106 + MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 107 107 + MX53_PAD_EIM_D19__GPIO3_19 0x80000000 108 108 + MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 109 109 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 110 110 + >; 111 111 + }; 113 112 114 114 - pinctrl_ecspi1: ecspi1grp { 115 115 - fsl,pins = < 116 116 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 117 117 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 118 118 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 119 119 - >; 120 120 - }; 113 113 + pinctrl_ecspi1: ecspi1grp { 114 114 + fsl,pins = < 115 115 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 116 116 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 117 117 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 118 118 + >; 119 119 + }; 121 120 122 122 - pinctrl_esdhc1: esdhc1grp { 123 123 - fsl,pins = < 124 124 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 125 125 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 126 126 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 127 127 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 128 128 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 129 129 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 130 130 - >; 131 131 - }; 121 121 + pinctrl_esdhc1: esdhc1grp { 122 122 + fsl,pins = < 123 123 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 124 124 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 125 125 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 126 126 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 127 127 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 128 128 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 129 129 + >; 130 130 + }; 132 131 133 133 - pinctrl_esdhc2: esdhc2grp { 134 134 - fsl,pins = < 135 135 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 136 136 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 137 137 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 138 138 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 139 139 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 140 140 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 141 141 - >; 142 142 - }; 132 132 + pinctrl_esdhc2: esdhc2grp { 133 133 + fsl,pins = < 134 134 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 135 135 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 136 136 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 137 137 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 138 138 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 139 139 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 140 140 + >; 141 141 + }; 143 142 144 144 - pinctrl_esdhc3: esdhc3grp { 145 145 - fsl,pins = < 146 146 - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 147 147 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 148 148 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 149 149 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 150 150 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 151 151 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 152 152 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 153 153 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 154 154 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 155 155 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 156 156 - >; 157 157 - }; 143 143 + pinctrl_esdhc3: esdhc3grp { 144 144 + fsl,pins = < 145 145 + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 146 146 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 147 147 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 148 148 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 149 149 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 150 150 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 151 151 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 152 152 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 153 153 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 154 154 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 155 155 + >; 156 156 + }; 158 157 159 159 - pinctrl_fec: fecgrp { 160 160 - fsl,pins = < 161 161 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 162 162 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 163 163 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 164 164 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 165 165 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 166 166 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 167 167 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 168 168 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 169 169 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 170 170 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 171 171 - >; 172 172 - }; 158 158 + pinctrl_fec: fecgrp { 159 159 + fsl,pins = < 160 160 + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 161 161 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 162 162 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 163 163 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 164 164 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 165 165 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 166 166 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 167 167 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 168 168 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 169 169 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 170 170 + >; 171 171 + }; 173 172 174 174 - pinctrl_i2c1: i2c1grp { 175 175 - fsl,pins = < 176 176 - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 177 177 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 178 178 - >; 179 179 - }; 173 173 + pinctrl_i2c1: i2c1grp { 174 174 + fsl,pins = < 175 175 + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 176 176 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 177 177 + >; 178 178 + }; 180 179 181 181 - pinctrl_i2c2: i2c2grp { 182 182 - fsl,pins = < 183 183 - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 184 184 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 185 185 - >; 186 186 - }; 180 180 + pinctrl_i2c2: i2c2grp { 181 181 + fsl,pins = < 182 182 + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 183 183 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 184 184 + >; 185 185 + }; 187 186 188 188 - pinctrl_ipu_csi0: ipucsi0grp { 189 189 - fsl,pins = < 190 190 - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 191 191 - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 192 192 - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 193 193 - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 194 194 - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 195 195 - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 196 196 - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 197 197 - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 198 198 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 199 199 - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 200 200 - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 201 201 - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 202 202 - >; 203 203 - }; 187 187 + pinctrl_ipu_csi0: ipucsi0grp { 188 188 + fsl,pins = < 189 189 + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 190 190 + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 191 191 + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 192 192 + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 193 193 + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 194 194 + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 195 195 + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 196 196 + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 197 197 + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 198 198 + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 199 199 + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 200 200 + MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 201 201 + >; 202 202 + }; 204 203 205 205 - pinctrl_ov5642: ov5642grp { 206 206 - fsl,pins = < 207 207 - MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 208 208 - MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 209 209 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 210 210 - >; 211 211 - }; 204 204 + pinctrl_ov5642: ov5642grp { 205 205 + fsl,pins = < 206 206 + MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 207 207 + MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 208 208 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 209 209 + >; 210 210 + }; 212 211 213 213 - pinctrl_uart1: uart1grp { 214 214 - fsl,pins = < 215 215 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 216 216 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 217 217 - >; 218 218 - }; 212 212 + pinctrl_uart1: uart1grp { 213 213 + fsl,pins = < 214 214 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 215 215 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 216 216 + >; 217 217 + }; 219 218 220 220 - pinctrl_uart2: uart2grp { 221 221 - fsl,pins = < 222 222 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 223 223 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 224 224 - >; 225 225 - }; 219 219 + pinctrl_uart2: uart2grp { 220 220 + fsl,pins = < 221 221 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 222 222 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 223 223 + >; 224 224 + }; 226 225 227 227 - pinctrl_uart3: uart3grp { 228 228 - fsl,pins = < 229 229 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 230 230 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 231 231 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 232 232 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 233 233 - >; 234 234 - }; 226 226 + pinctrl_uart3: uart3grp { 227 227 + fsl,pins = < 228 228 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 229 229 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 230 230 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 231 231 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 232 232 + >; 235 233 }; 236 234 }; 237 235

+122 -124

arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi

reviewed

··· 61 61 pinctrl-names = "default"; 62 62 pinctrl-0 = <&pinctrl_hog>; 63 63 64 64 - imx53-tqma53 { 65 65 - pinctrl_hog: hoggrp { 66 66 - fsl,pins = < 67 67 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ 68 68 - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ 69 69 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ 70 70 - MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ 71 71 - MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ 72 72 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ 73 73 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ 74 74 - MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ 75 75 - MX53_PAD_GPIO_3__GPIO1_3 0x80000000 76 76 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ 77 77 - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ 78 78 - >; 79 79 - }; 64 64 + pinctrl_hog: hoggrp { 65 65 + fsl,pins = < 66 66 + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ 67 67 + MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ 68 68 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ 69 69 + MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ 70 70 + MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ 71 71 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ 72 72 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ 73 73 + MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ 74 74 + MX53_PAD_GPIO_3__GPIO1_3 0x80000000 75 75 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ 76 76 + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ 77 77 + >; 78 78 + }; 80 79 81 81 - pinctrl_audmux: audmuxgrp { 82 82 - fsl,pins = < 83 83 - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 84 84 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 85 85 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 86 86 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 87 87 - >; 88 88 - }; 80 80 + pinctrl_audmux: audmuxgrp { 81 81 + fsl,pins = < 82 82 + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 83 83 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 84 84 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 85 85 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 86 86 + >; 87 87 + }; 89 88 90 90 - pinctrl_can1: can1grp { 91 91 - fsl,pins = < 92 92 - MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 93 93 - MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 94 94 - >; 95 95 - }; 89 89 + pinctrl_can1: can1grp { 90 90 + fsl,pins = < 91 91 + MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 92 92 + MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 93 93 + >; 94 94 + }; 96 95 97 97 - pinctrl_can2: can2grp { 98 98 - fsl,pins = < 99 99 - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 100 100 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 101 101 - >; 102 102 - }; 96 96 + pinctrl_can2: can2grp { 97 97 + fsl,pins = < 98 98 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 99 99 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 100 100 + >; 101 101 + }; 103 102 104 104 - pinctrl_cspi: cspigrp { 105 105 - fsl,pins = < 106 106 - MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 107 107 - MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 108 108 - MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 109 109 - >; 110 110 - }; 103 103 + pinctrl_cspi: cspigrp { 104 104 + fsl,pins = < 105 105 + MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 106 106 + MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 107 107 + MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 108 108 + >; 109 109 + }; 111 110 112 112 - pinctrl_ecspi1: ecspi1grp { 113 113 - fsl,pins = < 114 114 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 115 115 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 116 116 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 117 117 - >; 118 118 - }; 111 111 + pinctrl_ecspi1: ecspi1grp { 112 112 + fsl,pins = < 113 113 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 114 114 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 115 115 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 116 116 + >; 117 117 + }; 119 118 120 120 - pinctrl_esdhc2: esdhc2grp { 121 121 - fsl,pins = < 122 122 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 123 123 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 124 124 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 125 125 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 126 126 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 127 127 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 128 128 - >; 129 129 - }; 119 119 + pinctrl_esdhc2: esdhc2grp { 120 120 + fsl,pins = < 121 121 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 122 122 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 123 123 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 124 124 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 125 125 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 126 126 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 127 127 + >; 128 128 + }; 130 129 131 131 - pinctrl_esdhc2_cdwp: esdhc2cdwp { 132 132 - fsl,pins = < 133 133 - MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ 134 134 - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ 135 135 - >; 136 136 - }; 130 130 + pinctrl_esdhc2_cdwp: esdhc2cdwpgrp { 131 131 + fsl,pins = < 132 132 + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ 133 133 + MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ 134 134 + >; 135 135 + }; 137 136 138 138 - pinctrl_esdhc3: esdhc3grp { 139 139 - fsl,pins = < 140 140 - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 141 141 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 142 142 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 143 143 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 144 144 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 145 145 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 146 146 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 147 147 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 148 148 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 149 149 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 150 150 - >; 151 151 - }; 137 137 + pinctrl_esdhc3: esdhc3grp { 138 138 + fsl,pins = < 139 139 + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 140 140 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 141 141 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 142 142 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 143 143 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 144 144 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 145 145 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 146 146 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 147 147 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 148 148 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 149 149 + >; 150 150 + }; 152 151 153 153 - pinctrl_fec: fecgrp { 154 154 - fsl,pins = < 155 155 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 156 156 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 157 157 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 158 158 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 159 159 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 160 160 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 161 161 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 162 162 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 163 163 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 164 164 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 165 165 - >; 166 166 - }; 152 152 + pinctrl_fec: fecgrp { 153 153 + fsl,pins = < 154 154 + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 155 155 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 156 156 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 157 157 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 158 158 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 159 159 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 160 160 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 161 161 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 162 162 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 163 163 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 164 164 + >; 165 165 + }; 167 166 168 168 - pinctrl_i2c2: i2c2grp { 169 169 - fsl,pins = < 170 170 - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 171 171 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 172 172 - >; 173 173 - }; 167 167 + pinctrl_i2c2: i2c2grp { 168 168 + fsl,pins = < 169 169 + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 170 170 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 171 171 + >; 172 172 + }; 174 173 175 175 - pinctrl_i2c3: i2c3grp { 176 176 - fsl,pins = < 177 177 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 178 178 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 179 179 - >; 180 180 - }; 174 174 + pinctrl_i2c3: i2c3grp { 175 175 + fsl,pins = < 176 176 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 177 177 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 178 178 + >; 179 179 + }; 181 180 182 182 - pinctrl_uart1: uart1grp { 183 183 - fsl,pins = < 184 184 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 185 185 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 186 186 - >; 187 187 - }; 181 181 + pinctrl_uart1: uart1grp { 182 182 + fsl,pins = < 183 183 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 184 184 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 185 185 + >; 186 186 + }; 188 187 189 189 - pinctrl_uart2: uart2grp { 190 190 - fsl,pins = < 191 191 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 192 192 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 193 193 - >; 194 194 - }; 188 188 + pinctrl_uart2: uart2grp { 189 189 + fsl,pins = < 190 190 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 191 191 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 192 192 + >; 193 193 + }; 195 194 196 196 - pinctrl_uart3: uart3grp { 197 197 - fsl,pins = < 198 198 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 199 199 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 200 200 - >; 201 201 - }; 195 195 + pinctrl_uart3: uart3grp { 196 196 + fsl,pins = < 197 197 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 198 198 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 199 199 + >; 202 200 }; 203 201 }; 204 202

+55 -57

arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts

reviewed

··· 262 262 }; 263 263 264 264 &iomuxc { 265 265 - imx53-tx53-x03x { 266 266 - pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { 267 267 - fsl,pins = < 268 268 - MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ 269 269 - MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ 270 270 - MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ 271 271 - >; 272 272 - }; 265 265 + pinctrl_edt_ft5x06_1: edt-ft5x06-1-grp { 266 266 + fsl,pins = < 267 267 + MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ 268 268 + MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ 269 269 + MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ 270 270 + >; 271 271 + }; 273 272 274 274 - pinctrl_kpp: kppgrp { 275 275 - fsl,pins = < 276 276 - MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 277 277 - MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 278 278 - MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 279 279 - MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 280 280 - MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 281 281 - MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 282 282 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 283 283 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 284 284 - >; 285 285 - }; 273 273 + pinctrl_kpp: kppgrp { 274 274 + fsl,pins = < 275 275 + MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 276 276 + MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 277 277 + MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 278 278 + MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 279 279 + MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 280 280 + MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 281 281 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 282 282 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 283 283 + >; 284 284 + }; 286 285 287 287 - pinctrl_rgb24_vga1: rgb24-vgagrp1 { 288 288 - fsl,pins = < 289 289 - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 290 290 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 291 291 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 292 292 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 293 293 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 294 294 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 295 295 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 296 296 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 297 297 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 298 298 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 299 299 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 300 300 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 301 301 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 302 302 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 303 303 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 304 304 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 305 305 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 306 306 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 307 307 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 308 308 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 309 309 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 310 310 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 311 311 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 312 312 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 313 313 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 314 314 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 315 315 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 316 316 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 317 317 - >; 318 318 - }; 286 286 + pinctrl_rgb24_vga1: rgb24-vga1grp { 287 287 + fsl,pins = < 288 288 + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 289 289 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 290 290 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 291 291 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 292 292 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 293 293 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 294 294 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 295 295 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 296 296 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 297 297 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 298 298 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 299 299 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 300 300 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 301 301 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 302 302 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 303 303 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 304 304 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 305 305 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 306 306 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 307 307 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 308 308 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 309 309 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 310 310 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 311 311 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 312 312 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 313 313 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 314 314 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 315 315 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 316 316 + >; 317 317 + }; 319 318 320 320 - pinctrl_tsc2007: tsc2007grp { 321 321 - fsl,pins = < 322 322 - MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ 323 323 - >; 324 324 - }; 319 319 + pinctrl_tsc2007: tsc2007grp { 320 320 + fsl,pins = < 321 321 + MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ 322 322 + >; 325 323 }; 326 324 }; 327 325

+30 -32

arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts

reviewed

··· 139 139 }; 140 140 141 141 &iomuxc { 142 142 - imx53-tx53-x13x { 143 143 - pinctrl_lvds0: lvds0grp { 144 144 - fsl,pins = < 145 145 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 146 146 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 147 147 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 148 148 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 149 149 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 150 150 - >; 151 151 - }; 142 142 + pinctrl_lvds0: lvds0grp { 143 143 + fsl,pins = < 144 144 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 145 145 + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 146 146 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 147 147 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 148 148 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 149 149 + >; 150 150 + }; 152 151 153 153 - pinctrl_lvds1: lvds1grp { 154 154 - fsl,pins = < 155 155 - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 156 156 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 157 157 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 158 158 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 159 159 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 160 160 - >; 161 161 - }; 152 152 + pinctrl_lvds1: lvds1grp { 153 153 + fsl,pins = < 154 154 + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 155 155 + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 156 156 + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 157 157 + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 158 158 + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 159 159 + >; 160 160 + }; 162 161 163 163 - pinctrl_pwm1: pwm1grp { 164 164 - fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>; 165 165 - }; 162 162 + pinctrl_pwm1: pwm1grp { 163 163 + fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>; 164 164 + }; 166 165 167 167 - pinctrl_eeti1: eeti1grp { 168 168 - fsl,pins = < 169 169 - MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ 170 170 - >; 171 171 - }; 166 166 + pinctrl_eeti1: eeti1grp { 167 167 + fsl,pins = < 168 168 + MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ 169 169 + >; 170 170 + }; 172 171 173 173 - pinctrl_eeti2: eeti2grp { 174 174 - fsl,pins = < 175 175 - MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ 176 176 - >; 177 177 - }; 172 172 + pinctrl_eeti2: eeti2grp { 173 173 + fsl,pins = < 174 174 + MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ 175 175 + >; 178 176 }; 179 177 }; 180 178

+229 -231

arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi

reviewed

··· 257 257 pinctrl-names = "default"; 258 258 pinctrl-0 = <&pinctrl_hog>; 259 259 260 260 - imx53-tx53 { 261 261 - pinctrl_hog: hoggrp { 262 262 - /* pins not in use by any device on the Starterkit board series */ 263 263 - fsl,pins = < 264 264 - /* CMOS Sensor Interface */ 265 265 - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 266 266 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 267 267 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 268 268 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 269 269 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 270 270 - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 271 271 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 272 272 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 273 273 - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 274 274 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 275 275 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 276 276 - MX53_PAD_GPIO_0__GPIO1_0 0x1f4 277 277 - /* Module Specific Signal */ 278 278 - /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ 279 279 - /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ 280 280 - MX53_PAD_EIM_D29__GPIO3_29 0x1f4 281 281 - MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 282 282 - /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ 283 283 - /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ 284 284 - MX53_PAD_EIM_A19__GPIO2_19 0x1f4 285 285 - MX53_PAD_EIM_A20__GPIO2_18 0x1f4 286 286 - MX53_PAD_EIM_A21__GPIO2_17 0x1f4 287 287 - MX53_PAD_EIM_A22__GPIO2_16 0x1f4 288 288 - MX53_PAD_EIM_A23__GPIO6_6 0x1f4 289 289 - MX53_PAD_EIM_A24__GPIO5_4 0x1f4 290 290 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 291 291 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 292 292 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 293 293 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 294 294 - /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ 295 295 - /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ 296 296 - MX53_PAD_GPIO_13__GPIO4_3 0x1f4 297 297 - MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 298 298 - MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 299 299 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 300 300 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 301 301 - MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 302 302 - MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 303 303 - MX53_PAD_EIM_OE__GPIO2_25 0x1f4 304 304 - MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 305 305 - MX53_PAD_EIM_RW__GPIO2_26 0x1f4 306 306 - MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 307 307 - MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 308 308 - MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 309 309 - MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 310 310 - MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 311 311 - MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 312 312 - MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 313 313 - MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 314 314 - >; 315 315 - }; 316 316 - 317 317 - pinctrl_can1: can1grp { 318 318 - fsl,pins = < 319 319 - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 320 320 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 260 260 + pinctrl_hog: hoggrp { 261 261 + /* pins not in use by any device on the Starterkit board series */ 262 262 + fsl,pins = < 263 263 + /* CMOS Sensor Interface */ 264 264 + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 265 265 + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 266 266 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 267 267 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 268 268 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 269 269 + MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 270 270 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 271 271 + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 272 272 + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 273 273 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 274 274 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 275 275 + MX53_PAD_GPIO_0__GPIO1_0 0x1f4 276 276 + /* Module Specific Signal */ 277 277 + /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ 278 278 + /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ 279 279 + MX53_PAD_EIM_D29__GPIO3_29 0x1f4 280 280 + MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 281 281 + /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ 282 282 + /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ 283 283 + MX53_PAD_EIM_A19__GPIO2_19 0x1f4 284 284 + MX53_PAD_EIM_A20__GPIO2_18 0x1f4 285 285 + MX53_PAD_EIM_A21__GPIO2_17 0x1f4 286 286 + MX53_PAD_EIM_A22__GPIO2_16 0x1f4 287 287 + MX53_PAD_EIM_A23__GPIO6_6 0x1f4 288 288 + MX53_PAD_EIM_A24__GPIO5_4 0x1f4 289 289 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 290 290 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 291 291 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 292 292 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 293 293 + /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ 294 294 + /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ 295 295 + MX53_PAD_GPIO_13__GPIO4_3 0x1f4 296 296 + MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 297 297 + MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 298 298 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 299 299 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 300 300 + MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 301 301 + MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 302 302 + MX53_PAD_EIM_OE__GPIO2_25 0x1f4 303 303 + MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 304 304 + MX53_PAD_EIM_RW__GPIO2_26 0x1f4 305 305 + MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 306 306 + MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 307 307 + MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 308 308 + MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 309 309 + MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 310 310 + MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 311 311 + MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 312 312 + MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 321 313 >; 322 322 - }; 314 314 + }; 323 315 324 324 - pinctrl_can2: can2grp { 325 325 - fsl,pins = < 326 326 - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 327 327 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 328 328 - >; 329 329 - }; 316 316 + pinctrl_can1: can1grp { 317 317 + fsl,pins = < 318 318 + MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 319 319 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 320 320 + >; 321 321 + }; 330 322 331 331 - pinctrl_can_xcvr: can-xcvrgrp { 332 332 - fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */ 333 333 - }; 323 323 + pinctrl_can2: can2grp { 324 324 + fsl,pins = < 325 325 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 326 326 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 327 327 + >; 328 328 + }; 334 329 335 335 - pinctrl_ds1339: ds1339grp { 336 336 - fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>; 337 337 - }; 330 330 + pinctrl_can_xcvr: can-xcvrgrp { 331 331 + fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */ 332 332 + }; 338 333 339 339 - pinctrl_ecspi1: ecspi1grp { 340 340 - fsl,pins = < 341 341 - MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 342 342 - MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 343 343 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 344 344 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 345 345 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 346 346 - MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 347 347 - >; 348 348 - }; 334 334 + pinctrl_ds1339: ds1339grp { 335 335 + fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>; 336 336 + }; 349 337 350 350 - pinctrl_esdhc1: esdhc1grp { 351 351 - fsl,pins = < 352 352 - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 353 353 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 354 354 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 355 355 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 356 356 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 357 357 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 358 358 - MX53_PAD_EIM_D24__GPIO3_24 0x1f0 359 359 - >; 360 360 - }; 338 338 + pinctrl_ecspi1: ecspi1grp { 339 339 + fsl,pins = < 340 340 + MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 341 341 + MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 342 342 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 343 343 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 344 344 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 345 345 + MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 346 346 + >; 347 347 + }; 361 348 362 362 - pinctrl_esdhc2: esdhc2grp { 363 363 - fsl,pins = < 364 364 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 365 365 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 366 366 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 367 367 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 368 368 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 369 369 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 370 370 - MX53_PAD_EIM_D25__GPIO3_25 0x1f0 371 371 - >; 372 372 - }; 349 349 + pinctrl_esdhc1: esdhc1grp { 350 350 + fsl,pins = < 351 351 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 352 352 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 353 353 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 354 354 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 355 355 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 356 356 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 357 357 + MX53_PAD_EIM_D24__GPIO3_24 0x1f0 358 358 + >; 359 359 + }; 373 360 374 374 - pinctrl_fec: fecgrp { 375 375 - fsl,pins = < 376 376 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 377 377 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 378 378 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 379 379 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 380 380 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 381 381 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 382 382 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 383 383 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 384 384 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 385 385 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 386 386 - >; 387 387 - }; 361 361 + pinctrl_esdhc2: esdhc2grp { 362 362 + fsl,pins = < 363 363 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 364 364 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 365 365 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 366 366 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 367 367 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 368 368 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 369 369 + MX53_PAD_EIM_D25__GPIO3_25 0x1f0 370 370 + >; 371 371 + }; 388 372 389 389 - pinctrl_gpio_key: gpio-keygrp { 390 390 - fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>; 391 391 - }; 373 373 + pinctrl_fec: fecgrp { 374 374 + fsl,pins = < 375 375 + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 376 376 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 377 377 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 378 378 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 379 379 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 380 380 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 381 381 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 382 382 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 383 383 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 384 384 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 385 385 + >; 386 386 + }; 392 387 393 393 - pinctrl_i2c1: i2c1grp { 394 394 - fsl,pins = < 395 395 - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 396 396 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 397 397 - >; 398 398 - }; 388 388 + pinctrl_gpio_key: gpio-keygrp { 389 389 + fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>; 390 390 + }; 399 391 400 400 - pinctrl_i2c1_gpio: i2c1-gpiogrp { 401 401 - fsl,pins = < 402 402 - MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 403 403 - MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 404 404 - >; 405 405 - }; 392 392 + pinctrl_i2c1: i2c1grp { 393 393 + fsl,pins = < 394 394 + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 395 395 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 396 396 + >; 397 397 + }; 406 398 407 407 - pinctrl_i2c3: i2c3grp { 408 408 - fsl,pins = < 409 409 - MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 410 410 - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 411 411 - >; 412 412 - }; 399 399 + pinctrl_i2c1_gpio: i2c1-gpiogrp { 400 400 + fsl,pins = < 401 401 + MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 402 402 + MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 403 403 + >; 404 404 + }; 413 405 414 414 - pinctrl_i2c3_gpio: i2c3-gpiogrp { 415 415 - fsl,pins = < 416 416 - MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 417 417 - MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 418 418 - >; 419 419 - }; 406 406 + pinctrl_i2c3: i2c3grp { 407 407 + fsl,pins = < 408 408 + MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 409 409 + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 410 410 + >; 411 411 + }; 420 412 421 421 - pinctrl_nand: nandgrp { 422 422 - fsl,pins = < 423 423 - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 424 424 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 425 425 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 426 426 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 427 427 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 428 428 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 429 429 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 430 430 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 431 431 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 432 432 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 433 433 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 434 434 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 435 435 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 436 436 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 437 437 - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 438 438 - >; 439 439 - }; 413 413 + pinctrl_i2c3_gpio: i2c3-gpiogrp { 414 414 + fsl,pins = < 415 415 + MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 416 416 + MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 417 417 + >; 418 418 + }; 440 419 441 441 - pinctrl_pwm2: pwm2grp { 442 442 - fsl,pins = < 443 443 - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 444 444 - >; 445 445 - }; 420 420 + pinctrl_nand: nandgrp { 421 421 + fsl,pins = < 422 422 + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 423 423 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 424 424 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 425 425 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 426 426 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 427 427 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 428 428 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 429 429 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 430 430 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 431 431 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 432 432 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 433 433 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 434 434 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 435 435 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 436 436 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 437 437 + >; 438 438 + }; 446 439 447 447 - pinctrl_ssi1: ssi1grp { 448 448 - fsl,pins = < 449 449 - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 450 450 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 451 451 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 452 452 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 453 453 - >; 454 454 - }; 440 440 + pinctrl_pwm2: pwm2grp { 441 441 + fsl,pins = < 442 442 + MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 443 443 + >; 444 444 + }; 455 445 456 456 - pinctrl_ssi2: ssi2grp { 457 457 - fsl,pins = < 458 458 - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 459 459 - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 460 460 - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 461 461 - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 462 462 - MX53_PAD_EIM_D27__GPIO3_27 0x1f0 463 463 - >; 464 464 - }; 446 446 + pinctrl_ssi1: ssi1grp { 447 447 + fsl,pins = < 448 448 + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 449 449 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 450 450 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 451 451 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 452 452 + >; 453 453 + }; 465 454 466 466 - pinctrl_stk5led: stk5ledgrp { 467 467 - fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>; 468 468 - }; 455 455 + pinctrl_ssi2: ssi2grp { 456 456 + fsl,pins = < 457 457 + MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 458 458 + MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 459 459 + MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 460 460 + MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 461 461 + MX53_PAD_EIM_D27__GPIO3_27 0x1f0 462 462 + >; 463 463 + }; 469 464 470 470 - pinctrl_uart1: uart1grp { 471 471 - fsl,pins = < 472 472 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 473 473 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 474 474 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 475 475 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 476 476 - >; 477 477 - }; 465 465 + pinctrl_stk5led: stk5ledgrp { 466 466 + fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>; 467 467 + }; 478 468 479 479 - pinctrl_uart2: uart2grp { 480 480 - fsl,pins = < 481 481 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 482 482 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 483 483 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 484 484 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 485 485 - >; 486 486 - }; 469 469 + pinctrl_uart1: uart1grp { 470 470 + fsl,pins = < 471 471 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 472 472 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 473 473 + MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 474 474 + MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 475 475 + >; 476 476 + }; 487 477 488 488 - pinctrl_uart3: uart3grp { 489 489 - fsl,pins = < 490 490 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 491 491 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 492 492 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 493 493 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 494 494 - >; 495 495 - }; 478 478 + pinctrl_uart2: uart2grp { 479 479 + fsl,pins = < 480 480 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 481 481 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 482 482 + MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 483 483 + MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 484 484 + >; 485 485 + }; 496 486 497 497 - pinctrl_usbh1: usbh1grp { 498 498 - fsl,pins = < 499 499 - MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ 500 500 - >; 501 501 - }; 487 487 + pinctrl_uart3: uart3grp { 488 488 + fsl,pins = < 489 489 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 490 490 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 491 491 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 492 492 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 493 493 + >; 494 494 + }; 502 495 503 503 - pinctrl_usbh1_vbus: usbh1-vbusgrp { 504 504 - fsl,pins = < 505 505 - MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ 506 506 - >; 507 507 - }; 496 496 + pinctrl_usbh1: usbh1grp { 497 497 + fsl,pins = < 498 498 + MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ 499 499 + >; 500 500 + }; 508 501 509 509 - pinctrl_usbotg_vbus: usbotg-vbusgrp { 510 510 - fsl,pins = < 511 511 - MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ 512 512 - MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ 513 513 - >; 514 514 - }; 502 502 + pinctrl_usbh1_vbus: usbh1-vbusgrp { 503 503 + fsl,pins = < 504 504 + MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ 505 505 + >; 506 506 + }; 507 507 + 508 508 + pinctrl_usbotg_vbus: usbotg-vbusgrp { 509 509 + fsl,pins = < 510 510 + MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ 511 511 + MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ 512 512 + >; 515 513 }; 516 514 }; 517 515

+53 -55

arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts

reviewed

··· 40 40 41 41 &iomuxc { 42 42 pinctrl-names = "default"; 43 43 - pinctrl-0 = <&pinctrl_hog>; 43 43 + pinctrl-0 = <&pinctrl_hogbsb>; 44 44 45 45 - imx53-voipac { 46 46 - pinctrl_hog: hoggrp { 47 47 - fsl,pins = < 48 48 - /* SD2_CD */ 49 49 - MX53_PAD_EIM_D25__GPIO3_25 0x80000000 50 50 - /* SD2_WP */ 51 51 - MX53_PAD_EIM_A19__GPIO2_19 0x80000000 52 52 - >; 53 53 - }; 45 45 + pinctrl_hogbsb: hogbsbgrp { 46 46 + fsl,pins = < 47 47 + /* SD2_CD */ 48 48 + MX53_PAD_EIM_D25__GPIO3_25 0x80000000 49 49 + /* SD2_WP */ 50 50 + MX53_PAD_EIM_A19__GPIO2_19 0x80000000 51 51 + >; 52 52 + }; 54 53 55 55 - led_pin_gpio: led_gpio { 56 56 - fsl,pins = < 57 57 - MX53_PAD_EIM_D29__GPIO3_29 0x80000000 58 58 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 59 59 - >; 60 60 - }; 54 54 + led_pin_gpio: ledgpiogrp { 55 55 + fsl,pins = < 56 56 + MX53_PAD_EIM_D29__GPIO3_29 0x80000000 57 57 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 58 58 + >; 59 59 + }; 61 60 62 62 - /* Keyboard controller */ 63 63 - pinctrl_kpp_1: kppgrp-1 { 64 64 - fsl,pins = < 65 65 - MX53_PAD_GPIO_9__KPP_COL_6 0xe8 66 66 - MX53_PAD_GPIO_4__KPP_COL_7 0xe8 67 67 - MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 68 68 - MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 69 69 - MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 70 70 - MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 71 71 - MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 72 72 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 73 73 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 74 74 - MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 75 75 - >; 76 76 - }; 61 61 + /* Keyboard controller */ 62 62 + pinctrl_kpp_1: kpp1grp { 63 63 + fsl,pins = < 64 64 + MX53_PAD_GPIO_9__KPP_COL_6 0xe8 65 65 + MX53_PAD_GPIO_4__KPP_COL_7 0xe8 66 66 + MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 67 67 + MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 68 68 + MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 69 69 + MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 70 70 + MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 71 71 + MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 72 72 + MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 73 73 + MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 74 74 + >; 75 75 + }; 77 76 78 78 - pinctrl_audmux: audmuxgrp { 79 79 - fsl,pins = < 80 80 - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 81 81 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 82 82 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 83 83 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 84 84 - >; 85 85 - }; 77 77 + pinctrl_audmux: audmuxgrp { 78 78 + fsl,pins = < 79 79 + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 80 80 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 81 81 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 82 82 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 83 83 + >; 84 84 + }; 86 85 87 87 - pinctrl_esdhc2: esdhc2grp { 88 88 - fsl,pins = < 89 89 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 90 90 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 91 91 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 92 92 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 93 93 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 94 94 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 95 95 - >; 96 96 - }; 86 86 + pinctrl_esdhc2: esdhc2grp { 87 87 + fsl,pins = < 88 88 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 89 89 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 90 90 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 91 91 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 92 92 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 93 93 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 94 94 + >; 95 95 + }; 97 96 98 98 - pinctrl_i2c3: i2c3grp { 99 99 - fsl,pins = < 100 100 - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 101 101 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 102 102 - >; 103 103 - }; 97 97 + pinctrl_i2c3: i2c3grp { 98 98 + fsl,pins = < 99 99 + MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 100 100 + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 101 101 + >; 104 102 }; 105 103 }; 106 104

+61 -63

arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi

reviewed

··· 37 37 pinctrl-names = "default"; 38 38 pinctrl-0 = <&pinctrl_hog>; 39 39 40 40 - imx53-voipac { 41 41 - pinctrl_hog: hoggrp { 42 42 - fsl,pins = < 43 43 - /* Make DA9053 regulator functional */ 44 44 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 45 45 - /* FEC Power enable */ 46 46 - MX53_PAD_GPIO_11__GPIO4_1 0x80000000 47 47 - /* FEC RST */ 48 48 - MX53_PAD_GPIO_12__GPIO4_2 0x80000000 49 49 - >; 50 50 - }; 40 40 + pinctrl_hog: hoggrp { 41 41 + fsl,pins = < 42 42 + /* Make DA9053 regulator functional */ 43 43 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 44 44 + /* FEC Power enable */ 45 45 + MX53_PAD_GPIO_11__GPIO4_1 0x80000000 46 46 + /* FEC RST */ 47 47 + MX53_PAD_GPIO_12__GPIO4_2 0x80000000 48 48 + >; 49 49 + }; 51 50 52 52 - pinctrl_ecspi1: ecspi1grp { 53 53 - fsl,pins = < 54 54 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 55 55 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 56 56 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 57 57 - >; 58 58 - }; 51 51 + pinctrl_ecspi1: ecspi1grp { 52 52 + fsl,pins = < 53 53 + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 54 54 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 55 55 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 56 56 + >; 57 57 + }; 59 58 60 60 - pinctrl_fec: fecgrp { 61 61 - fsl,pins = < 62 62 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 63 63 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 64 64 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 65 65 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 66 66 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 67 67 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 68 68 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 69 69 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 70 70 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 71 71 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 72 72 - >; 73 73 - }; 59 59 + pinctrl_fec: fecgrp { 60 60 + fsl,pins = < 61 61 + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 62 62 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 63 63 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 64 64 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 65 65 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 66 66 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 67 67 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 68 68 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 69 69 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 70 70 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 71 71 + >; 72 72 + }; 74 73 75 75 - pinctrl_i2c1: i2c1grp { 76 76 - fsl,pins = < 77 77 - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 78 78 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 79 79 - >; 80 80 - }; 74 74 + pinctrl_i2c1: i2c1grp { 75 75 + fsl,pins = < 76 76 + MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 77 77 + MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 78 78 + >; 79 79 + }; 81 80 82 82 - pinctrl_uart1: uart1grp { 83 83 - fsl,pins = < 84 84 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 85 85 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 86 86 - >; 87 87 - }; 81 81 + pinctrl_uart1: uart1grp { 82 82 + fsl,pins = < 83 83 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 84 84 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 85 85 + >; 86 86 + }; 88 87 89 89 - pinctrl_nand: nandgrp { 90 90 - fsl,pins = < 91 91 - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 92 92 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 93 93 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 94 94 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 95 95 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 96 96 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 97 97 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 98 98 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 99 99 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 100 100 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 101 101 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 102 102 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 103 103 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 104 104 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 105 105 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 106 106 - >; 107 107 - }; 88 88 + pinctrl_nand: nandgrp { 89 89 + fsl,pins = < 90 90 + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 91 91 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 92 92 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 93 93 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 94 94 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 95 95 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 96 96 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 97 97 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 98 98 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 99 99 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 100 100 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 101 101 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 102 102 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 103 103 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 104 104 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 105 105 + >; 108 106 }; 109 107 }; 110 108

+1 -1

arch/arm/boot/dts/nxp/imx/imx53.dtsi

reviewed

··· 458 458 clocks = <&clks IMX5_CLK_SRTC_GATE>; 459 459 }; 460 460 461 461 - iomuxc: iomuxc@53fa8000 { 461 461 + iomuxc: pinctrl@53fa8000 { 462 462 compatible = "fsl,imx53-iomuxc"; 463 463 reg = <0x53fa8000 0x4000>; 464 464 };

+2 -2

arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi

reviewed

··· 534 534 >; 535 535 }; 536 536 537 537 - pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { 537 537 + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhzgrp { 538 538 fsl,pins = < 539 539 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ 540 540 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 ··· 546 546 >; 547 547 }; 548 548 549 549 - pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { 549 549 + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhzgrp { 550 550 fsl,pins = < 551 551 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ 552 552 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts

reviewed

··· 52 52 &pinctrl_weim_gpio_5 53 53 >; 54 54 55 55 - pinctrl_gpio_aster: gpioaster { 55 55 + pinctrl_gpio_aster: gpioastergrp { 56 56 fsl,pins = < 57 57 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 58 58 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0

+20

arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-pdk2.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Copyright (C) 2024 Marek Vasut <marex@denx.de> 4 4 + * 5 5 + * DHCOM iMX6 variant: 6 6 + * DHCM-iMX6DL-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2 7 7 + * DHCOM PCB number: 493-400 or newer 8 8 + * PDK2 PCB number: 516-400 or newer 9 9 + */ 10 10 + /dts-v1/; 11 11 + 12 12 + #include "imx6dl.dtsi" 13 13 + #include "imx6qdl-dhcom-som.dtsi" 14 14 + #include "imx6qdl-dhcom-pdk2.dtsi" 15 15 + 16 16 + / { 17 17 + model = "DH electronics i.MX6DL DHCOM on Premium Developer Kit (2)"; 18 18 + compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom-som", 19 19 + "fsl,imx6dl"; 20 20 + };

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts

reviewed

··· 3 3 * Copyright (C) 2021 DH electronics GmbH 4 4 * 5 5 * DHCOM iMX6 variant: 6 6 - * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 6 6 + * DHCM-iMX6DL-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2 7 7 * DHCOM PCB number: 493-300 or newer 8 8 * PicoITX PCB number: 487-600 or newer 9 9 */

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts

reviewed

··· 139 139 pinctrl-names = "default"; 140 140 pinctrl-0 = <&pinctrl_hog>; 141 141 142 142 - pinctrl_hog: hog { 142 142 + pinctrl_hog: hoggrp { 143 143 fsl,pins = < 144 144 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ 145 145 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts

reviewed

··· 395 395 >; 396 396 }; 397 397 398 398 - pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ 398 398 + pinctrl_ipu1_lcdif: pinctrlipu1lcdifgrp { /* parallel port 24-bit */ 399 399 fsl,pins = < 400 400 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ 401 401 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts

reviewed

··· 773 773 >; 774 774 }; 775 775 776 776 - pinctrl_pca9539: pca9539 { 776 776 + pinctrl_pca9539: pca9539grp { 777 777 fsl,pins = < 778 778 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 779 779 >;

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts

reviewed

··· 133 133 }; 134 134 135 135 &iomuxc { 136 136 - pinctrl_can1phy: can1phy { 136 136 + pinctrl_can1phy: can1phygrp { 137 137 fsl,pins = < 138 138 /* CAN1_SR */ 139 139 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070

+1 -1

arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts

reviewed

··· 507 507 >; 508 508 }; 509 509 510 510 - pinctrl_can1phy: can1phy { 510 510 + pinctrl_can1phy: can1phygrp { 511 511 fsl,pins = < 512 512 /* CAN1_SR */ 513 513 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070

+222 -224

arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi

reviewed

··· 352 352 pinctrl-names = "default"; 353 353 pinctrl-0 = <&pinctrl_hog>; 354 354 355 355 - qmx6mux: imx6qdl-qmx6 { 356 356 - pinctrl_audmux: audmuxgrp { 357 357 - fsl,pins = < 358 358 - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ 359 359 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ 360 360 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ 361 361 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ 362 362 - >; 363 363 - }; 355 355 + pinctrl_audmux: audmuxgrp { 356 356 + fsl,pins = < 357 357 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ 358 358 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ 359 359 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ 360 360 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ 361 361 + >; 362 362 + }; 364 363 365 365 - /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ 366 366 - pinctrl_enet: enet { 367 367 - fsl,pins = < 368 368 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 369 369 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 370 370 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 371 371 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 372 372 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 373 373 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 374 374 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 375 375 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 376 376 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 377 377 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 378 378 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 379 379 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 380 380 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 381 381 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 382 382 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 383 383 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 384 384 - >; 385 385 - }; 364 364 + /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ 365 365 + pinctrl_enet: enetgrp { 366 366 + fsl,pins = < 367 367 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 368 368 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 369 369 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 370 370 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 371 371 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 372 372 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 373 373 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 374 374 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 375 375 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 376 376 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 377 377 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 378 378 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 379 379 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 380 380 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 381 381 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 382 382 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 383 383 + >; 384 384 + }; 386 385 387 387 - pinctrl_hog: hoggrp { 388 388 - fsl,pins = < 389 389 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ 390 390 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ 391 391 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ 392 392 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ 393 393 - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ 394 394 - >; 395 395 - }; 386 386 + pinctrl_hog: hoggrp { 387 387 + fsl,pins = < 388 388 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ 389 389 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ 390 390 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ 391 391 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ 392 392 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ 393 393 + >; 394 394 + }; 396 395 397 397 - pinctrl_i2c1: i2c1 { 398 398 - fsl,pins = < 399 399 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ 400 400 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ 401 401 - >; 402 402 - }; 396 396 + pinctrl_i2c1: i2c1grp { 397 397 + fsl,pins = < 398 398 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ 399 399 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ 400 400 + >; 401 401 + }; 403 402 404 404 - pinctrl_i2c1_gpio: i2c1-gpio { 405 405 - fsl,pins = < 406 406 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ 407 407 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ 408 408 - >; 409 409 - }; 403 403 + pinctrl_i2c1_gpio: i2c1-gpiogrp { 404 404 + fsl,pins = < 405 405 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ 406 406 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ 407 407 + >; 408 408 + }; 410 409 411 411 - pinctrl_i2c2: i2c2 { 412 412 - fsl,pins = < 413 413 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ 414 414 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ 415 415 - >; 416 416 - }; 410 410 + pinctrl_i2c2: i2c2grp { 411 411 + fsl,pins = < 412 412 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ 413 413 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ 414 414 + >; 415 415 + }; 417 416 418 418 - pinctrl_i2c2_gpio: i2c2-gpio { 419 419 - fsl,pins = < 420 420 - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ 421 421 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ 422 422 - >; 423 423 - }; 417 417 + pinctrl_i2c2_gpio: i2c2-gpiogrp { 418 418 + fsl,pins = < 419 419 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ 420 420 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ 421 421 + >; 422 422 + }; 424 423 425 425 - pinctrl_i2c3: i2c3 { 426 426 - fsl,pins = < 427 427 - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ 428 428 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ 429 429 - >; 430 430 - }; 424 424 + pinctrl_i2c3: i2c3grp { 425 425 + fsl,pins = < 426 426 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ 427 427 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ 428 428 + >; 429 429 + }; 431 430 432 432 - pinctrl_i2c3_gpio: i2c3-gpio { 433 433 - fsl,pins = < 434 434 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ 435 435 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ 436 436 - >; 437 437 - }; 431 431 + pinctrl_i2c3_gpio: i2c3-gpiogrp { 432 432 + fsl,pins = < 433 433 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ 434 434 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ 435 435 + >; 436 436 + }; 438 437 439 439 - pinctrl_phy_reset: phy-reset { 440 440 - fsl,pins = < 441 441 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ 442 442 - >; 443 443 - }; 438 438 + pinctrl_phy_reset: phy-resetgrp { 439 439 + fsl,pins = < 440 440 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ 441 441 + >; 442 442 + }; 444 443 445 445 - pinctrl_pwm4: pwm4 { 446 446 - fsl,pins = < 447 447 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ 448 448 - >; 449 449 - }; 444 444 + pinctrl_pwm4: pwm4grp { 445 445 + fsl,pins = < 446 446 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ 447 447 + >; 448 448 + }; 450 449 451 451 - pinctrl_q7_backlight_enable: q7-backlight-enable { 452 452 - fsl,pins = < 453 453 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ 454 454 - >; 455 455 - }; 450 450 + pinctrl_q7_backlight_enable: q7-backlight-enablegrp { 451 451 + fsl,pins = < 452 452 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ 453 453 + >; 454 454 + }; 456 455 457 457 - pinctrl_q7_gpio0: q7-gpio0 { 458 458 - fsl,pins = < 459 459 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ 460 460 - >; 461 461 - }; 456 456 + pinctrl_q7_gpio0: q7-gpio0grp { 457 457 + fsl,pins = < 458 458 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ 459 459 + >; 460 460 + }; 462 461 463 463 - pinctrl_q7_gpio1: q7-gpio1 { 464 464 - fsl,pins = < 465 465 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ 466 466 - >; 467 467 - }; 462 462 + pinctrl_q7_gpio1: q7-gpio1grp { 463 463 + fsl,pins = < 464 464 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ 465 465 + >; 466 466 + }; 468 467 469 469 - pinctrl_q7_gpio2: q7-gpio2 { 470 470 - fsl,pins = < 471 471 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ 472 472 - >; 473 473 - }; 468 468 + pinctrl_q7_gpio2: q7-gpio2grp { 469 469 + fsl,pins = < 470 470 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ 471 471 + >; 472 472 + }; 474 473 475 475 - pinctrl_q7_gpio3: q7-gpio3 { 476 476 - fsl,pins = < 477 477 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ 478 478 - >; 479 479 - }; 474 474 + pinctrl_q7_gpio3: q7-gpio3grp { 475 475 + fsl,pins = < 476 476 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ 477 477 + >; 478 478 + }; 480 479 481 481 - pinctrl_q7_gpio4: q7-gpio4 { 482 482 - fsl,pins = < 483 483 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ 484 484 - >; 485 485 - }; 480 480 + pinctrl_q7_gpio4: q7-gpio4grp { 481 481 + fsl,pins = < 482 482 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ 483 483 + >; 484 484 + }; 486 485 487 487 - pinctrl_q7_gpio5: q7-gpio5 { 488 488 - fsl,pins = < 489 489 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ 490 490 - >; 491 491 - }; 486 486 + pinctrl_q7_gpio5: q7-gpio5grp { 487 487 + fsl,pins = < 488 488 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ 489 489 + >; 490 490 + }; 492 491 493 493 - pinctrl_q7_gpio6: q7-gpio6 { 494 494 - fsl,pins = < 495 495 - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ 496 496 - >; 497 497 - }; 492 492 + pinctrl_q7_gpio6: q7-gpio6grp { 493 493 + fsl,pins = < 494 494 + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ 495 495 + >; 496 496 + }; 498 497 499 499 - pinctrl_q7_gpio7: q7-gpio7 { 500 500 - fsl,pins = < 501 501 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ 502 502 - >; 503 503 - }; 498 498 + pinctrl_q7_gpio7: q7-gpio7grp { 499 499 + fsl,pins = < 500 500 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ 501 501 + >; 502 502 + }; 504 503 505 505 - pinctrl_q7_hda_reset: q7-hda-reset { 506 506 - fsl,pins = < 507 507 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ 508 508 - >; 509 509 - }; 504 504 + pinctrl_q7_hda_reset: q7-hda-resetgrp { 505 505 + fsl,pins = < 506 506 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ 507 507 + >; 508 508 + }; 510 509 511 511 - pinctrl_q7_lcd_power: lcd-power { 512 512 - fsl,pins = < 513 513 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ 514 514 - >; 515 515 - }; 510 510 + pinctrl_q7_lcd_power: lcd-powergrp { 511 511 + fsl,pins = < 512 512 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ 513 513 + >; 514 514 + }; 516 515 517 517 - pinctrl_q7_sdio_power: q7-sdio-power { 518 518 - fsl,pins = < 519 519 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ 520 520 - >; 521 521 - }; 516 516 + pinctrl_q7_sdio_power: q7-sdio-powergrp { 517 517 + fsl,pins = < 518 518 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ 519 519 + >; 520 520 + }; 522 521 523 523 - pinctrl_q7_sleep_button: q7-sleep-button { 524 524 - fsl,pins = < 525 525 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ 526 526 - >; 527 527 - }; 522 522 + pinctrl_q7_sleep_button: q7-sleep-buttongrp { 523 523 + fsl,pins = < 524 524 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ 525 525 + >; 526 526 + }; 528 527 529 529 - pinctrl_q7_spi_cs1: spi-cs1 { 530 530 - fsl,pins = < 531 531 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ 532 532 - >; 533 533 - }; 528 528 + pinctrl_q7_spi_cs1: spi-cs1grp { 529 529 + fsl,pins = < 530 530 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ 531 531 + >; 532 532 + }; 534 533 535 535 - /* SPI1 bus does not leave System on Module */ 536 536 - pinctrl_spi1: spi1 { 537 537 - fsl,pins = < 538 538 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 539 539 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 540 540 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 541 541 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 542 542 - >; 543 543 - }; 534 534 + /* SPI1 bus does not leave System on Module */ 535 535 + pinctrl_spi1: spi1grp { 536 536 + fsl,pins = < 537 537 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 538 538 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 539 539 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 540 540 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 541 541 + >; 542 542 + }; 544 543 545 545 - /* Debug connector on Q7 module */ 546 546 - pinctrl_uart2: uart2 { 547 547 - fsl,pins = < 548 548 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 549 549 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 550 550 - >; 551 551 - }; 544 544 + /* Debug connector on Q7 module */ 545 545 + pinctrl_uart2: uart2grp { 546 546 + fsl,pins = < 547 547 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 548 548 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 549 549 + >; 550 550 + }; 552 551 553 553 - pinctrl_uart3: uart3 { 554 554 - fsl,pins = < 555 555 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ 556 556 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ 557 557 - >; 558 558 - }; 552 552 + pinctrl_uart3: uart3grp { 553 553 + fsl,pins = < 554 554 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ 555 555 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ 556 556 + >; 557 557 + }; 559 558 560 560 - pinctrl_usbotg: usbotg { 561 561 - fsl,pins = < 562 562 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ 563 563 - >; 564 564 - }; 559 559 + pinctrl_usbotg: usbotggrp { 560 560 + fsl,pins = < 561 561 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ 562 562 + >; 563 563 + }; 565 564 566 566 - /* µSD card slot on Q7 module */ 567 567 - pinctrl_usdhc2: usdhc2 { 568 568 - fsl,pins = < 569 569 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 570 570 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 571 571 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 572 572 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 573 573 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 574 574 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 575 575 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ 576 576 - >; 577 577 - }; 565 565 + /* µSD card slot on Q7 module */ 566 566 + pinctrl_usdhc2: usdhc2grp { 567 567 + fsl,pins = < 568 568 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 569 569 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 570 570 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 571 571 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 572 572 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 573 573 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 574 574 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ 575 575 + >; 576 576 + }; 578 577 579 579 - /* eMMC module on Q7 module */ 580 580 - pinctrl_usdhc3: usdhc3 { 581 581 - fsl,pins = < 582 582 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 583 583 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 584 584 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 585 585 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 586 586 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 587 587 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 588 588 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 589 589 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 590 590 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 591 591 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 592 592 - >; 593 593 - }; 578 578 + /* eMMC module on Q7 module */ 579 579 + pinctrl_usdhc3: usdhc3grp { 580 580 + fsl,pins = < 581 581 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 582 582 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 583 583 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 584 584 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 585 585 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 586 586 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 587 587 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 588 588 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 589 589 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 590 590 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 591 591 + >; 592 592 + }; 594 593 595 595 - pinctrl_usdhc4: usdhc4 { 596 596 - fsl,pins = < 597 597 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ 598 598 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ 599 599 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ 600 600 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ 601 601 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ 602 602 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ 603 603 - >; 604 604 - }; 594 594 + pinctrl_usdhc4: usdhc4grp { 595 595 + fsl,pins = < 596 596 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ 597 597 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ 598 598 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ 599 599 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ 600 600 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ 601 601 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ 602 602 + >; 603 603 + }; 605 604 606 606 - pinctrl_wdog: wdog { 607 607 - fsl,pins = < 608 608 - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ 609 609 - >; 610 610 - }; 605 605 + pinctrl_wdog: wdoggrp { 606 606 + fsl,pins = < 607 607 + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ 608 608 + >; 611 609 }; 612 610 };

+179 -181

arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts

reviewed

··· 391 391 &iomuxc { 392 392 pinctrl-names = "default"; 393 393 394 394 - imx6-riotboard { 395 395 - pinctrl_audmux: audmuxgrp { 396 396 - fsl,pins = < 397 397 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 398 398 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 399 399 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 400 400 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 401 401 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 402 402 - >; 403 403 - }; 394 394 + pinctrl_audmux: audmuxgrp { 395 395 + fsl,pins = < 396 396 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 397 397 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 398 398 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 399 399 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 400 400 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 401 401 + >; 402 402 + }; 404 403 405 405 - pinctrl_ecspi1: ecspi1grp { 406 406 - fsl,pins = < 407 407 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 408 408 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 409 409 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 410 410 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ 411 411 - >; 412 412 - }; 404 404 + pinctrl_ecspi1: ecspi1grp { 405 405 + fsl,pins = < 406 406 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 407 407 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 408 408 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 409 409 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ 410 410 + >; 411 411 + }; 413 412 414 414 - pinctrl_ecspi2: ecspi2grp { 415 415 - fsl,pins = < 416 416 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ 417 417 - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 418 418 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 419 419 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ 420 420 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 421 421 - >; 422 422 - }; 413 413 + pinctrl_ecspi2: ecspi2grp { 414 414 + fsl,pins = < 415 415 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ 416 416 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 417 417 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 418 418 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ 419 419 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 420 420 + >; 421 421 + }; 423 422 424 424 - pinctrl_ecspi3: ecspi3grp { 425 425 - fsl,pins = < 426 426 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 427 427 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 428 428 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 429 429 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ 430 430 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ 431 431 - >; 432 432 - }; 423 423 + pinctrl_ecspi3: ecspi3grp { 424 424 + fsl,pins = < 425 425 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 426 426 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 427 427 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 428 428 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ 429 429 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ 430 430 + >; 431 431 + }; 433 432 434 434 - pinctrl_enet: enetgrp { 435 435 - fsl,pins = < 436 436 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 437 437 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 438 438 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 439 439 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 440 440 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 441 441 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 442 442 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 443 443 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 444 444 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 445 445 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ 446 446 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ 447 447 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ 448 448 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ 449 449 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ 450 450 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 451 451 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ 452 452 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 453 453 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ 454 454 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 455 455 - >; 456 456 - }; 433 433 + pinctrl_enet: enetgrp { 434 434 + fsl,pins = < 435 435 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 436 436 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 437 437 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 438 438 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 439 439 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 440 440 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 441 441 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 442 442 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 443 443 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 444 444 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ 445 445 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ 446 446 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ 447 447 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ 448 448 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ 449 449 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 450 450 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ 451 451 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 452 452 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ 453 453 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 454 454 + >; 455 455 + }; 457 456 458 458 - pinctrl_i2c1: i2c1grp { 459 459 - fsl,pins = < 460 460 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 461 461 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 462 462 - >; 463 463 - }; 457 457 + pinctrl_i2c1: i2c1grp { 458 458 + fsl,pins = < 459 459 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 460 460 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 461 461 + >; 462 462 + }; 464 463 465 465 - pinctrl_i2c2: i2c2grp { 466 466 - fsl,pins = < 467 467 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 468 468 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 469 469 - >; 470 470 - }; 464 464 + pinctrl_i2c2: i2c2grp { 465 465 + fsl,pins = < 466 466 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 467 467 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 468 468 + >; 469 469 + }; 471 470 472 472 - pinctrl_i2c3: i2c3grp { 473 473 - fsl,pins = < 474 474 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 475 475 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 476 476 - >; 477 477 - }; 471 471 + pinctrl_i2c3: i2c3grp { 472 472 + fsl,pins = < 473 473 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 474 474 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 475 475 + >; 476 476 + }; 478 477 479 479 - pinctrl_i2c4: i2c4grp { 480 480 - fsl,pins = < 481 481 - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 482 482 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 483 483 - >; 484 484 - }; 478 478 + pinctrl_i2c4: i2c4grp { 479 479 + fsl,pins = < 480 480 + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 481 481 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 482 482 + >; 483 483 + }; 485 484 486 486 - pinctrl_led: ledgrp { 487 487 - fsl,pins = < 488 488 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ 489 489 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ 490 490 - >; 491 491 - }; 485 485 + pinctrl_led: ledgrp { 486 486 + fsl,pins = < 487 487 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ 488 488 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ 489 489 + >; 490 490 + }; 492 491 493 493 - pinctrl_pwm1: pwm1grp { 494 494 - fsl,pins = < 495 495 - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 496 496 - >; 497 497 - }; 492 492 + pinctrl_pwm1: pwm1grp { 493 493 + fsl,pins = < 494 494 + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 495 495 + >; 496 496 + }; 498 497 499 499 - pinctrl_pwm2: pwm2grp { 500 500 - fsl,pins = < 501 501 - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 502 502 - >; 503 503 - }; 498 498 + pinctrl_pwm2: pwm2grp { 499 499 + fsl,pins = < 500 500 + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 501 501 + >; 502 502 + }; 504 503 505 505 - pinctrl_pwm3: pwm3grp { 506 506 - fsl,pins = < 507 507 - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 508 508 - >; 509 509 - }; 504 504 + pinctrl_pwm3: pwm3grp { 505 505 + fsl,pins = < 506 506 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 507 507 + >; 508 508 + }; 510 509 511 511 - pinctrl_pwm4: pwm4grp { 512 512 - fsl,pins = < 513 513 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 514 514 - >; 515 515 - }; 510 510 + pinctrl_pwm4: pwm4grp { 511 511 + fsl,pins = < 512 512 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 513 513 + >; 514 514 + }; 516 515 517 517 - pinctrl_uart1: uart1grp { 518 518 - fsl,pins = < 519 519 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 520 520 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 521 521 - >; 522 522 - }; 516 516 + pinctrl_uart1: uart1grp { 517 517 + fsl,pins = < 518 518 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 519 519 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 520 520 + >; 521 521 + }; 523 522 524 524 - pinctrl_uart2: uart2grp { 525 525 - fsl,pins = < 526 526 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 527 527 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 528 528 - >; 529 529 - }; 523 523 + pinctrl_uart2: uart2grp { 524 524 + fsl,pins = < 525 525 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 526 526 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 527 527 + >; 528 528 + }; 530 529 531 531 - pinctrl_uart3: uart3grp { 532 532 - fsl,pins = < 533 533 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 534 534 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 535 535 - >; 536 536 - }; 530 530 + pinctrl_uart3: uart3grp { 531 531 + fsl,pins = < 532 532 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 533 533 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 534 534 + >; 535 535 + }; 537 536 538 538 - pinctrl_uart4: uart4grp { 539 539 - fsl,pins = < 540 540 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 541 541 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 542 542 - >; 543 543 - }; 537 537 + pinctrl_uart4: uart4grp { 538 538 + fsl,pins = < 539 539 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 540 540 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 541 541 + >; 542 542 + }; 544 543 545 545 - pinctrl_uart5: uart5grp { 546 546 - fsl,pins = < 547 547 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 548 548 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 549 549 - >; 550 550 - }; 544 544 + pinctrl_uart5: uart5grp { 545 545 + fsl,pins = < 546 546 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 547 547 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 548 548 + >; 549 549 + }; 551 550 552 552 - pinctrl_usbotg: usbotggrp { 553 553 - fsl,pins = < 554 554 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 555 555 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 556 556 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 557 557 - >; 558 558 - }; 551 551 + pinctrl_usbotg: usbotggrp { 552 552 + fsl,pins = < 553 553 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 554 554 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 555 555 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 556 556 + >; 557 557 + }; 559 558 560 560 - pinctrl_usdhc2: usdhc2grp { 561 561 - fsl,pins = < 562 562 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 563 563 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 564 564 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 565 565 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 566 566 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 567 567 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 568 568 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ 569 569 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ 570 570 - >; 571 571 - }; 559 559 + pinctrl_usdhc2: usdhc2grp { 560 560 + fsl,pins = < 561 561 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 562 562 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 563 563 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 564 564 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 565 565 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 566 566 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 567 567 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ 568 568 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ 569 569 + >; 570 570 + }; 572 571 573 573 - pinctrl_usdhc3: usdhc3grp { 574 574 - fsl,pins = < 575 575 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 576 576 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 577 577 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 578 578 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 579 579 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 580 580 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 581 581 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ 582 582 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ 583 583 - >; 584 584 - }; 572 572 + pinctrl_usdhc3: usdhc3grp { 573 573 + fsl,pins = < 574 574 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 575 575 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 576 576 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 577 577 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 578 578 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 579 579 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 580 580 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ 581 581 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ 582 582 + >; 583 583 + }; 585 584 586 586 - pinctrl_usdhc4: usdhc4grp { 587 587 - fsl,pins = < 588 588 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 589 589 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 590 590 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 591 591 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 592 592 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 593 593 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 594 594 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ 595 595 - >; 596 596 - }; 585 585 + pinctrl_usdhc4: usdhc4grp { 586 586 + fsl,pins = < 587 587 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 588 588 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 589 589 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 590 590 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 591 591 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 592 592 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 593 593 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ 594 594 + >; 597 595 }; 598 596 };

-1

arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts

reviewed

··· 51 51 52 52 &backlight { 53 53 pwms = <&pwm2 0 500000 0>; 54 54 - /delete-property/ turn-on-delay-ms; 55 54 }; 56 55 57 56 &can1 {

+2 -2

arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi

reviewed

··· 506 506 >; 507 507 }; 508 508 509 509 - pinctrl_usbh1_vbus: usbh1-vbus { 509 509 + pinctrl_usbh1_vbus: usbh1-vbusgrp { 510 510 fsl,pins = < 511 511 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 512 512 >; ··· 519 519 >; 520 520 }; 521 521 522 522 - pinctrl_usbotg_vbus: usbotg-vbus { 522 522 + pinctrl_usbotg_vbus: usbotg-vbusgrp { 523 523 fsl,pins = < 524 524 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 525 525 >;

+2 -2

arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi

reviewed

··· 500 500 >; 501 501 }; 502 502 503 503 - pinctrl_usbh1_vbus: usbh1-vbus { 503 503 + pinctrl_usbh1_vbus: usbh1-vbusgrp { 504 504 fsl,pins = < 505 505 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 506 506 >; ··· 513 513 >; 514 514 }; 515 515 516 516 - pinctrl_usbotg_vbus: usbotg-vbus { 516 516 + pinctrl_usbotg_vbus: usbotg-vbusgrp { 517 517 fsl,pins = < 518 518 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 519 519 >;

+98 -100

arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts

reviewed

··· 55 55 pinctrl-names = "default"; 56 56 pinctrl-0 = <&pinctrl_hog>; 57 57 58 58 - imx6q-arm2 { 59 59 - pinctrl_hog: hoggrp { 60 60 - fsl,pins = < 61 61 - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 62 62 - >; 63 63 - }; 58 58 + pinctrl_hog: hoggrp { 59 59 + fsl,pins = < 60 60 + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 61 61 + >; 62 62 + }; 64 63 65 65 - pinctrl_enet: enetgrp { 66 66 - fsl,pins = < 67 67 - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 68 68 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 69 69 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 70 70 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 71 71 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 72 72 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 73 73 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 74 74 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 75 75 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 76 76 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 77 77 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 78 78 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 79 79 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 80 80 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 81 81 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 82 82 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 83 83 - >; 84 84 - }; 64 64 + pinctrl_enet: enetgrp { 65 65 + fsl,pins = < 66 66 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 67 67 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 68 68 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 69 69 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 70 70 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 71 71 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 72 72 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 73 73 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 74 74 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 75 75 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 76 76 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 77 77 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 78 78 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 79 79 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 80 80 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 81 81 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 82 82 + >; 83 83 + }; 85 84 86 86 - pinctrl_gpmi_nand: gpminandgrp { 87 87 - fsl,pins = < 88 88 - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 89 89 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 90 90 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 91 91 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 92 92 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 93 93 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 94 94 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 95 95 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 96 96 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 97 97 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 98 98 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 99 99 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 100 100 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 101 101 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 102 102 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 103 103 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 104 104 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 105 105 - >; 106 106 - }; 85 85 + pinctrl_gpmi_nand: gpminandgrp { 86 86 + fsl,pins = < 87 87 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 88 88 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 89 89 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 90 90 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 91 91 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 92 92 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 93 93 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 94 94 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 95 95 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 96 96 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 97 97 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 98 98 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 99 99 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 100 100 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 101 101 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 102 102 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 103 103 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 104 104 + >; 105 105 + }; 107 106 108 108 - pinctrl_uart2: uart2grp { 109 109 - fsl,pins = < 110 110 - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 111 111 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 112 112 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 113 113 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 114 114 - >; 115 115 - }; 107 107 + pinctrl_uart2: uart2grp { 108 108 + fsl,pins = < 109 109 + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 110 110 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 111 111 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 112 112 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 113 113 + >; 114 114 + }; 116 115 117 117 - pinctrl_uart4: uart4grp { 118 118 - fsl,pins = < 119 119 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 120 120 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 121 121 - >; 122 122 - }; 116 116 + pinctrl_uart4: uart4grp { 117 117 + fsl,pins = < 118 118 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 119 119 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 120 120 + >; 121 121 + }; 123 122 124 124 - pinctrl_usbotg: usbotggrp { 125 125 - fsl,pins = < 126 126 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 127 127 - >; 128 128 - }; 123 123 + pinctrl_usbotg: usbotggrp { 124 124 + fsl,pins = < 125 125 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 126 126 + >; 127 127 + }; 129 128 130 130 - pinctrl_usdhc3: usdhc3grp { 131 131 - fsl,pins = < 132 132 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 133 133 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 134 134 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 135 135 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 136 136 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 137 137 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 138 138 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 139 139 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 140 140 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 141 141 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 142 142 - >; 143 143 - }; 129 129 + pinctrl_usdhc3: usdhc3grp { 130 130 + fsl,pins = < 131 131 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 132 132 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 133 133 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 134 134 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 135 135 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 136 136 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 137 137 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 138 138 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 139 139 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 140 140 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 141 141 + >; 142 142 + }; 144 143 145 145 - pinctrl_usdhc3_cdwp: usdhc3cdwp { 146 146 - fsl,pins = < 147 147 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 148 148 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 149 149 - >; 150 150 - }; 144 144 + pinctrl_usdhc3_cdwp: usdhc3cdwpgrp { 145 145 + fsl,pins = < 146 146 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 147 147 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 148 148 + >; 149 149 + }; 151 150 152 152 - pinctrl_usdhc4: usdhc4grp { 153 153 - fsl,pins = < 154 154 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 155 155 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 156 156 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 157 157 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 158 158 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 159 159 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 160 160 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 161 161 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 162 162 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 163 163 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 164 164 - >; 165 165 - }; 151 151 + pinctrl_usdhc4: usdhc4grp { 152 152 + fsl,pins = < 153 153 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 154 154 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 155 155 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 156 156 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 157 157 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 158 158 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 159 159 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 160 160 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 161 161 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 162 162 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 163 163 + >; 166 164 }; 167 165 }; 168 166

+1 -1

arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi

reviewed

··· 623 623 >; 624 624 }; 625 625 626 626 - pinctrl_usdhc3_reset: usdhc3grp-reset { 626 626 + pinctrl_usdhc3_reset: usdhc3-resetgrp { 627 627 fsl,pins = < 628 628 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 629 629 >;

+1 -1

arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts

reviewed

··· 4 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 5 * 6 6 * DHCOM iMX6 variant: 7 7 - * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 7 7 + * DHCM-iMX6Q-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2 8 8 * DHCOM PCB number: 493-300 or newer 9 9 * PDK2 PCB number: 516-400 or newer 10 10 */

+115 -117

arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts

reviewed

··· 283 283 pinctrl-names = "default"; 284 284 pinctrl-0 = <&pinctrl_hog>; 285 285 286 286 - imx6q-dmo-edmqmx6 { 287 287 - pinctrl_hog: hoggrp { 288 288 - fsl,pins = < 289 289 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 290 290 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 291 291 - >; 292 292 - }; 286 286 + pinctrl_hog: hoggrp { 287 287 + fsl,pins = < 288 288 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 289 289 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 290 290 + >; 291 291 + }; 293 292 294 294 - pinctrl_can1: can1grp { 295 295 - fsl,pins = < 296 296 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 297 297 - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 298 298 - >; 299 299 - }; 293 293 + pinctrl_can1: can1grp { 294 294 + fsl,pins = < 295 295 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 296 296 + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 297 297 + >; 298 298 + }; 300 299 301 301 - pinctrl_ecspi5: ecspi5rp-1 { 302 302 - fsl,pins = < 303 303 - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 304 304 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 305 305 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 306 306 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 307 307 - >; 308 308 - }; 300 300 + pinctrl_ecspi5: ecspi5rp-1grp { 301 301 + fsl,pins = < 302 302 + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 303 303 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 304 304 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 305 305 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 306 306 + >; 307 307 + }; 309 308 310 310 - pinctrl_enet: enetgrp { 311 311 - fsl,pins = < 312 312 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 313 313 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 314 314 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 315 315 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 316 316 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 317 317 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 318 318 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 319 319 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 320 320 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 321 321 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 322 322 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 323 323 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 324 324 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 325 325 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 326 326 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 327 327 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 328 328 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 329 329 - >; 330 330 - }; 309 309 + pinctrl_enet: enetgrp { 310 310 + fsl,pins = < 311 311 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 312 312 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 313 313 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 314 314 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 315 315 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 316 316 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 317 317 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 318 318 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 319 319 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 320 320 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 321 321 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 322 322 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 323 323 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 324 324 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 325 325 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 326 326 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 327 327 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 328 328 + >; 329 329 + }; 331 330 332 332 - pinctrl_i2c1: i2c1grp { 333 333 - fsl,pins = < 334 334 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 335 335 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 336 336 - >; 337 337 - }; 331 331 + pinctrl_i2c1: i2c1grp { 332 332 + fsl,pins = < 333 333 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 334 334 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 335 335 + >; 336 336 + }; 338 337 339 339 - pinctrl_i2c2: i2c2grp { 340 340 - fsl,pins = < 341 341 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 342 342 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 343 343 - >; 344 344 - }; 338 338 + pinctrl_i2c2: i2c2grp { 339 339 + fsl,pins = < 340 340 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 341 341 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 342 342 + >; 343 343 + }; 345 344 346 346 - pinctrl_i2c3: i2c3grp { 347 347 - fsl,pins = < 348 348 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 349 349 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 350 350 - >; 351 351 - }; 345 345 + pinctrl_i2c3: i2c3grp { 346 346 + fsl,pins = < 347 347 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 348 348 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 349 349 + >; 350 350 + }; 352 351 353 353 - pinctrl_pcie: pciegrp { 354 354 - fsl,pins = < 355 355 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 356 356 - >; 357 357 - }; 352 352 + pinctrl_pcie: pciegrp { 353 353 + fsl,pins = < 354 354 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 355 355 + >; 356 356 + }; 358 357 359 359 - pinctrl_pfuze: pfuze100grp1 { 360 360 - fsl,pins = < 361 361 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 362 362 - >; 363 363 - }; 358 358 + pinctrl_pfuze: pfuze100grp { 359 359 + fsl,pins = < 360 360 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 361 361 + >; 362 362 + }; 364 363 365 365 - pinctrl_stmpe1: stmpe1grp { 366 366 - fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; 367 367 - }; 364 364 + pinctrl_stmpe1: stmpe1grp { 365 365 + fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; 366 366 + }; 368 367 369 369 - pinctrl_stmpe2: stmpe2grp { 370 370 - fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>; 371 371 - }; 368 368 + pinctrl_stmpe2: stmpe2grp { 369 369 + fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>; 370 370 + }; 372 371 373 373 - pinctrl_uart1: uart1grp { 374 374 - fsl,pins = < 375 375 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 376 376 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 377 377 - >; 378 378 - }; 372 372 + pinctrl_uart1: uart1grp { 373 373 + fsl,pins = < 374 374 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 375 375 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 376 376 + >; 377 377 + }; 379 378 380 380 - pinctrl_uart2: uart2grp { 381 381 - fsl,pins = < 382 382 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 383 383 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 384 384 - >; 385 385 - }; 379 379 + pinctrl_uart2: uart2grp { 380 380 + fsl,pins = < 381 381 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 382 382 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 383 383 + >; 384 384 + }; 386 385 387 387 - pinctrl_usbotg: usbotggrp { 388 388 - fsl,pins = < 389 389 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 390 390 - >; 391 391 - }; 386 386 + pinctrl_usbotg: usbotggrp { 387 387 + fsl,pins = < 388 388 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 389 389 + >; 390 390 + }; 392 391 393 393 - pinctrl_usdhc3: usdhc3grp { 394 394 - fsl,pins = < 395 395 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 396 396 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 397 397 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 398 398 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 399 399 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 400 400 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 401 401 - >; 402 402 - }; 392 392 + pinctrl_usdhc3: usdhc3grp { 393 393 + fsl,pins = < 394 394 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 395 395 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 396 396 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 397 397 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 398 398 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 399 399 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 400 400 + >; 401 401 + }; 403 402 404 404 - pinctrl_usdhc4: usdhc4grp { 405 405 - fsl,pins = < 406 406 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 407 407 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 408 408 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 409 409 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 410 410 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 411 411 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 412 412 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 413 413 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 414 414 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 415 415 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 416 416 - >; 417 417 - }; 403 403 + pinctrl_usdhc4: usdhc4grp { 404 404 + fsl,pins = < 405 405 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 406 406 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 407 407 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 408 408 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 409 409 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 410 410 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 411 411 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 412 412 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 413 413 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 414 414 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 415 415 + >; 418 416 }; 419 417 }; 420 418

+45 -47

arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts

reviewed

··· 70 70 pinctrl-names = "default"; 71 71 pinctrl-0 = <&pinctrl_hog>; 72 72 73 73 - imx6q-gk802 { 74 74 - pinctrl_hog: hoggrp { 75 75 - fsl,pins = < 76 76 - /* Recovery button, active-low */ 77 77 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 78 78 - /* RTL8192CU enable GPIO, active-low */ 79 79 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 80 80 - >; 81 81 - }; 73 73 + pinctrl_hog: hoggrp { 74 74 + fsl,pins = < 75 75 + /* Recovery button, active-low */ 76 76 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 77 77 + /* RTL8192CU enable GPIO, active-low */ 78 78 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 79 79 + >; 80 80 + }; 82 81 83 83 - pinctrl_i2c2: i2c2grp { 84 84 - fsl,pins = < 85 85 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 86 86 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 87 87 - >; 88 88 - }; 82 82 + pinctrl_i2c2: i2c2grp { 83 83 + fsl,pins = < 84 84 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 85 85 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 86 86 + >; 87 87 + }; 89 88 90 90 - pinctrl_i2c3: i2c3grp { 91 91 - fsl,pins = < 92 92 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 93 93 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 94 94 - >; 95 95 - }; 89 89 + pinctrl_i2c3: i2c3grp { 90 90 + fsl,pins = < 91 91 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 92 92 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 93 93 + >; 94 94 + }; 96 95 97 97 - pinctrl_uart4: uart4grp { 98 98 - fsl,pins = < 99 99 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 100 100 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 101 101 - >; 102 102 - }; 96 96 + pinctrl_uart4: uart4grp { 97 97 + fsl,pins = < 98 98 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 99 99 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 100 100 + >; 101 101 + }; 103 102 104 104 - pinctrl_usdhc3: usdhc3grp { 105 105 - fsl,pins = < 106 106 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 107 107 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 108 108 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 109 109 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 110 110 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 111 111 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 112 112 - >; 113 113 - }; 103 103 + pinctrl_usdhc3: usdhc3grp { 104 104 + fsl,pins = < 105 105 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 106 106 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 107 107 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 108 108 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 109 109 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 110 110 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 111 111 + >; 112 112 + }; 114 113 115 115 - pinctrl_usdhc4: usdhc4grp { 116 116 - fsl,pins = < 117 117 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 118 118 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 119 119 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 120 120 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 121 121 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 122 122 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 123 123 - >; 124 124 - }; 114 114 + pinctrl_usdhc4: usdhc4grp { 115 115 + fsl,pins = < 116 116 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 117 117 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 118 118 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 119 119 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 120 120 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 121 121 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 122 122 + >; 125 123 }; 126 124 }; 127 125

+99 -101

arch/arm/boot/dts/nxp/imx/imx6q-h100.dts

reviewed

··· 217 217 }; 218 218 219 219 &iomuxc { 220 220 - h100 { 221 221 - pinctrl_h100_hdmi: h100-hdmi { 222 222 - fsl,pins = < 223 223 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 224 224 - >; 225 225 - }; 220 220 + pinctrl_h100_hdmi: h100-hdmigrp { 221 221 + fsl,pins = < 222 222 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 223 223 + >; 224 224 + }; 226 225 227 227 - pinctrl_h100_i2c1: h100-i2c1 { 228 228 - fsl,pins = < 229 229 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 230 230 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 231 231 - >; 232 232 - }; 226 226 + pinctrl_h100_i2c1: h100-i2c1grp { 227 227 + fsl,pins = < 228 228 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 229 229 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 230 230 + >; 231 231 + }; 233 232 234 234 - pinctrl_h100_i2c2: h100-i2c2 { 235 235 - fsl,pins = < 236 236 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 237 237 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 238 238 - >; 239 239 - }; 233 233 + pinctrl_h100_i2c2: h100-i2c2grp { 234 234 + fsl,pins = < 235 235 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 236 236 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 237 237 + >; 238 238 + }; 240 239 241 241 - pinctrl_h100_leds: pinctrl-h100-leds { 242 242 - fsl,pins = < 243 243 - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 244 244 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 245 245 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 246 246 - >; 247 247 - }; 240 240 + pinctrl_h100_leds: pinctrl-h100-ledsgrp { 241 241 + fsl,pins = < 242 242 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 243 243 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 244 244 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 245 245 + >; 246 246 + }; 248 247 249 249 - pinctrl_h100_reg_hdmi: h100-reg-hdmi { 250 250 - fsl,pins = < 251 251 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 252 252 - >; 253 253 - }; 248 248 + pinctrl_h100_reg_hdmi: h100-reg-hdmigrp { 249 249 + fsl,pins = < 250 250 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 251 251 + >; 252 252 + }; 254 253 255 255 - pinctrl_h100_sgtl5000: h100-sgtl5000 { 256 256 - fsl,pins = < 257 257 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 258 258 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 259 259 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 260 260 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 261 261 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 262 262 - >; 263 263 - }; 254 254 + pinctrl_h100_sgtl5000: h100-sgtl5000grp { 255 255 + fsl,pins = < 256 256 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 257 257 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 258 258 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 259 259 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 260 260 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 261 261 + >; 262 262 + }; 264 263 265 265 - pinctrl_h100_tc358743: h100-tc358743 { 266 266 - fsl,pins = < 267 267 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 268 268 - >; 269 269 - }; 264 264 + pinctrl_h100_tc358743: h100-tc358743grp { 265 265 + fsl,pins = < 266 266 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 267 267 + >; 268 268 + }; 270 269 271 271 - pinctrl_h100_uart2: h100-uart2 { 272 272 - fsl,pins = < 273 273 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 274 274 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 275 275 - >; 276 276 - }; 270 270 + pinctrl_h100_uart2: h100-uart2grp { 271 271 + fsl,pins = < 272 272 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 273 273 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 274 274 + >; 275 275 + }; 277 276 278 278 - pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { 279 279 - fsl,pins = < 280 280 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 281 281 - >; 282 282 - }; 277 277 + pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbusgrp { 278 278 + fsl,pins = < 279 279 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 280 280 + >; 281 281 + }; 283 282 284 284 - pinctrl_h100_usbotg_id: hummingboard-usbotg-id { 285 285 - fsl,pins = < 286 286 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 287 287 - >; 288 288 - }; 283 283 + pinctrl_h100_usbotg_id: hummingboard-usbotg-idgrp { 284 284 + fsl,pins = < 285 285 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 286 286 + >; 287 287 + }; 289 288 290 290 - pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { 291 291 - fsl,pins = < 292 292 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 293 293 - >; 294 294 - }; 289 289 + pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbusgrp { 290 290 + fsl,pins = < 291 291 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 292 292 + >; 293 293 + }; 295 294 296 296 - pinctrl_h100_usdhc2: h100-usdhc2 { 297 297 - fsl,pins = < 298 298 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 299 299 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 300 300 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 301 301 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 302 302 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 303 303 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 304 304 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 305 305 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 306 306 - >; 307 307 - }; 295 295 + pinctrl_h100_usdhc2: h100-usdhc2grp { 296 296 + fsl,pins = < 297 297 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 298 298 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 299 299 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 300 300 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 301 301 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 302 302 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 303 303 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 304 304 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 305 305 + >; 306 306 + }; 308 307 309 309 - pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { 310 310 - fsl,pins = < 311 311 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 312 312 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 313 313 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 314 314 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 315 315 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 316 316 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 317 317 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 318 318 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 319 319 - >; 320 320 - }; 308 308 + pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhzgrp { 309 309 + fsl,pins = < 310 310 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 311 311 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 312 312 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 313 313 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 314 314 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 315 315 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 316 316 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 317 317 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 318 318 + >; 319 319 + }; 321 320 322 322 - pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { 323 323 - fsl,pins = < 324 324 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 325 325 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 326 326 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 327 327 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 328 328 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 329 329 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 330 330 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 331 331 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 332 332 - >; 333 333 - }; 321 321 + pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhzgrp { 322 322 + fsl,pins = < 323 323 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 324 324 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 325 325 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 326 326 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 327 327 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 328 328 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 329 329 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 330 330 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 331 331 + >; 334 332 }; 335 333 }; 336 334

+2 -2

arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts

reviewed

··· 110 110 }; 111 111 112 112 &iomuxc { 113 113 - pinctrl_lcd_reg: lcdreg { 113 113 + pinctrl_lcd_reg: lcdreggrp { 114 114 fsl,pins = < 115 115 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ 116 116 >; 117 117 }; 118 118 119 119 - pinctrl_lcd_reset: lcdreset { 119 119 + pinctrl_lcd_reset: lcdresetgrp { 120 120 fsl,pins = < 121 121 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ 122 122 >;

+87

arch/arm/boot/dts/nxp/imx/imx6q-lxr.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + // 3 3 + // Copyright 2024 Comvetia AG 4 4 + 5 5 + /dts-v1/; 6 6 + #include "imx6q-phytec-pfla02.dtsi" 7 7 + 8 8 + / { 9 9 + model = "COMVETIA QSoIP LXR-2"; 10 10 + compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; 11 11 + 12 12 + chosen { 13 13 + stdout-path = &uart4; 14 14 + }; 15 15 + 16 16 + spi { 17 17 + compatible = "spi-gpio"; 18 18 + pinctrl-names = "default"; 19 19 + pinctrl-0 = <&pinctrl_spi_gpio>; 20 20 + sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 21 21 + mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; 22 22 + num-chipselects = <0>; 23 23 + #address-cells = <1>; 24 24 + #size-cells = <0>; 25 25 + 26 26 + fpga@0 { 27 27 + compatible = "altr,fpga-passive-serial"; 28 28 + reg = <0>; 29 29 + pinctrl-names = "default"; 30 30 + pinctrl-0 = <&pinctrl_fpga>; 31 31 + nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 32 32 + nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 33 33 + confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 34 34 + }; 35 35 + }; 36 36 + }; 37 37 + 38 38 + &ecspi3 { 39 39 + pinctrl-names = "default"; 40 40 + pinctrl-0 = <&pinctrl_ecspi3>; 41 41 + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 42 42 + status = "okay"; 43 43 + 44 44 + flash@0 { 45 45 + compatible = "jedec,spi-nor"; 46 46 + reg = <0>; 47 47 + spi-max-frequency = <20000000>; 48 48 + }; 49 49 + }; 50 50 + 51 51 + &fec { 52 52 + status = "okay"; 53 53 + }; 54 54 + 55 55 + &i2c3 { 56 56 + status = "okay"; 57 57 + }; 58 58 + 59 59 + &uart3 { 60 60 + status = "okay"; 61 61 + }; 62 62 + 63 63 + &uart4 { 64 64 + status = "okay"; 65 65 + }; 66 66 + 67 67 + &usdhc3 { 68 68 + no-1-8-v; 69 69 + status = "okay"; 70 70 + }; 71 71 + 72 72 + &iomuxc { 73 73 + pinctrl_fpga: fpgagrp { 74 74 + fsl,pins = < 75 75 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 76 76 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 77 77 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 78 78 + >; 79 79 + }; 80 80 + 81 81 + pinctrl_spi_gpio: spigpiogrp { 82 82 + fsl,pins = < 83 83 + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 84 84 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 85 85 + >; 86 86 + }; 87 87 + };

+1 -1

arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi

reviewed

··· 32 32 }; 33 33 34 34 &iomuxc { 35 35 - pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { 35 35 + pinctrl_ecspi5_mba6x: ecspi5-mba6xgrp { 36 36 fsl,pins = < 37 37 /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ 38 38 MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099

+24 -24

arch/arm/boot/dts/nxp/imx/imx6q-novena.dts

reviewed

··· 530 530 }; 531 531 532 532 &iomuxc { 533 533 - pinctrl_audmux_novena: audmuxgrp-novena { 533 533 + pinctrl_audmux_novena: audmux-novenagrp { 534 534 fsl,pins = < 535 535 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 536 536 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 ··· 539 539 >; 540 540 }; 541 541 542 542 - pinctrl_backlight_novena: backlightgrp-novena { 542 542 + pinctrl_backlight_novena: backlight-novenagrp { 543 543 fsl,pins = < 544 544 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 545 545 MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 ··· 547 547 >; 548 548 }; 549 549 550 550 - pinctrl_ecspi3_novena: ecspi3grp-novena { 550 550 + pinctrl_ecspi3_novena: ecspi3-novenagrp { 551 551 fsl,pins = < 552 552 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 553 553 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 ··· 555 555 >; 556 556 }; 557 557 558 558 - pinctrl_enet_novena: enetgrp-novena { 558 558 + pinctrl_enet_novena: enet-novenagrp { 559 559 fsl,pins = < 560 560 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 561 561 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 ··· 578 578 >; 579 579 }; 580 580 581 581 - pinctrl_fpga_gpio: fpgagpiogrp-novena { 581 581 + pinctrl_fpga_gpio: fpgagpio-novenagrp { 582 582 fsl,pins = < 583 583 /* FPGA power */ 584 584 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 ··· 614 614 >; 615 615 }; 616 616 617 617 - pinctrl_fpga_eim: fpgaeimgrp-novena { 617 617 + pinctrl_fpga_eim: fpgaeim-novenagrp { 618 618 fsl,pins = < 619 619 /* FPGA power */ 620 620 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 ··· 650 650 >; 651 651 }; 652 652 653 653 - pinctrl_gpio_keys_novena: gpiokeysgrp-novena { 653 653 + pinctrl_gpio_keys_novena: gpiokeys-novenagrp { 654 654 fsl,pins = < 655 655 /* User button */ 656 656 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 ··· 661 661 >; 662 662 }; 663 663 664 664 - pinctrl_hdmi_novena: hdmigrp-novena { 664 664 + pinctrl_hdmi_novena: hdmi-novenagrp { 665 665 fsl,pins = < 666 666 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 667 667 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 668 668 >; 669 669 }; 670 670 671 671 - pinctrl_i2c1_novena: i2c1grp-novena { 671 671 + pinctrl_i2c1_novena: i2c1-novenagrp { 672 672 fsl,pins = < 673 673 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 674 674 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 675 675 >; 676 676 }; 677 677 678 678 - pinctrl_i2c2_novena: i2c2grp-novena { 678 678 + pinctrl_i2c2_novena: i2c2-novenagrp { 679 679 fsl,pins = < 680 680 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 681 681 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 682 682 >; 683 683 }; 684 684 685 685 - pinctrl_i2c3_novena: i2c3grp-novena { 685 685 + pinctrl_i2c3_novena: i2c3-novenagrp { 686 686 fsl,pins = < 687 687 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 688 688 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 689 689 >; 690 690 }; 691 691 692 692 - pinctrl_kpp_novena: kppgrp-novena { 692 692 + pinctrl_kpp_novena: kpp-novenagrp { 693 693 fsl,pins = < 694 694 /* Front panel button */ 695 695 MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 ··· 698 698 >; 699 699 }; 700 700 701 701 - pinctrl_leds_novena: ledsgrp-novena { 701 701 + pinctrl_leds_novena: leds-novenagrp { 702 702 fsl,pins = < 703 703 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 704 704 >; 705 705 }; 706 706 707 707 - pinctrl_pcie_novena: pciegrp-novena { 707 707 + pinctrl_pcie_novena: pcie-novenagrp { 708 708 fsl,pins = < 709 709 /* Reset */ 710 710 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 ··· 715 715 >; 716 716 }; 717 717 718 718 - pinctrl_sata_novena: satagrp-novena { 718 718 + pinctrl_sata_novena: sata-novenagrp { 719 719 fsl,pins = < 720 720 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 721 721 >; 722 722 }; 723 723 724 724 - pinctrl_senoko_novena: senokogrp-novena { 724 724 + pinctrl_senoko_novena: senoko-novenagrp { 725 725 fsl,pins = < 726 726 /* Senoko IRQ line */ 727 727 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 ··· 730 730 >; 731 731 }; 732 732 733 733 - pinctrl_sound_novena: soundgrp-novena { 733 733 + pinctrl_sound_novena: sound-novenagrp { 734 734 fsl,pins = < 735 735 /* Audio power regulator */ 736 736 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 ··· 740 740 >; 741 741 }; 742 742 743 743 - pinctrl_stmpe_novena: stmpegrp-novena { 743 743 + pinctrl_stmpe_novena: stmpe-novenagrp { 744 744 fsl,pins = < 745 745 /* Touchscreen interrupt */ 746 746 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 747 747 >; 748 748 }; 749 749 750 750 - pinctrl_uart2_novena: uart2grp-novena { 750 750 + pinctrl_uart2_novena: uart2-novenagrp { 751 751 fsl,pins = < 752 752 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 753 753 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 754 754 >; 755 755 }; 756 756 757 757 - pinctrl_uart3_novena: uart3grp-novena { 757 757 + pinctrl_uart3_novena: uart3-novenagrp { 758 758 fsl,pins = < 759 759 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 760 760 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 761 761 >; 762 762 }; 763 763 764 764 - pinctrl_uart4_novena: uart4grp-novena { 764 764 + pinctrl_uart4_novena: uart4-novenagrp { 765 765 fsl,pins = < 766 766 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 767 767 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 768 768 >; 769 769 }; 770 770 771 771 - pinctrl_usbotg_novena: usbotggrp-novena { 771 771 + pinctrl_usbotg_novena: usbotg-novenagrp { 772 772 fsl,pins = < 773 773 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 774 774 >; 775 775 }; 776 776 777 777 - pinctrl_usdhc2_novena: usdhc2grp-novena { 777 777 + pinctrl_usdhc2_novena: usdhc2-novenagrp { 778 778 fsl,pins = < 779 779 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 780 780 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 ··· 789 789 >; 790 790 }; 791 791 792 792 - pinctrl_usdhc3_novena: usdhc3grp-novena { 792 792 + pinctrl_usdhc3_novena: usdhc3-novenagrp { 793 793 fsl,pins = < 794 794 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 795 795 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9

+1 -1

arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts

reviewed

··· 546 546 >; 547 547 }; 548 548 549 549 - pinctrl_wifi_npd: wifinpd { 549 549 + pinctrl_wifi_npd: wifinpdgrp { 550 550 fsl,pins = < 551 551 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 552 552 >;

+2 -2

arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts

reviewed

··· 133 133 pinctrl-names = "default"; 134 134 pinctrl-0 = <&pinctrl_usb_eth_chg>; 135 135 136 136 - pinctrl_can1phy: can1phy { 136 136 + pinctrl_can1phy: can1phygrp { 137 137 fsl,pins = < 138 138 /* CAN1_SR */ 139 139 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 ··· 187 187 >; 188 188 }; 189 189 190 190 - pinctrl_wifi_npd: wifinpd { 190 190 + pinctrl_wifi_npd: wifinpdgrp { 191 191 fsl,pins = < 192 192 /* WL_REG_ON */ 193 193 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069

+40 -42

arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts

reviewed

··· 25 25 }; 26 26 27 27 &iomuxc { 28 28 - imx6q-sbc6x { 29 29 - pinctrl_enet: enetgrp { 30 30 - fsl,pins = < 31 31 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 32 32 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 33 33 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 34 34 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 35 35 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 36 36 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 37 37 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 38 38 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 39 39 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 40 40 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 41 41 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 42 42 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 43 43 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 44 44 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 45 45 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 46 46 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 47 47 - >; 48 48 - }; 28 28 + pinctrl_enet: enetgrp { 29 29 + fsl,pins = < 30 30 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 31 31 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 32 32 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 33 33 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 34 34 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 35 35 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 36 36 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 37 37 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 38 38 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 39 39 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 40 40 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 41 41 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 42 42 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 43 43 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 44 44 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 45 45 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 46 46 + >; 47 47 + }; 49 48 50 50 - pinctrl_uart1: uart1grp { 51 51 - fsl,pins = < 52 52 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 53 53 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 54 54 - >; 55 55 - }; 49 49 + pinctrl_uart1: uart1grp { 50 50 + fsl,pins = < 51 51 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 52 52 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 53 53 + >; 54 54 + }; 56 55 57 57 - pinctrl_usbotg: usbotggrp { 58 58 - fsl,pins = < 59 59 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 60 60 - >; 61 61 - }; 56 56 + pinctrl_usbotg: usbotggrp { 57 57 + fsl,pins = < 58 58 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 59 59 + >; 60 60 + }; 62 61 63 63 - pinctrl_usdhc3: usdhc3grp { 64 64 - fsl,pins = < 65 65 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 66 66 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 67 67 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 68 68 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 69 69 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 70 70 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 71 71 - >; 72 72 - }; 62 62 + pinctrl_usdhc3: usdhc3grp { 63 63 + fsl,pins = < 64 64 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 65 65 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 66 66 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 67 67 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 68 68 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 69 69 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 70 70 + >; 73 71 }; 74 72 }; 75 73

-1

arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts

reviewed

··· 51 51 52 52 &backlight { 53 53 pwms = <&pwm2 0 500000 0>; 54 54 - /delete-property/ turn-on-delay-ms; 55 54 }; 56 55 57 56 &can1 {

-1

arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts

reviewed

··· 51 51 52 52 &backlight { 53 53 pwms = <&pwm2 0 500000 0>; 54 54 - /delete-property/ turn-on-delay-ms; 55 54 }; 56 55 57 56 &can1 {

+2 -2

arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts

reviewed

··· 296 296 >; 297 297 }; 298 298 299 299 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 299 299 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 300 300 fsl,pins = < 301 301 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 302 302 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 ··· 307 307 >; 308 308 }; 309 309 310 310 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 310 310 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 311 311 fsl,pins = < 312 312 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 313 313 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9

+1 -1

arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi

reviewed

··· 191 191 "MIC_IN", "Mic Jack", 192 192 "Mic Jack", "Mic Bias", 193 193 "Headphone Jack", "HP_OUT"; 194 194 - model = "imx6q-apalis-sgtl5000"; 194 194 + model = "apalis-imx6"; 195 195 mux-ext-port = <4>; 196 196 mux-int-port = <1>; 197 197 ssi-controller = <&ssi1>;

+212 -214

arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi

reviewed

··· 179 179 pinctrl-names = "default"; 180 180 pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; 181 181 182 182 - imx6qdl-aristainetos { 183 183 - pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { 184 184 - fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>; 185 185 - }; 182 182 + pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbusgrp { 183 183 + fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>; 184 184 + }; 186 185 187 187 - pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { 188 188 - fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>; 189 189 - }; 186 186 + pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbusgrp { 187 187 + fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>; 188 188 + }; 190 189 191 191 - pinctrl_audmux: audmuxgrp { 192 192 - fsl,pins = < 193 193 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 194 194 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 195 195 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 196 196 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 190 190 + pinctrl_audmux: audmuxgrp { 191 191 + fsl,pins = < 192 192 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 193 193 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 194 194 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 195 195 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 196 196 + >; 197 197 + }; 198 198 + 199 199 + pinctrl_backlight: backlightgrp { 200 200 + fsl,pins = < 201 201 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 202 202 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 203 203 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 204 204 + >; 205 205 + }; 206 206 + 207 207 + pinctrl_ecspi2: ecspi2grp { 208 208 + fsl,pins = < 209 209 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 210 210 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 211 211 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 212 212 + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 213 213 + >; 214 214 + }; 215 215 + 216 216 + pinctrl_ecspi4: ecspi4grp { 217 217 + fsl,pins = < 218 218 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 219 219 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 220 220 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 221 221 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 222 222 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ 223 223 + >; 224 224 + }; 225 225 + 226 226 + pinctrl_enet: enetgrp { 227 227 + fsl,pins = < 228 228 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 229 229 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 230 230 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 231 231 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 232 232 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 233 233 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 234 234 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 235 235 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 236 236 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 237 237 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 238 238 + >; 239 239 + }; 240 240 + 241 241 + pinctrl_flexcan1: flexcan1grp { 242 242 + fsl,pins = < 243 243 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 244 244 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 245 245 + >; 246 246 + }; 247 247 + 248 248 + pinctrl_flexcan2: flexcan2grp { 249 249 + fsl,pins = < 250 250 + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 251 251 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 197 252 >; 198 198 - }; 253 253 + }; 199 254 200 200 - pinctrl_backlight: backlightgrp { 201 201 - fsl,pins = < 202 202 - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 203 203 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 204 204 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 255 255 + pinctrl_gpio: gpiogrp { 256 256 + fsl,pins = < 257 257 + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 258 258 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 259 259 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 260 260 + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 261 261 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 262 262 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 263 263 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 264 264 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 265 265 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 266 266 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 267 267 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 268 268 + >; 269 269 + }; 270 270 + 271 271 + pinctrl_gpmi_nand: gpminandgrp { 272 272 + fsl,pins = < 273 273 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 274 274 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 275 275 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 276 276 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 277 277 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 278 278 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 279 279 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 280 280 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 281 281 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 282 282 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 283 283 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 284 284 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 285 285 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 286 286 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 287 287 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 288 288 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 289 289 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 290 290 + >; 291 291 + }; 292 292 + 293 293 + pinctrl_hog: hoggrp { 294 294 + fsl,pins = < 295 295 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 296 296 + >; 297 297 + }; 298 298 + 299 299 + pinctrl_i2c1: i2c1grp { 300 300 + fsl,pins = < 301 301 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 302 302 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 303 303 + >; 304 304 + }; 305 305 + 306 306 + pinctrl_i2c2: i2c2grp { 307 307 + fsl,pins = < 308 308 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 309 309 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 310 310 + >; 311 311 + }; 312 312 + 313 313 + pinctrl_i2c3: i2c3grp { 314 314 + fsl,pins = < 315 315 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 316 316 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 317 317 + >; 318 318 + }; 319 319 + 320 320 + pinctrl_ipu_disp: ipudisp1grp { 321 321 + fsl,pins = < 322 322 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 323 323 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 324 324 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 325 325 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 326 326 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 327 327 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 328 328 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 329 329 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 330 330 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 331 331 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 332 332 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 333 333 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 334 334 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 335 335 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 336 336 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 337 337 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 338 338 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 339 339 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 340 340 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 341 341 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 342 342 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 343 343 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 344 344 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 345 345 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 346 346 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 347 347 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 348 348 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 349 349 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 350 350 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 205 351 >; 206 206 - }; 352 352 + }; 207 353 208 208 - pinctrl_ecspi2: ecspi2grp { 209 209 - fsl,pins = < 210 210 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 211 211 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 212 212 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 213 213 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 214 214 - >; 215 215 - }; 354 354 + pinctrl_uart2: uart2grp { 355 355 + fsl,pins = < 356 356 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 357 357 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 358 358 + >; 359 359 + }; 216 360 217 217 - pinctrl_ecspi4: ecspi4grp { 218 218 - fsl,pins = < 219 219 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 220 220 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 221 221 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 222 222 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 223 223 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ 224 224 - >; 225 225 - }; 361 361 + pinctrl_uart4: uart4grp { 362 362 + fsl,pins = < 363 363 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 364 364 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 365 365 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 366 366 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 367 367 + >; 368 368 + }; 226 369 227 227 - pinctrl_enet: enetgrp { 228 228 - fsl,pins = < 229 229 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 230 230 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 231 231 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 232 232 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 233 233 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 234 234 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 235 235 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 236 236 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 237 237 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 238 238 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 239 239 - >; 240 240 - }; 370 370 + pinctrl_uart5: uart5grp { 371 371 + fsl,pins = < 372 372 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 373 373 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 374 374 + >; 375 375 + }; 241 376 242 242 - pinctrl_flexcan1: flexcan1grp { 243 243 - fsl,pins = < 244 244 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 245 245 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 246 246 - >; 247 247 - }; 377 377 + pinctrl_usbotg: usbotggrp { 378 378 + fsl,pins = < 379 379 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 380 380 + >; 381 381 + }; 248 382 249 249 - pinctrl_flexcan2: flexcan2grp { 250 250 - fsl,pins = < 251 251 - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 252 252 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 253 253 - >; 254 254 - }; 383 383 + pinctrl_usdhc1: usdhc1grp { 384 384 + fsl,pins = < 385 385 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 386 386 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 387 387 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 388 388 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 389 389 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 390 390 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 391 391 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 392 392 + >; 393 393 + }; 255 394 256 256 - pinctrl_gpio: gpiogrp { 257 257 - fsl,pins = < 258 258 - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 259 259 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 260 260 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 261 261 - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 262 262 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 263 263 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 264 264 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 265 265 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 266 266 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 267 267 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 268 268 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 269 269 - >; 270 270 - }; 271 271 - 272 272 - pinctrl_gpmi_nand: gpminandgrp { 273 273 - fsl,pins = < 274 274 - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 275 275 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 276 276 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 277 277 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 278 278 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 279 279 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 280 280 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 281 281 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 282 282 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 283 283 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 284 284 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 285 285 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 286 286 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 287 287 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 288 288 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 289 289 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 290 290 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 291 291 - >; 292 292 - }; 293 293 - 294 294 - pinctrl_hog: hoggrp { 295 295 - fsl,pins = < 296 296 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 297 297 - >; 298 298 - }; 299 299 - 300 300 - pinctrl_i2c1: i2c1grp { 301 301 - fsl,pins = < 302 302 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 303 303 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 304 304 - >; 305 305 - }; 306 306 - 307 307 - pinctrl_i2c2: i2c2grp { 308 308 - fsl,pins = < 309 309 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 310 310 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 311 311 - >; 312 312 - }; 313 313 - 314 314 - pinctrl_i2c3: i2c3grp { 315 315 - fsl,pins = < 316 316 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 317 317 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 318 318 - >; 319 319 - }; 320 320 - 321 321 - pinctrl_ipu_disp: ipudisp1grp { 322 322 - fsl,pins = < 323 323 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 324 324 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 325 325 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 326 326 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 327 327 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 328 328 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 329 329 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 330 330 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 331 331 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 332 332 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 333 333 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 334 334 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 335 335 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 336 336 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 337 337 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 338 338 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 339 339 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 340 340 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 341 341 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 342 342 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 343 343 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 344 344 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 345 345 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 346 346 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 347 347 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 348 348 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 349 349 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 350 350 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 351 351 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 352 352 - >; 353 353 - }; 354 354 - 355 355 - pinctrl_uart2: uart2grp { 356 356 - fsl,pins = < 357 357 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 358 358 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 359 359 - >; 360 360 - }; 361 361 - 362 362 - pinctrl_uart4: uart4grp { 363 363 - fsl,pins = < 364 364 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 365 365 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 366 366 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 367 367 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 368 368 - >; 369 369 - }; 370 370 - 371 371 - pinctrl_uart5: uart5grp { 372 372 - fsl,pins = < 373 373 - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 374 374 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 375 375 - >; 376 376 - }; 377 377 - 378 378 - pinctrl_usbotg: usbotggrp { 379 379 - fsl,pins = < 380 380 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 381 381 - >; 382 382 - }; 383 383 - 384 384 - pinctrl_usdhc1: usdhc1grp { 385 385 - fsl,pins = < 386 386 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 387 387 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 388 388 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 389 389 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 390 390 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 391 391 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 392 392 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 393 393 - >; 394 394 - }; 395 395 - 396 396 - pinctrl_usdhc2: usdhc2grp { 397 397 - fsl,pins = < 398 398 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 399 399 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 400 400 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 401 401 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 402 402 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 403 403 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 404 404 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 405 405 - >; 406 406 - }; 395 395 + pinctrl_usdhc2: usdhc2grp { 396 396 + fsl,pins = < 397 397 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 398 398 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 399 399 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 400 400 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 401 401 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 402 402 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 403 403 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 404 404 + >; 407 405 }; 408 406 };

+3 -3

arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi

reviewed

··· 413 413 pinctrl-names = "default"; 414 414 pinctrl-0 = <&pinctrl_gpio>; 415 415 416 416 - pinctrl_audmux: audmux { 416 416 + pinctrl_audmux: audmuxgrp { 417 417 fsl,pins = < 418 418 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 419 419 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 ··· 599 599 >; 600 600 }; 601 601 602 602 - pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { 602 602 + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbusgrp { 603 603 fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>; 604 604 }; 605 605 606 606 - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { 606 606 + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbusgrp { 607 607 fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>; 608 608 }; 609 609

+1 -1

arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi

reviewed

··· 136 136 "LINE_IN", "Line In Jack", 137 137 "MIC_IN", "Mic Jack", 138 138 "Mic Jack", "Mic Bias"; 139 139 - model = "imx6dl-colibri-sgtl5000"; 139 139 + model = "colibri-imx6"; 140 140 mux-int-port = <1>; 141 141 mux-ext-port = <5>; 142 142 ssi-controller = <&ssi1>;

+67 -69

arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi

reviewed

··· 153 153 }; 154 154 155 155 &iomuxc { 156 156 - cubox_i { 157 157 - pinctrl_cubox_i_hdmi: cubox-i-hdmi { 158 158 - fsl,pins = < 159 159 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 160 160 - >; 161 161 - }; 156 156 + pinctrl_cubox_i_hdmi: cubox-i-hdmigrp { 157 157 + fsl,pins = < 158 158 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 159 159 + >; 160 160 + }; 162 161 163 163 - pinctrl_cubox_i_i2c2: cubox-i-i2c2 { 164 164 - fsl,pins = < 165 165 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 166 166 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 167 167 - >; 168 168 - }; 162 162 + pinctrl_cubox_i_i2c2: cubox-i-i2c2grp { 163 163 + fsl,pins = < 164 164 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 165 165 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 166 166 + >; 167 167 + }; 169 168 170 170 - pinctrl_cubox_i_i2c3: cubox-i-i2c3 { 171 171 - fsl,pins = < 172 172 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 173 173 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 174 174 - >; 175 175 - }; 169 169 + pinctrl_cubox_i_i2c3: cubox-i-i2c3grp { 170 170 + fsl,pins = < 171 171 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 172 172 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 173 173 + >; 174 174 + }; 176 175 177 177 - pinctrl_cubox_i_ir: cubox-i-ir { 178 178 - fsl,pins = < 179 179 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 180 180 - >; 181 181 - }; 176 176 + pinctrl_cubox_i_ir: cubox-i-irgrp { 177 177 + fsl,pins = < 178 178 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 179 179 + >; 180 180 + }; 182 181 183 183 - pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { 184 184 - fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>; 185 185 - }; 182 182 + pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-ledgrp { 183 183 + fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>; 184 184 + }; 186 185 187 187 - pinctrl_cubox_i_spdif: cubox-i-spdif { 188 188 - fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 189 189 - }; 186 186 + pinctrl_cubox_i_spdif: cubox-i-spdifgrp { 187 187 + fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 188 188 + }; 190 189 191 191 - pinctrl_cubox_i_usbh1: cubox-i-usbh1 { 192 192 - fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>; 193 193 - }; 190 190 + pinctrl_cubox_i_usbh1: cubox-i-usbh1grp { 191 191 + fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>; 192 192 + }; 194 193 195 195 - pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { 196 196 - fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 197 197 - }; 194 194 + pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbusgrp { 195 195 + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 196 196 + }; 198 197 199 199 - pinctrl_cubox_i_usbotg: cubox-i-usbotg { 200 200 - /* 201 201 - * The Cubox-i pulls ID low, but as it's pointless 202 202 - * leaving it as a pull-up, even if it is just 10uA. 203 203 - */ 204 204 - fsl,pins = < 205 205 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 206 206 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 207 207 - >; 208 208 - }; 198 198 + pinctrl_cubox_i_usbotg: cubox-i-usbotggrp { 199 199 + /* 200 200 + * The Cubox-i pulls ID low, but as it's pointless 201 201 + * leaving it as a pull-up, even if it is just 10uA. 202 202 + */ 203 203 + fsl,pins = < 204 204 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 205 205 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 206 206 + >; 207 207 + }; 209 208 210 210 - pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { 211 211 - fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>; 212 212 - }; 209 209 + pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbusgrp { 210 210 + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>; 211 211 + }; 213 212 214 214 - pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { 215 215 - fsl,pins = < 216 216 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 217 217 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 218 218 - >; 219 219 - }; 213 213 + pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-auxgrp { 214 214 + fsl,pins = < 215 215 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 216 216 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 217 217 + >; 218 218 + }; 220 219 221 221 - pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { 222 222 - fsl,pins = < 223 223 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 224 224 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 225 225 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 226 226 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 227 227 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 228 228 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 229 229 - >; 230 230 - }; 220 220 + pinctrl_cubox_i_usdhc2: cubox-i-usdhc2grp { 221 221 + fsl,pins = < 222 222 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 223 223 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 224 224 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 225 225 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 226 226 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 227 227 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 228 228 + >; 229 229 + }; 231 230 232 232 - pinctrl_gpio_key: gpio-key { 233 233 - fsl,pins = < 234 234 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 235 235 - >; 236 236 - }; 231 231 + pinctrl_gpio_key: gpio-keygrp { 232 232 + fsl,pins = < 233 233 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 234 234 + >; 237 235 }; 238 236 }; 239 237

+87 -89

arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi

reviewed

··· 47 47 pinctrl-names = "default"; 48 48 pinctrl-0 = <&pinctrl_hog>; 49 49 50 50 - imx6qdl-dfi-fs700-m60 { 51 51 - pinctrl_hog: hoggrp { 52 52 - fsl,pins = < 53 53 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 54 54 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ 55 55 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ 56 56 - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ 57 57 - >; 58 58 - }; 50 50 + pinctrl_hog: hoggrp { 51 51 + fsl,pins = < 52 52 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 53 53 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ 54 54 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ 55 55 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ 56 56 + >; 57 57 + }; 59 58 60 60 - pinctrl_enet: enetgrp { 61 61 - fsl,pins = < 62 62 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 63 63 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 64 64 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 65 65 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 66 66 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 67 67 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 68 68 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 69 69 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 70 70 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 71 71 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 72 72 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 73 73 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 74 74 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 75 75 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 76 76 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 77 77 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 78 78 - >; 79 79 - }; 59 59 + pinctrl_enet: enetgrp { 60 60 + fsl,pins = < 61 61 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 62 62 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 63 63 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 64 64 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 65 65 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 66 66 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 67 67 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 68 68 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 69 69 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 70 70 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 71 71 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 72 72 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 73 73 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 74 74 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 75 75 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 76 76 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 77 77 + >; 78 78 + }; 80 79 81 81 - pinctrl_i2c2: i2c2grp { 82 82 - fsl,pins = < 83 83 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 84 84 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 85 85 - >; 86 86 - }; 80 80 + pinctrl_i2c2: i2c2grp { 81 81 + fsl,pins = < 82 82 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 83 83 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 84 84 + >; 85 85 + }; 87 86 88 88 - pinctrl_uart1: uart1grp { 89 89 - fsl,pins = < 90 90 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 91 91 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 92 92 - >; 93 93 - }; 87 87 + pinctrl_uart1: uart1grp { 88 88 + fsl,pins = < 89 89 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 90 90 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 91 91 + >; 92 92 + }; 94 93 95 95 - pinctrl_usbotg: usbotggrp { 96 96 - fsl,pins = < 97 97 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 98 98 - >; 99 99 - }; 94 94 + pinctrl_usbotg: usbotggrp { 95 95 + fsl,pins = < 96 96 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 97 97 + >; 98 98 + }; 100 99 101 101 - pinctrl_usdhc2: usdhc2grp { 102 102 - fsl,pins = < 103 103 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 104 104 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 105 105 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 106 106 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 107 107 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 108 108 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 109 109 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ 110 110 - >; 111 111 - }; 100 100 + pinctrl_usdhc2: usdhc2grp { 101 101 + fsl,pins = < 102 102 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 103 103 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 104 104 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 105 105 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 106 106 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 107 107 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 108 108 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ 109 109 + >; 110 110 + }; 112 111 113 113 - pinctrl_usdhc3: usdhc3grp { 114 114 - fsl,pins = < 115 115 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 116 116 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 117 117 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 118 118 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 119 119 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 120 120 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 121 121 - >; 122 122 - }; 112 112 + pinctrl_usdhc3: usdhc3grp { 113 113 + fsl,pins = < 114 114 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 115 115 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 116 116 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 117 117 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 118 118 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 119 119 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 120 120 + >; 121 121 + }; 123 122 124 124 - pinctrl_usdhc4: usdhc4grp { 125 125 - fsl,pins = < 126 126 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 127 127 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 128 128 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 129 129 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 130 130 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 131 131 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 132 132 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 133 133 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 134 134 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 135 135 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 136 136 - >; 137 137 - }; 123 123 + pinctrl_usdhc4: usdhc4grp { 124 124 + fsl,pins = < 125 125 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 126 126 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 127 127 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 128 128 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 129 129 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 130 130 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 131 131 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 132 132 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 133 133 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 134 134 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 135 135 + >; 136 136 + }; 138 137 139 139 - pinctrl_ecspi3: ecspi3grp { 140 140 - fsl,pins = < 141 141 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 142 142 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 143 143 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 144 144 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ 145 145 - >; 146 146 - }; 138 138 + pinctrl_ecspi3: ecspi3grp { 139 139 + fsl,pins = < 140 140 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 141 141 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 142 142 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 143 143 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ 144 144 + >; 147 145 }; 148 146 }; 149 147

+20 -1

arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi

reviewed

··· 56 56 }; 57 57 58 58 gpio-keys { 59 59 - #size-cells = <0>; 60 59 compatible = "gpio-keys"; 61 60 62 61 button-0 { ··· 143 144 panel { 144 145 backlight = <&display_bl>; 145 146 compatible = "edt,etm0700g0edh6"; 147 147 + power-supply = <&reg_panel_3v3>; 146 148 147 149 port { 148 150 lcd_panel_in: endpoint { 149 151 remote-endpoint = <&lcd_display_out>; 150 152 }; 151 153 }; 154 154 + }; 155 155 + 156 156 + /* Filtered supply voltage */ 157 157 + reg_pdk2_24v: regulator-pdk2-24v { 158 158 + compatible = "regulator-fixed"; 159 159 + regulator-always-on; 160 160 + regulator-max-microvolt = <24000000>; 161 161 + regulator-min-microvolt = <24000000>; 162 162 + regulator-name = "24V_PDK2"; 163 163 + }; 164 164 + 165 165 + /* 560-200 U1 */ 166 166 + reg_panel_3v3: regulator-panel-3v3 { 167 167 + compatible = "regulator-fixed"; 168 168 + regulator-always-on; 169 169 + regulator-min-microvolt = <3300000>; 170 170 + regulator-max-microvolt = <3300000>; 171 171 + regulator-name = "3V3_PANEL"; 172 172 + vin-supply = <&reg_pdk2_24v>; 152 173 }; 153 174 154 175 sound {

-2

arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi

reviewed

··· 256 256 regulator-max-microvolt = <1527272>; 257 257 regulator-min-microvolt = <787500>; 258 258 regulator-ramp-delay = <7000>; 259 259 - regulator-suspend-mem-microvolt = <1040000>; 260 259 }; 261 260 262 261 sw2_reg: sw2 { ··· 274 275 regulator-max-microvolt = <1527272>; 275 276 regulator-min-microvolt = <787500>; 276 277 regulator-ramp-delay = <7000>; 277 277 - regulator-suspend-mem-microvolt = <980000>; 278 278 }; 279 279 280 280 sw4_reg: sw4 {

+3 -3

arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi

reviewed

··· 253 253 >; 254 254 }; 255 255 256 256 - pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { 256 256 + pinctrl_ecspi1_gpio: ecspi1gpiogrp { 257 257 fsl,pins = < 258 258 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 259 259 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 ··· 349 349 >; 350 350 }; 351 351 352 352 - pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { 352 352 + pinctrl_usdhc1_gpio: usdhc1gpiogrp { 353 353 fsl,pins = < 354 354 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 355 355 >; ··· 366 366 >; 367 367 }; 368 368 369 369 - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 369 369 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 370 370 fsl,pins = < 371 371 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 372 372 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0

+19 -20

arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi

reviewed

··· 330 330 }; 331 331 332 332 &iomuxc { 333 333 - 334 333 pinctrl_audmux: audmuxgrp { 335 334 fsl,pins = < 336 335 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 ··· 381 382 >; 382 383 }; 383 384 384 384 - pinctrl_emcon_gpio1: emcongpio1 { 385 385 + pinctrl_emcon_gpio1: emcongpio1grp { 385 386 fsl,pins = < 386 387 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 387 388 >; 388 389 }; 389 390 390 390 - pinctrl_emcon_gpio2: emcongpio2 { 391 391 + pinctrl_emcon_gpio2: emcongpio2grp { 391 392 fsl,pins = < 392 393 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 393 394 >; 394 395 }; 395 396 396 396 - pinctrl_emcon_gpio3: emcongpio3 { 397 397 + pinctrl_emcon_gpio3: emcongpio3grp { 397 398 fsl,pins = < 398 399 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 399 400 >; 400 401 }; 401 402 402 402 - pinctrl_emcon_gpio4: emcongpio4 { 403 403 + pinctrl_emcon_gpio4: emcongpio4grp { 403 404 fsl,pins = < 404 405 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 405 406 >; 406 407 }; 407 408 408 408 - pinctrl_emcon_gpio5: emcongpio5 { 409 409 + pinctrl_emcon_gpio5: emcongpio5grp { 409 410 fsl,pins = < 410 411 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 411 412 >; 412 413 }; 413 414 414 414 - pinctrl_emcon_gpio6: emcongpio6 { 415 415 + pinctrl_emcon_gpio6: emcongpio6grp { 415 416 fsl,pins = < 416 417 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 417 418 >; 418 419 }; 419 420 420 420 - pinctrl_emcon_gpio7: emcongpio7 { 421 421 + pinctrl_emcon_gpio7: emcongpio7grp { 421 422 fsl,pins = < 422 423 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 423 424 >; 424 425 }; 425 426 426 426 - pinctrl_emcon_gpio8: emcongpio8 { 427 427 + pinctrl_emcon_gpio8: emcongpio8grp { 427 428 fsl,pins = < 428 429 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 429 430 >; 430 431 }; 431 432 432 432 - pinctrl_emcon_irq_a: emconirqa { 433 433 + pinctrl_emcon_irq_a: emconirqagrp { 433 434 fsl,pins = < 434 435 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 435 436 >; 436 437 }; 437 438 438 438 - pinctrl_emcon_irq_b: emconirqb { 439 439 + pinctrl_emcon_irq_b: emconirqbgrp { 439 440 fsl,pins = < 440 441 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 441 442 >; 442 443 }; 443 444 444 444 - pinctrl_emcon_irq_c: emconirqc { 445 445 + pinctrl_emcon_irq_c: emconirqcgrp { 445 446 fsl,pins = < 446 447 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 447 448 >; 448 449 }; 449 450 450 450 - pinctrl_emcon_irq_pwr: emconirqpwr { 451 451 + pinctrl_emcon_irq_pwr: emconirqpwrgrp { 451 452 fsl,pins = < 452 453 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 453 454 >; 454 455 }; 455 456 456 456 - pinctrl_emcon_wake: emconwake { 457 457 + pinctrl_emcon_wake: emconwakegrp { 457 458 fsl,pins = < 458 459 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 459 460 >; ··· 502 503 >; 503 504 }; 504 505 505 505 - pinctrl_irq_touch1: irqtouch1 { 506 506 + pinctrl_irq_touch1: irqtouch1grp { 506 507 fsl,pins = < 507 508 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 508 509 >; 509 510 }; 510 511 511 511 - pinctrl_irq_touch2: irqtouch2 { 512 512 + pinctrl_irq_touch2: irqtouch2grp { 512 513 fsl,pins = < 513 514 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 514 515 >; ··· 551 552 >; 552 553 }; 553 554 554 554 - pinctrl_pwm_fan: pwmfan { 555 555 + pinctrl_pwm_fan: pwmfangrp { 555 556 fsl,pins = < 556 557 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 557 558 >; ··· 564 565 >; 565 566 }; 566 567 567 567 - pinctrl_rgb_bl_en: rgbenable { 568 568 + pinctrl_rgb_bl_en: rgbenablegrp { 568 569 fsl,pins = < 569 570 MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 570 571 >; ··· 616 617 >; 617 618 }; 618 619 619 619 - pinctrl_spdif_in: spdifin { 620 620 + pinctrl_spdif_in: spdifingrp { 620 621 fsl,pins = < 621 622 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 622 623 >; 623 624 }; 624 625 625 625 - pinctrl_spdif_out: spdifout { 626 626 + pinctrl_spdif_out: spdifoutgrp { 626 627 fsl,pins = < 627 628 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 628 629 >;

+2 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi

reviewed

··· 770 770 >; 771 771 }; 772 772 773 773 - pinctrl_pwm4_backlight: pwm4grpbacklight { 773 773 + pinctrl_pwm4_backlight: pwm4backlightgrp { 774 774 fsl,pins = < 775 775 /* LVDS_PWM J6.5 */ 776 776 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 777 777 >; 778 778 }; 779 779 780 780 - pinctrl_pwm4_dio: pwm4grpdio { 780 780 + pinctrl_pwm4_dio: pwm4diogrp { 781 781 fsl,pins = < 782 782 /* DIO3 J16.4 */ 783 783 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1

+79 -81

arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi

reviewed

··· 223 223 }; 224 224 225 225 &iomuxc { 226 226 - hummingboard { 227 227 - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { 228 228 - fsl,pins = < 229 229 - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 230 230 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 231 231 - >; 232 232 - }; 226 226 + pinctrl_hummingboard_flexcan1: hummingboard-flexcan1grp { 227 227 + fsl,pins = < 228 228 + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 229 229 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 230 230 + >; 231 231 + }; 233 232 234 234 - pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { 235 235 - fsl,pins = < 236 236 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 237 237 - >; 238 238 - }; 233 233 + pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5grp { 234 234 + fsl,pins = < 235 235 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 236 236 + >; 237 237 + }; 239 238 240 240 - pinctrl_hummingboard_hdmi: hummingboard-hdmi { 241 241 - fsl,pins = < 242 242 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 243 243 - >; 244 244 - }; 239 239 + pinctrl_hummingboard_hdmi: hummingboard-hdmigrp { 240 240 + fsl,pins = < 241 241 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 242 242 + >; 243 243 + }; 245 244 246 246 - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { 247 247 - fsl,pins = < 248 248 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 249 249 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 250 250 - >; 251 251 - }; 245 245 + pinctrl_hummingboard_i2c1: hummingboard-i2c1grp { 246 246 + fsl,pins = < 247 247 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 248 248 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 249 249 + >; 250 250 + }; 252 251 253 253 - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { 254 254 - fsl,pins = < 255 255 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 256 256 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 257 257 - >; 258 258 - }; 252 252 + pinctrl_hummingboard_i2c2: hummingboard-i2c2grp { 253 253 + fsl,pins = < 254 254 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 255 255 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 256 256 + >; 257 257 + }; 259 258 260 260 - pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { 261 261 - fsl,pins = < 262 262 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 263 263 - >; 264 264 - }; 259 259 + pinctrl_hummingboard_pcie_reset: hummingboard-pcie-resetgrp { 260 260 + fsl,pins = < 261 261 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 262 262 + >; 263 263 + }; 265 264 266 266 - pinctrl_hummingboard_pwm1: pwm1grp { 267 267 - fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>; 268 268 - }; 265 265 + pinctrl_hummingboard_pwm1: pwm1grp { 266 266 + fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>; 267 267 + }; 269 268 270 270 - pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { 271 271 - fsl,pins = < 272 272 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 273 273 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 274 274 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 275 275 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 276 276 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 277 277 - >; 278 278 - }; 269 269 + pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000grp { 270 270 + fsl,pins = < 271 271 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 272 272 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 273 273 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 274 274 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 275 275 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 276 276 + >; 277 277 + }; 279 278 280 280 - pinctrl_hummingboard_spdif: hummingboard-spdif { 281 281 - fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 282 282 - }; 279 279 + pinctrl_hummingboard_spdif: hummingboard-spdifgrp { 280 280 + fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 281 281 + }; 283 282 284 284 - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { 285 285 - fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; 286 286 - }; 283 283 + pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbusgrp { 284 284 + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; 285 285 + }; 287 286 288 288 - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { 289 289 - /* 290 290 - * We want it pulled down for a fixed host connection. 291 291 - */ 292 292 - fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>; 293 293 - }; 287 287 + pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-idgrp { 288 288 + /* 289 289 + * We want it pulled down for a fixed host connection. 290 290 + */ 291 291 + fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>; 292 292 + }; 294 293 295 295 - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { 296 296 - fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; 297 297 - }; 294 294 + pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbusgrp { 295 295 + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; 296 296 + }; 298 297 299 299 - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { 300 300 - fsl,pins = < 301 301 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 302 302 - >; 303 303 - }; 298 298 + pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-auxgrp { 299 299 + fsl,pins = < 300 300 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 301 301 + >; 302 302 + }; 304 303 305 305 - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { 306 306 - fsl,pins = < 307 307 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 308 308 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 309 309 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 310 310 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 311 311 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 312 312 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 313 313 - >; 314 314 - }; 315 315 - pinctrl_hummingboard_vmmc: hummingboard-vmmc { 316 316 - fsl,pins = < 317 317 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 318 318 - >; 319 319 - }; 304 304 + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2grp { 305 305 + fsl,pins = < 306 306 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 307 307 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 308 308 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 309 309 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 310 310 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 311 311 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 312 312 + >; 313 313 + }; 314 314 + pinctrl_hummingboard_vmmc: hummingboard-vmmcgrp { 315 315 + fsl,pins = < 316 316 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 317 317 + >; 320 318 }; 321 319 }; 322 320

+14 -16

arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi

reviewed

··· 42 42 */ 43 43 44 44 &iomuxc { 45 45 - hummingboard2 { 46 46 - pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { 47 47 - fsl,pins = < 48 48 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 49 49 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 50 50 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 51 51 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 52 52 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 53 53 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 54 54 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 55 55 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 56 56 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 57 57 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 58 58 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 59 59 - >; 60 60 - }; 45 45 + pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3grp { 46 46 + fsl,pins = < 47 47 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 48 48 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 49 49 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 50 50 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 51 51 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 52 52 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 53 53 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 54 54 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 55 55 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 56 56 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 57 57 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 58 58 + >; 61 59 }; 62 60 }; 63 61

+240 -242

arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi

reviewed

··· 261 261 pinctrl-names = "default"; 262 262 pinctrl-0 = <&pinctrl_hog>; 263 263 264 264 - hummingboard2 { 265 265 - pinctrl_hog: hoggrp { 264 264 + pinctrl_hog: hoggrp { 266 265 fsl,pins = < 267 267 - /* 268 268 - * 36 pin headers GPIO description. The pins 269 269 - * numbering as following - 270 270 - * 271 271 - * 3.2v 5v 74 75 272 272 - * 73 72 71 70 273 273 - * 69 68 67 66 274 274 - * 275 275 - * 77 78 79 76 276 276 - * 65 64 61 60 277 277 - * 53 52 51 50 278 278 - * 49 48 166 132 279 279 - * 95 94 90 91 280 280 - * GND 54 24 204 281 281 - * 282 282 - * The GPIO numbers can be extracted using 283 283 - * signal name from below. 284 284 - * Example - 285 285 - * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is 286 286 - * GPIO(3,10) which is (3-1)*32+10 = gpio 74 287 287 - * 288 288 - * i.e. The mapping of GPIO(X,Y) to Linux gpio 289 289 - * number is : gpio number = (X-1) * 32 + Y 290 290 - */ 291 291 - /* DI1_PIN15 */ 292 292 - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 293 293 - /* DI1_PIN02 */ 294 294 - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 295 295 - /* DISP1_DATA00 */ 296 296 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 297 297 - /* DISP1_DATA01 */ 298 298 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 299 299 - /* DISP1_DATA02 */ 300 300 - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 301 301 - /* DISP1_DATA03 */ 302 302 - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 303 303 - /* DISP1_DATA04 */ 304 304 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 305 305 - /* DISP1_DATA05 */ 306 306 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 307 307 - /* DISP1_DATA06 */ 308 308 - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 309 309 - /* DISP1_DATA07 */ 310 310 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 311 311 - /* DI1_D0_CS */ 312 312 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 313 313 - /* DI1_D1_CS */ 314 314 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 315 315 - /* DI1_PIN01 */ 316 316 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 317 317 - /* DI1_PIN03 */ 318 318 - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 319 319 - /* DISP1_DATA08 */ 320 320 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 321 321 - /* DISP1_DATA09 */ 322 322 - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 323 323 - /* DISP1_DATA10 */ 324 324 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 325 325 - /* DISP1_DATA11 */ 326 326 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 327 327 - /* DISP1_DATA12 */ 328 328 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 329 329 - /* DISP1_DATA13 */ 330 330 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 331 331 - /* DISP1_DATA14 */ 332 332 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 333 333 - /* DISP1_DATA15 */ 334 334 - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 335 335 - /* DISP1_DATA16 */ 336 336 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 337 337 - /* DISP1_DATA17 */ 338 338 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 339 339 - /* DISP1_DATA18 */ 340 340 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 341 341 - /* DISP1_DATA19 */ 342 342 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 343 343 - /* DISP1_DATA20 */ 344 344 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 345 345 - /* DISP1_DATA21 */ 346 346 - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 347 347 - /* DISP1_DATA22 */ 348 348 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 349 349 - /* DISP1_DATA23 */ 350 350 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 351 351 - /* DI1_DISP_CLK */ 352 352 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 353 353 - /* SPDIF_IN */ 354 354 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 355 355 - /* SPDIF_OUT */ 356 356 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 357 357 - 358 358 - /* MikroBUS GPIO pin number 10 */ 359 359 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 360 360 - >; 361 361 - }; 362 362 - 363 363 - pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { 364 364 - fsl,pins = < 365 365 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 366 366 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 367 367 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 368 368 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ 369 369 - >; 370 370 - }; 371 371 - 372 372 - pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { 373 373 - fsl,pins = < 374 374 - MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 375 375 - >; 376 376 - }; 377 377 - 378 378 - pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { 379 379 - fsl,pins = < 380 380 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 381 381 - >; 382 382 - }; 383 383 - 384 384 - pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { 385 385 - fsl,pins = < 386 386 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 387 387 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 388 388 - >; 389 389 - }; 390 390 - 391 391 - pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { 392 392 - fsl,pins = < 393 393 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 394 394 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 395 395 - >; 396 396 - }; 397 397 - 398 398 - pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { 399 399 - fsl,pins = < 400 400 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 401 401 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 402 402 - >; 403 403 - }; 404 404 - 405 405 - pinctrl_hummingboard2_mipi: hummingboard2_mipi { 406 406 - fsl,pins = < 407 407 - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 408 408 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 409 409 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 410 410 - >; 411 411 - }; 412 412 - 413 413 - pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { 414 414 - fsl,pins = < 415 415 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 416 416 - >; 417 417 - }; 418 418 - 419 419 - pinctrl_hummingboard2_pwm1: pwm1grp { 420 420 - fsl,pins = < 421 421 - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 422 422 - >; 423 423 - }; 424 424 - 425 425 - pinctrl_hummingboard2_pwm3: pwm3grp { 426 426 - fsl,pins = < 427 427 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 428 428 - >; 429 429 - }; 430 430 - 431 431 - pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { 432 432 - fsl,pins = < 433 433 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 434 434 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 435 435 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 436 436 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 437 437 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 438 438 - >; 439 439 - }; 440 440 - 441 441 - pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { 442 442 - fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; 443 443 - }; 444 444 - 445 445 - pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { 446 446 - fsl,pins = <MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0>; 447 447 - }; 448 448 - 449 449 - pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { 450 450 - fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0>; 451 451 - }; 452 452 - 453 453 - pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { 454 266 /* 455 455 - * We want it pulled down for a fixed host connection. 267 267 + * 36 pin headers GPIO description. The pins 268 268 + * numbering as following - 269 269 + * 270 270 + * 3.2v 5v 74 75 271 271 + * 73 72 71 70 272 272 + * 69 68 67 66 273 273 + * 274 274 + * 77 78 79 76 275 275 + * 65 64 61 60 276 276 + * 53 52 51 50 277 277 + * 49 48 166 132 278 278 + * 95 94 90 91 279 279 + * GND 54 24 204 280 280 + * 281 281 + * The GPIO numbers can be extracted using 282 282 + * signal name from below. 283 283 + * Example - 284 284 + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is 285 285 + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 286 286 + * 287 287 + * i.e. The mapping of GPIO(X,Y) to Linux gpio 288 288 + * number is : gpio number = (X-1) * 32 + Y 456 289 */ 457 457 - fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; 458 458 - }; 290 290 + /* DI1_PIN15 */ 291 291 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 292 292 + /* DI1_PIN02 */ 293 293 + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 294 294 + /* DISP1_DATA00 */ 295 295 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 296 296 + /* DISP1_DATA01 */ 297 297 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 298 298 + /* DISP1_DATA02 */ 299 299 + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 300 300 + /* DISP1_DATA03 */ 301 301 + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 302 302 + /* DISP1_DATA04 */ 303 303 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 304 304 + /* DISP1_DATA05 */ 305 305 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 306 306 + /* DISP1_DATA06 */ 307 307 + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 308 308 + /* DISP1_DATA07 */ 309 309 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 310 310 + /* DI1_D0_CS */ 311 311 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 312 312 + /* DI1_D1_CS */ 313 313 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 314 314 + /* DI1_PIN01 */ 315 315 + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 316 316 + /* DI1_PIN03 */ 317 317 + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 318 318 + /* DISP1_DATA08 */ 319 319 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 320 320 + /* DISP1_DATA09 */ 321 321 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 322 322 + /* DISP1_DATA10 */ 323 323 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 324 324 + /* DISP1_DATA11 */ 325 325 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 326 326 + /* DISP1_DATA12 */ 327 327 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 328 328 + /* DISP1_DATA13 */ 329 329 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 330 330 + /* DISP1_DATA14 */ 331 331 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 332 332 + /* DISP1_DATA15 */ 333 333 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 334 334 + /* DISP1_DATA16 */ 335 335 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 336 336 + /* DISP1_DATA17 */ 337 337 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 338 338 + /* DISP1_DATA18 */ 339 339 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 340 340 + /* DISP1_DATA19 */ 341 341 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 342 342 + /* DISP1_DATA20 */ 343 343 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 344 344 + /* DISP1_DATA21 */ 345 345 + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 346 346 + /* DISP1_DATA22 */ 347 347 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 348 348 + /* DISP1_DATA23 */ 349 349 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 350 350 + /* DI1_DISP_CLK */ 351 351 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 352 352 + /* SPDIF_IN */ 353 353 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 354 354 + /* SPDIF_OUT */ 355 355 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 459 356 460 460 - pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { 461 461 - fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; 462 462 - }; 357 357 + /* MikroBUS GPIO pin number 10 */ 358 358 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 359 359 + >; 360 360 + }; 463 361 464 464 - pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { 465 465 - fsl,pins = < 466 466 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 467 467 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 468 468 - >; 469 469 - }; 362 362 + pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { 363 363 + fsl,pins = < 364 364 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 365 365 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 366 366 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 367 367 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ 368 368 + >; 369 369 + }; 470 370 471 471 - pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { 472 472 - fsl,pins = < 473 473 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 474 474 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 475 475 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 476 476 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 477 477 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 478 478 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 479 479 - >; 480 480 - }; 371 371 + pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9grp { 372 372 + fsl,pins = < 373 373 + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 374 374 + >; 375 375 + }; 481 376 482 482 - pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { 483 483 - fsl,pins = < 484 484 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 485 485 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 486 486 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 487 487 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 488 488 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 489 489 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 490 490 - >; 491 491 - }; 377 377 + pinctrl_hummingboard2_hdmi: hummingboard2-hdmigrp { 378 378 + fsl,pins = < 379 379 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 380 380 + >; 381 381 + }; 492 382 493 493 - pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { 494 494 - fsl,pins = < 495 495 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 496 496 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 497 497 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 498 498 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 499 499 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 500 500 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 501 501 - >; 502 502 - }; 383 383 + pinctrl_hummingboard2_i2c1: hummingboard2-i2c1grp { 384 384 + fsl,pins = < 385 385 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 386 386 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 387 387 + >; 388 388 + }; 503 389 504 504 - pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { 505 505 - fsl,pins = < 506 506 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 507 507 - >; 508 508 - }; 390 390 + pinctrl_hummingboard2_i2c2: hummingboard2-i2c2grp { 391 391 + fsl,pins = < 392 392 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 393 393 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 394 394 + >; 395 395 + }; 509 396 510 510 - pinctrl_hummingboard2_uart3: hummingboard2-uart3 { 511 511 - fsl,pins = < 512 512 - MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 513 513 - MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 514 514 - >; 515 515 - }; 397 397 + pinctrl_hummingboard2_i2c3: hummingboard2-i2c3grp { 398 398 + fsl,pins = < 399 399 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 400 400 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 401 401 + >; 402 402 + }; 403 403 + 404 404 + pinctrl_hummingboard2_mipi: hummingboard2_mipigrp { 405 405 + fsl,pins = < 406 406 + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 407 407 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 408 408 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 409 409 + >; 410 410 + }; 411 411 + 412 412 + pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-resetgrp { 413 413 + fsl,pins = < 414 414 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 415 415 + >; 416 416 + }; 417 417 + 418 418 + pinctrl_hummingboard2_pwm1: pwm1grp { 419 419 + fsl,pins = < 420 420 + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 421 421 + >; 422 422 + }; 423 423 + 424 424 + pinctrl_hummingboard2_pwm3: pwm3grp { 425 425 + fsl,pins = < 426 426 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 427 427 + >; 428 428 + }; 429 429 + 430 430 + pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000grp { 431 431 + fsl,pins = < 432 432 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 433 433 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 434 434 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 435 435 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 436 436 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 437 437 + >; 438 438 + }; 439 439 + 440 440 + pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbusgrp { 441 441 + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; 442 442 + }; 443 443 + 444 444 + pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbusgrp { 445 445 + fsl,pins = <MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0>; 446 446 + }; 447 447 + 448 448 + pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbusgrp { 449 449 + fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0>; 450 450 + }; 451 451 + 452 452 + pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-idgrp { 453 453 + /* 454 454 + * We want it pulled down for a fixed host connection. 455 455 + */ 456 456 + fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; 457 457 + }; 458 458 + 459 459 + pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbusgrp { 460 460 + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; 461 461 + }; 462 462 + 463 463 + pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-auxgrp { 464 464 + fsl,pins = < 465 465 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 466 466 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 467 467 + >; 468 468 + }; 469 469 + 470 470 + pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2grp { 471 471 + fsl,pins = < 472 472 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 473 473 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 474 474 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 475 475 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 476 476 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 477 477 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 478 478 + >; 479 479 + }; 480 480 + 481 481 + pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhzgrp { 482 482 + fsl,pins = < 483 483 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 484 484 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 485 485 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 486 486 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 487 487 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 488 488 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 489 489 + >; 490 490 + }; 491 491 + 492 492 + pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhzgrp { 493 493 + fsl,pins = < 494 494 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 495 495 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 496 496 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 497 497 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 498 498 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 499 499 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 500 500 + >; 501 501 + }; 502 502 + 503 503 + pinctrl_hummingboard2_vmmc: hummingboard2-vmmcgrp { 504 504 + fsl,pins = < 505 505 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 506 506 + >; 507 507 + }; 508 508 + 509 509 + pinctrl_hummingboard2_uart3: hummingboard2-uart3grp { 510 510 + fsl,pins = < 511 511 + MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 512 512 + MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 513 513 + >; 516 514 }; 517 515 }; 518 516

+1 -1

arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi

reviewed

··· 728 728 >; 729 729 }; 730 730 731 731 - pinctrl_wdog1: wdog1rp { 731 731 + pinctrl_wdog1: wdog1grp { 732 732 fsl,pins = < 733 733 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 734 734 >;

+14

arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi

reviewed

··· 106 106 vin-supply = <&reg_mba6_3p3v>; 107 107 }; 108 108 109 109 + reserved-memory { 110 110 + #address-cells = <1>; 111 111 + #size-cells = <1>; 112 112 + ranges; 113 113 + 114 114 + linux,cma { 115 115 + compatible = "shared-dma-pool"; 116 116 + reusable; 117 117 + size = <0x14000000>; 118 118 + alloc-ranges = <0x10000000 0x20000000>; 119 119 + linux,cma-default; 120 120 + }; 121 121 + }; 122 122 + 109 123 sound { 110 124 compatible = "fsl,imx-audio-tlv320aic32x4"; 111 125 pinctrl-names = "default";

+176 -178

arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi

reviewed

··· 276 276 pinctrl-0 = <&pinctrl_j10>; 277 277 pinctrl-1 = <&pinctrl_j28>; 278 278 279 279 - imx6dl-nit6xlite { 280 280 - pinctrl_audmux: audmuxgrp { 281 281 - fsl,pins = < 282 282 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 283 283 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 284 284 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 285 285 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 286 286 - >; 287 287 - }; 279 279 + pinctrl_audmux: audmuxgrp { 280 280 + fsl,pins = < 281 281 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 282 282 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 283 283 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 284 284 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 285 285 + >; 286 286 + }; 288 287 289 289 - pinctrl_ecspi1: ecspi1grp { 290 290 - fsl,pins = < 291 291 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 292 292 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 293 293 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 294 294 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 295 295 - >; 296 296 - }; 288 288 + pinctrl_ecspi1: ecspi1grp { 289 289 + fsl,pins = < 290 290 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 291 291 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 292 292 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 293 293 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 294 294 + >; 295 295 + }; 297 296 298 298 - pinctrl_enet: enetgrp { 299 299 - fsl,pins = < 300 300 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 301 301 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 302 302 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 303 303 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 304 304 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 305 305 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 306 306 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 307 307 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 308 308 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 309 309 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 310 310 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 311 311 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 312 312 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 313 313 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 314 314 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 315 315 - /* Phy reset */ 316 316 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 317 317 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 318 318 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 319 319 - >; 320 320 - }; 297 297 + pinctrl_enet: enetgrp { 298 298 + fsl,pins = < 299 299 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 300 300 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 301 301 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 302 302 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 303 303 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 304 304 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 305 305 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 306 306 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 307 307 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 308 308 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 309 309 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 310 310 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 311 311 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 312 312 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 313 313 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 314 314 + /* Phy reset */ 315 315 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 316 316 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 317 317 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 318 318 + >; 319 319 + }; 321 320 322 322 - pinctrl_gpio_keys: gpio-keysgrp { 323 323 - fsl,pins = < 324 324 - /* Home Button: J14 pin 5 */ 325 325 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 326 326 - /* Back Button: J14 pin 7 */ 327 327 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 328 328 - >; 329 329 - }; 321 321 + pinctrl_gpio_keys: gpio-keysgrp { 322 322 + fsl,pins = < 323 323 + /* Home Button: J14 pin 5 */ 324 324 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 325 325 + /* Back Button: J14 pin 7 */ 326 326 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 327 327 + >; 328 328 + }; 330 329 331 331 - pinctrl_i2c1: i2c1grp { 332 332 - fsl,pins = < 333 333 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 334 334 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 335 335 - >; 336 336 - }; 330 330 + pinctrl_i2c1: i2c1grp { 331 331 + fsl,pins = < 332 332 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 333 333 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 334 334 + >; 335 335 + }; 337 336 338 338 - pinctrl_i2c2: i2c2grp { 339 339 - fsl,pins = < 340 340 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 341 341 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 342 342 - >; 343 343 - }; 337 337 + pinctrl_i2c2: i2c2grp { 338 338 + fsl,pins = < 339 339 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 340 340 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 341 341 + >; 342 342 + }; 344 343 345 345 - pinctrl_i2c3: i2c3grp { 346 346 - fsl,pins = < 347 347 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 348 348 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 349 349 - /* Touch IRQ: J7 pin 4 */ 350 350 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 351 351 - /* tcs2004 IRQ */ 352 352 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 353 353 - /* tsc2004 reset */ 354 354 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 355 355 - >; 356 356 - }; 344 344 + pinctrl_i2c3: i2c3grp { 345 345 + fsl,pins = < 346 346 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 347 347 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 348 348 + /* Touch IRQ: J7 pin 4 */ 349 349 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 350 350 + /* tcs2004 IRQ */ 351 351 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 352 352 + /* tsc2004 reset */ 353 353 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 354 354 + >; 355 355 + }; 357 356 358 358 - pinctrl_j10: j10grp { 359 359 - fsl,pins = < 360 360 - /* Broadcom WiFi module pins */ 361 361 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 362 362 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 363 363 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 364 364 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 365 365 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 366 366 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 367 367 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 368 368 - >; 369 369 - }; 357 357 + pinctrl_j10: j10grp { 358 358 + fsl,pins = < 359 359 + /* Broadcom WiFi module pins */ 360 360 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 361 361 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 362 362 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 363 363 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 364 364 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 365 365 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 366 366 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 367 367 + >; 368 368 + }; 370 369 371 371 - pinctrl_j28: j28grp { 372 372 - fsl,pins = < 373 373 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 374 374 - >; 375 375 - }; 370 370 + pinctrl_j28: j28grp { 371 371 + fsl,pins = < 372 372 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 373 373 + >; 374 374 + }; 376 375 377 377 - pinctrl_leds: ledsgrp { 378 378 - fsl,pins = < 379 379 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 380 380 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 381 381 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 382 382 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 383 383 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 384 384 - >; 385 385 - }; 376 376 + pinctrl_leds: ledsgrp { 377 377 + fsl,pins = < 378 378 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 379 379 + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 380 380 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 381 381 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 382 382 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 383 383 + >; 384 384 + }; 386 385 387 387 - pinctrl_pwm1: pwm1grp { 388 388 - fsl,pins = < 389 389 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 390 390 - >; 391 391 - }; 386 386 + pinctrl_pwm1: pwm1grp { 387 387 + fsl,pins = < 388 388 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 389 389 + >; 390 390 + }; 392 391 393 393 - pinctrl_pwm3: pwm3grp { 394 394 - fsl,pins = < 395 395 - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 396 396 - >; 397 397 - }; 392 392 + pinctrl_pwm3: pwm3grp { 393 393 + fsl,pins = < 394 394 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 395 395 + >; 396 396 + }; 398 397 399 399 - pinctrl_pwm4: pwm4grp { 400 400 - fsl,pins = < 401 401 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 402 402 - >; 403 403 - }; 398 398 + pinctrl_pwm4: pwm4grp { 399 399 + fsl,pins = < 400 400 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 401 401 + >; 402 402 + }; 404 403 405 405 - pinctrl_wlan_vmmc: wlan-vmmcgrp { 406 406 - fsl,pins = < 407 407 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 408 408 - >; 409 409 - }; 404 404 + pinctrl_wlan_vmmc: wlan-vmmcgrp { 405 405 + fsl,pins = < 406 406 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 407 407 + >; 408 408 + }; 410 409 411 411 - pinctrl_rtc: rtcgrp { 412 412 - fsl,pins = < 413 413 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 414 414 - >; 415 415 - }; 410 410 + pinctrl_rtc: rtcgrp { 411 411 + fsl,pins = < 412 412 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 413 413 + >; 414 414 + }; 416 415 417 417 - pinctrl_sgtl5000: sgtl5000grp { 418 418 - fsl,pins = < 419 419 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 420 420 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 421 421 - >; 422 422 - }; 416 416 + pinctrl_sgtl5000: sgtl5000grp { 417 417 + fsl,pins = < 418 418 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 419 419 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 420 420 + >; 421 421 + }; 423 422 424 424 - pinctrl_uart1: uart1grp { 425 425 - fsl,pins = < 426 426 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 427 427 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 428 428 - >; 429 429 - }; 423 423 + pinctrl_uart1: uart1grp { 424 424 + fsl,pins = < 425 425 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 426 426 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 427 427 + >; 428 428 + }; 430 429 431 431 - pinctrl_uart2: uart2grp { 432 432 - fsl,pins = < 433 433 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 434 434 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 435 435 - >; 436 436 - }; 430 430 + pinctrl_uart2: uart2grp { 431 431 + fsl,pins = < 432 432 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 433 433 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 434 434 + >; 435 435 + }; 437 436 438 438 - pinctrl_uart3: uart3grp { 439 439 - fsl,pins = < 440 440 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 441 441 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 442 442 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 443 443 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 444 444 - >; 445 445 - }; 437 437 + pinctrl_uart3: uart3grp { 438 438 + fsl,pins = < 439 439 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 440 440 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 441 441 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 442 442 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 443 443 + >; 444 444 + }; 446 445 447 447 - pinctrl_usbotg: usbotggrp { 448 448 - fsl,pins = < 449 449 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 450 450 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 451 451 - /* power enable, high active */ 452 452 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 453 453 - >; 454 454 - }; 446 446 + pinctrl_usbotg: usbotggrp { 447 447 + fsl,pins = < 448 448 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 449 449 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 450 450 + /* power enable, high active */ 451 451 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 452 452 + >; 453 453 + }; 455 454 456 456 - pinctrl_usdhc2: usdhc2grp { 457 457 - fsl,pins = < 458 458 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 459 459 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 460 460 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 461 461 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 462 462 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 463 463 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 464 464 - >; 465 465 - }; 455 455 + pinctrl_usdhc2: usdhc2grp { 456 456 + fsl,pins = < 457 457 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 458 458 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 459 459 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 460 460 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 461 461 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 462 462 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 463 463 + >; 464 464 + }; 466 465 467 467 - pinctrl_usdhc3: usdhc3grp { 468 468 - fsl,pins = < 469 469 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 470 470 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 471 471 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 472 472 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 473 473 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 474 474 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 475 475 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 476 476 - >; 477 477 - }; 466 466 + pinctrl_usdhc3: usdhc3grp { 467 467 + fsl,pins = < 468 468 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 469 469 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 470 470 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 471 471 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 472 472 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 473 473 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 474 474 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 475 475 + >; 478 476 }; 479 477 }; 480 478

+252 -254

arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi

reviewed

··· 411 411 }; 412 412 413 413 &iomuxc { 414 414 - imx6q-nitrogen6-max { 415 415 - pinctrl_audmux: audmuxgrp { 416 416 - fsl,pins = < 417 417 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 418 418 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 419 419 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 420 420 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 421 421 - >; 422 422 - }; 414 414 + pinctrl_audmux: audmuxgrp { 415 415 + fsl,pins = < 416 416 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 417 417 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 418 418 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 419 419 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 420 420 + >; 421 421 + }; 423 422 424 424 - pinctrl_can1: can1grp { 425 425 - fsl,pins = < 426 426 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 427 427 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 428 428 - >; 429 429 - }; 423 423 + pinctrl_can1: can1grp { 424 424 + fsl,pins = < 425 425 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 426 426 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 427 427 + >; 428 428 + }; 430 429 431 431 - pinctrl_can_xcvr: can-xcvrgrp { 432 432 - fsl,pins = < 433 433 - /* Flexcan XCVR enable */ 434 434 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 435 435 - >; 436 436 - }; 430 430 + pinctrl_can_xcvr: can-xcvrgrp { 431 431 + fsl,pins = < 432 432 + /* Flexcan XCVR enable */ 433 433 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 434 434 + >; 435 435 + }; 437 436 438 438 - pinctrl_ecspi1: ecspi1grp { 439 439 - fsl,pins = < 440 440 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 441 441 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 442 442 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 443 443 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 444 444 - >; 445 445 - }; 437 437 + pinctrl_ecspi1: ecspi1grp { 438 438 + fsl,pins = < 439 439 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 440 440 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 441 441 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 442 442 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 443 443 + >; 444 444 + }; 446 445 447 447 - pinctrl_enet: enetgrp { 448 448 - fsl,pins = < 449 449 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 450 450 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 451 451 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 452 452 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 453 453 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 454 454 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 455 455 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 456 456 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 457 457 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 458 458 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 459 459 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 460 460 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 461 461 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 462 462 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 463 463 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 464 464 - /* Phy reset */ 465 465 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 466 466 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 467 467 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 468 468 - >; 469 469 - }; 446 446 + pinctrl_enet: enetgrp { 447 447 + fsl,pins = < 448 448 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 449 449 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 450 450 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 451 451 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 452 452 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 453 453 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 454 454 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 455 455 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 456 456 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 457 457 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 458 458 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 459 459 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 460 460 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 461 461 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 462 462 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 463 463 + /* Phy reset */ 464 464 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 465 465 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 466 466 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 467 467 + >; 468 468 + }; 470 469 471 471 - pinctrl_gpio_keys: gpio-keysgrp { 472 472 - fsl,pins = < 473 473 - /* Power Button */ 474 474 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 475 475 - /* Menu Button */ 476 476 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 477 477 - /* Home Button */ 478 478 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 479 479 - /* Back Button */ 480 480 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 481 481 - /* Volume Up Button */ 482 482 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 483 483 - /* Volume Down Button */ 484 484 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 485 485 - >; 486 486 - }; 470 470 + pinctrl_gpio_keys: gpio-keysgrp { 471 471 + fsl,pins = < 472 472 + /* Power Button */ 473 473 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 474 474 + /* Menu Button */ 475 475 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 476 476 + /* Home Button */ 477 477 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 478 478 + /* Back Button */ 479 479 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 480 480 + /* Volume Up Button */ 481 481 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 482 482 + /* Volume Down Button */ 483 483 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 484 484 + >; 485 485 + }; 487 486 488 488 - pinctrl_i2c1: i2c1grp { 489 489 - fsl,pins = < 490 490 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 491 491 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 492 492 - >; 493 493 - }; 487 487 + pinctrl_i2c1: i2c1grp { 488 488 + fsl,pins = < 489 489 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 490 490 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 491 491 + >; 492 492 + }; 494 493 495 495 - pinctrl_i2c2: i2c2grp { 496 496 - fsl,pins = < 497 497 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 498 498 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 499 499 - >; 500 500 - }; 494 494 + pinctrl_i2c2: i2c2grp { 495 495 + fsl,pins = < 496 496 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 497 497 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 498 498 + >; 499 499 + }; 501 500 502 502 - pinctrl_i2c2mux: i2c2muxgrp { 503 503 - fsl,pins = < 504 504 - /* ov5642 camera i2c enable */ 505 505 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 506 506 - /* ov5640_mipi camera i2c enable */ 507 507 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 508 508 - >; 509 509 - }; 501 501 + pinctrl_i2c2mux: i2c2muxgrp { 502 502 + fsl,pins = < 503 503 + /* ov5642 camera i2c enable */ 504 504 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 505 505 + /* ov5640_mipi camera i2c enable */ 506 506 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 507 507 + >; 508 508 + }; 510 509 511 511 - pinctrl_i2c3: i2c3grp { 512 512 - fsl,pins = < 513 513 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 514 514 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 515 515 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 516 516 - >; 517 517 - }; 510 510 + pinctrl_i2c3: i2c3grp { 511 511 + fsl,pins = < 512 512 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 513 513 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 514 514 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 515 515 + >; 516 516 + }; 518 517 519 519 - pinctrl_i2c3mux: i2c3muxgrp { 520 520 - fsl,pins = < 521 521 - /* PCIe I2C enable */ 522 522 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 523 523 - >; 524 524 - }; 518 518 + pinctrl_i2c3mux: i2c3muxgrp { 519 519 + fsl,pins = < 520 520 + /* PCIe I2C enable */ 521 521 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 522 522 + >; 523 523 + }; 525 524 526 526 - pinctrl_j15: j15grp { 527 527 - fsl,pins = < 528 528 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 529 529 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 530 530 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 531 531 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 532 532 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 533 533 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 534 534 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 535 535 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 536 536 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 537 537 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 538 538 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 539 539 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 540 540 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 541 541 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 542 542 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 543 543 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 544 544 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 545 545 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 546 546 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 547 547 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 548 548 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 549 549 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 550 550 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 551 551 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 552 552 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 553 553 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 554 554 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 555 555 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 556 556 - >; 557 557 - }; 525 525 + pinctrl_j15: j15grp { 526 526 + fsl,pins = < 527 527 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 528 528 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 529 529 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 530 530 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 531 531 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 532 532 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 533 533 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 534 534 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 535 535 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 536 536 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 537 537 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 538 538 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 539 539 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 540 540 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 541 541 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 542 542 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 543 543 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 544 544 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 545 545 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 546 546 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 547 547 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 548 548 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 549 549 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 550 550 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 551 551 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 552 552 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 553 553 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 554 554 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 555 555 + >; 556 556 + }; 558 557 559 559 - pinctrl_pcie: pciegrp { 560 560 - fsl,pins = < 561 561 - /* PCIe reset */ 562 562 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 563 563 - >; 564 564 - }; 558 558 + pinctrl_pcie: pciegrp { 559 559 + fsl,pins = < 560 560 + /* PCIe reset */ 561 561 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 562 562 + >; 563 563 + }; 565 564 566 566 - pinctrl_pwm1: pwm1grp { 567 567 - fsl,pins = < 568 568 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 569 569 - >; 570 570 - }; 565 565 + pinctrl_pwm1: pwm1grp { 566 566 + fsl,pins = < 567 567 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 568 568 + >; 569 569 + }; 571 570 572 572 - pinctrl_pwm2: pwm2grp { 573 573 - fsl,pins = < 574 574 - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 575 575 - >; 576 576 - }; 571 571 + pinctrl_pwm2: pwm2grp { 572 572 + fsl,pins = < 573 573 + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 574 574 + >; 575 575 + }; 577 576 578 578 - pinctrl_pwm3: pwm3grp { 579 579 - fsl,pins = < 580 580 - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 581 581 - >; 582 582 - }; 577 577 + pinctrl_pwm3: pwm3grp { 578 578 + fsl,pins = < 579 579 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 580 580 + >; 581 581 + }; 583 582 584 584 - pinctrl_pwm4: pwm4grp { 585 585 - fsl,pins = < 586 586 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 587 587 - >; 588 588 - }; 583 583 + pinctrl_pwm4: pwm4grp { 584 584 + fsl,pins = < 585 585 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 586 586 + >; 587 587 + }; 589 588 590 590 - pinctrl_rv4162: rv4162grp { 591 591 - fsl,pins = < 592 592 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 593 593 - >; 594 594 - }; 589 589 + pinctrl_rv4162: rv4162grp { 590 590 + fsl,pins = < 591 591 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 592 592 + >; 593 593 + }; 595 594 596 596 - pinctrl_sgtl5000: sgtl5000grp { 597 597 - fsl,pins = < 598 598 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 599 599 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 600 600 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 601 601 - >; 602 602 - }; 595 595 + pinctrl_sgtl5000: sgtl5000grp { 596 596 + fsl,pins = < 597 597 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 598 598 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 599 599 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 600 600 + >; 601 601 + }; 603 602 604 604 - pinctrl_uart1: uart1grp { 605 605 - fsl,pins = < 606 606 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 607 607 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 608 608 - >; 609 609 - }; 603 603 + pinctrl_uart1: uart1grp { 604 604 + fsl,pins = < 605 605 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 606 606 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 607 607 + >; 608 608 + }; 610 609 611 611 - pinctrl_uart2: uart2grp { 612 612 - fsl,pins = < 613 613 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 614 614 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 615 615 - >; 616 616 - }; 610 610 + pinctrl_uart2: uart2grp { 611 611 + fsl,pins = < 612 612 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 613 613 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 614 614 + >; 615 615 + }; 617 616 618 618 - pinctrl_uart5: uart5grp { 619 619 - fsl,pins = < 620 620 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 621 621 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 622 622 - /* RS485 RX Enable: pull up */ 623 623 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 624 624 - /* RS485 DEN: pull down */ 625 625 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 626 626 - /* RS485/!RS232 Select: pull down (rs232) */ 627 627 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 628 628 - /* ON: pull down */ 629 629 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 630 630 - >; 631 631 - }; 617 617 + pinctrl_uart5: uart5grp { 618 618 + fsl,pins = < 619 619 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 620 620 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 621 621 + /* RS485 RX Enable: pull up */ 622 622 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 623 623 + /* RS485 DEN: pull down */ 624 624 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 625 625 + /* RS485/!RS232 Select: pull down (rs232) */ 626 626 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 627 627 + /* ON: pull down */ 628 628 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 629 629 + >; 630 630 + }; 632 631 633 633 - pinctrl_usbh1: usbh1grp { 634 634 - fsl,pins = < 635 635 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 636 636 - >; 637 637 - }; 632 632 + pinctrl_usbh1: usbh1grp { 633 633 + fsl,pins = < 634 634 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 635 635 + >; 636 636 + }; 638 637 639 639 - pinctrl_usbotg: usbotggrp { 640 640 - fsl,pins = < 641 641 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 642 642 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 643 643 - /* power enable, high active */ 644 644 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 645 645 - >; 646 646 - }; 638 638 + pinctrl_usbotg: usbotggrp { 639 639 + fsl,pins = < 640 640 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 641 641 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 642 642 + /* power enable, high active */ 643 643 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 644 644 + >; 645 645 + }; 647 646 648 648 - pinctrl_usdhc2: usdhc2grp { 649 649 - fsl,pins = < 650 650 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 651 651 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 652 652 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 653 653 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 654 654 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 655 655 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 656 656 - >; 657 657 - }; 647 647 + pinctrl_usdhc2: usdhc2grp { 648 648 + fsl,pins = < 649 649 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 650 650 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 651 651 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 652 652 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 653 653 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 654 654 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 655 655 + >; 656 656 + }; 658 657 659 659 - pinctrl_usdhc3: usdhc3grp { 660 660 - fsl,pins = < 661 661 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 662 662 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 663 663 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 664 664 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 665 665 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 666 666 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 667 667 - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 668 668 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 669 669 - >; 670 670 - }; 658 658 + pinctrl_usdhc3: usdhc3grp { 659 659 + fsl,pins = < 660 660 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 661 661 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 662 662 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 663 663 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 664 664 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 665 665 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 666 666 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 667 667 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 668 668 + >; 669 669 + }; 671 670 672 672 - pinctrl_usdhc4: usdhc4grp { 673 673 - fsl,pins = < 674 674 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 675 675 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 676 676 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 677 677 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 678 678 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 679 679 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 680 680 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 681 681 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 682 682 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 683 683 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 684 684 - >; 685 685 - }; 671 671 + pinctrl_usdhc4: usdhc4grp { 672 672 + fsl,pins = < 673 673 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 674 674 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 675 675 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 676 676 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 677 677 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 678 678 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 679 679 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 680 680 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 681 681 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 682 682 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 683 683 + >; 684 684 + }; 686 685 687 687 - pinctrl_wlan_vmmc: wlan-vmmcgrp { 688 688 - fsl,pins = < 689 689 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 690 690 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 691 691 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 692 692 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 693 693 - >; 694 694 - }; 686 686 + pinctrl_wlan_vmmc: wlan-vmmcgrp { 687 687 + fsl,pins = < 688 688 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 689 689 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 690 690 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 691 691 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 692 692 + >; 695 693 }; 696 694 }; 697 695

+202 -204

arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi

reviewed

··· 343 343 pinctrl-names = "default"; 344 344 pinctrl-0 = <&pinctrl_hog>; 345 345 346 346 - imx6q-nitrogen6x { 347 347 - pinctrl_hog: hoggrp { 348 348 - fsl,pins = < 349 349 - /* SGTL5000 sys_mclk */ 350 350 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 351 351 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 352 352 - >; 353 353 - }; 346 346 + pinctrl_hog: hoggrp { 347 347 + fsl,pins = < 348 348 + /* SGTL5000 sys_mclk */ 349 349 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 350 350 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 351 351 + >; 352 352 + }; 354 353 355 355 - pinctrl_audmux: audmuxgrp { 356 356 - fsl,pins = < 357 357 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 358 358 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 359 359 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 360 360 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 361 361 - >; 362 362 - }; 354 354 + pinctrl_audmux: audmuxgrp { 355 355 + fsl,pins = < 356 356 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 357 357 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 358 358 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 359 359 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 360 360 + >; 361 361 + }; 363 362 364 364 - pinctrl_can1: can1grp { 365 365 - fsl,pins = < 366 366 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 367 367 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 368 368 - >; 369 369 - }; 363 363 + pinctrl_can1: can1grp { 364 364 + fsl,pins = < 365 365 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 366 366 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 367 367 + >; 368 368 + }; 370 369 371 371 - pinctrl_can_xcvr: can-xcvrgrp { 372 372 - fsl,pins = < 373 373 - /* Flexcan XCVR enable */ 374 374 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 375 375 - >; 376 376 - }; 370 370 + pinctrl_can_xcvr: can-xcvrgrp { 371 371 + fsl,pins = < 372 372 + /* Flexcan XCVR enable */ 373 373 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 374 374 + >; 375 375 + }; 377 376 378 378 - pinctrl_ecspi1: ecspi1grp { 379 379 - fsl,pins = < 380 380 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 381 381 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 382 382 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 383 383 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ 384 384 - >; 385 385 - }; 377 377 + pinctrl_ecspi1: ecspi1grp { 378 378 + fsl,pins = < 379 379 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 380 380 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 381 381 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 382 382 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ 383 383 + >; 384 384 + }; 386 385 387 387 - pinctrl_enet: enetgrp { 388 388 - fsl,pins = < 389 389 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 390 390 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 391 391 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 392 392 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 393 393 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 394 394 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 395 395 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 396 396 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 397 397 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 398 398 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 399 399 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 400 400 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 401 401 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 402 402 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 403 403 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 404 404 - /* Phy reset */ 405 405 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 406 406 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 407 407 - >; 408 408 - }; 386 386 + pinctrl_enet: enetgrp { 387 387 + fsl,pins = < 388 388 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 389 389 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 390 390 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 391 391 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 392 392 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 393 393 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 394 394 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 395 395 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 396 396 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 397 397 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 398 398 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 399 399 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 400 400 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 401 401 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 402 402 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 403 403 + /* Phy reset */ 404 404 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 405 405 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 406 406 + >; 407 407 + }; 409 408 410 410 - pinctrl_gpio_keys: gpio-keysgrp { 411 411 - fsl,pins = < 412 412 - /* Power Button */ 413 413 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 414 414 - /* Menu Button */ 415 415 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 416 416 - /* Home Button */ 417 417 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 418 418 - /* Back Button */ 419 419 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 420 420 - /* Volume Up Button */ 421 421 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 422 422 - /* Volume Down Button */ 423 423 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 424 424 - >; 425 425 - }; 409 409 + pinctrl_gpio_keys: gpio-keysgrp { 410 410 + fsl,pins = < 411 411 + /* Power Button */ 412 412 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 413 413 + /* Menu Button */ 414 414 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 415 415 + /* Home Button */ 416 416 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 417 417 + /* Back Button */ 418 418 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 419 419 + /* Volume Up Button */ 420 420 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 421 421 + /* Volume Down Button */ 422 422 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 423 423 + >; 424 424 + }; 426 425 427 427 - pinctrl_i2c1: i2c1grp { 428 428 - fsl,pins = < 429 429 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 430 430 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 431 431 - >; 432 432 - }; 426 426 + pinctrl_i2c1: i2c1grp { 427 427 + fsl,pins = < 428 428 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 429 429 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 430 430 + >; 431 431 + }; 433 432 434 434 - pinctrl_i2c2: i2c2grp { 435 435 - fsl,pins = < 436 436 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 437 437 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 438 438 - >; 439 439 - }; 433 433 + pinctrl_i2c2: i2c2grp { 434 434 + fsl,pins = < 435 435 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 436 436 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 437 437 + >; 438 438 + }; 440 439 441 441 - pinctrl_i2c3: i2c3grp { 442 442 - fsl,pins = < 443 443 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 444 444 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 445 445 - >; 446 446 - }; 440 440 + pinctrl_i2c3: i2c3grp { 441 441 + fsl,pins = < 442 442 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 443 443 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 444 444 + >; 445 445 + }; 447 446 448 448 - pinctrl_j15: j15grp { 449 449 - fsl,pins = < 450 450 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 451 451 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 452 452 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 453 453 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 454 454 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 455 455 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 456 456 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 457 457 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 458 458 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 459 459 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 460 460 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 461 461 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 462 462 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 463 463 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 464 464 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 465 465 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 466 466 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 467 467 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 468 468 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 469 469 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 470 470 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 471 471 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 472 472 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 473 473 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 474 474 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 475 475 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 476 476 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 477 477 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 478 478 - >; 479 479 - }; 447 447 + pinctrl_j15: j15grp { 448 448 + fsl,pins = < 449 449 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 450 450 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 451 451 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 452 452 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 453 453 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 454 454 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 455 455 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 456 456 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 457 457 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 458 458 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 459 459 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 460 460 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 461 461 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 462 462 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 463 463 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 464 464 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 465 465 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 466 466 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 467 467 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 468 468 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 469 469 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 470 470 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 471 471 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 472 472 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 473 473 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 474 474 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 475 475 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 476 476 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 477 477 + >; 478 478 + }; 480 479 481 481 - pinctrl_pwm1: pwm1grp { 482 482 - fsl,pins = < 483 483 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 484 484 - >; 485 485 - }; 480 480 + pinctrl_pwm1: pwm1grp { 481 481 + fsl,pins = < 482 482 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 483 483 + >; 484 484 + }; 486 485 487 487 - pinctrl_pwm3: pwm3grp { 488 488 - fsl,pins = < 489 489 - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 490 490 - >; 491 491 - }; 486 486 + pinctrl_pwm3: pwm3grp { 487 487 + fsl,pins = < 488 488 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 489 489 + >; 490 490 + }; 492 491 493 493 - pinctrl_pwm4: pwm4grp { 494 494 - fsl,pins = < 495 495 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 496 496 - >; 497 497 - }; 492 492 + pinctrl_pwm4: pwm4grp { 493 493 + fsl,pins = < 494 494 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 495 495 + >; 496 496 + }; 498 497 499 499 - pinctrl_uart1: uart1grp { 500 500 - fsl,pins = < 501 501 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 502 502 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 503 503 - >; 504 504 - }; 498 498 + pinctrl_uart1: uart1grp { 499 499 + fsl,pins = < 500 500 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 501 501 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 502 502 + >; 503 503 + }; 505 504 506 506 - pinctrl_uart2: uart2grp { 507 507 - fsl,pins = < 508 508 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 509 509 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 510 510 - >; 511 511 - }; 505 505 + pinctrl_uart2: uart2grp { 506 506 + fsl,pins = < 507 507 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 508 508 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 509 509 + >; 510 510 + }; 512 511 513 513 - pinctrl_usbh1: usbh1grp { 514 514 - fsl,pins = < 515 515 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 516 516 - >; 517 517 - }; 512 512 + pinctrl_usbh1: usbh1grp { 513 513 + fsl,pins = < 514 514 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 515 515 + >; 516 516 + }; 518 517 519 519 - pinctrl_usbotg: usbotggrp { 520 520 - fsl,pins = < 521 521 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 522 522 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 523 523 - /* power enable, high active */ 524 524 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 525 525 - >; 526 526 - }; 518 518 + pinctrl_usbotg: usbotggrp { 519 519 + fsl,pins = < 520 520 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 521 521 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 522 522 + /* power enable, high active */ 523 523 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 524 524 + >; 525 525 + }; 527 526 528 528 - pinctrl_usdhc2: usdhc2grp { 529 529 - fsl,pins = < 530 530 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 531 531 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 532 532 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 533 533 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 534 534 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 535 535 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 536 536 - >; 537 537 - }; 527 527 + pinctrl_usdhc2: usdhc2grp { 528 528 + fsl,pins = < 529 529 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 530 530 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 531 531 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 532 532 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 533 533 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 534 534 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 535 535 + >; 536 536 + }; 538 537 539 539 - pinctrl_usdhc3: usdhc3grp { 540 540 - fsl,pins = < 541 541 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 542 542 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 543 543 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 544 544 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 545 545 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 546 546 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 547 547 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 548 548 - >; 549 549 - }; 538 538 + pinctrl_usdhc3: usdhc3grp { 539 539 + fsl,pins = < 540 540 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 541 541 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 542 542 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 543 543 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 544 544 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 545 545 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 546 546 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 547 547 + >; 548 548 + }; 550 549 551 551 - pinctrl_usdhc4: usdhc4grp { 552 552 - fsl,pins = < 553 553 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 554 554 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 555 555 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 556 556 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 557 557 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 558 558 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 559 559 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ 560 560 - >; 561 561 - }; 550 550 + pinctrl_usdhc4: usdhc4grp { 551 551 + fsl,pins = < 552 552 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 553 553 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 554 554 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 555 555 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 556 556 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 557 557 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 558 558 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ 559 559 + >; 560 560 + }; 562 561 563 563 - pinctrl_wlan_vmmc: wlan-vmmcgrp { 564 564 - fsl,pins = < 565 565 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 566 566 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 567 567 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 568 568 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 569 569 - >; 570 570 - }; 562 562 + pinctrl_wlan_vmmc: wlan-vmmcgrp { 563 563 + fsl,pins = < 564 564 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 565 565 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 566 566 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 567 567 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 568 568 + >; 571 569 }; 572 570 }; 573 571

+2 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi

reviewed

··· 54 54 }; 55 55 56 56 &iomuxc { 57 57 - pinctrl_uart3_bt: uart3grp-bt { 57 57 + pinctrl_uart3_bt: uart3-btgrp { 58 58 fsl,pins = < 59 59 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 60 60 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ··· 66 66 >; 67 67 }; 68 68 69 69 - pinctrl_usdhc3_wl: usdhc3grp-wl { 69 69 + pinctrl_usdhc3_wl: usdhc3-wlgrp { 70 70 fsl,pins = < 71 71 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 72 72 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059

+145 -147

arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi

reviewed

··· 227 227 }; 228 228 229 229 &iomuxc { 230 230 - imx6q-phytec-pfla02 { 231 231 - pinctrl_ecspi3: ecspi3grp { 232 232 - fsl,pins = < 233 233 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 234 234 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 235 235 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 236 236 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ 237 237 - >; 238 238 - }; 230 230 + pinctrl_ecspi3: ecspi3grp { 231 231 + fsl,pins = < 232 232 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 233 233 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 234 234 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 235 235 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ 236 236 + >; 237 237 + }; 239 238 240 240 - pinctrl_enet: enetgrp { 241 241 - fsl,pins = < 242 242 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 243 243 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 244 244 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 245 245 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 246 246 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 247 247 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 248 248 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 249 249 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 250 250 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 251 251 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 252 252 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 253 253 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 254 254 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 255 255 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 256 256 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 257 257 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 258 258 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ 259 259 - >; 260 260 - }; 239 239 + pinctrl_enet: enetgrp { 240 240 + fsl,pins = < 241 241 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 242 242 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 243 243 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 244 244 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 245 245 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 246 246 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 247 247 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 248 248 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 249 249 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 250 250 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 251 251 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 252 252 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 253 253 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 254 254 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 255 255 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 256 256 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 257 257 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ 258 258 + >; 259 259 + }; 261 260 262 262 - pinctrl_flexcan1: flexcan1grp { 263 263 - fsl,pins = < 264 264 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 265 265 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 266 266 - >; 267 267 - }; 261 261 + pinctrl_flexcan1: flexcan1grp { 262 262 + fsl,pins = < 263 263 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 264 264 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 265 265 + >; 266 266 + }; 268 267 269 269 - pinctrl_gpmi_nand: gpminandgrp { 270 270 - fsl,pins = < 271 271 - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 272 272 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 273 273 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 274 274 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 275 275 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 276 276 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 277 277 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 278 278 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 279 279 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 280 280 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 281 281 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 282 282 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 283 283 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 284 284 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 285 285 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 286 286 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 287 287 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 288 288 - >; 289 289 - }; 268 268 + pinctrl_gpmi_nand: gpminandgrp { 269 269 + fsl,pins = < 270 270 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 271 271 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 272 272 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 273 273 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 274 274 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 275 275 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 276 276 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 277 277 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 278 278 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 279 279 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 280 280 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 281 281 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 282 282 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 283 283 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 284 284 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 285 285 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 286 286 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 287 287 + >; 288 288 + }; 290 289 291 291 - pinctrl_i2c1: i2c1grp { 292 292 - fsl,pins = < 293 293 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 294 294 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 295 295 - >; 296 296 - }; 290 290 + pinctrl_i2c1: i2c1grp { 291 291 + fsl,pins = < 292 292 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 293 293 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 294 294 + >; 295 295 + }; 297 296 298 298 - pinctrl_i2c2: i2c2grp { 299 299 - fsl,pins = < 300 300 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 301 301 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 302 302 - >; 303 303 - }; 297 297 + pinctrl_i2c2: i2c2grp { 298 298 + fsl,pins = < 299 299 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 300 300 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 301 301 + >; 302 302 + }; 304 303 305 305 - pinctrl_i2c3: i2c3grp { 306 306 - fsl,pins = < 307 307 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 308 308 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 309 309 - >; 310 310 - }; 304 304 + pinctrl_i2c3: i2c3grp { 305 305 + fsl,pins = < 306 306 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 307 307 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 308 308 + >; 309 309 + }; 311 310 312 312 - pinctrl_leds: ledsgrp { 313 313 - fsl,pins = < 314 314 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ 315 315 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ 316 316 - >; 317 317 - }; 311 311 + pinctrl_leds: ledsgrp { 312 312 + fsl,pins = < 313 313 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ 314 314 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ 315 315 + >; 316 316 + }; 318 317 319 319 - pinctrl_pcie: pciegrp { 320 320 - fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; 321 321 - }; 318 318 + pinctrl_pcie: pciegrp { 319 319 + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; 320 320 + }; 322 321 323 323 - pinctrl_pmic: pmicgrp { 324 324 - fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */ 325 325 - }; 322 322 + pinctrl_pmic: pmicgrp { 323 323 + fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */ 324 324 + }; 326 325 327 327 - pinctrl_uart3: uart3grp { 328 328 - fsl,pins = < 329 329 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 330 330 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 331 331 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 332 332 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 333 333 - >; 334 334 - }; 326 326 + pinctrl_uart3: uart3grp { 327 327 + fsl,pins = < 328 328 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 329 329 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 330 330 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 331 331 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 332 332 + >; 333 333 + }; 335 334 336 336 - pinctrl_uart4: uart4grp { 337 337 - fsl,pins = < 338 338 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 339 339 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 340 340 - >; 341 341 - }; 335 335 + pinctrl_uart4: uart4grp { 336 336 + fsl,pins = < 337 337 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 338 338 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 339 339 + >; 340 340 + }; 342 341 343 343 - pinctrl_usbh1_vbus: usbh1vbusgrp { 344 344 - fsl,pins = < 345 345 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 346 346 - >; 347 347 - }; 342 342 + pinctrl_usbh1_vbus: usbh1vbusgrp { 343 343 + fsl,pins = < 344 344 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 345 345 + >; 346 346 + }; 348 347 349 349 - pinctrl_usbotg: usbotggrp { 350 350 - fsl,pins = < 351 351 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 352 352 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 353 353 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 354 354 - >; 355 355 - }; 348 348 + pinctrl_usbotg: usbotggrp { 349 349 + fsl,pins = < 350 350 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 351 351 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 352 352 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 353 353 + >; 354 354 + }; 356 355 357 357 - pinctrl_usdhc2: usdhc2grp { 358 358 - fsl,pins = < 359 359 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 360 360 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 361 361 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 362 362 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 363 363 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 364 364 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 365 365 - >; 366 366 - }; 356 356 + pinctrl_usdhc2: usdhc2grp { 357 357 + fsl,pins = < 358 358 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 359 359 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 360 360 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 361 361 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 362 362 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 363 363 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 364 364 + >; 365 365 + }; 367 366 368 368 - pinctrl_usdhc3: usdhc3grp { 369 369 - fsl,pins = < 370 370 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 371 371 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 372 372 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 373 373 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 374 374 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 375 375 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 376 376 - >; 377 377 - }; 367 367 + pinctrl_usdhc3: usdhc3grp { 368 368 + fsl,pins = < 369 369 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 370 370 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 371 371 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 372 372 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 373 373 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 374 374 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 375 375 + >; 376 376 + }; 378 377 379 379 - pinctrl_usdhc3_cdwp: usdhc3cdwp { 380 380 - fsl,pins = < 381 381 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 382 382 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 383 383 - >; 384 384 - }; 378 378 + pinctrl_usdhc3_cdwp: usdhc3cdwpgrp { 379 379 + fsl,pins = < 380 380 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 381 381 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 382 382 + >; 383 383 + }; 385 384 386 386 - pinctrl_audmux: audmuxgrp { 387 387 - fsl,pins = < 388 388 - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 389 389 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 390 390 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 391 391 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 392 392 - >; 393 393 - }; 385 385 + pinctrl_audmux: audmuxgrp { 386 386 + fsl,pins = < 387 387 + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 388 388 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 389 389 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 390 390 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 391 391 + >; 394 392 }; 395 393 }; 396 394

+136 -138

arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi

reviewed

··· 154 154 pinctrl-names = "default"; 155 155 pinctrl-0 = <&pinctrl_hog>; 156 156 157 157 - imx6qdl-rex { 158 158 - pinctrl_hog: hoggrp { 159 159 - fsl,pins = < 160 160 - /* SGTL5000 sys_mclk */ 161 161 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 162 162 - >; 163 163 - }; 157 157 + pinctrl_hog: hoggrp { 158 158 + fsl,pins = < 159 159 + /* SGTL5000 sys_mclk */ 160 160 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 161 161 + >; 162 162 + }; 164 163 165 165 - pinctrl_audmux: audmuxgrp { 166 166 - fsl,pins = < 167 167 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 168 168 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 169 169 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 170 170 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 171 171 - >; 172 172 - }; 164 164 + pinctrl_audmux: audmuxgrp { 165 165 + fsl,pins = < 166 166 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 167 167 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 168 168 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 169 169 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 170 170 + >; 171 171 + }; 173 172 174 174 - pinctrl_ecspi2: ecspi2grp { 175 175 - fsl,pins = < 176 176 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 177 177 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 178 178 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 179 179 - /* CS */ 180 180 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 181 181 - >; 182 182 - }; 173 173 + pinctrl_ecspi2: ecspi2grp { 174 174 + fsl,pins = < 175 175 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 176 176 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 177 177 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 178 178 + /* CS */ 179 179 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 180 180 + >; 181 181 + }; 183 182 184 184 - pinctrl_ecspi3: ecspi3grp { 185 185 - fsl,pins = < 186 186 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 187 187 - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 188 188 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 189 189 - /* CS */ 190 190 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 191 191 - >; 192 192 - }; 183 183 + pinctrl_ecspi3: ecspi3grp { 184 184 + fsl,pins = < 185 185 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 186 186 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 187 187 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 188 188 + /* CS */ 189 189 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 190 190 + >; 191 191 + }; 193 192 194 194 - pinctrl_enet: enetgrp { 195 195 - fsl,pins = < 196 196 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 197 197 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 198 198 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 199 199 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 200 200 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 201 201 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 202 202 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 203 203 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 204 204 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 205 205 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 206 206 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 207 207 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 208 208 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 209 209 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 210 210 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 211 211 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 212 212 - /* Phy reset */ 213 213 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 214 214 - >; 215 215 - }; 193 193 + pinctrl_enet: enetgrp { 194 194 + fsl,pins = < 195 195 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 196 196 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 197 197 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 198 198 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 199 199 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 200 200 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 201 201 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 202 202 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 203 203 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 204 204 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 205 205 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 206 206 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 207 207 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 208 208 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 209 209 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 210 210 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 211 211 + /* Phy reset */ 212 212 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 213 213 + >; 214 214 + }; 216 215 217 217 - pinctrl_i2c1: i2c1grp { 218 218 - fsl,pins = < 219 219 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 220 220 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 221 221 - >; 222 222 - }; 216 216 + pinctrl_i2c1: i2c1grp { 217 217 + fsl,pins = < 218 218 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 219 219 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 220 220 + >; 221 221 + }; 223 222 224 224 - pinctrl_i2c2: i2c2grp { 225 225 - fsl,pins = < 226 226 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 227 227 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 228 228 - >; 229 229 - }; 223 223 + pinctrl_i2c2: i2c2grp { 224 224 + fsl,pins = < 225 225 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 226 226 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 227 227 + >; 228 228 + }; 230 229 231 231 - pinctrl_i2c3: i2c3grp { 232 232 - fsl,pins = < 233 233 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 234 234 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 235 235 - >; 236 236 - }; 230 230 + pinctrl_i2c3: i2c3grp { 231 231 + fsl,pins = < 232 232 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 233 233 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 234 234 + >; 235 235 + }; 237 236 238 238 - pinctrl_led: ledgrp { 239 239 - fsl,pins = < 240 240 - /* user led */ 241 241 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 242 242 - >; 243 243 - }; 237 237 + pinctrl_led: ledgrp { 238 238 + fsl,pins = < 239 239 + /* user led */ 240 240 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 241 241 + >; 242 242 + }; 244 243 245 245 - pinctrl_pca9535: pca9535grp { 246 246 - fsl,pins = < 247 247 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 248 248 - >; 249 249 - }; 244 244 + pinctrl_pca9535: pca9535grp { 245 245 + fsl,pins = < 246 246 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 247 247 + >; 248 248 + }; 250 249 251 251 - pinctrl_uart1: uart1grp { 252 252 - fsl,pins = < 253 253 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 254 254 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 255 255 - >; 256 256 - }; 250 250 + pinctrl_uart1: uart1grp { 251 251 + fsl,pins = < 252 252 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 253 253 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 254 254 + >; 255 255 + }; 257 256 258 258 - pinctrl_uart2: uart2grp { 259 259 - fsl,pins = < 260 260 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 261 261 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 262 262 - >; 263 263 - }; 257 257 + pinctrl_uart2: uart2grp { 258 258 + fsl,pins = < 259 259 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 260 260 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 261 261 + >; 262 262 + }; 264 263 265 265 - pinctrl_usbh1: usbh1grp { 266 266 - fsl,pins = < 267 267 - /* power enable, high active */ 268 268 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 269 269 - >; 270 270 - }; 264 264 + pinctrl_usbh1: usbh1grp { 265 265 + fsl,pins = < 266 266 + /* power enable, high active */ 267 267 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 268 268 + >; 269 269 + }; 271 270 272 272 - pinctrl_usbotg: usbotggrp { 273 273 - fsl,pins = < 274 274 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 275 275 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 276 276 - /* power enable, high active */ 277 277 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 278 278 - >; 279 279 - }; 271 271 + pinctrl_usbotg: usbotggrp { 272 272 + fsl,pins = < 273 273 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 274 274 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 275 275 + /* power enable, high active */ 276 276 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 277 277 + >; 278 278 + }; 280 279 281 281 - pinctrl_usdhc2: usdhc2grp { 282 282 - fsl,pins = < 283 283 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 284 284 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 285 285 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 286 286 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 287 287 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 288 288 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 289 289 - /* CD */ 290 290 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 291 291 - /* WP */ 292 292 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 293 293 - >; 294 294 - }; 280 280 + pinctrl_usdhc2: usdhc2grp { 281 281 + fsl,pins = < 282 282 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 283 283 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 284 284 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 285 285 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 286 286 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 287 287 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 288 288 + /* CD */ 289 289 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 290 290 + /* WP */ 291 291 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 292 292 + >; 293 293 + }; 295 294 296 296 - pinctrl_usdhc3: usdhc3grp { 297 297 - fsl,pins = < 298 298 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 299 299 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 300 300 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 301 301 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 302 302 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 303 303 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 304 304 - /* CD */ 305 305 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 306 306 - /* WP */ 307 307 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 308 308 - >; 309 309 - }; 295 295 + pinctrl_usdhc3: usdhc3grp { 296 296 + fsl,pins = < 297 297 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 298 298 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 299 299 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 300 300 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 301 301 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 302 302 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 303 303 + /* CD */ 304 304 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 305 305 + /* WP */ 306 306 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 307 307 + >; 310 308 }; 311 309 }; 312 310

+276 -278

arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi

reviewed

··· 472 472 pinctrl-names = "default"; 473 473 pinctrl-0 = <&pinctrl_hog>; 474 474 475 475 - imx6qdl-sabreauto { 476 476 - pinctrl_hog: hoggrp { 477 477 - fsl,pins = < 478 478 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 479 479 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 480 480 - MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 481 481 - >; 482 482 - }; 475 475 + pinctrl_hog: hoggrp { 476 476 + fsl,pins = < 477 477 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 478 478 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 479 479 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 480 480 + >; 481 481 + }; 483 482 484 484 - pinctrl_ecspi1: ecspi1grp { 485 485 - fsl,pins = < 486 486 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 487 487 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 488 488 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 489 489 - >; 490 490 - }; 483 483 + pinctrl_ecspi1: ecspi1grp { 484 484 + fsl,pins = < 485 485 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 486 486 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 487 487 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 488 488 + >; 489 489 + }; 491 490 492 492 - pinctrl_ecspi1_cs: ecspi1cs { 493 493 - fsl,pins = < 494 494 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 495 495 - >; 496 496 - }; 491 491 + pinctrl_ecspi1_cs: ecspi1csgrp { 492 492 + fsl,pins = < 493 493 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 494 494 + >; 495 495 + }; 497 496 498 498 - pinctrl_egalax_int: egalax-intgrp { 499 499 - fsl,pins = < 500 500 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 501 501 - >; 502 502 - }; 497 497 + pinctrl_egalax_int: egalax-intgrp { 498 498 + fsl,pins = < 499 499 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 500 500 + >; 501 501 + }; 503 502 504 504 - pinctrl_enet: enetgrp { 505 505 - fsl,pins = < 506 506 - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 507 507 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 508 508 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 509 509 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 510 510 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 511 511 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 512 512 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 513 513 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 514 514 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 515 515 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 516 516 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 517 517 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 518 518 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 519 519 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 520 520 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 521 521 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 522 522 - >; 523 523 - }; 503 503 + pinctrl_enet: enetgrp { 504 504 + fsl,pins = < 505 505 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 506 506 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 507 507 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 508 508 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 509 509 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 510 510 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 511 511 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 512 512 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 513 513 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 514 514 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 515 515 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 516 516 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 517 517 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 518 518 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 519 519 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 520 520 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 521 521 + >; 522 522 + }; 524 523 525 525 - pinctrl_esai: esaigrp { 526 526 - fsl,pins = < 527 527 - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 528 528 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 529 529 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 530 530 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 531 531 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 532 532 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 533 533 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 534 534 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 535 535 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 536 536 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 537 537 - >; 538 538 - }; 524 524 + pinctrl_esai: esaigrp { 525 525 + fsl,pins = < 526 526 + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 527 527 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 528 528 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 529 529 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 530 530 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 531 531 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 532 532 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 533 533 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 534 534 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 535 535 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 536 536 + >; 537 537 + }; 539 538 540 540 - pinctrl_flexcan1: flexcan1grp { 541 541 - fsl,pins = < 542 542 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 543 543 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 544 544 - >; 545 545 - }; 539 539 + pinctrl_flexcan1: flexcan1grp { 540 540 + fsl,pins = < 541 541 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 542 542 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 543 543 + >; 544 544 + }; 546 545 547 547 - pinctrl_flexcan2: flexcan2grp { 548 548 - fsl,pins = < 549 549 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 550 550 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 551 551 - >; 552 552 - }; 546 546 + pinctrl_flexcan2: flexcan2grp { 547 547 + fsl,pins = < 548 548 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 549 549 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 550 550 + >; 551 551 + }; 553 552 554 554 - pinctrl_gpio_keys: gpiokeysgrp { 555 555 - fsl,pins = < 556 556 - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 557 557 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 558 558 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 559 559 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 560 560 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 561 561 - >; 562 562 - }; 553 553 + pinctrl_gpio_keys: gpiokeysgrp { 554 554 + fsl,pins = < 555 555 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 556 556 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 557 557 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 558 558 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 559 559 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 560 560 + >; 561 561 + }; 563 562 564 564 - pinctrl_gpio_leds: gpioledsgrp { 565 565 - fsl,pins = < 566 566 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 567 567 - >; 568 568 - }; 563 563 + pinctrl_gpio_leds: gpioledsgrp { 564 564 + fsl,pins = < 565 565 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 566 566 + >; 567 567 + }; 569 568 570 570 - pinctrl_gpmi_nand: gpminandgrp { 571 571 - fsl,pins = < 572 572 - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 573 573 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 574 574 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 575 575 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 576 576 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 577 577 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 578 578 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 579 579 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 580 580 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 581 581 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 582 582 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 583 583 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 584 584 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 585 585 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 586 586 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 587 587 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 588 588 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 589 589 - >; 590 590 - }; 569 569 + pinctrl_gpmi_nand: gpminandgrp { 570 570 + fsl,pins = < 571 571 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 572 572 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 573 573 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 574 574 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 575 575 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 576 576 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 577 577 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 578 578 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 579 579 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 580 580 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 581 581 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 582 582 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 583 583 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 584 584 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 585 585 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 586 586 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 587 587 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 588 588 + >; 589 589 + }; 591 590 592 592 - pinctrl_hdmi_cec: hdmicecgrp { 593 593 - fsl,pins = < 594 594 - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 595 595 - >; 596 596 - }; 591 591 + pinctrl_hdmi_cec: hdmicecgrp { 592 592 + fsl,pins = < 593 593 + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 594 594 + >; 595 595 + }; 597 596 598 598 - pinctrl_i2c2: i2c2grp { 599 599 - fsl,pins = < 600 600 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 601 601 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 602 602 - >; 603 603 - }; 597 597 + pinctrl_i2c2: i2c2grp { 598 598 + fsl,pins = < 599 599 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 600 600 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 601 601 + >; 602 602 + }; 604 603 605 605 - pinctrl_i2c3: i2c3grp { 606 606 - fsl,pins = < 607 607 - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 608 608 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 609 609 - >; 610 610 - }; 604 604 + pinctrl_i2c3: i2c3grp { 605 605 + fsl,pins = < 606 606 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 607 607 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 608 608 + >; 609 609 + }; 611 610 612 612 - pinctrl_i2c3mux: i2c3muxgrp { 613 613 - fsl,pins = < 614 614 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 615 615 - >; 616 616 - }; 611 611 + pinctrl_i2c3mux: i2c3muxgrp { 612 612 + fsl,pins = < 613 613 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 614 614 + >; 615 615 + }; 617 616 618 618 - pinctrl_ipu1_csi0: ipu1csi0grp { 619 619 - fsl,pins = < 620 620 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 621 621 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 622 622 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 623 623 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 624 624 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 625 625 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 626 626 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 627 627 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 628 628 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 629 629 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 630 630 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 631 631 - >; 632 632 - }; 617 617 + pinctrl_ipu1_csi0: ipu1csi0grp { 618 618 + fsl,pins = < 619 619 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 620 620 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 621 621 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 622 622 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 623 623 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 624 624 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 625 625 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 626 626 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 627 627 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 628 628 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 629 629 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 630 630 + >; 631 631 + }; 633 632 634 634 - pinctrl_max7310: max7310grp { 635 635 - fsl,pins = < 636 636 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 637 637 - >; 638 638 - }; 633 633 + pinctrl_max7310: max7310grp { 634 634 + fsl,pins = < 635 635 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 636 636 + >; 637 637 + }; 639 638 640 640 - pinctrl_mma8451_int: mma8451intgrp { 641 641 - fsl,pins = < 642 642 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 643 643 - >; 644 644 - }; 639 639 + pinctrl_mma8451_int: mma8451intgrp { 640 640 + fsl,pins = < 641 641 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 642 642 + >; 643 643 + }; 645 644 646 646 - pinctrl_pwm3: pwm1grp { 647 647 - fsl,pins = < 648 648 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 649 649 - >; 650 650 - }; 645 645 + pinctrl_pwm3: pwm1grp { 646 646 + fsl,pins = < 647 647 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 648 648 + >; 649 649 + }; 651 650 652 652 - pinctrl_gpt_input_capture0: gptinputcapture0grp { 653 653 - fsl,pins = < 654 654 - MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 655 655 - >; 656 656 - }; 651 651 + pinctrl_gpt_input_capture0: gptinputcapture0grp { 652 652 + fsl,pins = < 653 653 + MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 654 654 + >; 655 655 + }; 657 656 658 658 - pinctrl_gpt_input_capture1: gptinputcapture1grp { 659 659 - fsl,pins = < 660 660 - MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 661 661 - >; 662 662 - }; 657 657 + pinctrl_gpt_input_capture1: gptinputcapture1grp { 658 658 + fsl,pins = < 659 659 + MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 660 660 + >; 661 661 + }; 663 662 664 664 - pinctrl_spdif: spdifgrp { 665 665 - fsl,pins = < 666 666 - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 667 667 - >; 668 668 - }; 663 663 + pinctrl_spdif: spdifgrp { 664 664 + fsl,pins = < 665 665 + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 666 666 + >; 667 667 + }; 669 668 670 670 - pinctrl_uart4: uart4grp { 671 671 - fsl,pins = < 672 672 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 673 673 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 674 674 - >; 675 675 - }; 669 669 + pinctrl_uart4: uart4grp { 670 670 + fsl,pins = < 671 671 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 672 672 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 673 673 + >; 674 674 + }; 676 675 677 677 - pinctrl_usbotg: usbotggrp { 678 678 - fsl,pins = < 679 679 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 680 680 - >; 681 681 - }; 676 676 + pinctrl_usbotg: usbotggrp { 677 677 + fsl,pins = < 678 678 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 679 679 + >; 680 680 + }; 682 681 683 683 - pinctrl_usdhc3: usdhc3grp { 684 684 - fsl,pins = < 685 685 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 686 686 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 687 687 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 688 688 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 689 689 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 690 690 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 691 691 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 692 692 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 693 693 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 694 694 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 695 695 - >; 696 696 - }; 682 682 + pinctrl_usdhc3: usdhc3grp { 683 683 + fsl,pins = < 684 684 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 685 685 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 686 686 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 687 687 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 688 688 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 689 689 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 690 690 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 691 691 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 692 692 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 693 693 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 694 694 + >; 695 695 + }; 697 696 698 698 - pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 699 699 - fsl,pins = < 700 700 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 701 701 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 702 702 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 703 703 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 704 704 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 705 705 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 706 706 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 707 707 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 708 708 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 709 709 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 710 710 - >; 711 711 - }; 697 697 + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 698 698 + fsl,pins = < 699 699 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 700 700 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 701 701 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 702 702 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 703 703 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 704 704 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 705 705 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 706 706 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 707 707 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 708 708 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 709 709 + >; 710 710 + }; 712 711 713 713 - pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 714 714 - fsl,pins = < 715 715 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 716 716 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 717 717 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 718 718 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 719 719 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 720 720 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 721 721 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 722 722 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 723 723 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 724 724 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 725 725 - >; 726 726 - }; 712 712 + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 713 713 + fsl,pins = < 714 714 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 715 715 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 716 716 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 717 717 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 718 718 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 719 719 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 720 720 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 721 721 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 722 722 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 723 723 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 724 724 + >; 725 725 + }; 727 726 728 728 - pinctrl_weim_cs0: weimcs0grp { 729 729 - fsl,pins = < 730 730 - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 731 731 - >; 732 732 - }; 727 727 + pinctrl_weim_cs0: weimcs0grp { 728 728 + fsl,pins = < 729 729 + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 730 730 + >; 731 731 + }; 733 732 734 734 - pinctrl_weim_nor: weimnorgrp { 735 735 - fsl,pins = < 736 736 - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 737 737 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 738 738 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 739 739 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 740 740 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 741 741 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 742 742 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 743 743 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 744 744 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 745 745 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 746 746 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 747 747 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 748 748 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 749 749 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 750 750 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 751 751 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 752 752 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 753 753 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 754 754 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 755 755 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 756 756 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 757 757 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 758 758 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 759 759 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 760 760 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 761 761 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 762 762 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 763 763 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 764 764 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 765 765 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 766 766 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 767 767 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 768 768 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 769 769 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 770 770 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 771 771 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 772 772 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 773 773 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 774 774 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 775 775 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 776 776 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 777 777 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 778 778 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 779 779 - >; 780 780 - }; 733 733 + pinctrl_weim_nor: weimnorgrp { 734 734 + fsl,pins = < 735 735 + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 736 736 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 737 737 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 738 738 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 739 739 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 740 740 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 741 741 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 742 742 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 743 743 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 744 744 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 745 745 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 746 746 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 747 747 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 748 748 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 749 749 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 750 750 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 751 751 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 752 752 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 753 753 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 754 754 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 755 755 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 756 756 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 757 757 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 758 758 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 759 759 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 760 760 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 761 761 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 762 762 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 763 763 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 764 764 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 765 765 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 766 766 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 767 767 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 768 768 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 769 769 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 770 770 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 771 771 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 772 772 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 773 773 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 774 774 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 775 775 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 776 776 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 777 777 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 778 778 + >; 781 779 }; 782 780 }; 783 781

+213 -215

arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi

reviewed

··· 389 389 pinctrl-names = "default"; 390 390 pinctrl-0 = <&pinctrl_hog>; 391 391 392 392 - imx6q-sabrelite { 393 393 - pinctrl_hog: hoggrp { 394 394 - fsl,pins = < 395 395 - /* SGTL5000 sys_mclk */ 396 396 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 397 397 - >; 398 398 - }; 392 392 + pinctrl_hog: hoggrp { 393 393 + fsl,pins = < 394 394 + /* SGTL5000 sys_mclk */ 395 395 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 396 396 + >; 397 397 + }; 399 398 400 400 - pinctrl_audmux: audmuxgrp { 401 401 - fsl,pins = < 402 402 - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 403 403 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 404 404 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 405 405 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 406 406 - >; 407 407 - }; 399 399 + pinctrl_audmux: audmuxgrp { 400 400 + fsl,pins = < 401 401 + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 402 402 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 403 403 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 404 404 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 405 405 + >; 406 406 + }; 408 407 409 409 - pinctrl_can1: can1grp { 410 410 - fsl,pins = < 411 411 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 412 412 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 413 413 - >; 414 414 - }; 408 408 + pinctrl_can1: can1grp { 409 409 + fsl,pins = < 410 410 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 411 411 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 412 412 + >; 413 413 + }; 415 414 416 416 - pinctrl_can_xcvr: can-xcvrgrp { 417 417 - fsl,pins = < 418 418 - /* Flexcan XCVR enable */ 419 419 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 420 420 - >; 421 421 - }; 415 415 + pinctrl_can_xcvr: can-xcvrgrp { 416 416 + fsl,pins = < 417 417 + /* Flexcan XCVR enable */ 418 418 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 419 419 + >; 420 420 + }; 422 421 423 423 - pinctrl_ecspi1: ecspi1grp { 424 424 - fsl,pins = < 425 425 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 426 426 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 427 427 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 428 428 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ 429 429 - >; 430 430 - }; 422 422 + pinctrl_ecspi1: ecspi1grp { 423 423 + fsl,pins = < 424 424 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 425 425 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 426 426 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 427 427 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ 428 428 + >; 429 429 + }; 431 430 432 432 - pinctrl_enet: enetgrp { 433 433 - fsl,pins = < 434 434 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 435 435 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 436 436 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 437 437 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 438 438 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 439 439 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 440 440 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 441 441 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 442 442 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 443 443 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 444 444 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 445 445 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 446 446 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 447 447 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 448 448 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 449 449 - /* Phy reset */ 450 450 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 451 451 - >; 452 452 - }; 431 431 + pinctrl_enet: enetgrp { 432 432 + fsl,pins = < 433 433 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 434 434 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 435 435 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 436 436 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 437 437 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 438 438 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 439 439 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 440 440 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 441 441 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 442 442 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 443 443 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 444 444 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 445 445 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 446 446 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 447 447 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 448 448 + /* Phy reset */ 449 449 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 450 450 + >; 451 451 + }; 453 452 454 454 - pinctrl_gpio_keys: gpio-keysgrp { 455 455 - fsl,pins = < 456 456 - /* Power Button */ 457 457 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 458 458 - /* Menu Button */ 459 459 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 460 460 - /* Home Button */ 461 461 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 462 462 - /* Back Button */ 463 463 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 464 464 - /* Volume Up Button */ 465 465 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 466 466 - /* Volume Down Button */ 467 467 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 468 468 - >; 469 469 - }; 453 453 + pinctrl_gpio_keys: gpio-keysgrp { 454 454 + fsl,pins = < 455 455 + /* Power Button */ 456 456 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 457 457 + /* Menu Button */ 458 458 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 459 459 + /* Home Button */ 460 460 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 461 461 + /* Back Button */ 462 462 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 463 463 + /* Volume Up Button */ 464 464 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 465 465 + /* Volume Down Button */ 466 466 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 467 467 + >; 468 468 + }; 470 469 471 471 - pinctrl_i2c1: i2c1grp { 472 472 - fsl,pins = < 473 473 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 474 474 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 475 475 - >; 476 476 - }; 470 470 + pinctrl_i2c1: i2c1grp { 471 471 + fsl,pins = < 472 472 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 473 473 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 474 474 + >; 475 475 + }; 477 476 478 478 - pinctrl_i2c2: i2c2grp { 479 479 - fsl,pins = < 480 480 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 481 481 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 482 482 - >; 483 483 - }; 477 477 + pinctrl_i2c2: i2c2grp { 478 478 + fsl,pins = < 479 479 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 480 480 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 481 481 + >; 482 482 + }; 484 483 485 485 - pinctrl_i2c3: i2c3grp { 486 486 - fsl,pins = < 487 487 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 488 488 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 489 489 - >; 490 490 - }; 484 484 + pinctrl_i2c3: i2c3grp { 485 485 + fsl,pins = < 486 486 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 487 487 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 488 488 + >; 489 489 + }; 491 490 492 492 - pinctrl_ipu1_csi0: ipu1csi0grp { 493 493 - fsl,pins = < 494 494 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 495 495 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 496 496 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 497 497 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 498 498 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 499 499 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 500 500 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 501 501 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 502 502 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 503 503 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 504 504 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 505 505 - MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 506 506 - >; 507 507 - }; 491 491 + pinctrl_ipu1_csi0: ipu1csi0grp { 492 492 + fsl,pins = < 493 493 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 494 494 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 495 495 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 496 496 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 497 497 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 498 498 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 499 499 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 500 500 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 501 501 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 502 502 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 503 503 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 504 504 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 505 505 + >; 506 506 + }; 508 507 509 509 - pinctrl_j15: j15grp { 510 510 - fsl,pins = < 511 511 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 512 512 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 513 513 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 514 514 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 515 515 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 516 516 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 517 517 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 518 518 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 519 519 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 520 520 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 521 521 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 522 522 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 523 523 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 524 524 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 525 525 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 526 526 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 527 527 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 528 528 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 529 529 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 530 530 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 531 531 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 532 532 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 533 533 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 534 534 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 535 535 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 536 536 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 537 537 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 538 538 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 539 539 - >; 540 540 - }; 508 508 + pinctrl_j15: j15grp { 509 509 + fsl,pins = < 510 510 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 511 511 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 512 512 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 513 513 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 514 514 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 515 515 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 516 516 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 517 517 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 518 518 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 519 519 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 520 520 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 521 521 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 522 522 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 523 523 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 524 524 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 525 525 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 526 526 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 527 527 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 528 528 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 529 529 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 530 530 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 531 531 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 532 532 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 533 533 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 534 534 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 535 535 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 536 536 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 537 537 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 538 538 + >; 539 539 + }; 541 540 542 542 - pinctrl_ov5640: ov5640grp { 543 543 - fsl,pins = < 544 544 - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 545 545 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 546 546 - >; 547 547 - }; 541 541 + pinctrl_ov5640: ov5640grp { 542 542 + fsl,pins = < 543 543 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 544 544 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 545 545 + >; 546 546 + }; 548 547 549 549 - pinctrl_ov5642: ov5642grp { 550 550 - fsl,pins = < 551 551 - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 552 552 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 553 553 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 554 554 - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 555 555 - >; 556 556 - }; 548 548 + pinctrl_ov5642: ov5642grp { 549 549 + fsl,pins = < 550 550 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 551 551 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 552 552 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 553 553 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 554 554 + >; 555 555 + }; 557 556 558 558 - pinctrl_pwm1: pwm1grp { 559 559 - fsl,pins = < 560 560 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 561 561 - >; 562 562 - }; 557 557 + pinctrl_pwm1: pwm1grp { 558 558 + fsl,pins = < 559 559 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 560 560 + >; 561 561 + }; 563 562 564 564 - pinctrl_pwm3: pwm3grp { 565 565 - fsl,pins = < 566 566 - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 567 567 - >; 568 568 - }; 563 563 + pinctrl_pwm3: pwm3grp { 564 564 + fsl,pins = < 565 565 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 566 566 + >; 567 567 + }; 569 568 570 570 - pinctrl_pwm4: pwm4grp { 571 571 - fsl,pins = < 572 572 - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 573 573 - >; 574 574 - }; 569 569 + pinctrl_pwm4: pwm4grp { 570 570 + fsl,pins = < 571 571 + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 572 572 + >; 573 573 + }; 575 574 576 576 - pinctrl_uart1: uart1grp { 577 577 - fsl,pins = < 578 578 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 579 579 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 580 580 - >; 581 581 - }; 575 575 + pinctrl_uart1: uart1grp { 576 576 + fsl,pins = < 577 577 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 578 578 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 579 579 + >; 580 580 + }; 582 581 583 583 - pinctrl_uart2: uart2grp { 584 584 - fsl,pins = < 585 585 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 586 586 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 587 587 - >; 588 588 - }; 582 582 + pinctrl_uart2: uart2grp { 583 583 + fsl,pins = < 584 584 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 585 585 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 586 586 + >; 587 587 + }; 589 588 590 590 - pinctrl_usbh1: usbh1grp { 591 591 - fsl,pins = < 592 592 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 593 593 - >; 594 594 - }; 589 589 + pinctrl_usbh1: usbh1grp { 590 590 + fsl,pins = < 591 591 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 592 592 + >; 593 593 + }; 595 594 596 596 - pinctrl_usbotg: usbotggrp { 597 597 - fsl,pins = < 598 598 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 599 599 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 600 600 - /* power enable, high active */ 601 601 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 602 602 - >; 603 603 - }; 595 595 + pinctrl_usbotg: usbotggrp { 596 596 + fsl,pins = < 597 597 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 598 598 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 599 599 + /* power enable, high active */ 600 600 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 601 601 + >; 602 602 + }; 604 603 605 605 - pinctrl_usdhc3: usdhc3grp { 606 606 - fsl,pins = < 607 607 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 608 608 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 609 609 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 610 610 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 611 611 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 612 612 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 613 613 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 614 614 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ 615 615 - >; 616 616 - }; 604 604 + pinctrl_usdhc3: usdhc3grp { 605 605 + fsl,pins = < 606 606 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 607 607 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 608 608 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 609 609 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 610 610 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 611 611 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 612 612 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 613 613 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ 614 614 + >; 615 615 + }; 617 616 618 618 - pinctrl_usdhc4: usdhc4grp { 619 619 - fsl,pins = < 620 620 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 621 621 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 622 622 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 623 623 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 624 624 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 625 625 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 626 626 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ 627 627 - >; 628 628 - }; 617 617 + pinctrl_usdhc4: usdhc4grp { 618 618 + fsl,pins = < 619 619 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 620 620 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 621 621 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 622 622 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 623 623 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 624 624 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 625 625 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ 626 626 + >; 629 627 }; 630 628 }; 631 629

+239 -243

arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi

reviewed

··· 480 480 pinctrl-names = "default"; 481 481 pinctrl-0 = <&pinctrl_hog>; 482 482 483 483 - imx6qdl-sabresd { 484 484 - pinctrl_hog: hoggrp { 485 485 - fsl,pins = < 486 486 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 487 487 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 488 488 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 489 489 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 490 490 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 491 491 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 492 492 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 493 493 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 494 494 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 495 495 - >; 496 496 - }; 497 497 - 498 498 - pinctrl_audmux: audmuxgrp { 499 499 - fsl,pins = < 500 500 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 501 501 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 502 502 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 503 503 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 504 504 - >; 505 505 - }; 506 506 - 507 507 - pinctrl_ecspi1: ecspi1grp { 508 508 - fsl,pins = < 509 509 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 510 510 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 511 511 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 512 512 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 513 513 - >; 514 514 - }; 515 515 - 516 516 - pinctrl_enet: enetgrp { 517 517 - fsl,pins = < 518 518 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 519 519 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 520 520 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 521 521 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 522 522 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 523 523 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 524 524 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 525 525 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 526 526 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 527 527 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 528 528 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 529 529 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 530 530 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 531 531 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 532 532 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 533 533 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 534 534 - >; 535 535 - }; 536 536 - 537 537 - pinctrl_gpio_keys: gpio_keysgrp { 538 538 - fsl,pins = < 539 539 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 540 540 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 541 541 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 542 542 - >; 543 543 - }; 544 544 - 545 545 - pinctrl_hdmi_cec: hdmicecgrp { 546 546 - fsl,pins = < 547 547 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 548 548 - >; 549 549 - }; 550 550 - 551 551 - pinctrl_hp: hpgrp { 552 552 - fsl,pins = < 553 553 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 554 554 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 555 555 - >; 556 556 - }; 557 557 - 558 558 - pinctrl_i2c1: i2c1grp { 559 559 - fsl,pins = < 560 560 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 561 561 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 562 562 - >; 563 563 - }; 564 564 - 565 565 - pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { 566 566 - fsl,pins = < 567 567 - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 568 568 - >; 569 569 - }; 570 570 - 571 571 - pinctrl_i2c2: i2c2grp { 572 572 - fsl,pins = < 573 573 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 574 574 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 575 575 - >; 576 576 - }; 577 577 - 578 578 - pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { 579 579 - fsl,pins = < 580 580 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 581 581 - >; 582 582 - }; 583 583 - 584 584 - pinctrl_i2c3: i2c3grp { 585 585 - fsl,pins = < 586 586 - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 587 587 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 588 588 - >; 589 589 - }; 590 590 - 591 591 - pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { 592 592 - fsl,pins = < 593 593 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 594 594 - >; 595 595 - }; 596 596 - 597 597 - pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { 598 598 - fsl,pins = < 599 599 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 600 600 - >; 601 601 - }; 602 602 - 603 603 - pinctrl_ipu1_csi0: ipu1csi0grp { 604 604 - fsl,pins = < 605 605 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 606 606 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 607 607 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 608 608 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 609 609 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 610 610 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 611 611 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 612 612 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 613 613 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 614 614 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 615 615 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 616 616 - >; 617 617 - }; 618 618 - 619 619 - pinctrl_ov5640: ov5640grp { 620 620 - fsl,pins = < 621 621 - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 622 622 - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 623 623 - >; 624 624 - }; 625 625 - 626 626 - pinctrl_ov5642: ov5642grp { 627 627 - fsl,pins = < 628 628 - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 629 629 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 630 630 - >; 631 631 - }; 632 632 - 633 633 - pinctrl_pcie: pciegrp { 634 634 - fsl,pins = < 635 635 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 636 636 - >; 637 637 - }; 638 638 - 639 639 - pinctrl_pcie_reg: pciereggrp { 640 640 - fsl,pins = < 641 641 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 642 642 - >; 643 643 - }; 644 644 - 645 645 - pinctrl_pwm1: pwm1grp { 646 646 - fsl,pins = < 647 647 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 648 648 - >; 649 649 - }; 650 650 - 651 651 - pinctrl_sensors_reg: sensorsreggrp { 652 652 - fsl,pins = < 653 653 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 654 654 - >; 655 655 - }; 656 656 - 657 657 - pinctrl_uart1: uart1grp { 658 658 - fsl,pins = < 659 659 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 660 660 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 661 661 - >; 662 662 - }; 663 663 - 664 664 - pinctrl_usbotg: usbotggrp { 665 665 - fsl,pins = < 666 666 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 667 667 - >; 668 668 - }; 669 669 - 670 670 - pinctrl_usdhc2: usdhc2grp { 671 671 - fsl,pins = < 672 672 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 673 673 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 674 674 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 675 675 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 676 676 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 677 677 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 678 678 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 679 679 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 680 680 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 681 681 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 682 682 - >; 683 683 - }; 684 684 - 685 685 - pinctrl_usdhc3: usdhc3grp { 686 686 - fsl,pins = < 687 687 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 688 688 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 689 689 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 690 690 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 691 691 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 692 692 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 693 693 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 694 694 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 695 695 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 696 696 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 697 697 - >; 698 698 - }; 699 699 - 700 700 - pinctrl_usdhc4: usdhc4grp { 701 701 - fsl,pins = < 702 702 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 703 703 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 704 704 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 705 705 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 706 706 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 707 707 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 708 708 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 709 709 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 710 710 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 711 711 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 712 712 - >; 713 713 - }; 714 714 - 715 715 - pinctrl_wdog: wdoggrp { 716 716 - fsl,pins = < 717 717 - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 718 718 - >; 719 719 - }; 483 483 + pinctrl_hog: hoggrp { 484 484 + fsl,pins = < 485 485 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 486 486 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 487 487 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 488 488 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 489 489 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 490 490 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 491 491 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 492 492 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 493 493 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 494 494 + >; 720 495 }; 721 496 722 722 - gpio_leds { 723 723 - pinctrl_gpio_leds: gpioledsgrp { 724 724 - fsl,pins = < 725 725 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 726 726 - >; 727 727 - }; 497 497 + pinctrl_audmux: audmuxgrp { 498 498 + fsl,pins = < 499 499 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 500 500 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 501 501 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 502 502 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 503 503 + >; 504 504 + }; 505 505 + 506 506 + pinctrl_ecspi1: ecspi1grp { 507 507 + fsl,pins = < 508 508 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 509 509 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 510 510 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 511 511 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 512 512 + >; 513 513 + }; 514 514 + 515 515 + pinctrl_enet: enetgrp { 516 516 + fsl,pins = < 517 517 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 518 518 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 519 519 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 520 520 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 521 521 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 522 522 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 523 523 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 524 524 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 525 525 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 526 526 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 527 527 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 528 528 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 529 529 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 530 530 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 531 531 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 532 532 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 533 533 + >; 534 534 + }; 535 535 + 536 536 + pinctrl_gpio_keys: gpio_keysgrp { 537 537 + fsl,pins = < 538 538 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 539 539 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 540 540 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 541 541 + >; 542 542 + }; 543 543 + 544 544 + pinctrl_hdmi_cec: hdmicecgrp { 545 545 + fsl,pins = < 546 546 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 547 547 + >; 548 548 + }; 549 549 + 550 550 + pinctrl_hp: hpgrp { 551 551 + fsl,pins = < 552 552 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 553 553 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 554 554 + >; 555 555 + }; 556 556 + 557 557 + pinctrl_i2c1: i2c1grp { 558 558 + fsl,pins = < 559 559 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 560 560 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 561 561 + >; 562 562 + }; 563 563 + 564 564 + pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { 565 565 + fsl,pins = < 566 566 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 567 567 + >; 568 568 + }; 569 569 + 570 570 + pinctrl_i2c2: i2c2grp { 571 571 + fsl,pins = < 572 572 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 573 573 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 574 574 + >; 575 575 + }; 576 576 + 577 577 + pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { 578 578 + fsl,pins = < 579 579 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 580 580 + >; 581 581 + }; 582 582 + 583 583 + pinctrl_i2c3: i2c3grp { 584 584 + fsl,pins = < 585 585 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 586 586 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 587 587 + >; 588 588 + }; 589 589 + 590 590 + pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { 591 591 + fsl,pins = < 592 592 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 593 593 + >; 594 594 + }; 595 595 + 596 596 + pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { 597 597 + fsl,pins = < 598 598 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 599 599 + >; 600 600 + }; 601 601 + 602 602 + pinctrl_ipu1_csi0: ipu1csi0grp { 603 603 + fsl,pins = < 604 604 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 605 605 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 606 606 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 607 607 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 608 608 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 609 609 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 610 610 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 611 611 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 612 612 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 613 613 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 614 614 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 615 615 + >; 616 616 + }; 617 617 + 618 618 + pinctrl_ov5640: ov5640grp { 619 619 + fsl,pins = < 620 620 + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 621 621 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 622 622 + >; 623 623 + }; 624 624 + 625 625 + pinctrl_ov5642: ov5642grp { 626 626 + fsl,pins = < 627 627 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 628 628 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 629 629 + >; 630 630 + }; 631 631 + 632 632 + pinctrl_pcie: pciegrp { 633 633 + fsl,pins = < 634 634 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 635 635 + >; 636 636 + }; 637 637 + 638 638 + pinctrl_pcie_reg: pciereggrp { 639 639 + fsl,pins = < 640 640 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 641 641 + >; 642 642 + }; 643 643 + 644 644 + pinctrl_pwm1: pwm1grp { 645 645 + fsl,pins = < 646 646 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 647 647 + >; 648 648 + }; 649 649 + 650 650 + pinctrl_sensors_reg: sensorsreggrp { 651 651 + fsl,pins = < 652 652 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 653 653 + >; 654 654 + }; 655 655 + 656 656 + pinctrl_uart1: uart1grp { 657 657 + fsl,pins = < 658 658 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 659 659 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 660 660 + >; 661 661 + }; 662 662 + 663 663 + pinctrl_usbotg: usbotggrp { 664 664 + fsl,pins = < 665 665 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 666 666 + >; 667 667 + }; 668 668 + 669 669 + pinctrl_usdhc2: usdhc2grp { 670 670 + fsl,pins = < 671 671 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 672 672 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 673 673 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 674 674 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 675 675 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 676 676 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 677 677 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 678 678 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 679 679 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 680 680 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 681 681 + >; 682 682 + }; 683 683 + 684 684 + pinctrl_usdhc3: usdhc3grp { 685 685 + fsl,pins = < 686 686 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 687 687 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 688 688 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 689 689 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 690 690 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 691 691 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 692 692 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 693 693 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 694 694 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 695 695 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 696 696 + >; 697 697 + }; 698 698 + 699 699 + pinctrl_usdhc4: usdhc4grp { 700 700 + fsl,pins = < 701 701 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 702 702 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 703 703 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 704 704 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 705 705 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 706 706 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 707 707 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 708 708 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 709 709 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 710 710 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 711 711 + >; 712 712 + }; 713 713 + 714 714 + pinctrl_wdog: wdoggrp { 715 715 + fsl,pins = < 716 716 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 717 717 + >; 718 718 + }; 719 719 + 720 720 + pinctrl_gpio_leds: gpioledsgrp { 721 721 + fsl,pins = < 722 722 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 723 723 + >; 728 724 }; 729 725 }; 730 726

+38 -40

arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi

reviewed

··· 93 93 &iomuxc { 94 94 pinctrl-0 = <&pinctrl_hog>, <&pinctrl_solidsense_hog>; 95 95 96 96 - solidsense { 97 97 - pinctrl_solidsense_hog: solidsense-hog { 98 98 - fsl,pins = < 99 99 - /* Nordic RESET_N */ 100 100 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x400130b1 101 101 - /* Nordic Chip 1 SWDIO - GPIO 125 */ 102 102 - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x400130b1 103 103 - /* Nordic Chip 1 SWDCLK - GPIO 59 */ 104 104 - /* already claimed in the HB2 hogs */ 105 105 - /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */ 106 106 - /* Nordic Chip 2 SWDIO - GPIO 81 */ 107 107 - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x400130b1 108 108 - /* Nordic Chip 2 SWCLK - GPIO 82 */ 109 109 - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x400130b1 110 110 - >; 111 111 - }; 96 96 + pinctrl_solidsense_hog: solidsense-hoggrp { 97 97 + fsl,pins = < 98 98 + /* Nordic RESET_N */ 99 99 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x400130b1 100 100 + /* Nordic Chip 1 SWDIO - GPIO 125 */ 101 101 + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x400130b1 102 102 + /* Nordic Chip 1 SWDCLK - GPIO 59 */ 103 103 + /* already claimed in the HB2 hogs */ 104 104 + /* MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 */ 105 105 + /* Nordic Chip 2 SWDIO - GPIO 81 */ 106 106 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x400130b1 107 107 + /* Nordic Chip 2 SWCLK - GPIO 82 */ 108 108 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x400130b1 109 109 + >; 110 110 + }; 112 111 113 113 - pinctrl_solidsense_leds: solidsense-leds { 114 114 - fsl,pins = < 115 115 - /* Red LED 1 - GPIO 58 */ 116 116 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x400130b1 117 117 - /* Green LED 1 - GPIO 55 */ 118 118 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x400130b1 119 119 - /* Red LED 2 - GPIO 57 */ 120 120 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x400130b1 121 121 - /* Green LED 2 - GPIO 56 */ 122 122 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x400130b1 123 123 - >; 124 124 - }; 112 112 + pinctrl_solidsense_leds: solidsense-ledsgrp { 113 113 + fsl,pins = < 114 114 + /* Red LED 1 - GPIO 58 */ 115 115 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x400130b1 116 116 + /* Green LED 1 - GPIO 55 */ 117 117 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x400130b1 118 118 + /* Red LED 2 - GPIO 57 */ 119 119 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x400130b1 120 120 + /* Green LED 2 - GPIO 56 */ 121 121 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x400130b1 122 122 + >; 123 123 + }; 125 124 126 126 - pinctrl_solidsense_uart2: solidsense-uart2 { 127 127 - fsl,pins = < 128 128 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 129 129 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 130 130 - >; 131 131 - }; 125 125 + pinctrl_solidsense_uart2: solidsense-uart2grp { 126 126 + fsl,pins = < 127 127 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 128 128 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 129 129 + >; 130 130 + }; 132 131 133 133 - pinctrl_solidsense_uart3: solidsense-uart3 { 134 134 - fsl,pins = < 135 135 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 136 136 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 137 137 - >; 138 138 - }; 132 132 + pinctrl_solidsense_uart3: solidsense-uart3grp { 133 133 + fsl,pins = < 134 134 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 135 135 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 136 136 + >; 139 137 }; 140 138 }; 141 139

+42 -44

arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi

reviewed

··· 70 70 }; 71 71 72 72 &iomuxc { 73 73 - microsom { 74 74 - pinctrl_microsom_brcm_bt: microsom-brcm-bt { 75 75 - fsl,pins = < 76 76 - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 77 77 - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 78 78 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 79 79 - >; 80 80 - }; 73 73 + pinctrl_microsom_brcm_bt: microsom-brcm-btgrp { 74 74 + fsl,pins = < 75 75 + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 76 76 + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 77 77 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 78 78 + >; 79 79 + }; 81 80 82 82 - pinctrl_microsom_brcm_osc: microsom-brcm-osc { 83 83 - fsl,pins = < 84 84 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 85 85 - >; 86 86 - }; 81 81 + pinctrl_microsom_brcm_osc: microsom-brcm-oscgrp { 82 82 + fsl,pins = < 83 83 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 84 84 + >; 85 85 + }; 87 86 88 88 - pinctrl_microsom_brcm_reg: microsom-brcm-reg { 89 89 - fsl,pins = < 90 90 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 91 91 - >; 92 92 - }; 87 87 + pinctrl_microsom_brcm_reg: microsom-brcm-reggrp { 88 88 + fsl,pins = < 89 89 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 90 90 + >; 91 91 + }; 93 92 94 94 - pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { 95 95 - fsl,pins = < 96 96 - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 97 97 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 98 98 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 99 99 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 100 100 - >; 101 101 - }; 93 93 + pinctrl_microsom_brcm_wifi: microsom-brcm-wifigrp { 94 94 + fsl,pins = < 95 95 + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 96 96 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 97 97 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 98 98 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 99 99 + >; 100 100 + }; 102 101 103 103 - pinctrl_microsom_uart4: microsom-uart4 { 104 104 - fsl,pins = < 105 105 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 106 106 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 107 107 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 108 108 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 109 109 - >; 110 110 - }; 102 102 + pinctrl_microsom_uart4: microsom-uart4grp { 103 103 + fsl,pins = < 104 104 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 105 105 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 106 106 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 107 107 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 108 108 + >; 109 109 + }; 111 110 112 112 - pinctrl_microsom_usdhc1: microsom-usdhc1 { 113 113 - fsl,pins = < 114 114 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 115 115 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 116 116 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 117 117 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 118 118 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 119 119 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 120 120 - >; 121 121 - }; 111 111 + pinctrl_microsom_usdhc1: microsom-usdhc1grp { 112 112 + fsl,pins = < 113 113 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 114 114 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 115 115 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 116 116 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 117 117 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 118 118 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 119 119 + >; 122 120 }; 123 121 }; 124 122

+14 -16

arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi

reviewed

··· 40 40 */ 41 41 42 42 &iomuxc { 43 43 - microsom { 44 44 - pinctrl_microsom_usdhc3: microsom-usdhc3 { 45 45 - fsl,pins = < 46 46 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 47 47 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 48 48 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 49 49 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 50 50 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 51 51 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 52 52 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 53 53 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 54 54 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 55 55 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 56 56 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 57 57 - >; 58 58 - }; 43 43 + pinctrl_microsom_usdhc3: microsom-usdhc3grp { 44 44 + fsl,pins = < 45 45 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 46 46 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 47 47 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 48 48 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 49 49 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 50 50 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 51 51 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 52 52 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 53 53 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 54 54 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 55 55 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 56 56 + >; 59 57 }; 60 58 }; 61 59

+43 -45

arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi

reviewed

··· 76 76 }; 77 77 78 78 &iomuxc { 79 79 - microsom { 80 80 - pinctrl_microsom_ti_bt: microsom-ti-bt { 81 81 - fsl,pins = < 82 82 - /* BT_EN_SOC */ 83 83 - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 84 84 - >; 85 85 - }; 79 79 + pinctrl_microsom_ti_bt: microsom-ti-btgrp { 80 80 + fsl,pins = < 81 81 + /* BT_EN_SOC */ 82 82 + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 83 83 + >; 84 84 + }; 86 85 87 87 - pinctrl_microsom_ti_clk: microsom-ti-clk { 88 88 - fsl,pins = < 89 89 - /* EXT_32K */ 90 90 - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 91 91 - /* WL_XTAL_PU (unrouted) */ 92 92 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 93 93 - >; 94 94 - }; 86 86 + pinctrl_microsom_ti_clk: microsom-ti-clkgrp { 87 87 + fsl,pins = < 88 88 + /* EXT_32K */ 89 89 + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 90 90 + /* WL_XTAL_PU (unrouted) */ 91 91 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 92 92 + >; 93 93 + }; 95 94 96 96 - pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { 97 97 - fsl,pins = < 98 98 - /* WLAN_EN_SOC */ 99 99 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 100 100 - >; 101 101 - }; 95 95 + pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-engrp { 96 96 + fsl,pins = < 97 97 + /* WLAN_EN_SOC */ 98 98 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 99 99 + >; 100 100 + }; 102 101 103 103 - pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { 104 104 - fsl,pins = < 105 105 - /* WLAN_IRQ */ 106 106 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 107 107 - >; 108 108 - }; 102 102 + pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irqgrp { 103 103 + fsl,pins = < 104 104 + /* WLAN_IRQ */ 105 105 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 106 106 + >; 107 107 + }; 109 108 110 110 - pinctrl_microsom_uart4: microsom-uart4 { 111 111 - fsl,pins = < 112 112 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 113 113 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 114 114 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 115 115 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 116 116 - >; 117 117 - }; 109 109 + pinctrl_microsom_uart4: microsom-uart4grp { 110 110 + fsl,pins = < 111 111 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 112 112 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 113 113 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 114 114 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 115 115 + >; 116 116 + }; 118 117 119 119 - pinctrl_microsom_usdhc1: microsom-usdhc1 { 120 120 - fsl,pins = < 121 121 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 122 122 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 123 123 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 124 124 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 125 125 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 126 126 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 127 127 - >; 128 128 - }; 118 118 + pinctrl_microsom_usdhc1: microsom-usdhc1grp { 119 119 + fsl,pins = < 120 120 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 121 121 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 122 122 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 123 123 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 124 124 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 125 125 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 126 126 + >; 129 127 }; 130 128 }; 131 129

+47 -49

arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi

reviewed

··· 97 97 }; 98 98 99 99 &iomuxc { 100 100 - microsom { 101 101 - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 102 102 - fsl,pins = < 103 103 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 104 104 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 105 105 - /* AR8035 reset */ 106 106 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 107 107 - /* AR8035 interrupt */ 108 108 - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 109 109 - /* GPIO16 -> AR8035 25MHz */ 110 110 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 111 111 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 112 112 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 113 113 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 114 114 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 115 115 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 116 116 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 117 117 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 118 118 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 119 119 - /* AR8035 pin strapping: IO voltage: pull up */ 120 120 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 121 121 - /* AR8035 pin strapping: PHYADDR#0: pull down */ 122 122 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 123 123 - /* AR8035 pin strapping: PHYADDR#1: pull down */ 124 124 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 125 125 - /* AR8035 pin strapping: MODE#1: pull up */ 126 126 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 127 127 - /* AR8035 pin strapping: MODE#3: pull up */ 128 128 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 129 129 - /* AR8035 pin strapping: MODE#0: pull down */ 130 130 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 100 100 + pinctrl_microsom_enet_ar8035: microsom-enet-ar8035grp { 101 101 + fsl,pins = < 102 102 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 103 103 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 104 104 + /* AR8035 reset */ 105 105 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 106 106 + /* AR8035 interrupt */ 107 107 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 108 108 + /* GPIO16 -> AR8035 25MHz */ 109 109 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 110 110 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 111 111 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 112 112 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 113 113 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 114 114 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 115 115 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 116 116 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 117 117 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 118 118 + /* AR8035 pin strapping: IO voltage: pull up */ 119 119 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 120 120 + /* AR8035 pin strapping: PHYADDR#0: pull down */ 121 121 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 122 122 + /* AR8035 pin strapping: PHYADDR#1: pull down */ 123 123 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 124 124 + /* AR8035 pin strapping: MODE#1: pull up */ 125 125 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 126 126 + /* AR8035 pin strapping: MODE#3: pull up */ 127 127 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 128 128 + /* AR8035 pin strapping: MODE#0: pull down */ 129 129 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 131 130 132 132 - /* 133 133 - * As the RMII pins are also connected to RGMII 134 134 - * so that an AR8030 can be placed, set these 135 135 - * to high-z with the same pulls as above. 136 136 - * Use the GPIO settings to avoid changing the 137 137 - * input select registers. 138 138 - */ 139 139 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 140 140 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 141 141 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 142 142 - >; 143 143 - }; 131 131 + /* 132 132 + * As the RMII pins are also connected to RGMII 133 133 + * so that an AR8030 can be placed, set these 134 134 + * to high-z with the same pulls as above. 135 135 + * Use the GPIO settings to avoid changing the 136 136 + * input select registers. 137 137 + */ 138 138 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 139 139 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 140 140 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 141 141 + >; 142 142 + }; 144 143 145 145 - pinctrl_microsom_uart1: microsom-uart1 { 146 146 - fsl,pins = < 147 147 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 148 148 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 149 149 - >; 150 150 - }; 144 144 + pinctrl_microsom_uart1: microsom-uart1grp { 145 145 + fsl,pins = < 146 146 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 147 147 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 148 148 + >; 151 149 }; 152 150 }; 153 151

+2 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi

reviewed

··· 265 265 >; 266 266 }; 267 267 268 268 - pinctrl_ecspi2: ecspi2 { 268 268 + pinctrl_ecspi2: ecspi2grp { 269 269 fsl,pins = < 270 270 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 271 271 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 ··· 280 280 >; 281 281 }; 282 282 283 283 - pinctrl_enet: enet { 283 283 + pinctrl_enet: enetgrp { 284 284 fsl,pins = < 285 285 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 286 286 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0

-1

arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi

reviewed

··· 51 51 pinctrl-0 = <&pinctrl_lcd1_pwr>; 52 52 enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; 53 53 power-supply = <&reg_3v3>; 54 54 - turn-on-delay-ms = <35>; 55 54 /* 56 55 * a poor man's way to create a 1:1 relationship between 57 56 * the PWM value and the actual duty cycle

-2

arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi

reviewed

··· 42 42 / { 43 43 backlight0 { 44 44 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; 45 45 - turn-on-delay-ms = <35>; 46 45 power-supply = <&reg_lcd1_pwr>; 47 46 }; 48 47 49 48 backlight1 { 50 49 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; 51 51 - turn-on-delay-ms = <35>; 52 50 power-supply = <&reg_lcd1_pwr>; 53 51 }; 54 52

+1 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi

reviewed

··· 70 70 #address-cells = <1>; 71 71 #size-cells = <0>; 72 72 73 73 - mclk: clock@0 { 73 73 + mclk: clock { 74 74 compatible = "fixed-clock"; 75 75 - reg = <0>; 76 75 #clock-cells = <0>; 77 76 clock-frequency = <26000000>; 78 77 };

+111 -113

arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi

reviewed

··· 117 117 }; 118 118 119 119 &iomuxc { 120 120 - imx6q-udoo { 121 121 - pinctrl_enet: enetgrp { 122 122 - fsl,pins = < 123 123 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 124 124 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 125 125 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 126 126 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 127 127 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 128 128 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 129 129 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 130 130 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 131 131 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 132 132 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 133 133 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 134 134 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 135 135 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 136 136 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 137 137 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 138 138 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 139 139 - >; 140 140 - }; 120 120 + pinctrl_enet: enetgrp { 121 121 + fsl,pins = < 122 122 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 123 123 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 124 124 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 125 125 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 126 126 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 127 127 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 128 128 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 129 129 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 130 130 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 131 131 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 132 132 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 133 133 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 134 134 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 135 135 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 136 136 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 137 137 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 138 138 + >; 139 139 + }; 141 140 142 142 - pinctrl_i2c2: i2c2grp { 143 143 - fsl,pins = < 144 144 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 145 145 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 146 146 - >; 147 147 - }; 141 141 + pinctrl_i2c2: i2c2grp { 142 142 + fsl,pins = < 143 143 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 144 144 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 145 145 + >; 146 146 + }; 148 147 149 149 - pinctrl_i2c3: i2c3grp { 150 150 - fsl,pins = < 151 151 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 152 152 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 153 153 - >; 154 154 - }; 148 148 + pinctrl_i2c3: i2c3grp { 149 149 + fsl,pins = < 150 150 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 151 151 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 152 152 + >; 153 153 + }; 155 154 156 156 - pinctrl_panel: panelgrp { 157 157 - fsl,pins = < 158 158 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 159 159 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 160 160 - >; 161 161 - }; 155 155 + pinctrl_panel: panelgrp { 156 156 + fsl,pins = < 157 157 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 158 158 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 159 159 + >; 160 160 + }; 162 161 163 163 - pinctrl_power_off: poweroffgrp { 164 164 - fsl,pins = < 165 165 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 166 166 - >; 167 167 - }; 162 162 + pinctrl_power_off: poweroffgrp { 163 163 + fsl,pins = < 164 164 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 165 165 + >; 166 166 + }; 168 167 169 169 - pinctrl_touchscreenp7: touchscreenp7grp { 170 170 - fsl,pins = < 171 171 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 172 172 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 173 173 - >; 174 174 - }; 168 168 + pinctrl_touchscreenp7: touchscreenp7grp { 169 169 + fsl,pins = < 170 170 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 171 171 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 172 172 + >; 173 173 + }; 175 174 176 176 - pinctrl_uart2: uart2grp { 177 177 - fsl,pins = < 178 178 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 179 179 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 180 180 - >; 181 181 - }; 175 175 + pinctrl_uart2: uart2grp { 176 176 + fsl,pins = < 177 177 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 178 178 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 179 179 + >; 180 180 + }; 182 181 183 183 - pinctrl_uart4: uart4grp { 184 184 - fsl,pins = < 185 185 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 186 186 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 187 187 - >; 188 188 - }; 182 182 + pinctrl_uart4: uart4grp { 183 183 + fsl,pins = < 184 184 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 185 185 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 186 186 + >; 187 187 + }; 189 188 190 190 - pinctrl_usbh: usbhgrp { 191 191 - fsl,pins = < 192 192 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 193 193 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 194 194 - >; 195 195 - }; 189 189 + pinctrl_usbh: usbhgrp { 190 190 + fsl,pins = < 191 191 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 192 192 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 193 193 + >; 194 194 + }; 196 195 197 197 - pinctrl_usbotg: usbotg { 198 198 - fsl,pins = < 199 199 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 200 200 - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 201 201 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 202 202 - >; 203 203 - }; 196 196 + pinctrl_usbotg: usbotggrp { 197 197 + fsl,pins = < 198 198 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 199 199 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 200 200 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 201 201 + >; 202 202 + }; 204 203 205 205 - pinctrl_usdhc3: usdhc3grp { 206 206 - fsl,pins = < 207 207 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 208 208 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 209 209 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 210 210 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 211 211 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 212 212 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 213 213 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 214 214 - >; 215 215 - }; 204 204 + pinctrl_usdhc3: usdhc3grp { 205 205 + fsl,pins = < 206 206 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 207 207 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 208 208 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 209 209 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 210 210 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 211 211 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 212 212 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 213 213 + >; 214 214 + }; 216 215 217 217 - pinctrl_ac97_running: ac97running { 218 218 - fsl,pins = < 219 219 - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 220 220 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 221 221 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 222 222 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 223 223 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 224 224 - >; 225 225 - }; 216 216 + pinctrl_ac97_running: ac97runninggrp { 217 217 + fsl,pins = < 218 218 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 219 219 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 220 220 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 221 221 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 222 222 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 223 223 + >; 224 224 + }; 226 225 227 227 - pinctrl_ac97_warm_reset: ac97warmreset { 228 228 - fsl,pins = < 229 229 - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 230 230 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 231 231 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 232 232 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 233 233 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 234 234 - >; 235 235 - }; 226 226 + pinctrl_ac97_warm_reset: ac97warmresetgrp { 227 227 + fsl,pins = < 228 228 + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 229 229 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 230 230 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 231 231 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 232 232 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 233 233 + >; 234 234 + }; 236 235 237 237 - pinctrl_ac97_reset: ac97reset { 238 238 - fsl,pins = < 239 239 - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 240 240 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 241 241 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 242 242 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 243 243 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 244 244 - >; 245 245 - }; 236 236 + pinctrl_ac97_reset: ac97resetgrp { 237 237 + fsl,pins = < 238 238 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 239 239 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 240 240 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 241 241 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 242 242 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 243 243 + >; 246 244 }; 247 245 }; 248 246

+2 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi

reviewed

··· 194 194 }; 195 195 196 196 &iomuxc { 197 197 - pinctrl_audmux: audmux { 197 197 + pinctrl_audmux: audmuxgrp { 198 198 fsl,pins = < 199 199 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 200 200 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 ··· 205 205 >; 206 206 }; 207 207 208 208 - pinctrl_bt: bt { 208 208 + pinctrl_bt: btgrp { 209 209 fsl,pins = < 210 210 /* Bluetooth enable */ 211 211 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1

+2 -2

arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi

reviewed

··· 529 529 }; 530 530 531 531 &usbphy1 { 532 532 - fsl,tx-d-cal = <0x5>; 532 532 + fsl,tx-d-cal = <106>; 533 533 }; 534 534 535 535 &usbphy2 { 536 536 - fsl,tx-d-cal = <0x5>; 536 536 + fsl,tx-d-cal = <106>; 537 537 }; 538 538 539 539 &usdhc1 {

+14 -16

arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi

reviewed

··· 9 9 &iomuxc { 10 10 pinctrl-0 = <&pinctrl_hog>; 11 11 12 12 - imx6qdl-wandboard { 13 13 - pinctrl_hog: hoggrp { 14 14 - fsl,pins = < 15 15 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ 16 16 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 17 17 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ 18 18 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ 19 19 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ 20 20 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ 21 21 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ 22 22 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ 23 23 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ 24 24 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ 25 25 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ 26 26 - >; 27 27 - }; 12 12 + pinctrl_hog: hoggrp { 13 13 + fsl,pins = < 14 14 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ 15 15 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 16 16 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ 17 17 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ 18 18 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ 19 19 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ 20 20 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ 21 21 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ 22 22 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ 23 23 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ 24 24 + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ 25 25 + >; 28 26 }; 29 27 }; 30 28

+15 -17

arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi

reviewed

··· 7 7 #include "imx6qdl-wandboard.dtsi" 8 8 9 9 &iomuxc { 10 10 - pinctrl-0 = <&pinctrl_hog>; 10 10 + pinctrl-0 = <&pinctrl_hog_c1>; 11 11 12 12 - imx6qdl-wandboard { 13 13 - pinctrl_hog: hoggrp { 14 14 - fsl,pins = < 15 15 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ 16 16 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 17 17 - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ 18 18 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ 19 19 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ 20 20 - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ 21 21 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ 22 22 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ 23 23 - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ 24 24 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ 25 25 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ 26 26 - >; 27 27 - }; 12 12 + pinctrl_hog_c1: hogc1grp { 13 13 + fsl,pins = < 14 14 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ 15 15 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 16 16 + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ 17 17 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ 18 18 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ 19 19 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ 20 20 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ 21 21 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ 22 22 + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ 23 23 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ 24 24 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ 25 25 + >; 28 26 }; 29 27 }; 30 28

+37 -39

arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi

reviewed

··· 137 137 }; 138 138 139 139 &iomuxc { 140 140 - pinctrl-0 = <&pinctrl_hog>; 140 140 + pinctrl-0 = <&pinctrl_hog_d1>; 141 141 142 142 - imx6qdl-wandboard { 143 143 - pinctrl_hog: hoggrp { 144 144 - fsl,pins = < 145 145 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ 146 146 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 147 147 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ 148 148 - >; 149 149 - }; 142 142 + pinctrl_hog_d1: hoggrp { 143 143 + fsl,pins = < 144 144 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ 145 145 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ 146 146 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ 147 147 + >; 148 148 + }; 150 149 151 151 - pinctrl_enet: enetgrp { 152 152 - fsl,pins = < 153 153 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 154 154 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 155 155 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 156 156 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 157 157 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 158 158 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 159 159 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 160 160 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 161 161 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 162 162 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 163 163 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 164 164 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 165 165 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 166 166 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 167 167 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 168 168 - >; 169 169 - }; 150 150 + enetgrp { 151 151 + fsl,pins = < 152 152 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 153 153 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 154 154 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 155 155 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 156 156 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 157 157 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 158 158 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 159 159 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 160 160 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 161 161 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 162 162 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 163 163 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 164 164 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 165 165 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 166 166 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 167 167 + >; 168 168 + }; 170 169 171 171 - pinctrl_i2c3: i2c3grp { 172 172 - fsl,pins = < 173 173 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 174 174 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 175 175 - >; 176 176 - }; 170 170 + pinctrl_i2c3: i2c3grp { 171 171 + fsl,pins = < 172 172 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 173 173 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 174 174 + >; 175 175 + }; 177 176 178 178 - pinctrl_spdif: spdifgrp { 179 179 - fsl,pins = < 180 180 - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 181 181 - >; 182 182 - }; 177 177 + pinctrl_spdif: spdifgrp { 178 178 + fsl,pins = < 179 179 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 180 180 + >; 183 181 }; 184 182 }; 185 183

+122 -125

arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi

reviewed

··· 157 157 &iomuxc { 158 158 pinctrl-names = "default"; 159 159 160 160 - imx6qdl-wandboard { 160 160 + pinctrl_audmux: audmuxgrp { 161 161 + fsl,pins = < 162 162 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 163 163 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 164 164 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 165 165 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 166 166 + >; 167 167 + }; 161 168 162 162 - pinctrl_audmux: audmuxgrp { 163 163 - fsl,pins = < 164 164 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 165 165 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 166 166 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 167 167 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 168 168 - >; 169 169 - }; 169 169 + pinctrl_enet: enetgrp { 170 170 + fsl,pins = < 171 171 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 172 172 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 173 173 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 174 174 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 175 175 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 176 176 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 177 177 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 178 178 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 179 179 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 180 180 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 181 181 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 182 182 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 183 183 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 184 184 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 185 185 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 186 186 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 187 187 + >; 188 188 + }; 170 189 171 171 - pinctrl_enet: enetgrp { 172 172 - fsl,pins = < 173 173 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 174 174 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 175 175 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 176 176 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 177 177 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 178 178 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 179 179 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 180 180 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 181 181 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 182 182 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 183 183 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 184 184 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 185 185 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 186 186 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 187 187 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 188 188 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 189 189 - >; 190 190 - }; 190 190 + pinctrl_i2c1: i2c1grp { 191 191 + fsl,pins = < 192 192 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 193 193 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 194 194 + >; 195 195 + }; 191 196 192 192 - pinctrl_i2c1: i2c1grp { 193 193 - fsl,pins = < 194 194 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 195 195 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 196 196 - >; 197 197 - }; 197 197 + pinctrl_i2c1_gpio: i2c1gpiogrp { 198 198 + fsl,pins = < 199 199 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 200 200 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 201 201 + >; 202 202 + }; 198 203 199 199 - pinctrl_i2c1_gpio: i2c1gpiogrp { 200 200 - fsl,pins = < 201 201 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0 202 202 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0 203 203 - >; 204 204 - }; 204 204 + pinctrl_i2c2: i2c2grp { 205 205 + fsl,pins = < 206 206 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 207 207 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 208 208 + >; 209 209 + }; 205 210 206 206 - pinctrl_i2c2: i2c2grp { 207 207 - fsl,pins = < 208 208 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 209 209 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 210 210 - >; 211 211 - }; 211 211 + pinctrl_i2c2_gpio: i2c2gpiogrp { 212 212 + fsl,pins = < 213 213 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 214 214 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 215 215 + >; 216 216 + }; 212 217 213 213 - pinctrl_i2c2_gpio: i2c2gpiogrp { 214 214 - fsl,pins = < 215 215 - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0 216 216 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0 217 217 - >; 218 218 - }; 218 218 + pinctrl_mclk: mclkgrp { 219 219 + fsl,pins = < 220 220 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 221 221 + >; 222 222 + }; 219 223 220 220 - pinctrl_mclk: mclkgrp { 221 221 - fsl,pins = < 222 222 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 223 223 - >; 224 224 - }; 224 224 + pinctrl_ov5645: ov5645grp { 225 225 + fsl,pins = < 226 226 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 227 227 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 228 228 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 229 229 + >; 230 230 + }; 225 231 226 226 - pinctrl_ov5645: ov5645grp { 227 227 - fsl,pins = < 228 228 - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 229 229 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 230 230 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 231 231 - >; 232 232 - }; 232 232 + pinctrl_spdif: spdifgrp { 233 233 + fsl,pins = < 234 234 + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 235 235 + >; 236 236 + }; 233 237 234 234 - pinctrl_spdif: spdifgrp { 235 235 - fsl,pins = < 236 236 - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 237 237 - >; 238 238 - }; 238 238 + pinctrl_uart1: uart1grp { 239 239 + fsl,pins = < 240 240 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 241 241 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 242 242 + >; 243 243 + }; 239 244 240 240 - pinctrl_uart1: uart1grp { 241 241 - fsl,pins = < 242 242 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 243 243 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 244 244 - >; 245 245 - }; 245 245 + pinctrl_uart3: uart3grp { 246 246 + fsl,pins = < 247 247 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 248 248 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 249 249 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 250 250 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 251 251 + >; 252 252 + }; 246 253 247 247 - pinctrl_uart3: uart3grp { 248 248 - fsl,pins = < 249 249 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 250 250 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 251 251 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 252 252 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 253 253 - >; 254 254 - }; 254 254 + pinctrl_usbotg: usbotggrp { 255 255 + fsl,pins = < 256 256 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 257 257 + >; 258 258 + }; 255 259 256 256 - pinctrl_usbotg: usbotggrp { 257 257 - fsl,pins = < 258 258 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 259 259 - >; 260 260 - }; 260 260 + pinctrl_usbotgvbus: usbotgvbusgrp { 261 261 + fsl,pins = < 262 262 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 263 263 + >; 264 264 + }; 261 265 262 262 - pinctrl_usbotgvbus: usbotgvbusgrp { 263 263 - fsl,pins = < 264 264 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 265 265 - >; 266 266 - }; 266 266 + pinctrl_usdhc1: usdhc1grp { 267 267 + fsl,pins = < 268 268 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 269 269 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 270 270 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 271 271 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 272 272 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 273 273 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 274 274 + >; 275 275 + }; 267 276 268 268 - pinctrl_usdhc1: usdhc1grp { 269 269 - fsl,pins = < 270 270 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 271 271 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 272 272 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 273 273 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 274 274 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 275 275 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 276 276 - >; 277 277 - }; 277 277 + pinctrl_usdhc2: usdhc2grp { 278 278 + fsl,pins = < 279 279 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 280 280 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 281 281 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 282 282 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 283 283 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 284 284 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 285 285 + >; 286 286 + }; 278 287 279 279 - pinctrl_usdhc2: usdhc2grp { 280 280 - fsl,pins = < 281 281 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 282 282 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 283 283 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 284 284 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 285 285 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 286 286 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 287 287 - >; 288 288 - }; 289 289 - 290 290 - pinctrl_usdhc3: usdhc3grp { 291 291 - fsl,pins = < 292 292 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 293 293 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 294 294 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 295 295 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 296 296 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 297 297 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 298 298 - >; 299 299 - }; 288 288 + pinctrl_usdhc3: usdhc3grp { 289 289 + fsl,pins = < 290 290 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 291 291 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 292 292 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 293 293 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 294 294 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 295 295 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 296 296 + >; 300 297 }; 301 298 }; 302 299

+1 -1

arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts

reviewed

··· 548 548 >; 549 549 }; 550 550 551 551 - pinctrl_wifi_npd: wifinpd { 551 551 + pinctrl_wifi_npd: wifinpdgrp { 552 552 fsl,pins = < 553 553 /* WL_REG_ON */ 554 554 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069

+19 -21

arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts

reviewed

··· 22 22 }; 23 23 24 24 &iomuxc { 25 25 - imx6qdl-sabreauto { 26 26 - pinctrl_enet: enetgrp { 27 27 - fsl,pins = < 28 28 - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 29 29 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 30 30 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 31 31 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 32 32 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 33 33 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 34 34 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 35 35 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 36 36 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 37 37 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 38 38 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 39 39 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 40 40 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 41 41 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 42 42 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 43 43 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 44 44 - >; 45 45 - }; 25 25 + pinctrl_enet: enetgrp { 26 26 + fsl,pins = < 27 27 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 28 28 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 29 29 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 30 30 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 31 31 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 32 32 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 33 33 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 34 34 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 35 35 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 36 36 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 37 37 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 38 38 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 39 39 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 40 40 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 41 41 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 42 42 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 43 43 + >; 46 44 }; 47 45 }; 48 46

+27 -29

arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts

reviewed

··· 17 17 }; 18 18 19 19 &iomuxc { 20 20 - imx6qdl-sabresd { 21 21 - pinctrl_usdhc2: usdhc2grp { 22 22 - fsl,pins = < 23 23 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 24 24 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 25 25 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 26 26 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 27 27 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 28 28 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 29 29 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 30 30 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 31 31 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 32 32 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 33 33 - >; 34 34 - }; 20 20 + pinctrl_usdhc2: usdhc2grp { 21 21 + fsl,pins = < 22 22 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 23 23 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 24 24 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 25 25 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 26 26 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 27 27 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 28 28 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 29 29 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 30 30 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 31 31 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 32 32 + >; 33 33 + }; 35 34 36 36 - pinctrl_usdhc3: usdhc3grp { 37 37 - fsl,pins = < 38 38 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 39 39 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 40 40 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 41 41 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 42 42 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 43 43 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 44 44 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 45 45 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 46 46 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 47 47 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 48 48 - >; 49 49 - }; 35 35 + pinctrl_usdhc3: usdhc3grp { 36 36 + fsl,pins = < 37 37 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 38 38 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 39 39 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 40 40 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 41 41 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 42 42 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 43 43 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 44 44 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 45 45 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 46 46 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 47 47 + >; 50 48 }; 51 49 }; 52 50

+1 -1

arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts

reviewed

··· 3 3 * Copyright (C) 2021 DH electronics GmbH 4 4 * 5 5 * DHCOM iMX6 variant: 6 6 - * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 6 6 + * DHCM-iMX6S-C080-R102-F0409-E-CAN2-RTC-I-01D2 7 7 * DHCOM PCB number: 493-400 or newer 8 8 * DRC02 PCB number: 568-100 or newer 9 9 */

+239 -241

arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts

reviewed

··· 287 287 pinctrl-names = "default"; 288 288 pinctrl-0 = <&pinctrl_hog>; 289 289 290 290 - imx6sl-evk { 291 291 - pinctrl_hog: hoggrp { 292 292 - fsl,pins = < 293 293 - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 294 294 - MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 295 295 - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 296 296 - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 297 297 - MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 298 298 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 299 299 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 300 300 - MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 301 301 - >; 302 302 - }; 290 290 + pinctrl_hog: hoggrp { 291 291 + fsl,pins = < 292 292 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 293 293 + MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 294 294 + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 295 295 + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 296 296 + MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 297 297 + MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 298 298 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 299 299 + MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 300 300 + >; 301 301 + }; 303 302 304 304 - pinctrl_audmux3: audmux3grp { 305 305 - fsl,pins = < 306 306 - MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 307 307 - MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 308 308 - MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 309 309 - MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 310 310 - >; 311 311 - }; 303 303 + pinctrl_audmux3: audmux3grp { 304 304 + fsl,pins = < 305 305 + MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 306 306 + MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 307 307 + MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 308 308 + MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 309 309 + >; 310 310 + }; 312 311 313 313 - pinctrl_ecspi1: ecspi1grp { 314 314 - fsl,pins = < 315 315 - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 316 316 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 317 317 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 318 318 - MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 319 319 - >; 320 320 - }; 312 312 + pinctrl_ecspi1: ecspi1grp { 313 313 + fsl,pins = < 314 314 + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 315 315 + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 316 316 + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 317 317 + MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 318 318 + >; 319 319 + }; 321 320 322 322 - pinctrl_fec: fecgrp { 323 323 - fsl,pins = < 324 324 - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 325 325 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 326 326 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 327 327 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 328 328 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 329 329 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 330 330 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 331 331 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 332 332 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 333 333 - >; 334 334 - }; 321 321 + pinctrl_fec: fecgrp { 322 322 + fsl,pins = < 323 323 + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 324 324 + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 325 325 + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 326 326 + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 327 327 + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 328 328 + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 329 329 + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 330 330 + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 331 331 + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 332 332 + >; 333 333 + }; 335 334 336 336 - pinctrl_fec_sleep: fecgrp-sleep { 337 337 - fsl,pins = < 338 338 - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 339 339 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 340 340 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 341 341 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 342 342 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 343 343 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 344 344 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 345 345 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 346 346 - >; 347 347 - }; 335 335 + pinctrl_fec_sleep: fec-sleep-grp { 336 336 + fsl,pins = < 337 337 + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 338 338 + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 339 339 + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 340 340 + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 341 341 + MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 342 342 + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 343 343 + MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 344 344 + MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 345 345 + >; 346 346 + }; 348 347 349 349 - pinctrl_hp: hpgrp { 350 350 - fsl,pins = < 351 351 - MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 352 352 - >; 353 353 - }; 348 348 + pinctrl_hp: hpgrp { 349 349 + fsl,pins = < 350 350 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 351 351 + >; 352 352 + }; 354 353 355 355 - pinctrl_i2c1: i2c1grp { 356 356 - fsl,pins = < 357 357 - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 358 358 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 359 359 - >; 360 360 - }; 354 354 + pinctrl_i2c1: i2c1grp { 355 355 + fsl,pins = < 356 356 + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 357 357 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 358 358 + >; 359 359 + }; 361 360 362 361 363 363 - pinctrl_i2c2: i2c2grp { 364 364 - fsl,pins = < 365 365 - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 366 366 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 367 367 - >; 368 368 - }; 362 362 + pinctrl_i2c2: i2c2grp { 363 363 + fsl,pins = < 364 364 + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 365 365 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 366 366 + >; 367 367 + }; 369 368 370 370 - pinctrl_kpp: kppgrp { 371 371 - fsl,pins = < 372 372 - MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 373 373 - MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 374 374 - MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 375 375 - MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 376 376 - MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 377 377 - MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 378 378 - >; 379 379 - }; 369 369 + pinctrl_kpp: kppgrp { 370 370 + fsl,pins = < 371 371 + MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 372 372 + MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 373 373 + MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 374 374 + MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 375 375 + MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 376 376 + MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 377 377 + >; 378 378 + }; 380 379 381 381 - pinctrl_lcd: lcdgrp { 382 382 - fsl,pins = < 383 383 - MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 384 384 - MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 385 385 - MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 386 386 - MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 387 387 - MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 388 388 - MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 389 389 - MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 390 390 - MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 391 391 - MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 392 392 - MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 393 393 - MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 394 394 - MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 395 395 - MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 396 396 - MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 397 397 - MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 398 398 - MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 399 399 - MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 400 400 - MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 401 401 - MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 402 402 - MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 403 403 - MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 404 404 - MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 405 405 - MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 406 406 - MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 407 407 - MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 408 408 - MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 409 409 - MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 410 410 - MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 411 411 - >; 412 412 - }; 380 380 + pinctrl_lcd: lcdgrp { 381 381 + fsl,pins = < 382 382 + MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 383 383 + MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 384 384 + MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 385 385 + MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 386 386 + MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 387 387 + MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 388 388 + MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 389 389 + MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 390 390 + MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 391 391 + MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 392 392 + MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 393 393 + MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 394 394 + MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 395 395 + MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 396 396 + MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 397 397 + MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 398 398 + MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 399 399 + MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 400 400 + MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 401 401 + MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 402 402 + MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 403 403 + MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 404 404 + MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 405 405 + MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 406 406 + MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 407 407 + MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 408 408 + MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 409 409 + MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 410 410 + >; 411 411 + }; 413 412 414 414 - pinctrl_led: ledgrp { 415 415 - fsl,pins = < 416 416 - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 417 417 - >; 418 418 - }; 413 413 + pinctrl_led: ledgrp { 414 414 + fsl,pins = < 415 415 + MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 416 416 + >; 417 417 + }; 419 418 420 420 - pinctrl_pwm1: pwmgrp { 421 421 - fsl,pins = < 422 422 - MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 423 423 - >; 424 424 - }; 419 419 + pinctrl_pwm1: pwmgrp { 420 420 + fsl,pins = < 421 421 + MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 422 422 + >; 423 423 + }; 425 424 426 426 - pinctrl_reg_lcd_3v3: reglcd3v3grp { 427 427 - fsl,pins = < 428 428 - MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 429 429 - >; 430 430 - }; 425 425 + pinctrl_reg_lcd_3v3: reglcd3v3grp { 426 426 + fsl,pins = < 427 427 + MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 428 428 + >; 429 429 + }; 431 430 432 432 - pinctrl_uart1: uart1grp { 433 433 - fsl,pins = < 434 434 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 435 435 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 436 436 - >; 437 437 - }; 431 431 + pinctrl_uart1: uart1grp { 432 432 + fsl,pins = < 433 433 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 434 434 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 435 435 + >; 436 436 + }; 438 437 439 439 - pinctrl_usbotg1: usbotg1grp { 440 440 - fsl,pins = < 441 441 - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 442 442 - >; 443 443 - }; 438 438 + pinctrl_usbotg1: usbotg1grp { 439 439 + fsl,pins = < 440 440 + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 441 441 + >; 442 442 + }; 444 443 445 445 - pinctrl_usdhc1: usdhc1grp { 446 446 - fsl,pins = < 447 447 - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 448 448 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 449 449 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 450 450 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 451 451 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 452 452 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 453 453 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 454 454 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 455 455 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 456 456 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 457 457 - >; 458 458 - }; 444 444 + pinctrl_usdhc1: usdhc1grp { 445 445 + fsl,pins = < 446 446 + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 447 447 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 448 448 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 449 449 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 450 450 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 451 451 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 452 452 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 453 453 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 454 454 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 455 455 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 456 456 + >; 457 457 + }; 459 458 460 460 - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 461 461 - fsl,pins = < 462 462 - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 463 463 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 464 464 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 465 465 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 466 466 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 467 467 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 468 468 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 469 469 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 470 470 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 471 471 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 472 472 - >; 473 473 - }; 459 459 + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 460 460 + fsl,pins = < 461 461 + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 462 462 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 463 463 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 464 464 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 465 465 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 466 466 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 467 467 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 468 468 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 469 469 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 470 470 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 471 471 + >; 472 472 + }; 474 473 475 475 - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 476 476 - fsl,pins = < 477 477 - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 478 478 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 479 479 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 480 480 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 481 481 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 482 482 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 483 483 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 484 484 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 485 485 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 486 486 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 487 487 - >; 488 488 - }; 474 474 + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 475 475 + fsl,pins = < 476 476 + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 477 477 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 478 478 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 479 479 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 480 480 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 481 481 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 482 482 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 483 483 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 484 484 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 485 485 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 486 486 + >; 487 487 + }; 489 488 490 490 - pinctrl_usdhc2: usdhc2grp { 491 491 - fsl,pins = < 492 492 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 493 493 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 494 494 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 495 495 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 496 496 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 497 497 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 498 498 - >; 499 499 - }; 489 489 + pinctrl_usdhc2: usdhc2grp { 490 490 + fsl,pins = < 491 491 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 492 492 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 493 493 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 494 494 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 495 495 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 496 496 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 497 497 + >; 498 498 + }; 500 499 501 501 - pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 502 502 - fsl,pins = < 503 503 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 504 504 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 505 505 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 506 506 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 507 507 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 508 508 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 509 509 - >; 510 510 - }; 500 500 + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 501 501 + fsl,pins = < 502 502 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 503 503 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 504 504 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 505 505 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 506 506 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 507 507 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 508 508 + >; 509 509 + }; 511 510 512 512 - pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 513 513 - fsl,pins = < 514 514 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 515 515 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 516 516 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 517 517 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 518 518 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 519 519 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 520 520 - >; 521 521 - }; 511 511 + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 512 512 + fsl,pins = < 513 513 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 514 514 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 515 515 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 516 516 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 517 517 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 518 518 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 519 519 + >; 520 520 + }; 522 521 523 523 - pinctrl_usdhc3: usdhc3grp { 524 524 - fsl,pins = < 525 525 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 526 526 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 527 527 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 528 528 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 529 529 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 530 530 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 531 531 - >; 532 532 - }; 522 522 + pinctrl_usdhc3: usdhc3grp { 523 523 + fsl,pins = < 524 524 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 525 525 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 526 526 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 527 527 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 528 528 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 529 529 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 530 530 + >; 531 531 + }; 533 532 534 534 - pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 535 535 - fsl,pins = < 536 536 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 537 537 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 538 538 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 539 539 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 540 540 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 541 541 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 542 542 - >; 543 543 - }; 533 533 + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 534 534 + fsl,pins = < 535 535 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 536 536 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 537 537 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 538 538 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 539 539 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 540 540 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 541 541 + >; 542 542 + }; 544 543 545 545 - pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 546 546 - fsl,pins = < 547 547 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 548 548 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 549 549 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 550 550 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 551 551 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 552 552 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 553 553 - >; 554 554 - }; 544 544 + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 545 545 + fsl,pins = < 546 546 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 547 547 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 548 548 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 549 549 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 550 550 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 551 551 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 552 552 + >; 555 553 }; 556 554 }; 557 555

+8 -8

arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts

reviewed

··· 382 382 >; 383 383 }; 384 384 385 385 - pinctrl_i2c1_sleep: i2c1grp-sleep { 385 385 + pinctrl_i2c1_sleep: i2c1sleep-grp { 386 386 fsl,pins = < 387 387 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 388 388 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 ··· 396 396 >; 397 397 }; 398 398 399 399 - pinctrl_i2c2_sleep: i2c2grp-sleep { 399 399 + pinctrl_i2c2_sleep: i2c2sleep-grp { 400 400 fsl,pins = < 401 401 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 402 402 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 ··· 456 456 >; 457 457 }; 458 458 459 459 - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 459 459 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 460 460 fsl,pins = < 461 461 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 462 462 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 ··· 467 467 >; 468 468 }; 469 469 470 470 - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 470 470 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 471 471 fsl,pins = < 472 472 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 473 473 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 ··· 478 478 >; 479 479 }; 480 480 481 481 - pinctrl_usdhc2_sleep: usdhc2grp-sleep { 481 481 + pinctrl_usdhc2_sleep: usdhc2sleep-grp { 482 482 fsl,pins = < 483 483 MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 484 484 MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 ··· 500 500 >; 501 501 }; 502 502 503 503 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 503 503 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 504 504 fsl,pins = < 505 505 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 506 506 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 ··· 511 511 >; 512 512 }; 513 513 514 514 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 514 514 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 515 515 fsl,pins = < 516 516 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 517 517 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 ··· 522 522 >; 523 523 }; 524 524 525 525 - pinctrl_usdhc3_sleep: usdhc3grp-sleep { 525 525 + pinctrl_usdhc3_sleep: usdhc3sleep-grp { 526 526 fsl,pins = < 527 527 MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 528 528 MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1

+8 -8

arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts

reviewed

··· 111 111 >; 112 112 }; 113 113 114 114 - pinctrl_i2c1_sleep: i2c1grp-sleep { 114 114 + pinctrl_i2c1_sleep: i2c1sleep-grp { 115 115 fsl,pins = < 116 116 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 117 117 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 ··· 125 125 >; 126 126 }; 127 127 128 128 - pinctrl_i2c2_sleep: i2c2grp-sleep { 128 128 + pinctrl_i2c2_sleep: i2c2sleep-grp { 129 129 fsl,pins = < 130 130 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 131 131 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 ··· 190 190 >; 191 191 }; 192 192 193 193 - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 193 193 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 194 194 fsl,pins = < 195 195 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 196 196 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 ··· 201 201 >; 202 202 }; 203 203 204 204 - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 204 204 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 205 205 fsl,pins = < 206 206 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 207 207 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 ··· 212 212 >; 213 213 }; 214 214 215 215 - pinctrl_usdhc2_sleep: usdhc2grp-sleep { 215 215 + pinctrl_usdhc2_sleep: usdhc2sleep-grp { 216 216 fsl,pins = < 217 217 MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 218 218 MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 ··· 234 234 >; 235 235 }; 236 236 237 237 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 237 237 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 238 238 fsl,pins = < 239 239 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 240 240 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 ··· 245 245 >; 246 246 }; 247 247 248 248 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 248 248 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 249 249 fsl,pins = < 250 250 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 251 251 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 ··· 256 256 >; 257 257 }; 258 258 259 259 - pinctrl_usdhc3_sleep: usdhc3grp-sleep { 259 259 + pinctrl_usdhc3_sleep: usdhc3sleep-grp { 260 260 fsl,pins = < 261 261 MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 262 262 MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1

+2 -2

arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts

reviewed

··· 111 111 >; 112 112 }; 113 113 114 114 - pinctrl_i2c1_sleep: i2c1grp-sleep { 114 114 + pinctrl_i2c1_sleep: i2c1sleep-grp { 115 115 fsl,pins = < 116 116 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 117 117 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 ··· 125 125 >; 126 126 }; 127 127 128 128 - pinctrl_i2c2_sleep: i2c2grp-sleep { 128 128 + pinctrl_i2c2_sleep: i2c2sleep-grp { 129 129 fsl,pins = < 130 130 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 131 131 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1

+94 -96

arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts

reviewed

··· 125 125 }; 126 126 127 127 &iomuxc { 128 128 - imx6sl-warp { 129 129 - pinctrl_uart1: uart1grp { 130 130 - fsl,pins = < 131 131 - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 132 132 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 133 133 - >; 134 134 - }; 128 128 + pinctrl_uart1: uart1grp { 129 129 + fsl,pins = < 130 130 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 131 131 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 132 132 + >; 133 133 + }; 135 134 136 135 137 137 - pinctrl_uart3: uart3grp { 138 138 - fsl,pins = < 139 139 - MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 140 140 - MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 141 141 - >; 142 142 - }; 136 136 + pinctrl_uart3: uart3grp { 137 137 + fsl,pins = < 138 138 + MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 139 139 + MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 140 140 + >; 141 141 + }; 143 142 144 144 - pinctrl_uart5: uart5grp { 145 145 - fsl,pins = < 146 146 - MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 147 147 - MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 148 148 - MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 149 149 - MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 150 150 - >; 151 151 - }; 143 143 + pinctrl_uart5: uart5grp { 144 144 + fsl,pins = < 145 145 + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 146 146 + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 147 147 + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 148 148 + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 149 149 + >; 150 150 + }; 152 151 153 153 - pinctrl_usdhc2: usdhc2grp { 154 154 - fsl,pins = < 155 155 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 156 156 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 157 157 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 158 158 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 159 159 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 160 160 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 161 161 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 162 162 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 163 163 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 164 164 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 165 165 - MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 166 166 - >; 167 167 - }; 152 152 + pinctrl_usdhc2: usdhc2grp { 153 153 + fsl,pins = < 154 154 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 155 155 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 156 156 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 157 157 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 158 158 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 159 159 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 160 160 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 161 161 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 162 162 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 163 163 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 164 164 + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 165 165 + >; 166 166 + }; 168 167 169 169 - pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 170 170 - fsl,pins = < 171 171 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 172 172 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 173 173 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 174 174 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 175 175 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 176 176 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 177 177 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 178 178 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 179 179 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 180 180 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 181 181 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 182 182 - >; 183 183 - }; 168 168 + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 169 169 + fsl,pins = < 170 170 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 171 171 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 172 172 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 173 173 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 174 174 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 175 175 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 176 176 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 177 177 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 178 178 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 179 179 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 180 180 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 181 181 + >; 182 182 + }; 184 183 185 185 - pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 186 186 - fsl,pins = < 187 187 - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 188 188 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 189 189 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 190 190 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 191 191 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 192 192 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 193 193 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 194 194 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 195 195 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 196 196 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 197 197 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 198 198 - >; 199 199 - }; 184 184 + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 185 185 + fsl,pins = < 186 186 + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 187 187 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 188 188 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 189 189 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 190 190 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 191 191 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 192 192 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 193 193 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 194 194 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 195 195 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 196 196 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 197 197 + >; 198 198 + }; 200 199 201 201 - pinctrl_usdhc3: usdhc3grp { 202 202 - fsl,pins = < 203 203 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 204 204 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 205 205 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 206 206 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 207 207 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 208 208 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 209 209 - >; 210 210 - }; 200 200 + pinctrl_usdhc3: usdhc3grp { 201 201 + fsl,pins = < 202 202 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 203 203 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 204 204 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 205 205 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 206 206 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 207 207 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 208 208 + >; 209 209 + }; 211 210 212 212 - pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 213 213 - fsl,pins = < 214 214 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 215 215 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 216 216 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 217 217 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 218 218 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 219 219 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 220 220 - >; 221 221 - }; 211 211 + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 212 212 + fsl,pins = < 213 213 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 214 214 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 215 215 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 216 216 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 217 217 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 218 218 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 219 219 + >; 220 220 + }; 222 221 223 223 - pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 224 224 - fsl,pins = < 225 225 - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 226 226 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 227 227 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 228 228 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 229 229 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 230 230 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 231 231 - >; 232 232 - }; 222 222 + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 223 223 + fsl,pins = < 224 224 + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 225 225 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 226 226 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 227 227 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 228 228 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 229 229 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 230 230 + >; 233 231 }; 234 232 };

+6 -5

arch/arm/boot/dts/nxp/imx/imx6sl.dtsi

reviewed

··· 378 378 }; 379 379 380 380 gpt: timer@2098000 { 381 381 - compatible = "fsl,imx6sl-gpt"; 381 381 + compatible = "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; 382 382 reg = <0x02098000 0x4000>; 383 383 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 384 384 clocks = <&clks IMX6SL_CLK_GPT>, ··· 631 631 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 632 632 nvmem-cell-names = "calib", "temp_grade"; 633 633 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; 634 634 + #thermal-sensor-cells = <0>; 634 635 }; 635 636 }; 636 637 ··· 860 859 }; 861 860 862 861 usdhc1: mmc@2190000 { 863 863 - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 862 862 + compatible = "fsl,imx6sl-usdhc"; 864 863 reg = <0x02190000 0x4000>; 865 864 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 866 865 clocks = <&clks IMX6SL_CLK_USDHC1>, ··· 872 871 }; 873 872 874 873 usdhc2: mmc@2194000 { 875 875 - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 874 874 + compatible = "fsl,imx6sl-usdhc"; 876 875 reg = <0x02194000 0x4000>; 877 876 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 878 877 clocks = <&clks IMX6SL_CLK_USDHC2>, ··· 884 883 }; 885 884 886 885 usdhc3: mmc@2198000 { 887 887 - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 886 886 + compatible = "fsl,imx6sl-usdhc"; 888 887 reg = <0x02198000 0x4000>; 889 888 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 890 889 clocks = <&clks IMX6SL_CLK_USDHC3>, ··· 896 895 }; 897 896 898 897 usdhc4: mmc@219c000 { 899 899 - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 898 898 + compatible = "fsl,imx6sl-usdhc"; 900 899 reg = <0x0219c000 0x4000>; 901 900 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 902 901 clocks = <&clks IMX6SL_CLK_USDHC4>,

+6 -6

arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts

reviewed

··· 461 461 >; 462 462 }; 463 463 464 464 - pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { 464 464 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 465 465 fsl,pins = < 466 466 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 467 467 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 ··· 472 472 >; 473 473 }; 474 474 475 475 - pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { 475 475 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 476 476 fsl,pins = < 477 477 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 478 478 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 ··· 499 499 >; 500 500 }; 501 501 502 502 - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 502 502 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 503 503 fsl,pins = < 504 504 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 505 505 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 ··· 515 515 >; 516 516 }; 517 517 518 518 - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 518 518 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 519 519 fsl,pins = < 520 520 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 521 521 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 ··· 549 549 >; 550 550 }; 551 551 552 552 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 552 552 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 553 553 fsl,pins = < 554 554 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 555 555 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 ··· 561 561 >; 562 562 }; 563 563 564 564 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 564 564 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 565 565 fsl,pins = < 566 566 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 567 567 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9

+23

arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-a.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0) 2 2 + /* 3 3 + * Device tree for the Kobo Clara 2E rev A ebook reader 4 4 + * 5 5 + * Name on mainboard is: 37NB-E60K2M+4A2 6 6 + * Serials start with: E60K2M (a number also seen in 7 7 + * vendor kernel sources) 8 8 + * 9 9 + * Copyright 2024 Andreas Kemnade 10 10 + */ 11 11 + 12 12 + /dts-v1/; 13 13 + 14 14 + #include "imx6sll-kobo-clara2e-common.dtsi" 15 15 + 16 16 + / { 17 17 + model = "Kobo Clara 2E"; 18 18 + compatible = "kobo,clara2e-b", "kobo,clara2e", "fsl,imx6sll"; 19 19 + }; 20 20 + 21 21 + &i2c2 { 22 22 + /* EPD PMIC SY7636 at 0x62 */ 23 23 + };

+23

arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0) 2 2 + /* 3 3 + * Device tree for the Kobo Clara 2E rev B ebook reader 4 4 + * 5 5 + * Name on mainboard is: 37NB-E60K2M+4B0 6 6 + * Serials start with: E60K2M (a number also seen in 7 7 + * vendor kernel sources) 8 8 + * 9 9 + * Copyright 2024 Andreas Kemnade 10 10 + */ 11 11 + 12 12 + /dts-v1/; 13 13 + 14 14 + #include "imx6sll-kobo-clara2e-common.dtsi" 15 15 + 16 16 + / { 17 17 + model = "Kobo Clara 2E"; 18 18 + compatible = "kobo,clara2e-b", "kobo,clara2e", "fsl,imx6sll"; 19 19 + }; 20 20 + 21 21 + &i2c2 { 22 22 + /* EPD PMIC JD9930 at 0x18 */ 23 23 + };

+511

arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-common.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0) 2 2 + /* 3 3 + * Common part for Kobo Clara 2e device tree 4 4 + * Copyright 2024 Andreas Kemnade 5 5 + */ 6 6 + 7 7 + /dts-v1/; 8 8 + 9 9 + #include <dt-bindings/input/input.h> 10 10 + #include <dt-bindings/gpio/gpio.h> 11 11 + #include <dt-bindings/leds/common.h> 12 12 + #include "imx6sll.dtsi" 13 13 + 14 14 + / { 15 15 + aliases { 16 16 + mmc0 = &usdhc2; 17 17 + mmc1 = &usdhc3; 18 18 + }; 19 19 + 20 20 + chosen { 21 21 + stdout-path = &uart1; 22 22 + }; 23 23 + 24 24 + gpio-keys { 25 25 + compatible = "gpio-keys"; 26 26 + pinctrl-names = "default"; 27 27 + pinctrl-0 = <&pinctrl_gpio_keys>; 28 28 + 29 29 + key-cover { 30 30 + label = "Cover"; 31 31 + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; 32 32 + linux,code = <SW_LID>; 33 33 + linux,input-type = <EV_SW>; 34 34 + wakeup-source; 35 35 + }; 36 36 + }; 37 37 + 38 38 + leds { 39 39 + compatible = "gpio-leds"; 40 40 + pinctrl-names = "default"; 41 41 + pinctrl-0 = <&pinctrl_led>; 42 42 + 43 43 + led { 44 44 + color = <LED_COLOR_ID_WHITE>; 45 45 + function = LED_FUNCTION_POWER; 46 46 + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 47 47 + linux,default-trigger = "timer"; 48 48 + }; 49 49 + }; 50 50 + 51 51 + memory@80000000 { 52 52 + device_type = "memory"; 53 53 + reg = <0x80000000 0x20000000>; 54 54 + }; 55 55 + 56 56 + reg_wifi: regulator-wifi { 57 57 + compatible = "regulator-fixed"; 58 58 + regulator-name = "SD3_SPWR"; 59 59 + regulator-min-microvolt = <3000000>; 60 60 + regulator-max-microvolt = <3000000>; 61 61 + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 62 62 + enable-active-high; 63 63 + }; 64 64 + }; 65 65 + 66 66 + &clks { 67 67 + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; 68 68 + assigned-clock-rates = <393216000>; 69 69 + }; 70 70 + 71 71 + &cpu0 { 72 72 + arm-supply = <&buck1>; 73 73 + soc-supply = <&buck2>; 74 74 + }; 75 75 + 76 76 + &i2c1 { 77 77 + pinctrl-names = "default","sleep"; 78 78 + pinctrl-0 = <&pinctrl_i2c1>; 79 79 + pinctrl-1 = <&pinctrl_i2c1_sleep>; 80 80 + clock-frequency = <100000>; 81 81 + status = "okay"; 82 82 + 83 83 + /* backlight aw99703 at 0x36 */ 84 84 + }; 85 85 + 86 86 + &i2c2 { 87 87 + pinctrl-names = "default","sleep"; 88 88 + pinctrl-0 = <&pinctrl_i2c2>; 89 89 + pinctrl-1 = <&pinctrl_i2c2_sleep>; 90 90 + clock-frequency = <100000>; 91 91 + status = "okay"; 92 92 + 93 93 + /* backlight aw99703 at 0x36 */ 94 94 + 95 95 + touchscreen@38 { 96 96 + compatible = "focaltech,ft5426"; 97 97 + reg = <0x38>; 98 98 + pinctrl-names = "default", "suspend"; 99 99 + pinctrl-0 = <&pinctrl_touch_gpio>; 100 100 + pinctrl-1 = <&pinctrl_touch_gpio_sleep>; 101 101 + interrupt-parent = <&gpio4>; 102 102 + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; 103 103 + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 104 104 + touchscreen-size-x = <1072>; 105 105 + touchscreen-size-y = <1448>; 106 106 + touchscreen-swapped-x-y; 107 107 + }; 108 108 + }; 109 109 + 110 110 + &i2c3 { 111 111 + /* Bus seems to be in bad state after boot, allow full recovery */ 112 112 + pinctrl-names = "default", "gpio"; 113 113 + pinctrl-0 = <&pinctrl_i2c3>; 114 114 + pinctrl-1 = <&pinctrl_i2c3_gpio>; 115 115 + sda-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 116 116 + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 117 117 + clock-frequency = <100000>; 118 118 + status = "okay"; 119 119 + 120 120 + pmic@4b { 121 121 + compatible = "rohm,bd71879", "rohm,bd71828"; 122 122 + reg = <0x4b>; 123 123 + pinctrl-names = "default"; 124 124 + pinctrl-0 = <&pinctrl_bd71828>; 125 125 + interrupt-parent = <&gpio4>; 126 126 + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 127 127 + system-power-controller; 128 128 + clocks = <&clks 0>; 129 129 + #clock-cells = <0>; 130 130 + clock-output-names = "bd71828-32k-out"; 131 131 + gpio-controller; 132 132 + #gpio-cells = <2>; 133 133 + gpio-reserved-ranges = <0 1>, <2 1>; 134 134 + 135 135 + /* charge sense resistor is 30 milli-ohm */ 136 136 + 137 137 + regulators { 138 138 + LDO1 { 139 139 + name = "LDO1"; 140 140 + regulator-name = "ldo1"; 141 141 + regulator-min-microvolt = <800000>; 142 142 + regulator-max-microvolt = <3300000>; 143 143 + }; 144 144 + 145 145 + LDO2 { 146 146 + name = "LDO2"; 147 147 + regulator-name = "ldo2"; 148 148 + regulator-min-microvolt = <800000>; 149 149 + regulator-max-microvolt = <3300000>; 150 150 + }; 151 151 + 152 152 + LDO3 { 153 153 + name = "LDO3"; 154 154 + regulator-name = "ldo3"; 155 155 + regulator-min-microvolt = <800000>; 156 156 + regulator-max-microvolt = <3300000>; 157 157 + }; 158 158 + 159 159 + ldo4: LDO4 { 160 160 + name = "LDO4"; 161 161 + regulator-name = "ldo4"; 162 162 + regulator-always-on; 163 163 + regulator-min-microvolt = <1100000>; 164 164 + regulator-max-microvolt = <1100000>; 165 165 + }; 166 166 + 167 167 + LDO5 { 168 168 + name = "LDO5"; 169 169 + regulator-name = "ldo5"; 170 170 + regulator-always-on; 171 171 + regulator-min-microvolt = <800000>; 172 172 + regulator-max-microvolt = <3300000>; 173 173 + }; 174 174 + 175 175 + LDO6 { 176 176 + name = "LDO6"; 177 177 + regulator-name = "ldo6"; 178 178 + regulator-min-microvolt = <1800000>; 179 179 + regulator-max-microvolt = <1800000>; 180 180 + }; 181 181 + 182 182 + LDO7 { 183 183 + name = "LDO7"; 184 184 + regulator-name = "ldo7"; 185 185 + regulator-always-on; 186 186 + regulator-min-microvolt = <800000>; 187 187 + regulator-max-microvolt = <3300000>; 188 188 + regulator-boot-on; 189 189 + }; 190 190 + 191 191 + buck1: BUCK1 { 192 192 + name = "BUCK1"; 193 193 + regulator-name = "buck1"; 194 194 + regulator-always-on; 195 195 + regulator-min-microvolt = <500000>; 196 196 + regulator-max-microvolt = <1400000>; 197 197 + regulator-boot-on; 198 198 + }; 199 199 + 200 200 + buck2: BUCK2 { 201 201 + name = "BUCK2"; 202 202 + regulator-name = "buck2"; 203 203 + regulator-always-on; 204 204 + regulator-min-microvolt = <500000>; 205 205 + regulator-max-microvolt = <2000000>; 206 206 + regulator-boot-on; 207 207 + }; 208 208 + 209 209 + BUCK3 { 210 210 + name = "BUCK3"; 211 211 + regulator-name = "buck3"; 212 212 + regulator-always-on; 213 213 + regulator-min-microvolt = <1200000>; 214 214 + regulator-max-microvolt = <1800000>; 215 215 + regulator-boot-on; 216 216 + }; 217 217 + 218 218 + BUCK4 { 219 219 + name = "BUCK4"; 220 220 + regulator-name = "buck4"; 221 221 + regulator-always-on; 222 222 + regulator-min-microvolt = <1000000>; 223 223 + regulator-max-microvolt = <1200000>; 224 224 + regulator-boot-on; 225 225 + }; 226 226 + 227 227 + BUCK5 { 228 228 + name = "BUCK5"; 229 229 + regulator-name = "buck5"; 230 230 + regulator-always-on; 231 231 + regulator-min-microvolt = <2500000>; 232 232 + regulator-max-microvolt = <3300000>; 233 233 + regulator-boot-on; 234 234 + }; 235 235 + 236 236 + BUCK6 { 237 237 + name = "BUCK6"; 238 238 + regulator-name = "buck6"; 239 239 + regulator-min-microvolt = <500000>; 240 240 + regulator-max-microvolt = <2000000>; 241 241 + }; 242 242 + 243 243 + BUCK7 { 244 244 + name = "BUCK7"; 245 245 + regulator-name = "buck7"; 246 246 + regulator-min-microvolt = <500000>; 247 247 + regulator-max-microvolt = <2000000>; 248 248 + }; 249 249 + }; 250 250 + }; 251 251 + }; 252 252 + 253 253 + &iomuxc { 254 254 + pinctrl_bd71828: bd71828-gpiogrp { 255 255 + fsl,pins = < 256 256 + MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x1b8b1 257 257 + MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 258 258 + >; 259 259 + }; 260 260 + 261 261 + pinctrl_gpio_keys: gpio-keysgrp { 262 262 + fsl,pins = < 263 263 + MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ 264 264 + MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */ 265 265 + >; 266 266 + }; 267 267 + 268 268 + pinctrl_i2c1: i2c1grp { 269 269 + fsl,pins = < 270 270 + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 271 271 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 272 272 + >; 273 273 + }; 274 274 + 275 275 + pinctrl_i2c1_sleep: i2c1-sleepgrp { 276 276 + fsl,pins = < 277 277 + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 278 278 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 279 279 + >; 280 280 + }; 281 281 + 282 282 + pinctrl_i2c2: i2c2grp { 283 283 + fsl,pins = < 284 284 + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 285 285 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 286 286 + >; 287 287 + }; 288 288 + 289 289 + pinctrl_i2c2_sleep: i2c2-sleepgrp { 290 290 + fsl,pins = < 291 291 + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 292 292 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 293 293 + >; 294 294 + }; 295 295 + 296 296 + pinctrl_i2c3: i2c3grp { 297 297 + fsl,pins = < 298 298 + MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 299 299 + MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 300 300 + >; 301 301 + }; 302 302 + 303 303 + pinctrl_i2c3_gpio: i2c3-gpiogrp { 304 304 + fsl,pins = < 305 305 + MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x4001f8b1 306 306 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x4001f8b1 307 307 + >; 308 308 + }; 309 309 + 310 310 + pinctrl_led: ledgrp { 311 311 + fsl,pins = < 312 312 + MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059 313 313 + >; 314 314 + }; 315 315 + 316 316 + pinctrl_touch_gpio: touch-gpiogrp { 317 317 + fsl,pins = < 318 318 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* TP_INT */ 319 319 + MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ 320 320 + >; 321 321 + }; 322 322 + 323 323 + pinctrl_touch_gpio_sleep: touch-gpio-sleepgrp { 324 324 + fsl,pins = < 325 325 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x10059 /* TP_INT */ 326 326 + MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ 327 327 + >; 328 328 + }; 329 329 + 330 330 + pinctrl_uart1: uart1grp { 331 331 + fsl,pins = < 332 332 + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 333 333 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 334 334 + >; 335 335 + }; 336 336 + 337 337 + pinctrl_uart2: uart2grp { 338 338 + fsl,pins = < 339 339 + MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x41b0b1 340 340 + MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x41b0b1 341 341 + MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x41b0b1 342 342 + MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x41b0b1 343 343 + >; 344 344 + }; 345 345 + 346 346 + pinctrl_uart2_sleep: uart2-sleepgrp { 347 347 + fsl,pins = < 348 348 + MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x10059 349 349 + MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x10059 350 350 + MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x10059 351 351 + MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x10059 352 352 + >; 353 353 + }; 354 354 + 355 355 + pinctrl_usbotg1: usbotg1grp { 356 356 + fsl,pins = < 357 357 + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 358 358 + >; 359 359 + }; 360 360 + 361 361 + pinctrl_usdhc2: usdhc2grp { 362 362 + fsl,pins = < 363 363 + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 364 364 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 365 365 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 366 366 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 367 367 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 368 368 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 369 369 + >; 370 370 + }; 371 371 + 372 372 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 373 373 + fsl,pins = < 374 374 + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 375 375 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 376 376 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 377 377 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 378 378 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 379 379 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 380 380 + >; 381 381 + }; 382 382 + 383 383 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 384 384 + fsl,pins = < 385 385 + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 386 386 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 387 387 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 388 388 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 389 389 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 390 390 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 391 391 + >; 392 392 + }; 393 393 + 394 394 + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { 395 395 + fsl,pins = < 396 396 + MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 397 397 + MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 398 398 + MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 399 399 + MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 400 400 + MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 401 401 + MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 402 402 + >; 403 403 + }; 404 404 + 405 405 + pinctrl_usdhc3: usdhc3grp { 406 406 + fsl,pins = < 407 407 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 408 408 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 409 409 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 410 410 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 411 411 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 412 412 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 413 413 + >; 414 414 + }; 415 415 + 416 416 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 417 417 + fsl,pins = < 418 418 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 419 419 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 420 420 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 421 421 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 422 422 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 423 423 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 424 424 + >; 425 425 + }; 426 426 + 427 427 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 428 428 + fsl,pins = < 429 429 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 430 430 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 431 431 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 432 432 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 433 433 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 434 434 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 435 435 + >; 436 436 + }; 437 437 + 438 438 + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { 439 439 + fsl,pins = < 440 440 + MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 441 441 + MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 442 442 + MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 443 443 + MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 444 444 + MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 445 445 + MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 446 446 + >; 447 447 + }; 448 448 + 449 449 + pinctrl_wifi_power: wifi-powergrp { 450 450 + fsl,pins = < 451 451 + MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 452 452 + >; 453 453 + }; 454 454 + }; 455 455 + 456 456 + &snvs_rtc { 457 457 + /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ 458 458 + status = "disabled"; 459 459 + }; 460 460 + 461 461 + &uart1 { 462 462 + pinctrl-names = "default"; 463 463 + pinctrl-0 = <&pinctrl_uart1>; 464 464 + status = "okay"; 465 465 + }; 466 466 + 467 467 + &uart2 { 468 468 + pinctrl-names = "default", "sleep"; 469 469 + pinctrl-0 = <&pinctrl_uart2>; 470 470 + pinctrl-1 = <&pinctrl_uart2_sleep>; 471 471 + status = "okay"; 472 472 + 473 473 + /* requires LDO4 + power enable gpio */ 474 474 + bluetooth { 475 475 + compatible = "nxp,88w8987-bt"; 476 476 + fw-init-baudrate = <1500000>; 477 477 + }; 478 478 + }; 479 479 + 480 480 + &usbotg1 { 481 481 + pinctrl-names = "default"; 482 482 + pinctrl-0 = <&pinctrl_usbotg1>; 483 483 + disable-over-current; 484 484 + srp-disable; 485 485 + hnp-disable; 486 486 + adp-disable; 487 487 + status = "okay"; 488 488 + }; 489 489 + 490 490 + &usdhc2 { 491 491 + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 492 492 + pinctrl-0 = <&pinctrl_usdhc2>; 493 493 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 494 494 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 495 495 + pinctrl-3 = <&pinctrl_usdhc2_sleep>; 496 496 + non-removable; 497 497 + status = "okay"; 498 498 + }; 499 499 + 500 500 + &usdhc3 { 501 501 + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 502 502 + pinctrl-0 = <&pinctrl_usdhc3>; 503 503 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 504 504 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 505 505 + pinctrl-3 = <&pinctrl_usdhc3_sleep>; 506 506 + /* card requires also ldo4 */ 507 507 + vmmc-supply = <&reg_wifi>; 508 508 + cap-power-off-card; 509 509 + non-removable; 510 510 + status = "okay"; 511 511 + };

+8 -8

arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts

reviewed

··· 121 121 >; 122 122 }; 123 123 124 124 - pinctrl_i2c1_sleep: i2c1grp-sleep { 124 124 + pinctrl_i2c1_sleep: i2c1sleep-grp { 125 125 fsl,pins = < 126 126 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 127 127 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 ··· 135 135 >; 136 136 }; 137 137 138 138 - pinctrl_i2c2_sleep: i2c2grp-sleep { 138 138 + pinctrl_i2c2_sleep: i2c2sleep-grp { 139 139 fsl,pins = < 140 140 MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 141 141 MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 ··· 200 200 >; 201 201 }; 202 202 203 203 - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 203 203 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 204 204 fsl,pins = < 205 205 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 206 206 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 ··· 211 211 >; 212 212 }; 213 213 214 214 - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 214 214 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 215 215 fsl,pins = < 216 216 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 217 217 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 ··· 222 222 >; 223 223 }; 224 224 225 225 - pinctrl_usdhc2_sleep: usdhc2grp-sleep { 225 225 + pinctrl_usdhc2_sleep: usdhc2sleep-grp { 226 226 fsl,pins = < 227 227 MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 228 228 MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 ··· 244 244 >; 245 245 }; 246 246 247 247 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 247 247 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 248 248 fsl,pins = < 249 249 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 250 250 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 ··· 255 255 >; 256 256 }; 257 257 258 258 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 258 258 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 259 259 fsl,pins = < 260 260 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 261 261 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 ··· 266 266 >; 267 267 }; 268 268 269 269 - pinctrl_usdhc3_sleep: usdhc3grp-sleep { 269 269 + pinctrl_usdhc3_sleep: usdhc3sleep-grp { 270 270 fsl,pins = < 271 271 MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 272 272 MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1

+2 -2

arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts

reviewed

··· 121 121 >; 122 122 }; 123 123 124 124 - pinctrl_i2c1_sleep: i2c1grp-sleep { 124 124 + pinctrl_i2c1_sleep: i2c1sleep-grp { 125 125 fsl,pins = < 126 126 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 127 127 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 ··· 135 135 >; 136 136 }; 137 137 138 138 - pinctrl_i2c2_sleep: i2c2grp-sleep { 138 138 + pinctrl_i2c2_sleep: i2c2sleep-grp { 139 139 fsl,pins = < 140 140 MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 141 141 MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1

+17 -7

arch/arm/boot/dts/nxp/imx/imx6sll.dtsi

reviewed

··· 173 173 "rxtx1", "rxtx2", 174 174 "rxtx3", "rxtx4", 175 175 "rxtx5", "rxtx6", 176 176 - "rxtx7", "dma"; 176 176 + "rxtx7", "spba"; 177 177 status = "disabled"; 178 178 }; 179 179 ··· 358 358 }; 359 359 360 360 gpt1: timer@2098000 { 361 361 - compatible = "fsl,imx6sl-gpt"; 361 361 + compatible = "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; 362 362 reg = <0x02098000 0x4000>; 363 363 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 364 364 clocks = <&clks IMX6SLL_CLK_GPT_BUS>, ··· 507 507 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 508 508 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 509 509 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 510 510 - #address-cells = <1>; 511 511 - #size-cells = <0>; 512 510 513 513 - reg_3p0: regulator-3p0@20c8120 { 511 511 + reg_3p0: regulator-3p0 { 514 512 compatible = "fsl,anatop-regulator"; 515 515 - reg = <0x20c8120>; 516 513 regulator-name = "vdd3p0"; 517 514 regulator-min-microvolt = <2625000>; 518 515 regulator-max-microvolt = <3400000>; ··· 522 525 anatop-enable-bit = <0>; 523 526 }; 524 527 525 525 - tempmon: temperature-sensor { 528 528 + tempmon: tempmon { 526 529 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; 527 530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 528 531 interrupt-parent = <&gpc>; ··· 530 533 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 531 534 nvmem-cell-names = "calib", "temp_grade"; 532 535 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; 536 536 + #thermal-sensor-cells = <0>; 533 537 }; 534 538 }; 535 539 ··· 599 601 #interrupt-cells = <3>; 600 602 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 601 603 interrupt-parent = <&intc>; 604 604 + clocks = <&clks IMX6SLL_CLK_IPG>; 605 605 + clock-names = "ipg"; 606 606 + 607 607 + pgc { 608 608 + #address-cells = <1>; 609 609 + #size-cells = <0>; 610 610 + 611 611 + power-domain@0 { 612 612 + reg = <0>; 613 613 + #power-domain-cells = <0>; 614 614 + }; 615 615 + }; 602 616 }; 603 617 604 618 iomuxc: pinctrl@20e0000 {

+2 -2

arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts

reviewed

··· 333 333 >; 334 334 }; 335 335 336 336 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 336 336 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 337 337 fsl,pins = < 338 338 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 339 339 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 ··· 348 348 >; 349 349 }; 350 350 351 351 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 351 351 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 352 352 fsl,pins = < 353 353 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 354 354 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9

+285 -287

arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi

reviewed

··· 399 399 }; 400 400 401 401 &iomuxc { 402 402 - imx6x-sdb { 403 403 - pinctrl_audmux: audmuxgrp { 404 404 - fsl,pins = < 405 405 - MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 406 406 - MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 407 407 - MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 408 408 - MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 409 409 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 410 410 - >; 411 411 - }; 402 402 + pinctrl_audmux: audmuxgrp { 403 403 + fsl,pins = < 404 404 + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 405 405 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 406 406 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 407 407 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 408 408 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 409 409 + >; 410 410 + }; 412 411 413 413 - pinctrl_enet1: enet1grp { 414 414 - fsl,pins = < 415 415 - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 416 416 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 417 417 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 418 418 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 419 419 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 420 420 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 421 421 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 422 422 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 423 423 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 424 424 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 425 425 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 426 426 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 427 427 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 428 428 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 429 429 - MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 430 430 - /* phy reset */ 431 431 - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 432 432 - >; 433 433 - }; 412 412 + pinctrl_enet1: enet1grp { 413 413 + fsl,pins = < 414 414 + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 415 415 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 416 416 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 417 417 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 418 418 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 419 419 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 420 420 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 421 421 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 422 422 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 423 423 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 424 424 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 425 425 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 426 426 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 427 427 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 428 428 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 429 429 + /* phy reset */ 430 430 + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 431 431 + >; 432 432 + }; 434 433 435 435 - pinctrl_enet_3v3: enet3v3grp { 436 436 - fsl,pins = < 437 437 - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 438 438 - >; 439 439 - }; 434 434 + pinctrl_enet_3v3: enet3v3grp { 435 435 + fsl,pins = < 436 436 + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 437 437 + >; 438 438 + }; 440 439 441 441 - pinctrl_enet2: enet2grp { 442 442 - fsl,pins = < 443 443 - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 444 444 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 445 445 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 446 446 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 447 447 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 448 448 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 449 449 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 450 450 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 451 451 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 452 452 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 453 453 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 454 454 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 455 455 - >; 456 456 - }; 440 440 + pinctrl_enet2: enet2grp { 441 441 + fsl,pins = < 442 442 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 443 443 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 444 444 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 445 445 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 446 446 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 447 447 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 448 448 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 449 449 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 450 450 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 451 451 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 452 452 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 453 453 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 454 454 + >; 455 455 + }; 457 456 458 458 - pinctrl_flexcan1: flexcan1grp { 459 459 - fsl,pins = < 460 460 - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 461 461 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 462 462 - >; 463 463 - }; 457 457 + pinctrl_flexcan1: flexcan1grp { 458 458 + fsl,pins = < 459 459 + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 460 460 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 461 461 + >; 462 462 + }; 464 463 465 465 - pinctrl_flexcan2: flexcan2grp { 466 466 - fsl,pins = < 467 467 - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 468 468 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 469 469 - >; 470 470 - }; 464 464 + pinctrl_flexcan2: flexcan2grp { 465 465 + fsl,pins = < 466 466 + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 467 467 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 468 468 + >; 469 469 + }; 471 470 472 472 - pinctrl_gpio_keys: gpio_keysgrp { 473 473 - fsl,pins = < 474 474 - MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 475 475 - MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 476 476 - >; 477 477 - }; 471 471 + pinctrl_gpio_keys: gpio_keysgrp { 472 472 + fsl,pins = < 473 473 + MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 474 474 + MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 475 475 + >; 476 476 + }; 478 477 479 479 - pinctrl_hp: hpgrp { 480 480 - fsl,pins = < 481 481 - MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 482 482 - >; 483 483 - }; 478 478 + pinctrl_hp: hpgrp { 479 479 + fsl,pins = < 480 480 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 481 481 + >; 482 482 + }; 484 483 485 485 - pinctrl_i2c1: i2c1grp { 486 486 - fsl,pins = < 487 487 - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 488 488 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 489 489 - >; 490 490 - }; 484 484 + pinctrl_i2c1: i2c1grp { 485 485 + fsl,pins = < 486 486 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 487 487 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 488 488 + >; 489 489 + }; 491 490 492 492 - pinctrl_i2c3: i2c3grp { 493 493 - fsl,pins = < 494 494 - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 495 495 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 496 496 - >; 497 497 - }; 491 491 + pinctrl_i2c3: i2c3grp { 492 492 + fsl,pins = < 493 493 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 494 494 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 495 495 + >; 496 496 + }; 498 497 499 499 - pinctrl_i2c4: i2c4grp { 500 500 - fsl,pins = < 501 501 - MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 502 502 - MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 503 503 - >; 504 504 - }; 498 498 + pinctrl_i2c4: i2c4grp { 499 499 + fsl,pins = < 500 500 + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 501 501 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 502 502 + >; 503 503 + }; 505 504 506 506 - pinctrl_lcd: lcdgrp { 507 507 - fsl,pins = < 508 508 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 509 509 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 510 510 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 511 511 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 512 512 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 513 513 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 514 514 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 515 515 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 516 516 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 517 517 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 518 518 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 519 519 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 520 520 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 521 521 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 522 522 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 523 523 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 524 524 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 525 525 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 526 526 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 527 527 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 528 528 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 529 529 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 530 530 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 531 531 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 532 532 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 533 533 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 534 534 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 535 535 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 536 536 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 537 537 - >; 538 538 - }; 505 505 + pinctrl_lcd: lcdgrp { 506 506 + fsl,pins = < 507 507 + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 508 508 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 509 509 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 510 510 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 511 511 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 512 512 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 513 513 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 514 514 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 515 515 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 516 516 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 517 517 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 518 518 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 519 519 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 520 520 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 521 521 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 522 522 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 523 523 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 524 524 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 525 525 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 526 526 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 527 527 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 528 528 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 529 529 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 530 530 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 531 531 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 532 532 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 533 533 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 534 534 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 535 535 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 536 536 + >; 537 537 + }; 539 538 540 540 - pinctrl_mqs: mqsgrp { 541 541 - fsl,pins = < 542 542 - MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 543 543 - MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 544 544 - >; 545 545 - }; 539 539 + pinctrl_mqs: mqsgrp { 540 540 + fsl,pins = < 541 541 + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 542 542 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 543 543 + >; 544 544 + }; 546 545 547 547 - pinctrl_pcie: pciegrp { 548 548 - fsl,pins = < 549 549 - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 550 550 - >; 551 551 - }; 546 546 + pinctrl_pcie: pciegrp { 547 547 + fsl,pins = < 548 548 + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 549 549 + >; 550 550 + }; 552 551 553 553 - pinctrl_pcie_reg: pciereggrp { 554 554 - fsl,pins = < 555 555 - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 556 556 - >; 557 557 - }; 552 552 + pinctrl_pcie_reg: pciereggrp { 553 553 + fsl,pins = < 554 554 + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 555 555 + >; 556 556 + }; 558 557 559 559 - pinctrl_peri_3v3: peri3v3grp { 560 560 - fsl,pins = < 561 561 - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 562 562 - >; 563 563 - }; 558 558 + pinctrl_peri_3v3: peri3v3grp { 559 559 + fsl,pins = < 560 560 + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 561 561 + >; 562 562 + }; 564 563 565 565 - pinctrl_pwm3: pwm3grp-1 { 566 566 - fsl,pins = < 567 567 - MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 568 568 - >; 569 569 - }; 564 564 + pinctrl_pwm3: pwm3-1grp { 565 565 + fsl,pins = < 566 566 + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 567 567 + >; 568 568 + }; 570 569 571 571 - pinctrl_qspi2: qspi2grp { 572 572 - fsl,pins = < 573 573 - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 574 574 - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 575 575 - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 576 576 - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 577 577 - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 578 578 - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 579 579 - MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 580 580 - MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 581 581 - MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 582 582 - MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 583 583 - MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 584 584 - MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 585 585 - >; 586 586 - }; 570 570 + pinctrl_qspi2: qspi2grp { 571 571 + fsl,pins = < 572 572 + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 573 573 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 574 574 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 575 575 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 576 576 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 577 577 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 578 578 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 579 579 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 580 580 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 581 581 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 582 582 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 583 583 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 584 584 + >; 585 585 + }; 587 586 588 588 - pinctrl_vcc_sd3: vccsd3grp { 589 589 - fsl,pins = < 590 590 - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 591 591 - >; 592 592 - }; 587 587 + pinctrl_vcc_sd3: vccsd3grp { 588 588 + fsl,pins = < 589 589 + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 590 590 + >; 591 591 + }; 593 592 594 594 - pinctrl_sai1: sai1grp { 595 595 - fsl,pins = < 596 596 - MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 597 597 - MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 598 598 - MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 599 599 - MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 600 600 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 601 601 - >; 602 602 - }; 593 593 + pinctrl_sai1: sai1grp { 594 594 + fsl,pins = < 595 595 + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 596 596 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 597 597 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 598 598 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 599 599 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 600 600 + >; 601 601 + }; 603 602 604 604 - pinctrl_spdif: spdifgrp { 605 605 - fsl,pins = < 606 606 - MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 607 607 - >; 608 608 - }; 603 603 + pinctrl_spdif: spdifgrp { 604 604 + fsl,pins = < 605 605 + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 606 606 + >; 607 607 + }; 609 608 610 610 - pinctrl_uart1: uart1grp { 611 611 - fsl,pins = < 612 612 - MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 613 613 - MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 614 614 - >; 615 615 - }; 609 609 + pinctrl_uart1: uart1grp { 610 610 + fsl,pins = < 611 611 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 612 612 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 613 613 + >; 614 614 + }; 616 615 617 617 - pinctrl_uart5: uart5grp { 618 618 - fsl,pins = < 619 619 - MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 620 620 - MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 621 621 - MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 622 622 - MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 623 623 - >; 624 624 - }; 616 616 + pinctrl_uart5: uart5grp { 617 617 + fsl,pins = < 618 618 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 619 619 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 620 620 + MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 621 621 + MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 622 622 + >; 623 623 + }; 625 624 626 626 - pinctrl_usb_otg1: usbotg1grp { 627 627 - fsl,pins = < 628 628 - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 629 629 - >; 630 630 - }; 625 625 + pinctrl_usb_otg1: usbotg1grp { 626 626 + fsl,pins = < 627 627 + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 628 628 + >; 629 629 + }; 631 630 632 632 - pinctrl_usb_otg1_id: usbotg1idgrp { 633 633 - fsl,pins = < 634 634 - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 635 635 - >; 636 636 - }; 631 631 + pinctrl_usb_otg1_id: usbotg1idgrp { 632 632 + fsl,pins = < 633 633 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 634 634 + >; 635 635 + }; 637 636 638 638 - pinctrl_usb_otg2: usbot2ggrp { 639 639 - fsl,pins = < 640 640 - MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 641 641 - >; 642 642 - }; 637 637 + pinctrl_usb_otg2: usbot2ggrp { 638 638 + fsl,pins = < 639 639 + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 640 640 + >; 641 641 + }; 643 642 644 644 - pinctrl_usdhc2: usdhc2grp { 645 645 - fsl,pins = < 646 646 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 647 647 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 648 648 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 649 649 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 650 650 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 651 651 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 652 652 - >; 653 653 - }; 643 643 + pinctrl_usdhc2: usdhc2grp { 644 644 + fsl,pins = < 645 645 + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 646 646 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 647 647 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 648 648 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 649 649 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 650 650 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 651 651 + >; 652 652 + }; 654 653 655 655 - pinctrl_usdhc3: usdhc3grp { 656 656 - fsl,pins = < 657 657 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 658 658 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 659 659 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 660 660 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 661 661 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 662 662 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 663 663 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 664 664 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 665 665 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 666 666 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 667 667 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 668 668 - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 669 669 - >; 670 670 - }; 654 654 + pinctrl_usdhc3: usdhc3grp { 655 655 + fsl,pins = < 656 656 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 657 657 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 658 658 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 659 659 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 660 660 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 661 661 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 662 662 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 663 663 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 664 664 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 665 665 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 666 666 + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 667 667 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 668 668 + >; 669 669 + }; 671 670 672 672 - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 673 673 - fsl,pins = < 674 674 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 675 675 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 676 676 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 677 677 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 678 678 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 679 679 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 680 680 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 681 681 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 682 682 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 683 683 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 684 684 - >; 685 685 - }; 671 671 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 672 672 + fsl,pins = < 673 673 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 674 674 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 675 675 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 676 676 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 677 677 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 678 678 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 679 679 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 680 680 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 681 681 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 682 682 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 683 683 + >; 684 684 + }; 686 685 687 687 - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 688 688 - fsl,pins = < 689 689 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 690 690 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 691 691 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 692 692 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 693 693 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 694 694 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 695 695 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 696 696 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 697 697 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 698 698 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 699 699 - >; 700 700 - }; 686 686 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 687 687 + fsl,pins = < 688 688 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 689 689 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 690 690 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 691 691 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 692 692 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 693 693 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 694 694 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 695 695 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 696 696 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 697 697 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 698 698 + >; 699 699 + }; 701 700 702 702 - pinctrl_usdhc4: usdhc4grp { 703 703 - fsl,pins = < 704 704 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 705 705 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 706 706 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 707 707 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 708 708 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 709 709 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 710 710 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 711 711 - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 712 712 - >; 713 713 - }; 701 701 + pinctrl_usdhc4: usdhc4grp { 702 702 + fsl,pins = < 703 703 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 704 704 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 705 705 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 706 706 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 707 707 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 708 708 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 709 709 + MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 710 710 + MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 711 711 + >; 712 712 + }; 714 713 715 715 - pinctrl_wdog: wdoggrp { 716 716 - fsl,pins = < 717 717 - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 718 718 - >; 719 719 - }; 714 714 + pinctrl_wdog: wdoggrp { 715 715 + fsl,pins = < 716 716 + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 717 717 + >; 720 718 }; 721 719 };

+9 -9

arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts

reviewed

··· 358 358 >; 359 359 }; 360 360 361 361 - pinctrl_pwm1: pwm1grp-1 { 361 361 + pinctrl_pwm1: pwm1-1grp { 362 362 fsl,pins = < 363 363 /* blue LED */ 364 364 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 365 365 >; 366 366 }; 367 367 368 368 - pinctrl_pwm2: pwm2grp-1 { 368 368 + pinctrl_pwm2: pwm2-1grp { 369 369 fsl,pins = < 370 370 /* green LED */ 371 371 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 372 372 >; 373 373 }; 374 374 375 375 - pinctrl_pwm6: pwm6grp-1 { 375 375 + pinctrl_pwm6: pwm6-1grp { 376 376 fsl,pins = < 377 377 /* red LED */ 378 378 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 ··· 414 414 >; 415 415 }; 416 416 417 417 - pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { 417 417 + pinctrl_usdhc2_50mhz: usdhc2-50mhzgrp { 418 418 fsl,pins = < 419 419 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 420 420 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 ··· 427 427 >; 428 428 }; 429 429 430 430 - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 430 430 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 431 431 fsl,pins = < 432 432 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 433 433 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 ··· 438 438 >; 439 439 }; 440 440 441 441 - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 441 441 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 442 442 fsl,pins = < 443 443 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 444 444 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 ··· 449 449 >; 450 450 }; 451 451 452 452 - pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { 452 452 + pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { 453 453 fsl,pins = < 454 454 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 455 455 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 ··· 465 465 >; 466 466 }; 467 467 468 468 - pinctrl_usdhc4_100mhz: usdhc4-100mhz { 468 468 + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { 469 469 fsl,pins = < 470 470 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 471 471 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 ··· 480 480 >; 481 481 }; 482 482 483 483 - pinctrl_usdhc4_200mhz: usdhc4-200mhz { 483 483 + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { 484 484 fsl,pins = < 485 485 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 486 486 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9

+6 -5

arch/arm/boot/dts/nxp/imx/imx6sx.dtsi

reviewed

··· 715 715 }; 716 716 717 717 tempmon: tempmon { 718 718 - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 718 718 + compatible = "fsl,imx6sx-tempmon"; 719 719 interrupt-parent = <&gpc>; 720 720 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 721 721 fsl,tempmon = <&anatop>; 722 722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 723 723 nvmem-cell-names = "calib", "temp_grade"; 724 724 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 725 725 + #thermal-sensor-cells = <0>; 725 726 }; 726 727 }; 727 728 ··· 999 998 }; 1000 999 1001 1000 usdhc1: mmc@2190000 { 1002 1002 - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1001 1001 + compatible = "fsl,imx6sx-usdhc"; 1003 1002 reg = <0x02190000 0x4000>; 1004 1003 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1005 1004 clocks = <&clks IMX6SX_CLK_USDHC1>, ··· 1013 1012 }; 1014 1013 1015 1014 usdhc2: mmc@2194000 { 1016 1016 - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1015 1015 + compatible = "fsl,imx6sx-usdhc"; 1017 1016 reg = <0x02194000 0x4000>; 1018 1017 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1019 1018 clocks = <&clks IMX6SX_CLK_USDHC2>, ··· 1027 1026 }; 1028 1027 1029 1028 usdhc3: mmc@2198000 { 1030 1030 - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1029 1029 + compatible = "fsl,imx6sx-usdhc"; 1031 1030 reg = <0x02198000 0x4000>; 1032 1031 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1033 1032 clocks = <&clks IMX6SX_CLK_USDHC3>, ··· 1041 1040 }; 1042 1041 1043 1042 usdhc4: mmc@219c000 { 1044 1044 - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1043 1043 + compatible = "fsl,imx6sx-usdhc"; 1045 1044 reg = <0x0219c000 0x4000>; 1046 1045 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1047 1046 clocks = <&clks IMX6SX_CLK_USDHC4>,

+1 -1

arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi

reviewed

··· 322 322 >; 323 323 }; 324 324 325 325 - pinctrl_stmpe: stmpegrp { 325 325 + pinctrl_stmpe: stmpegrp { 326 326 fsl,pins = < 327 327 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 328 328 >;

+16

arch/arm/boot/dts/nxp/imx/imx6ul.dtsi

reviewed

··· 274 274 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 275 275 <&clks IMX6UL_CLK_UART7_SERIAL>; 276 276 clock-names = "ipg", "per"; 277 277 + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; 278 278 + dma-names = "rx", "tx"; 277 279 status = "disabled"; 278 280 }; 279 281 ··· 287 285 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 288 286 <&clks IMX6UL_CLK_UART1_SERIAL>; 289 287 clock-names = "ipg", "per"; 288 288 + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 289 289 + dma-names = "rx", "tx"; 290 290 status = "disabled"; 291 291 }; 292 292 ··· 300 296 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 301 297 <&clks IMX6UL_CLK_UART8_SERIAL>; 302 298 clock-names = "ipg", "per"; 299 299 + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; 300 300 + dma-names = "rx", "tx"; 303 301 status = "disabled"; 304 302 }; 305 303 ··· 1081 1075 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 1082 1076 <&clks IMX6UL_CLK_UART2_SERIAL>; 1083 1077 clock-names = "ipg", "per"; 1078 1078 + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1079 1079 + dma-names = "rx", "tx"; 1084 1080 status = "disabled"; 1085 1081 }; 1086 1082 ··· 1094 1086 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 1095 1087 <&clks IMX6UL_CLK_UART3_SERIAL>; 1096 1088 clock-names = "ipg", "per"; 1089 1089 + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1090 1090 + dma-names = "rx", "tx"; 1097 1091 status = "disabled"; 1098 1092 }; 1099 1093 ··· 1107 1097 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 1108 1098 <&clks IMX6UL_CLK_UART4_SERIAL>; 1109 1099 clock-names = "ipg", "per"; 1100 1100 + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1101 1101 + dma-names = "rx", "tx"; 1110 1102 status = "disabled"; 1111 1103 }; 1112 1104 ··· 1120 1108 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 1121 1109 <&clks IMX6UL_CLK_UART5_SERIAL>; 1122 1110 clock-names = "ipg", "per"; 1111 1111 + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1112 1112 + dma-names = "rx", "tx"; 1123 1113 status = "disabled"; 1124 1114 }; 1125 1115 ··· 1143 1129 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 1144 1130 <&clks IMX6UL_CLK_UART6_SERIAL>; 1145 1131 clock-names = "ipg", "per"; 1132 1132 + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1133 1133 + dma-names = "rx", "tx"; 1146 1134 status = "disabled"; 1147 1135 }; 1148 1136 };

+2

arch/arm/boot/dts/nxp/imx/imx6ull.dtsi

reviewed

··· 88 88 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 89 89 <&clks IMX6UL_CLK_UART8_SERIAL>; 90 90 clock-names = "ipg", "per"; 91 91 + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; 92 92 + dma-names = "rx", "tx"; 91 93 status = "disabled"; 92 94 }; 93 95 };

+1 -1

arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi

reviewed

··· 120 120 simple-audio-card,bitclock-master = <&dailink_master>; 121 121 simple-audio-card,format = "i2s"; 122 122 simple-audio-card,frame-master = <&dailink_master>; 123 123 - simple-audio-card,name = "imx7-sgtl5000"; 123 123 + simple-audio-card,name = "colibri-imx7"; 124 124 125 125 simple-audio-card,cpu { 126 126 sound-dai = <&sai1>;

+3 -2

arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi

reviewed

··· 214 214 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 215 215 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; 216 216 #phy-cells = <0>; 217 217 + nxp,sim = <&sim>; 217 218 }; 218 219 219 220 usdhc0: mmc@40370000 { 220 220 - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; 221 221 + compatible = "fsl,imx7ulp-usdhc"; 221 222 reg = <0x40370000 0x10000>; 222 223 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 223 224 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, ··· 232 231 }; 233 232 234 233 usdhc1: mmc@40380000 { 235 235 - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; 234 234 + compatible = "fsl,imx7ulp-usdhc"; 236 235 reg = <0x40380000 0x10000>; 237 236 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 238 237 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,

+1 -1

arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts

reviewed

··· 116 116 }; 117 117 118 118 pcf8563: rtc@51 { 119 119 - compatible = "phg,pcf8563"; 119 119 + compatible = "nxp,pcf8563"; 120 120 reg = <0x51>; 121 121 }; 122 122 };