Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v6.18-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC fix from Ulf Hansson:
- sdhci-of-dwcmshc: Fix reset handling for some variants
* tag 'mmc-v6.18-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-of-dwcmshc: Promote the th1520 reset handling to ip level
+17
-12
+17
-12
drivers/mmc/host/sdhci-of-dwcmshc.c
+17
-12
drivers/mmc/host/sdhci-of-dwcmshc.c
···
289
289
sdhci_adma_write_desc(host, desc, addr, len, cmd);
290
290
}
291
291
292
+
static void dwcmshc_reset(struct sdhci_host *host, u8 mask)
293
+
{
294
+
sdhci_reset(host, mask);
295
+
296
+
/* The dwcmshc does not comply with the SDHCI specification
297
+
* regarding the "Software Reset for CMD line should clear 'Command
298
+
* Complete' in the Normal Interrupt Status Register." Clear the bit
299
+
* here to compensate for this quirk.
300
+
*/
301
+
if (mask & SDHCI_RESET_CMD)
302
+
sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
303
+
}
304
+
292
305
static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
293
306
{
294
307
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
···
845
832
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
846
833
u16 ctrl_2;
847
834
848
-
sdhci_reset(host, mask);
849
-
850
-
/* The T-Head 1520 SoC does not comply with the SDHCI specification
851
-
* regarding the "Software Reset for CMD line should clear 'Command
852
-
* Complete' in the Normal Interrupt Status Register." Clear the bit
853
-
* here to compensate for this quirk.
854
-
*/
855
-
if (mask & SDHCI_RESET_CMD)
856
-
sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
835
+
dwcmshc_reset(host, mask);
857
836
858
837
if (priv->flags & FLAG_IO_FIXED_1V8) {
859
838
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
···
891
886
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
892
887
u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
893
888
894
-
sdhci_reset(host, mask);
889
+
dwcmshc_reset(host, mask);
895
890
896
891
if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
897
892
val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
···
963
958
val |= SDHCI_INT_DATA_AVAIL;
964
959
sdhci_writel(host, val, SDHCI_INT_STATUS);
965
960
966
-
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
961
+
dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
967
962
}
968
963
969
964
static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
···
1105
1100
.set_bus_width = sdhci_set_bus_width,
1106
1101
.set_uhs_signaling = dwcmshc_set_uhs_signaling,
1107
1102
.get_max_clock = dwcmshc_get_max_clock,
1108
-
.reset = sdhci_reset,
1103
+
.reset = dwcmshc_reset,
1109
1104
.adma_write_desc = dwcmshc_adma_write_desc,
1110
1105
.irq = dwcmshc_cqe_irq_handler,
1111
1106
};