Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'char-misc-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver fixes from Greg KH:
"Here are some small driver fixes for 5.7-rc5 that resolve a number of
minor reported issues:
- mhi bus driver fixes found as people actually use the code
- phy driver fixes and compat string additions
- most driver fix due to link order changing when the core moved out
of staging
- mei driver fix
- interconnect build warning fix
All of these have been in linux-next for a while with no reported
issues"
* tag 'char-misc-5.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
bus: mhi: core: Fix channel device name conflict
bus: mhi: core: Fix typo in comment
bus: mhi: core: Offload register accesses to the controller
bus: mhi: core: Remove link_status() callback
bus: mhi: core: Make sure to powerdown if mhi_sync_power_up fails
bus: mhi: Fix parsing of mhi_flags
mei: me: disable mei interface on LBG servers.
phy: qualcomm: usb-hs-28nm: Prepare clocks in init
MAINTAINERS: Add Vinod Koul as Generic PHY co-maintainer
interconnect: qcom: Move the static keyword to the front of declaration
most: core: use function subsys_initcall()
bus: mhi: core: Fix a NULL vs IS_ERR check in mhi_create_devices()
phy: qcom-qusb2: Re add "qcom,sdm845-qusb2-phy" compat string
phy: tegra: Select USB_COMMON for usb_get_maximum_speed()
+77
-51
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
···
7119
7119
7120
7120
GENERIC PHY FRAMEWORK
7121
7121
M: Kishon Vijay Abraham I <kishon@ti.com>
7122
+
M: Vinod Koul <vkoul@kernel.org>
7122
7123
L: linux-kernel@vger.kernel.org
7123
7124
S: Supported
7124
-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git
7125
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
7125
7126
F: Documentation/devicetree/bindings/phy/
7126
7127
F: drivers/phy/
7127
7128
F: include/linux/phy/
+3
-4
drivers/bus/mhi/core/init.c
+3
-4
drivers/bus/mhi/core/init.c
···
812
812
if (!mhi_cntrl)
813
813
return -EINVAL;
814
814
815
-
if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put)
816
-
return -EINVAL;
817
-
818
-
if (!mhi_cntrl->status_cb || !mhi_cntrl->link_status)
815
+
if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
816
+
!mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
817
+
!mhi_cntrl->write_reg)
819
818
return -EINVAL;
820
819
821
820
ret = parse_config(mhi_cntrl, config);
-3
drivers/bus/mhi/core/internal.h
-3
drivers/bus/mhi/core/internal.h
+5
-13
drivers/bus/mhi/core/main.c
+5
-13
drivers/bus/mhi/core/main.c
···
18
18
int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
19
19
void __iomem *base, u32 offset, u32 *out)
20
20
{
21
-
u32 tmp = readl(base + offset);
22
-
23
-
/* If there is any unexpected value, query the link status */
24
-
if (PCI_INVALID_READ(tmp) &&
25
-
mhi_cntrl->link_status(mhi_cntrl))
26
-
return -EIO;
27
-
28
-
*out = tmp;
29
-
30
-
return 0;
21
+
return mhi_cntrl->read_reg(mhi_cntrl, base + offset, out);
31
22
}
32
23
33
24
int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
···
40
49
void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
41
50
u32 offset, u32 val)
42
51
{
43
-
writel(val, base + offset);
52
+
mhi_cntrl->write_reg(mhi_cntrl, base + offset, val);
44
53
}
45
54
46
55
void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base,
···
285
294
!(mhi_chan->ee_mask & BIT(mhi_cntrl->ee)))
286
295
continue;
287
296
mhi_dev = mhi_alloc_device(mhi_cntrl);
288
-
if (!mhi_dev)
297
+
if (IS_ERR(mhi_dev))
289
298
return;
290
299
291
300
mhi_dev->dev_type = MHI_DEVICE_XFER;
···
327
336
328
337
/* Channel name is same for both UL and DL */
329
338
mhi_dev->chan_name = mhi_chan->name;
330
-
dev_set_name(&mhi_dev->dev, "%04x_%s", mhi_chan->chan,
339
+
dev_set_name(&mhi_dev->dev, "%s_%s",
340
+
dev_name(mhi_cntrl->cntrl_dev),
331
341
mhi_dev->chan_name);
332
342
333
343
/* Init wakeup source if available */
+5
-1
drivers/bus/mhi/core/pm.c
+5
-1
drivers/bus/mhi/core/pm.c
···
902
902
MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
903
903
msecs_to_jiffies(mhi_cntrl->timeout_ms));
904
904
905
-
return (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -EIO;
905
+
ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
906
+
if (ret)
907
+
mhi_power_down(mhi_cntrl, false);
908
+
909
+
return ret;
906
910
}
907
911
EXPORT_SYMBOL(mhi_sync_power_up);
908
912
+2
-2
drivers/interconnect/qcom/osm-l3.c
+2
-2
drivers/interconnect/qcom/osm-l3.c
···
78
78
[SLAVE_OSM_L3] = &sdm845_osm_l3,
79
79
};
80
80
81
-
const static struct qcom_icc_desc sdm845_icc_osm_l3 = {
81
+
static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
82
82
.nodes = sdm845_osm_l3_nodes,
83
83
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
84
84
};
···
91
91
[SLAVE_OSM_L3] = &sc7180_osm_l3,
92
92
};
93
93
94
-
const static struct qcom_icc_desc sc7180_icc_osm_l3 = {
94
+
static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
95
95
.nodes = sc7180_osm_l3_nodes,
96
96
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
97
97
};
+8
-8
drivers/interconnect/qcom/sdm845.c
+8
-8
drivers/interconnect/qcom/sdm845.c
···
192
192
[SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
193
193
};
194
194
195
-
const static struct qcom_icc_desc sdm845_aggre1_noc = {
195
+
static const struct qcom_icc_desc sdm845_aggre1_noc = {
196
196
.nodes = aggre1_noc_nodes,
197
197
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
198
198
.bcms = aggre1_noc_bcms,
···
220
220
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
221
221
};
222
222
223
-
const static struct qcom_icc_desc sdm845_aggre2_noc = {
223
+
static const struct qcom_icc_desc sdm845_aggre2_noc = {
224
224
.nodes = aggre2_noc_nodes,
225
225
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
226
226
.bcms = aggre2_noc_bcms,
···
281
281
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
282
282
};
283
283
284
-
const static struct qcom_icc_desc sdm845_config_noc = {
284
+
static const struct qcom_icc_desc sdm845_config_noc = {
285
285
.nodes = config_noc_nodes,
286
286
.num_nodes = ARRAY_SIZE(config_noc_nodes),
287
287
.bcms = config_noc_bcms,
···
297
297
[SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
298
298
};
299
299
300
-
const static struct qcom_icc_desc sdm845_dc_noc = {
300
+
static const struct qcom_icc_desc sdm845_dc_noc = {
301
301
.nodes = dc_noc_nodes,
302
302
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
303
303
.bcms = dc_noc_bcms,
···
315
315
[SLAVE_SERVICE_GNOC] = &srvc_gnoc,
316
316
};
317
317
318
-
const static struct qcom_icc_desc sdm845_gladiator_noc = {
318
+
static const struct qcom_icc_desc sdm845_gladiator_noc = {
319
319
.nodes = gladiator_noc_nodes,
320
320
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
321
321
.bcms = gladiator_noc_bcms,
···
350
350
[SLAVE_EBI1] = &ebi,
351
351
};
352
352
353
-
const static struct qcom_icc_desc sdm845_mem_noc = {
353
+
static const struct qcom_icc_desc sdm845_mem_noc = {
354
354
.nodes = mem_noc_nodes,
355
355
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
356
356
.bcms = mem_noc_bcms,
···
384
384
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
385
385
};
386
386
387
-
const static struct qcom_icc_desc sdm845_mmss_noc = {
387
+
static const struct qcom_icc_desc sdm845_mmss_noc = {
388
388
.nodes = mmss_noc_nodes,
389
389
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
390
390
.bcms = mmss_noc_bcms,
···
430
430
[SLAVE_TCU] = &xs_sys_tcu_cfg,
431
431
};
432
432
433
-
const static struct qcom_icc_desc sdm845_system_noc = {
433
+
static const struct qcom_icc_desc sdm845_system_noc = {
434
434
.nodes = system_noc_nodes,
435
435
.num_nodes = ARRAY_SIZE(system_noc_nodes),
436
436
.bcms = system_noc_bcms,
+8
drivers/misc/mei/hw-me.c
+8
drivers/misc/mei/hw-me.c
···
1465
1465
MEI_CFG_DMA_128,
1466
1466
};
1467
1467
1468
+
/* LBG with quirk for SPS Firmware exclusion */
1469
+
static const struct mei_cfg mei_me_pch12_sps_cfg = {
1470
+
MEI_CFG_PCH8_HFS,
1471
+
MEI_CFG_FW_VER_SUPP,
1472
+
MEI_CFG_FW_SPS,
1473
+
};
1474
+
1468
1475
/* Tiger Lake and newer devices */
1469
1476
static const struct mei_cfg mei_me_pch15_cfg = {
1470
1477
MEI_CFG_PCH8_HFS,
···
1494
1487
[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1495
1488
[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
1496
1489
[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1490
+
[MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1497
1491
[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
1498
1492
};
1499
1493
+4
drivers/misc/mei/hw-me.h
+4
drivers/misc/mei/hw-me.h
···
80
80
* servers platforms with quirk for
81
81
* SPS firmware exclusion.
82
82
* @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
83
+
* @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 and newer
84
+
* servers platforms with quirk for
85
+
* SPS firmware exclusion.
83
86
* @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
84
87
* @MEI_ME_NUM_CFG: Upper Sentinel.
85
88
*/
···
96
93
MEI_ME_PCH8_CFG,
97
94
MEI_ME_PCH8_SPS_CFG,
98
95
MEI_ME_PCH12_CFG,
96
+
MEI_ME_PCH12_SPS_CFG,
99
97
MEI_ME_PCH15_CFG,
100
98
MEI_ME_NUM_CFG,
101
99
};
+1
-1
drivers/misc/mei/pci-me.c
+1
-1
drivers/misc/mei/pci-me.c
···
70
70
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
71
71
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
72
72
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
73
-
{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
73
+
{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_CFG)},
74
74
75
75
{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
76
76
{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
+1
-1
drivers/most/core.c
+1
-1
drivers/most/core.c
+7
drivers/phy/qualcomm/phy-qcom-qusb2.c
+7
drivers/phy/qualcomm/phy-qcom-qusb2.c
···
816
816
.compatible = "qcom,msm8998-qusb2-phy",
817
817
.data = &msm8998_phy_cfg,
818
818
}, {
819
+
/*
820
+
* Deprecated. Only here to support legacy device
821
+
* trees that didn't include "qcom,qusb2-v2-phy"
822
+
*/
823
+
.compatible = "qcom,sdm845-qusb2-phy",
824
+
.data = &qusb2_v2_phy_cfg,
825
+
}, {
819
826
.compatible = "qcom,qusb2-v2-phy",
820
827
.data = &qusb2_v2_phy_cfg,
821
828
},
+21
-11
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
+21
-11
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
···
160
160
ret = regulator_bulk_enable(VREG_NUM, priv->vregs);
161
161
if (ret)
162
162
return ret;
163
-
ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
164
-
if (ret)
165
-
goto err_disable_regulator;
163
+
166
164
qcom_snps_hsphy_disable_hv_interrupts(priv);
167
165
qcom_snps_hsphy_exit_retention(priv);
168
166
169
167
return 0;
170
-
171
-
err_disable_regulator:
172
-
regulator_bulk_disable(VREG_NUM, priv->vregs);
173
-
174
-
return ret;
175
168
}
176
169
177
170
static int qcom_snps_hsphy_power_off(struct phy *phy)
···
173
180
174
181
qcom_snps_hsphy_enter_retention(priv);
175
182
qcom_snps_hsphy_enable_hv_interrupts(priv);
176
-
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
177
183
regulator_bulk_disable(VREG_NUM, priv->vregs);
178
184
179
185
return 0;
···
258
266
struct hsphy_priv *priv = phy_get_drvdata(phy);
259
267
int ret;
260
268
261
-
ret = qcom_snps_hsphy_reset(priv);
269
+
ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
262
270
if (ret)
263
271
return ret;
272
+
273
+
ret = qcom_snps_hsphy_reset(priv);
274
+
if (ret)
275
+
goto disable_clocks;
264
276
265
277
qcom_snps_hsphy_init_sequence(priv);
266
278
267
279
ret = qcom_snps_hsphy_por_reset(priv);
268
280
if (ret)
269
-
return ret;
281
+
goto disable_clocks;
282
+
283
+
return 0;
284
+
285
+
disable_clocks:
286
+
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
287
+
return ret;
288
+
}
289
+
290
+
static int qcom_snps_hsphy_exit(struct phy *phy)
291
+
{
292
+
struct hsphy_priv *priv = phy_get_drvdata(phy);
293
+
294
+
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
270
295
271
296
return 0;
272
297
}
273
298
274
299
static const struct phy_ops qcom_snps_hsphy_ops = {
275
300
.init = qcom_snps_hsphy_init,
301
+
.exit = qcom_snps_hsphy_exit,
276
302
.power_on = qcom_snps_hsphy_power_on,
277
303
.power_off = qcom_snps_hsphy_power_off,
278
304
.set_mode = qcom_snps_hsphy_set_mode,
+10
-6
include/linux/mhi.h
+10
-6
include/linux/mhi.h
···
53
53
* @MHI_CHAIN: Linked transfer
54
54
*/
55
55
enum mhi_flags {
56
-
MHI_EOB,
57
-
MHI_EOT,
58
-
MHI_CHAIN,
56
+
MHI_EOB = BIT(0),
57
+
MHI_EOT = BIT(1),
58
+
MHI_CHAIN = BIT(2),
59
59
};
60
60
61
61
/**
···
335
335
* @syserr_worker: System error worker
336
336
* @state_event: State change event
337
337
* @status_cb: CB function to notify power states of the device (required)
338
-
* @link_status: CB function to query link status of the device (required)
339
338
* @wake_get: CB function to assert device wake (optional)
340
339
* @wake_put: CB function to de-assert device wake (optional)
341
340
* @wake_toggle: CB function to assert and de-assert device wake (optional)
342
341
* @runtime_get: CB function to controller runtime resume (required)
343
-
* @runtimet_put: CB function to decrement pm usage (required)
342
+
* @runtime_put: CB function to decrement pm usage (required)
344
343
* @map_single: CB function to create TRE buffer
345
344
* @unmap_single: CB function to destroy TRE buffer
345
+
* @read_reg: Read a MHI register via the physical link (required)
346
+
* @write_reg: Write a MHI register via the physical link (required)
346
347
* @buffer_len: Bounce buffer length
347
348
* @bounce_buf: Use of bounce buffer
348
349
* @fbc_download: MHI host needs to do complete image transfer (optional)
···
418
417
419
418
void (*status_cb)(struct mhi_controller *mhi_cntrl,
420
419
enum mhi_callback cb);
421
-
int (*link_status)(struct mhi_controller *mhi_cntrl);
422
420
void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override);
423
421
void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override);
424
422
void (*wake_toggle)(struct mhi_controller *mhi_cntrl);
···
427
427
struct mhi_buf_info *buf);
428
428
void (*unmap_single)(struct mhi_controller *mhi_cntrl,
429
429
struct mhi_buf_info *buf);
430
+
int (*read_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
431
+
u32 *out);
432
+
void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
433
+
u32 val);
430
434
431
435
size_t buffer_len;
432
436
bool bounce_buf;