tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
"This lot provides:

- plug a hotplug race in the new affinity infrastructure
- a fix for the trigger type of chained interrupts
- plug a potential memory leak in the core code
- a few fixes for ARM and MIPS GICs"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/mips-gic: Implement activate op for device domain
irqchip/mips-gic: Cleanup chip and handler setup
genirq/affinity: Use get/put_online_cpus around cpumask operations
genirq: Fix potential memleak when failing to get irq pm
irqchip/gicv3-its: Disable the ITS before initializing it
irqchip/gicv3: Remove disabling redistributor and group1 non-secure interrupts
irqchip/gic: Allow self-SGIs for SMP on UP configurations
genirq: Correctly configure the trigger on chained interrupts

Linus Torvalds 4340393e 037d2405

+55 -9
+6 -1
drivers/irqchip/irq-gic-v3-its.c
··· 1545 1545 u32 val; 1546 1546 1547 1547 val = readl_relaxed(base + GITS_CTLR); 1548 - if (val & GITS_CTLR_QUIESCENT) 1548 + /* 1549 + * GIC architecture specification requires the ITS to be both 1550 + * disabled and quiescent for writes to GITS_BASER<n> or 1551 + * GITS_CBASER to not have UNPREDICTABLE results. 1552 + */ 1553 + if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) 1549 1554 return 0; 1550 1555 1551 1556 /* Disable the generation of all interrupts to this ITS */
+9 -2
drivers/irqchip/irq-gic-v3.c
··· 667 667 #endif 668 668 669 669 #ifdef CONFIG_CPU_PM 670 + /* Check whether it's single security state view */ 671 + static bool gic_dist_security_disabled(void) 672 + { 673 + return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 674 + } 675 + 670 676 static int gic_cpu_pm_notifier(struct notifier_block *self, 671 677 unsigned long cmd, void *v) 672 678 { 673 679 if (cmd == CPU_PM_EXIT) { 674 - gic_enable_redist(true); 680 + if (gic_dist_security_disabled()) 681 + gic_enable_redist(true); 675 682 gic_cpu_sys_reg_init(); 676 - } else if (cmd == CPU_PM_ENTER) { 683 + } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 677 684 gic_write_grpen1(0); 678 685 gic_enable_redist(false); 679 686 }
+7
drivers/irqchip/irq-gic.c
··· 769 769 int cpu; 770 770 unsigned long flags, map = 0; 771 771 772 + if (unlikely(nr_cpu_ids == 1)) { 773 + /* Only one CPU? let's do a self-IPI... */ 774 + writel_relaxed(2 << 24 | irq, 775 + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 776 + return; 777 + } 778 + 772 779 raw_spin_lock_irqsave(&irq_controller_lock, flags); 773 780 774 781 /* Convert our logical CPU mask into a physical one. */
+14 -4
drivers/irqchip/irq-mips-gic.c
··· 713 713 unsigned long flags; 714 714 int i; 715 715 716 - irq_set_chip_and_handler(virq, &gic_level_irq_controller, 717 - handle_level_irq); 718 - 719 716 spin_lock_irqsave(&gic_lock, flags); 720 717 gic_map_to_pin(intr, gic_cpu_pin); 721 718 gic_map_to_vpe(intr, mips_cm_vp_id(vpe)); ··· 729 732 { 730 733 if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) 731 734 return gic_local_irq_domain_map(d, virq, hw); 735 + 736 + irq_set_chip_and_handler(virq, &gic_level_irq_controller, 737 + handle_level_irq); 738 + 732 739 return gic_shared_irq_domain_map(d, virq, hw, 0); 733 740 } 734 741 ··· 772 771 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); 773 772 774 773 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, 775 - &gic_edge_irq_controller, 774 + &gic_level_irq_controller, 776 775 NULL); 777 776 if (ret) 778 777 goto error; 778 + 779 + irq_set_handler(virq + i, handle_level_irq); 779 780 780 781 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); 781 782 if (ret) ··· 893 890 return; 894 891 } 895 892 893 + static void gic_dev_domain_activate(struct irq_domain *domain, 894 + struct irq_data *d) 895 + { 896 + gic_shared_irq_domain_map(domain, d->irq, d->hwirq, 0); 897 + } 898 + 896 899 static struct irq_domain_ops gic_dev_domain_ops = { 897 900 .xlate = gic_dev_domain_xlate, 898 901 .alloc = gic_dev_domain_alloc, 899 902 .free = gic_dev_domain_free, 903 + .activate = gic_dev_domain_activate, 900 904 }; 901 905 902 906 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+2
kernel/irq/affinity.c
··· 39 39 return NULL; 40 40 } 41 41 42 + get_online_cpus(); 42 43 if (max_vecs >= num_online_cpus()) { 43 44 cpumask_copy(affinity_mask, cpu_online_mask); 44 45 *nr_vecs = num_online_cpus(); ··· 57 56 } 58 57 *nr_vecs = vecs; 59 58 } 59 + put_online_cpus(); 60 60 61 61 return affinity_mask; 62 62 }
+11
kernel/irq/chip.c
··· 820 820 desc->name = name; 821 821 822 822 if (handle != handle_bad_irq && is_chained) { 823 + /* 824 + * We're about to start this interrupt immediately, 825 + * hence the need to set the trigger configuration. 826 + * But the .set_type callback may have overridden the 827 + * flow handler, ignoring that we're dealing with a 828 + * chained interrupt. Reset it immediately because we 829 + * do know better. 830 + */ 831 + __irq_set_trigger(desc, irqd_get_trigger_type(&desc->irq_data)); 832 + desc->handle_irq = handle; 833 + 823 834 irq_settings_set_noprobe(desc); 824 835 irq_settings_set_norequest(desc); 825 836 irq_settings_set_nothread(desc);
+6 -2
kernel/irq/manage.c
··· 1681 1681 action->dev_id = dev_id; 1682 1682 1683 1683 retval = irq_chip_pm_get(&desc->irq_data); 1684 - if (retval < 0) 1684 + if (retval < 0) { 1685 + kfree(action); 1685 1686 return retval; 1687 + } 1686 1688 1687 1689 chip_bus_lock(desc); 1688 1690 retval = __setup_irq(irq, desc, action); ··· 1987 1985 action->percpu_dev_id = dev_id; 1988 1986 1989 1987 retval = irq_chip_pm_get(&desc->irq_data); 1990 - if (retval < 0) 1988 + if (retval < 0) { 1989 + kfree(action); 1991 1990 return retval; 1991 + } 1992 1992 1993 1993 chip_bus_lock(desc); 1994 1994 retval = __setup_irq(irq, desc, action);