Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

+21 -15

arch/arm64/kvm/hyp/vgic-v3-sr.c

··· 169 169 * Make sure stores to the GIC via the memory mapped interface 170 170 * are now visible to the system register interface. 171 171 */ 172 - dsb(st); 172 + if (!cpu_if->vgic_sre) 173 + dsb(st); 173 174 174 175 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); 175 176 ··· 191 190 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i))) 192 191 continue; 193 192 194 - if (cpu_if->vgic_elrsr & (1 << i)) { 193 + if (cpu_if->vgic_elrsr & (1 << i)) 195 194 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE; 196 - continue; 197 - } 195 + else 196 + cpu_if->vgic_lr[i] = __gic_v3_get_lr(i); 198 197 199 - cpu_if->vgic_lr[i] = __gic_v3_get_lr(i); 200 198 __gic_v3_set_lr(0, i); 201 199 } 202 200 ··· 236 236 237 237 val = read_gicreg(ICC_SRE_EL2); 238 238 write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); 239 - isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ 240 - write_gicreg(1, ICC_SRE_EL1); 239 + 240 + if (!cpu_if->vgic_sre) { 241 + /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ 242 + isb(); 243 + write_gicreg(1, ICC_SRE_EL1); 244 + } 241 245 } 242 246 243 247 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) ··· 260 256 * been actually programmed with the value we want before 261 257 * starting to mess with the rest of the GIC. 262 258 */ 263 - write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1); 264 - isb(); 259 + if (!cpu_if->vgic_sre) { 260 + write_gicreg(0, ICC_SRE_EL1); 261 + isb(); 262 + } 265 263 266 264 val = read_gicreg(ICH_VTR_EL2); 267 265 max_lr_idx = vtr_to_max_lr_idx(val); ··· 312 306 * (re)distributors. This ensure the guest will read the 313 307 * correct values from the memory-mapped interface. 314 308 */ 315 - isb(); 316 - dsb(sy); 309 + if (!cpu_if->vgic_sre) { 310 + isb(); 311 + dsb(sy); 312 + } 317 313 vcpu->arch.vgic_cpu.live_lrs = live_lrs; 318 314 319 315 /* 320 316 * Prevent the guest from touching the GIC system registers if 321 317 * SRE isn't enabled for GICv3 emulation. 322 318 */ 323 - if (!cpu_if->vgic_sre) { 324 - write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, 325 - ICC_SRE_EL2); 326 - } 319 + write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, 320 + ICC_SRE_EL2); 327 321 } 328 322 329 323 void __hyp_text __vgic_v3_init_lrs(void)

+12 -1

arch/arm64/kvm/sys_regs.c

··· 134 134 return true; 135 135 } 136 136 137 + static bool access_gic_sre(struct kvm_vcpu *vcpu, 138 + struct sys_reg_params *p, 139 + const struct sys_reg_desc *r) 140 + { 141 + if (p->is_write) 142 + return ignore_write(vcpu, p); 143 + 144 + p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 145 + return true; 146 + } 147 + 137 148 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 138 149 struct sys_reg_params *p, 139 150 const struct sys_reg_desc *r) ··· 969 958 access_gic_sgi }, 970 959 /* ICC_SRE_EL1 */ 971 960 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101), 972 - trap_raz_wi }, 961 + access_gic_sre }, 973 962 974 963 /* CONTEXTIDR_EL1 */ 975 964 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),

+12 -10

arch/x86/kvm/cpuid.c

··· 181 181 struct kvm_cpuid_entry __user *entries) 182 182 { 183 183 int r, i; 184 - struct kvm_cpuid_entry *cpuid_entries; 184 + struct kvm_cpuid_entry *cpuid_entries = NULL; 185 185 186 186 r = -E2BIG; 187 187 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 188 188 goto out; 189 189 r = -ENOMEM; 190 - cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); 191 - if (!cpuid_entries) 192 - goto out; 193 - r = -EFAULT; 194 - if (copy_from_user(cpuid_entries, entries, 195 - cpuid->nent * sizeof(struct kvm_cpuid_entry))) 196 - goto out_free; 190 + if (cpuid->nent) { 191 + cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * 192 + cpuid->nent); 193 + if (!cpuid_entries) 194 + goto out; 195 + r = -EFAULT; 196 + if (copy_from_user(cpuid_entries, entries, 197 + cpuid->nent * sizeof(struct kvm_cpuid_entry))) 198 + goto out; 199 + } 197 200 for (i = 0; i < cpuid->nent; i++) { 198 201 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; 199 202 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; ··· 215 212 kvm_x86_ops->cpuid_update(vcpu); 216 213 r = kvm_update_cpuid(vcpu); 217 214 218 - out_free: 219 - vfree(cpuid_entries); 220 215 out: 216 + vfree(cpuid_entries); 221 217 return r; 222 218 } 223 219

+4 -4

arch/x86/kvm/mmu.c

··· 336 336 #ifdef CONFIG_X86_64 337 337 static void __set_spte(u64 *sptep, u64 spte) 338 338 { 339 - *sptep = spte; 339 + WRITE_ONCE(*sptep, spte); 340 340 } 341 341 342 342 static void __update_clear_spte_fast(u64 *sptep, u64 spte) 343 343 { 344 - *sptep = spte; 344 + WRITE_ONCE(*sptep, spte); 345 345 } 346 346 347 347 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) ··· 390 390 */ 391 391 smp_wmb(); 392 392 393 - ssptep->spte_low = sspte.spte_low; 393 + WRITE_ONCE(ssptep->spte_low, sspte.spte_low); 394 394 } 395 395 396 396 static void __update_clear_spte_fast(u64 *sptep, u64 spte) ··· 400 400 ssptep = (union split_spte *)sptep; 401 401 sspte = (union split_spte)spte; 402 402 403 - ssptep->spte_low = sspte.spte_low; 403 + WRITE_ONCE(ssptep->spte_low, sspte.spte_low); 404 404 405 405 /* 406 406 * If we map the spte from present to nonpresent, we should clear

+11 -1

arch/x86/kvm/x86.c

··· 2314 2314 case MSR_AMD64_NB_CFG: 2315 2315 case MSR_FAM10H_MMIO_CONF_BASE: 2316 2316 case MSR_AMD64_BU_CFG2: 2317 + case MSR_IA32_PERF_CTL: 2317 2318 msr_info->data = 0; 2318 2319 break; 2319 2320 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: ··· 2973 2972 | KVM_VCPUEVENT_VALID_SMM)) 2974 2973 return -EINVAL; 2975 2974 2975 + if (events->exception.injected && 2976 + (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 2977 + return -EINVAL; 2978 + 2976 2979 process_nmi(vcpu); 2977 2980 vcpu->arch.exception.pending = events->exception.injected; 2978 2981 vcpu->arch.exception.nr = events->exception.nr; ··· 3039 3034 struct kvm_debugregs *dbgregs) 3040 3035 { 3041 3036 if (dbgregs->flags) 3037 + return -EINVAL; 3038 + 3039 + if (dbgregs->dr6 & ~0xffffffffull) 3040 + return -EINVAL; 3041 + if (dbgregs->dr7 & ~0xffffffffull) 3042 3042 return -EINVAL; 3043 3043 3044 3044 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); ··· 7825 7815 7826 7816 slot = id_to_memslot(slots, id); 7827 7817 if (size) { 7828 - if (WARN_ON(slot->npages)) 7818 + if (slot->npages) 7829 7819 return -EEXIST; 7830 7820 7831 7821 /*

+3 -4

virt/kvm/arm/hyp/vgic-v2-sr.c

··· 100 100 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i))) 101 101 continue; 102 102 103 - if (cpu_if->vgic_elrsr & (1UL << i)) { 103 + if (cpu_if->vgic_elrsr & (1UL << i)) 104 104 cpu_if->vgic_lr[i] &= ~GICH_LR_STATE; 105 - continue; 106 - } 105 + else 106 + cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); 107 107 108 - cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); 109 108 writel_relaxed(0, base + GICH_LR0 + (i * 4)); 110 109 } 111 110 }

+1 -3

virt/kvm/arm/vgic/vgic-mmio.c

··· 191 191 * other thread sync back the IRQ. 192 192 */ 193 193 while (irq->vcpu && /* IRQ may have state in an LR somewhere */ 194 - irq->vcpu->cpu != -1) { /* VCPU thread is running */ 195 - BUG_ON(irq->intid < VGIC_NR_PRIVATE_IRQS); 194 + irq->vcpu->cpu != -1) /* VCPU thread is running */ 196 195 cond_resched_lock(&irq->irq_lock); 197 - } 198 196 199 197 irq->active = new_active_state; 200 198 if (new_active_state)

+9 -5

virt/kvm/arm/vgic/vgic-v2.c

··· 112 112 } 113 113 } 114 114 115 - /* Clear soft pending state when level IRQs have been acked */ 116 - if (irq->config == VGIC_CONFIG_LEVEL && 117 - !(val & GICH_LR_PENDING_BIT)) { 118 - irq->soft_pending = false; 119 - irq->pending = irq->line_level; 115 + /* 116 + * Clear soft pending state when level irqs have been acked. 117 + * Always regenerate the pending state. 118 + */ 119 + if (irq->config == VGIC_CONFIG_LEVEL) { 120 + if (!(val & GICH_LR_PENDING_BIT)) 121 + irq->soft_pending = false; 122 + 123 + irq->pending = irq->line_level || irq->soft_pending; 120 124 } 121 125 122 126 spin_unlock(&irq->irq_lock);

+9 -5

virt/kvm/arm/vgic/vgic-v3.c

··· 101 101 } 102 102 } 103 103 104 - /* Clear soft pending state when level irqs have been acked */ 105 - if (irq->config == VGIC_CONFIG_LEVEL && 106 - !(val & ICH_LR_PENDING_BIT)) { 107 - irq->soft_pending = false; 108 - irq->pending = irq->line_level; 104 + /* 105 + * Clear soft pending state when level irqs have been acked. 106 + * Always regenerate the pending state. 107 + */ 108 + if (irq->config == VGIC_CONFIG_LEVEL) { 109 + if (!(val & ICH_LR_PENDING_BIT)) 110 + irq->soft_pending = false; 111 + 112 + irq->pending = irq->line_level || irq->soft_pending; 109 113 } 110 114 111 115 spin_unlock(&irq->irq_lock);

+1 -1

virt/kvm/irqchip.c

··· 40 40 41 41 irq_rt = srcu_dereference_check(kvm->irq_routing, &kvm->irq_srcu, 42 42 lockdep_is_held(&kvm->irq_lock)); 43 - if (gsi < irq_rt->nr_rt_entries) { 43 + if (irq_rt && gsi < irq_rt->nr_rt_entries) { 44 44 hlist_for_each_entry(e, &irq_rt->map[gsi], link) { 45 45 entries[n] = *e; 46 46 ++n;

+12 -10

virt/kvm/kvm_main.c

··· 2935 2935 case KVM_SET_GSI_ROUTING: { 2936 2936 struct kvm_irq_routing routing; 2937 2937 struct kvm_irq_routing __user *urouting; 2938 - struct kvm_irq_routing_entry *entries; 2938 + struct kvm_irq_routing_entry *entries = NULL; 2939 2939 2940 2940 r = -EFAULT; 2941 2941 if (copy_from_user(&routing, argp, sizeof(routing))) ··· 2945 2945 goto out; 2946 2946 if (routing.flags) 2947 2947 goto out; 2948 - r = -ENOMEM; 2949 - entries = vmalloc(routing.nr * sizeof(*entries)); 2950 - if (!entries) 2951 - goto out; 2952 - r = -EFAULT; 2953 - urouting = argp; 2954 - if (copy_from_user(entries, urouting->entries, 2955 - routing.nr * sizeof(*entries))) 2956 - goto out_free_irq_routing; 2948 + if (routing.nr) { 2949 + r = -ENOMEM; 2950 + entries = vmalloc(routing.nr * sizeof(*entries)); 2951 + if (!entries) 2952 + goto out; 2953 + r = -EFAULT; 2954 + urouting = argp; 2955 + if (copy_from_user(entries, urouting->entries, 2956 + routing.nr * sizeof(*entries))) 2957 + goto out_free_irq_routing; 2958 + } 2957 2959 r = kvm_set_irq_routing(kvm, entries, routing.nr, 2958 2960 routing.flags); 2959 2961 out_free_irq_routing:

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